30 n-channel logic level enhancement mode field effect transistor features 30v , 40a , r ds(on) =19m @v gs =10v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-251 & to-252 package. absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 20 v -pulsed i d 40 a i dm 120 a drain-source diode forward current i s 40 a maximum power dissipation p d w operating and storage temperature range t j ,t stg -65 to 175 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 3 50 /w c /w c ? r ds(on) =32m @v gs =4.5v. ? CED703AL/ceu703al @tc=25 c derate above 25 c 50 0.3 w/ c drain current-continuous @t j =125 c a a a s g d 6 jun. 2002 ceu series to-252aa(d-pak) ced series to-251(l-pak) g g s s d d 6-47
CED703AL/ceu703al electrical characteristics (t c =25 c unless otherwise noted) parameter symbol condition min typ max unit off characteristics drain-source breakdown voltage bv dss = v gs 0v, i d 250 a = 30 v zero gate voltage drain current i dss v ds 24v, v gs 0v == 1 a gate-body leakage i gss v gs 20v, v ds =0v = 100 na on characteristics a gate threshold voltage v gs(th) v ds =v gs ,i d = 250 a = = 13 v drain-source on-state resistance r ds(on) v gs 10v, i d = 25a 15 19 m ? v gs 4.5v, i d = 10a 23 32 m ? on-state drain current i d(on) v gs = 10v, v ds =10v 60 30 a s forward transconductance fs g v ds = 10v, i d =25a dynamic characteristics b input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =15v, v gs =0v f =1.0mh z 1000 p f 420 p f p f 100 switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f v dd =15v, i d =25a, v gs = 10v, r gen =24 ? 18 23 ns ns ns ns 120 180 80 120 60 165 total gate charge gate-source charge gate-drain charge q g q gs q gd v ds =10v, i d =25a, v gs =5v 15 20 nc nc nc 4 6 fall time 6 6-48
CED703AL/ceu703al parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) drain-source diode characteristics diode forward voltage v sd v gs = 0v, is =25a 0.93 1.3 v b notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. [ [ 25 c -55 c 3.0 2.5 2.0 1.5 1.0 0.5 0 01020 30 40 tj=125 c v gs =10v figure 1. output characteristics figure 4. on-resistance variation with drain current and temperature figure 3. capacitance v ds , drain-to source voltage (v) v ds , drain-to-source voltage (v) i d , drain current(a) i d , drain current(a) c, capacitance (pf) drain-source on-resistance figure 2. transfer characteristics v gs , gate-to-source voltage (v) i d , drain current (a) r ds(on) , normalized 6 6-49 -55 c 40 30 20 10 0 0123 5 46 25 c t j =125 c 40 35 30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 v gs =10,8,7,6,5v v gs =4v v gs =3v ciss coss crss 3000 2500 2000 1500 1000 500 0 010 515202530
CED703AL/ceu703al with temperature figure 6. breakdown voltage variation figure 5. gate threshold variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) v gs , gate to source voltage (v) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) figure 7. transconductance variation with drain current i ds , drain-source current (a) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) i d , drain current (a) 6 40 10 1.0 0.1 0.4 0.6 0.8 1.0 1.2 1.4 1.15 1.10 1.05 1.0 0.95 0.90 0.85 0.80 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 3 a -50 -25 0 25 50 75 100 125 150 1.06 1.04 1.02 1.00 0.98 0.96 0.94 i d =250 3 a 50 40 30 20 10 5 0 01020 3040 v ds =10v 300 100 200 10 1 0.5 0.1 1 10 30 60 v gs =10v single pulse tc=25 c r d s (o n) limi t d c 1 0ms 1ms 1 0 0 3 s 10 3 s 6-50 10 8 6 4 2 0 048121620242832 v ds =10v i d =25a
figure 11. switching test circuit figure 12. switching waveforms CED703AL/ceu703al t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width 6 inverted v dd r d v v r s v g gs in gen out l transient thermal impedance square wave pulse duration (sec) figure 13. normalized thermal transient impedance curve r(t),normalized effective 2 1 0.1 0.01 10 -5 10 -4 10 -3 10 -2 10 -1 110 d=0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 1. r / ja (t)=r (t) * r / ja 2. r / ja =see datasheet 3. t jm- t a =p dm *r / ja (t) 4. duty cycle, d=t 1 /t 2 single pulse 6-51
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