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eroflex circuit technology ? mips turboengines for the future ? scd5271sc rev a 2/2/01 footprint compatible with aeroflex?s original act-4431sc 1mb secondary cache mcm in the 280 lead ceramic quad flat pack (cqfp) qed rm5271 dual issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle max system clock ? 25mhz, max secondary cache (sc) clock 75mhz, max pipeline 150mhz high performance system interface compatible with r4400 internal pll generates selectable 2x/3x sc bus speed operation vs external system bus speed generates r4400 style system clocks cpu cycle rate buffering fifo implemented in fpga 64-bit multiplexed system address/data bus for optimum price/performance high performance write protocols maximize uncached write bandwidth operates at processor clock multipliers 2, 2.5 & 3 integrated on-chip primary caches 32kb instruction - 2 way set associative 32kb data - 2 way set associative virtually indexed, physically tagged write-back and write-through on per page basis pipeline restart on first double for data cache misses integrated in-module secondary cache 2mb shared write-through 4-128k x 36 synchronous sram and 1-64k x 18 tag ram integrated memory management unit fully associative joint tlb (shared by i and d translations) 48 dual entries map 96 pages variable page size (4kb to 16mb in 4x increments) high-performance floating point unit single cycle repeat rate for common single precision operations and some double precision operations two cycle repeat rate for double precision multiply and double precision combined multiply-add operations single cycle repeat rate for single precision combined multiply-add operation mips iv instruction set floating point multiply-add instruction increases performance in signal processing and graphics applications conditional moves to reduce branch frequency index address modes (register + register) embedded application enhancements specialized dsp integer multiply-accumulate instruction and 3 operand multiply instruction i and d cache locking by set optional dedicated exception vector for interrupts microprocessor with 2m b secondary cache act-5271sc mu ltichip module features
aeroflex circuit technology act5271sc rev a 2/2/01 plainview ny (516) 694-6700 2 cpu reset cpu control s-cache control cpu sysad int* cpu syscmd fpga control clks multiplied clk (2x or 3x) control = validout*, release*, rdrdy*, wrrdy*, reset control clks sysad syscmd syncin int* cpu cycle fifo read data/cmd reg. parity invert control cpld rm5271 cpu secondary cache clock gen act-5271sc simplified block diagram secondary 2mb masterclock validin*, extrqst*, cpumult reset = vccok, modeclk, modedata, coldreset*, reset* clks = tclock (1:0), rclock (1:0), masterout, syncout
aeroflex circuit technology act5271sc rev a 2/2/01 plainview ny (516) 694-6700 3 description the act-5271sc mcm consists of a qed rm5271 mips microprocessor with 2 mbyte of shared, write-through secondary cache. the mcm translates the r4400 style clocking, bus and modebit information to what the rm5271 expects. this is accomplished by means of a pll clock generator, a control cpld and an fpga based cycle fifo. pinout compatibility the act-5271sc was designed as a high performance upgrade replacement for the act-4431sc. the 280 lead flatpack package outline was retained and the pinout is compatible, with the following exceptions: the reassignment of twenty-six - 3.3 volt supply pins to a core voltage of 2.5 volts. vccp, the quiet pll supply is now 2.5 volts ten previously unused pins are now used for test modes and programmable device configuration. they are pins 171-175, 177, 183, 184, 195 and 196. they should remain no connects (nc) at the board level. certain special r4400 and act-4431sc function signals are not available and are no connects (nc) within the module substrate. these signals include io_in, io_out, status[7:0], ivderrb, ivdackb, 256k/1mb and faultb. the jtag port does not support complete boundary scan for the module. the jtag is used to initialize the cpld, which is one component in a chain of four. clocking and speeds the design is tailored towards replacing an act-4431sc device running with a 50 mhz masterclock (100 mhz pipeline clock) and a tclock /rclock divisor of 4 (25 mhz). in order to mitigate the speed limitation of a 25 mhz sysad bus, the act-5271sc utilizes a pll clock multiplier and cpu cycle fifo to run the rm5271 and the secondary cache connected to its sysad bus at a higher rate. for a 25 mhz external bus, the cache bus can run at 50 mhz or 75 mhz (2x or 3x). the rm5271 pipeline can be 2, 2.5 or 3 times the cache speed. specifically, the r4400 style masterclock is buffered and output as masterout. modeclock is a divide by 256 of masterout. masterclock is also divided by 2 to produce rclock, tclock and syncout. tclock and syncout are delayed from rclock by one buffer. syncin feeds the internal pll multiplier circuit which drives the rm5271?s sysclock and secondary cache rams at 2x or 3x. the rm5271?s pipeline frequency is then determined by the modebit settings generated by the internal cpld. the two secondary cache multiplier variations are selectable at module pin 195, for experimentation purposes. start up sequence the process begins with the sram based fpgas loading from an on-module serial eeprom when vddok is asserted. at the same time, the standard r4400 startup sequence is followed via modeclock, modein, coldresetb up to when resetb is deasserted the rm5271 will, in turn, start its initialization when the internal pll is locked and coldresetb is deasserted. the cpus resetb is released with resetb after checking to see that the fpgas have configured. the actual mode bit stream sent to the rm5271 is created by the internal cpld with a few pertinent bits stripped off the incoming stream: endianness and secondary cache enable. for this design, the interface xmitdatpat is fixed at dddd. cycle fifo the fifo, implemented in an fpga, accepts rm5271 cpu read and write cycle information direct from the cpu sysad bus at the cpu clock rate and retransmits it to the mcm sysad at the board?s clock rate. since the rm5271 does not normally output parity information on the address phase or the command bus, the parity information is added to the data captured from the cpu before it is entered into the fifo. for read data, if bad data is indicated by the command bus (bit 5), the parity output to the rm5271 is inverted for that item, and all remaining ones in the case of a burst. read cycles that hit in the secondary cache are not entered into the fifo. for additional detail information regarding the operation of the quantum effect devices (qed) riscmark ? rm5271sc ? , 64-bit superscalar microprocessor see the latest qed datasheet (revision 1.3 2/2000).
aeroflex circuit technology act5271sc rev a 2/2/01 plainview ny (516) 694-6700 4 sysad(63:0) sysadc(7:0) syscmd(8:0) syscmdp validin* validout* extrqst* release* rdrdy* wrrdy* system interface cpuint(5:0)* nmi* modeclock modein vccok coldreset* reset* jtdi jtdo jtms jtck initialization interface jtag interface 64 8 9 6 act-5271sc multichip module vcc vss power act-5271sc symbolic pinouts interrupt interface vccint tclock(1:0) rclock(1:0) masterclock masterout syncout syncin vccp vssp clock/control interface 2 2 26 40 68 case ground nc 32 280 lead cqfp
aeroflex circuit technology act5271sc rev a 2/2/01 plainview ny (516) 694-6700 5 absolute maximum rating 1 symbol parameter limits units v term terminal voltage with respect to v ss -0.5 2 to +3.9 v v in input voltage range -0.5 2 to vcc+0.5 v t bias case operating temperature under bias -55 to +125 c t stg storage temperature -65 to +150 c p d maximum power dissipation 10 w ? jc thermal resistance (junction to case) 2.5 c/w t l maximum lead temperature (10 seconds) 300 c note 1: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a st ress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note 2: v in minimum = -2.0v for pulse width less than 15ns. v in should not exceed 3.9 volts. recommended operating conditions symbol parameter min max units v ss supply ground 0 v v cc supply voltage 3.1 3.5 v v cc int supply voltage for rm5271 core 2.4 2.6 v v cc pquiet v cc for pll 2.4 2.6 v v ih high level input voltage 2.0 vcc + 0.5 v v il low level input voltage -0.5 +0.66 v t c case operating temperature -55 125 c note: v cc i/o should not exceed vccint by greater than 1.2v during the power-up sequence. note: applying a logic high state to any i/o pin before vccint becomes stable is not recommended. note: as specified in ieee 1149.1 (jtag), the jtms pin must be held low during reset to avoid entering jtag test mode. refer to the rm5200 family users manual, appendix f.
aeroflex circuit technology act5271sc rev a 2/2/01 plainview ny (516) 694-6700 6 pin descriptions system interface: sysad(63:0) i/o system address/data bus : a 64 bit address and data bus for communication between the processor and an external agent. sysadc(7:0) i/o system address/data check bus: an 8 bit bus containing parity check bits for the sysad bus during data cycles. syscmd(8:0) i/o system command/identifier bus : a 9 bit bus for command and data identifier transmission between the processor and an external agent. syscmdp i/o system command /data identifier bus parity : unused on input, zero on output. validin* i valid input: an external agent asserts validin* when it is driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. validout* o valid output : the processor asserts validout* when it is driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. extrqst* i external request: an external agent asserts extrqst* to request the use of the system interface. the processor grants the request by asserting release*. release* o release interface: in response to the assertion of extrqst*, the processor asserts release* to signal the requesting device that the system interface is available. rdrdy* i read ready: the external agent asserts rdrdy*to indicate that it can accept processor read. wrrdy* i write ready: an external agent asserts wrrdy* when it can accept a processor write request. clock/control interface: tclock(1:0) o transmit clocks : two identical transmit clocks that establish the system interface frequency. rclock(1:0) o receive clocks: two identical receive clocks that establish the system interface frequency. masterclock i master clock: master clock input supplied by system. masterout o master clock out : clock output buffered masterclock. syncout o synchronization clock out: synchronization clock output must be connected to syncin through an interconnect that models the interconnect between masterout, tclock, rclock, and the external agent. syncin i synchronization clock in : synchronization clock input. vccp i quiet vcc for the pll : quiet vcc for the internal phase lock loop. vssp i quiet vss for the pll : quiet vss for the internal phase lock loop.
aeroflex circuit technology act5271sc rev a 2/2/01 plainview ny (516) 694-6700 7 interrupt interface: these signals comprise the interface used by external agents to interrupt the rm5271 processor. cpuint(5:0) i interrupt : six general processor interrupts, bit-wise ored with bits 5:0 of the interrupt register. nmi* i nonmaskable interrupt : nonmaskable interrupt ored with bit 6 of the interrupt register. initialization interface: these signals comprise the interface by which an external agent initializes the rm5271 operating parameters. coldreset* i cold reset: this signal must be asserted for a power on reset or a cold reset. modeclock o boot mode clock: serial boot-mode data clock output at the masterclock frequency divided by 256. modein i boot mode data in: serial boot-mode data input. reset* i reset: this signal must be asserted for any reset sequence. it may be asserted synchronously or asynchronously for a cold reset, or synchronously to initate a warm reset. vccok i vcc is ok: when asserted, this signal tells the rm5271 that the 3.3 volt power supply has been above 3.15 volts for more than 100 milliseconds & will remain stable . assertion of vccok starts initialization sequence. jtag interface: jtdi i jtag data in: data is serial, scanned in thru this pin. jtck i jtag clock input: on the rising edge of jtck, both jtdi and jtms are sampled. jtdo o jtag data out: data is serial, scanned out thru this pin. jtms i jtag: test mode select. power: vccint i supply voltage for rm5271 core. vcc i supply voltage. vss i supply ground. pin descriptions
aeroflex circuit technology act5271sc rev a 2/2/01 plainview ny (516) 694-6700 8 act-5271sc microprocessor cqfp pinouts ? "f10" pin #functionpin #function pin #function 1tclock048 vss 95 vss 2 vss 49 vssp 96 sysad59 3 sysad45 50 vcc 97 **vccint 4 vss 51 nc 98 sysad27 5tclock152 vss 99 vss 6 vss 53 vccp 100 nc 7 sysad13 54 **vccint 101 vcc 8 vss 55 nc 102 sysad58 9 sysad14 56 vss 103 vss 10 vcc 57 nc 104 sysad26 11 jtms 58 vcc 105 vcc 12 **vccint 59 nc 106 nc 13 sysad46 60 **vccint 107 vss 14 vcc 61 sysadc7 108 sysad57 15 jtdo 62 vcc 109 **vccint 16 **vccint 63 sysadc3 110 sysad25 17 sysad15 64 **vccint 111 vss 18 vcc 65 vccok 112 nc 19 sysad47 66 vcc 113 vcc 20 vss 67 sysad63 114 sysad56 21 nc 68 vss 115 vss 22 vcc 69 masterout 116 sysad24 23 jtdi 70 vss 117 **vccint 24 vss 71 sysad31 118 nc 25 sysadc1 72 vcc 119 vss 26 **vccint 73 sysad30 120 sysadc6 27 sysadc5 74 vcc 121 vcc 28 vcc 75 sysad62 122 sysadc2 29 nc 76 vss 123 vss 30 **vccint 77 syncout 124 nmi* 31 nc 78 vss 125 vcc 32 vcc 79 sysad29 126 sysad55 33 jtck 80 vss 127 vss 34 vss 81 rclock1 128 sysad23 35 syncin 82 vss 129 **vccint 36 vss 83 sys ad61 130 release* 37 nc 84 vss 131 vss 38 vss 85 rclock0 132 sysad22 39 nc 86 vss 133 vcc 40 vss 87 vcc 134 sysad54 41 masterclock 88 reset* 135 vss 42 vss 89 **vccint 136 modein 43 nc 90 sysad60 137 **vccint 44 vcc 91 vss 138 rdrdy* 45 nc 92 sysad28 139 vss 46 **vccint 93 vcc 140 sysad53 47 nc 94 coldreset* 141 sysad21 ** these 26 vccint pins may be 1.8v in future higher performance modules.
aeroflex circuit technology act5271sc rev a 2/2/01 plainview ny (516) 694-6700 9 pin #function pin #functionpin #function 142 vss 189 cpuint4 236 vss 143 extrqst* 190 **vccint 237 syscmd3 144 vcc 191 cpuint5 238 vcc 145 sysad52 192 vss 239 sysad7 146 vss 193 **vccint 240 vss 147 validout* 194 nc (256k/1mb) 241 sysad39 148 vcc 195 nc (cpumult) 242 vcc 149 sysad20 196 nc (prog_fpga) 243 syscmd4 150 vss 197 nc 244 vss 151 sysad19 198 case ground 245 sysadc0 152 **vccint 199 vss 246 vcc 153 sysad51 200 sysad32 247 sysadc4 154 vss 201 vcc 248 vss 155 validin* 202 sysad0 249 syscmd5 156 vcc 203 vss 250 **vccint 157 sysad18 204 sysad1 251 sysad8 158 vss 205 **vccint 252 vss 159 sysad50 206 sysad33 253 sysad40 160 **vccint 207 vss 254 vcc 161 cpuint0 208 sysad34 255 syscmd6 162 vss 209 vcc 256 vss 163 sysad49 210 sysad2 257 sysad9 164 vcc 211 vss 258 **vccint 165 sysad17 212 syscmd0 259 sysad41 166 vss 213 **vccint 260 vss 167 sysad16 214 sysad35 261 syscmd7 168 vcc 215 vss 262 vcc 169 sysad48 216 sysad3 263 sysad10 170 vss 217 vcc 264 vss 171 nc (sp_ser_en) 218 sysad4 265 sysad42 172 nc (sp_oe) 219 vss 266 **vccint 173 nc (sp_ce) 220 syscmd1 267 syscmd8 174 nc (sp_ccck) 221 vcc 268 vss 175 nc (sp_data) 222 sysad36 269 sysad11 176 nc 223 vss 270 vcc 177 nc (isp_en) 224 syscmd2 271 sysad43 178 vss 225 **vccint 272 vss 179 cpuint1 226 sysad5 273 syscmdp 180 vcc 227 sysad37 274 **vccint 181 cpuint2 228 vss 275 sysad12 182 vss 229 modeclock 276 vss 183 nc (in_p5064) 230 vcc 277 sysad44 184 nc (dcd_sel) 231 wrrdy* 278 vcc 185 cpuint3 232 vss 279 nc 186 nc 233 sysad6 280 vss 187 nc 234 **vccint 188 vss 235 sysad38 act-5271sc microprocessor cqfp pinouts ? "f10" ** these 26 vccint pins may be 1.8v in future higher performance modules.
aeroflex circuit technology act5271sc rev a 2/2/01 plainview ny (516) 694-6700 10 86 leads @ .025 spacing 1.768 max @ .025 spacing .012 pin 226 pin 141 pin 227 pin 140 pin 87 pin 86 pin 280 pin 1 .175 max .072 .010 2.525 max act-5271sc package information ? "f10" ? cqfp 280 leads note : outside ceramic tie bars not shown for clarity. contact factory for details 2.125 54 leads 1.325 .009 .008 .005 (dimensions are in inches)
aeroflex circuit technology act5271sc rev a 2/2/01 plainview ny (516) 694-6700 11 sample ordering information part number screening speed (mhz) package act-5271sc-150f10c commercial temperature 150 280 lead cqfp ACT-5271SC-150F10I industrial temperature act-5271sc-150f 10t military te mperature act-5271sc-150f10m military screening aeroflex circuit technology 35 south service road plainview new york 11803 telephone: (516) 694-6700 fax: (516) 694-6715 toll free inquiries: (800) 843-1553 www.aeroflex.com e-mail: sales-mcm@aeroflex.com circuit technology part number breakdown act? 5271 sc ? 150 f10 m aeroflex circuit technology base processor type 150 = 150mhz cache style package type & size c = commercial temp, 0c to +70c i = industrial temp, -40c to +85c t = military temp, -55c to +125c m = military temp, -55c to +125c, screened * screening * screened to the individual test methods of mil-std-883 sc = secondary cache maximum pipeline freq. surface mount package f10 = 2.525" x 1.768" x 280 lead cqfp this document may, wholly or partially, be subject to change without notice. aeroflex reserves the right to make changes to its products or specifications at any time without notice. aeroflex will not be held responsible for any damage to the user or any property that may result from accidents, misuse, or any other causes arising during operation of the user's unit. aeroflex does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a aeroflex product. the company makes no representations that the circuitry described herein is free from patent infringement or other rights of third parties, which ma y result from its use. no license is granted by implication or otherwise under any patent, patent rights, or other rights, of aeroflex. the qed logo and riscmark are trademarks of pmc-sierra, inc. mips is a registered trademark of mips technologies, inc. all other trademarks are the respective property of the trademark hol ders.

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