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1 of 42 may 25, 2004 ? 2002 integrated device technology, inc. dsc 6053 idt and the idt logo are trademarks of integrated device technology, inc. features list rc32300 32-bit microprocessor ? enhanced mips-ii isa ? enhanced mips-iv cache prefetch instruction ? dsp instructions ? mmu with 16-entry tlb ? 8kb instruction cache, 2-way set associative ? 2kb data cache, 2-way set associative ? per line cache locking ? write-through and write-back cache management ? debug interface through the ejtag port ? big or little endian support interrupt controller ? allows status of each interrupt to be read and masked uarts ? two 16550 compatible uarts ? baud rate support up to 1.5 mb/s counter/timers ? three general purpose 32-bit counter/timers general purpose i/o pins (gpiop) ? 32 individually programmable pins: each pin programmable as input, output, or alternate function, input can be an interrupt or nmi source, input can also be active high or active low ? 4 additional, auxiliary gpio pins can be configured as input or output sdram controller ? 2 memory banks, non-interleaved, 512 mb total ? 32-bit wide data path ? supports 4-bit, 8-bit, and 16-bit wide sdram chips ? sodimm support ? stays on page between transfers ? automatic refresh generation peripheral device controller ? 26-bit address bus ? 32-bit data bus with variable width support of 8-,16-, or 32-bits ? 8-bit boot rom support ? 6 banks available, up to 64mb per bank ? supports flash rom, prom, sram, dual-port memory, and peripheral devices ? supports external wait-state generation, intel or motorola style ? write protect capability ? direct control of optional external data transceivers system integrity ? programmable system watchdog timer resets system on time- out ? programmable bus transaction times memory and peripheral transactions and generates a warm reset on time-out dma ? 14 dma channels ? services on-chip and external peripherals ? supports memory-to-memory, memory-to-i/o, and i/o-to-i/o transfers ? supports flexible descriptor based operation and chaining via linked lists of records (scatter / gather capability) ? supports unaligned transfers block diagram ejtag mmu d. cache i. cache rc32300 cpu core ice interrupt controller 3 counter timers watchdog timer 10/100 ethernet interface usb interface 16 channel dma controller arbiter ext. bus master sdram & device controller 2 uarts (16550) gpio interface atm interface memory & peripheral bus ch. 1 ch. 2 serial channels gpio pins utopia 1 / 2 : : 79rc32351 idt tm interprise tm integrated communications processor
2 of 42 may 25, 2004 idt 79rc32351 ? supports burst transfers usb ? revision 1.1 compliant ? usb slave device controller ? supports a 6 th usb endpoint ? full speed operation at 12 mb/s ? supports control, interrupt, bulk and isochronous endpoints ? supports usb remote wakeup ? integrated usb transceiver ejtag ? run-time mode provides a standard jtag interface ? real-time mode provides additional pins for real-time trace information ethernet ? full duplex support for 10 and 100 mb/s ethernet ? ieee 802.3u compatible media independent interface (mii) with serial management interface ? ieee 802.3u auto-negotiation for automatic speed selection ? flexible address filtering modes ? 64-entry hash table based multicast address filtering atm sar ? can be configured as one utopia level 1 interface or 1 utopia level 2 interface with 2 address lines (3 phys max) ? supports 25mb/s and faster atm ? supports utopia data path interface operation at speeds up to 33 mhz ? supports standard 53-byte atm cells ? performs hec generation and checking ? cell processing discards short cells and clips long cells ? 16 cells worth of buffering ? utopia modes: 8 cell input buffer and 8 cell output buffer ? hardware support for crc-32 generation and checking for aal5 ? hardware support for crc-10 generation and checking ? virtual caching receive mechanism supports reception of any length packet without cpu intervention on up to eight simulta- neously active receive channels ? frame mode transmit mechanism supports transmission of any length packet without cpu intervention system features ? jtag interface (ieee std. 1149.1 compatible) ? 208 pin pqfp package ? 2.5v core supply and 3.3v i/o supply ? up to 133 mhz pipeline frequency and up to 66 mhz bus frequency figure 2 example of xdsl residential gateway using rc32351 ethernet transceiver mii i/f dma channels usb timers uart interrupt ctl rc32300 cpu core data buffers sdram ctl memory & i/o controller at m i / f ethernet mac ethernet to pc clock sdram memory & i/o transmission convergence data pump afe usb to pc debug port 32-bit data bus
3 of 42 may 25, 2004 idt 79rc32351 device overview the rc32351 is a ?system on a chip? which contains a high perfor- mance 32-bit microprocessor. the microprocessor core is used exten- sively at the heart of the device to implement the most needed functionalities in software with minimal hardware support. the high performance microprocessor handles diverse general computing tasks and specific application tasks that would have required dedicated hard- ware. specific application tasks implemented in software can include routing functions, fire wall functions, modem emulation, atm sar emulation, and others. the rc32351 meets the requirements of various embedded commu- nications and digital consumer applicat ions. it is a single chip solution that incorporates most of the generic system functionalities and applica- tion specific interfaces that enable rapid time to market, very low cost systems, simplified designs, and reduced board real estate. cpu execution core the rc32351 is built around the rc32300 32-bit high performance microprocessor core. the rc32300 implements the enhanced mips-ii isa and helps meet the real-time goals and maximize throughput of communications and consumer systems by providing capabilities such as a prefetch instruction, multiple dsp instructions, and cache locking. the dsp instructions enable the rc32300 to implement 33.6 and 56kbps modem functionality in software, removing the need for external dedicated hardware. cache locking guarantees real-time performance by holding critical dsp code and parameters in the cache for immediate availability. the microprocessor also implements an on-chip mmu with a tlb, making the it fully compliant with the requirements of real time operating systems. memory and io controller the rc32351 incorporates a flexible memory and peripheral device controller providing support for sdram, flash rom, sram, dual-port memory, and other i/o devices. it can interface directly to 8-bit boot rom for a very low cost system implementation. it enables access to high bandwidth external memory (200 mb/sec peak) at very low system costs. it also offers various trade-offs in cost / performance for the main memory architecture. the timers implemented on the rc32351 satisfy the requirements of most rtos. dma controller the dma controller off-loads the cpu core from moving data among the on-chip interfaces, external peripherals, and memory. the dma controller supports scatter / gather dma with no alignment restrictions, appropriate for communications and graphics systems. ethernet interface the rc32351 contains an on-chip ethernet mac capable of 10 and 100 mbps line interface with an mii interface. it supports up to 4 mac addresses. in a soho router, the high performance rc32300 cpu core routes the data between the ethernet and the atm interface. in other applications, such as high speed modems, the ethernet interface can be used to connect to the pc. usb device interface the rc32351 includes the industry standard usb device interface to enable consumer appliances to directly connect to the pc. atm sar the rc32351 includes a configurable atm sar that supports a utopia level 1 or a utopia level 2 interface. the atm sar is imple- mented as a hybrid between softwar e and hardware. a hardware block provides the necessary low level blocks (like crc generation and checking and cell buffering) while the software is used for higher level saring functions. in xdsl modem applications, the utopia port inter- faces directly to an xdsl chip set. in soho routers or in a line card for a layer 3 switch, it provides access to an atm network. enhanced jtag interface for ice for low-cost in-circuit emulation (ice), the rc32300 cpu core includes an enhanced jtag (ejtag) interface. this interface consists of two operation modes: run-time mode and real-time mode. the run-time mode provides a standard jtag interface for on-chip debugging, and the real-time mode prov ides additional status pins? pcst[2:0]?which are used in conjunction with the jtag pins for real- time trace information at the processor internal clock or any division of the pipeline clock.
4 of 42 may 25, 2004 idt 79rc32351 thermal considerations the rc32351 consumes less than 1.5 w peak power and is guaran- teed in an ambient temperature range of 0 to + 70 c (commercial). revision history january 7, 2002 : initial publication. may 20, 2002 : added values (in place of tbd) to table 18, power consumption. september 19, 2002 : added coldrstn trise1 parameter to table 5, reset and system ac timing characteristics. december 6, 2002 : in features section, changed uart speed from 115 kb/s to 1.5 mb/s. december 17, 2002 : added v oh parameter to table 16, dc elec- trical characteristics. may 25, 2004 : in table 7, signals miirxclk and miitxclk, the min and max values for 10 mbps thigh1/tlow1 were changed to 140 and 260 respectively and the min and max values for 100 mbps thigh1/ tlow1 were changed to 14.0 and 26.0 respectively.
5 of 42 may 25, 2004 idt 79rc32351 pin description table the following table lists the functions of the pins provided on the rc32351. some of the functions listed may be multiplexed on to the same pin. to define the active polarity of a signal, a suffix will be us ed. signals ending with an ?n? should be interpreted as being act ive, or asserted, when at a logic zero (low) level. all other signal s (including clocks, buses and select lines ) will be interpreted as being active, or asserted when at a logic one (high) level. note: the input pads of the rc32351 do not contain internal pull-ups or pull-downs. unused inputs should be tied off to appropriate l evels. this is especially critical for unused control signal inputs (such as brn) which, if left floating, could adversely affect the rc32351?s opera- tion. also, any input pin left floating can c ause a slight increase in power consumption. name type i/o type description system clkp i input system clock input. this is the system master clock input. the riscore 32300 pipeline frequency is a multiple (x2, x3, or x4) of this clock frequency. all other logic runs at this frequency or less. coldrstn i sti 1 cold reset. the assertion of this signal low initiates a cold reset. this causes the rc32351 state to be initialized, boot configuration to be loaded, and the internal processor pll to lock onto the system clock (clkp). rstn i/o low drive with sti reset. this bidirectional signal is either driven low or tri-stated, an external pull-up is required to supply the high state. the rc32351 drives rstn low during a reset (to inform the external system that a reset is taking place) and then tri-states it. the external system can drive rstn low to initiate a warm reset, and then should tri-state it. sysclkp o high drive system clock output. this is a buffered and delayed version of the system clock input (clkp). all sdram transactions are synchronous to this clock. this pin should be externally connected to the sdrams and to the rc32351 sdclkinp pin (sdram clock input). memory and peripheral bus maddr[25:0] o [21:0] high drive [25:22] low drive with sti memory address bus. 26-bit address bus for memory and peripheral accesses. maddr[20:17] are used for the sodimm data mask enables if sodimm mode is selected. maddr[22] primary function: general purpose i/o, gpiop[27]. maddr[23] primary function: general purpose i/o, gpiop[28]. maddr[24] primary function: general purpose i/o, gpiop[29]. maddr[25] primary function: general purpose i/o, gpiop[30]. mdata[31:0] i/o high drive memory data bus. 32-bit data bus for memory and peripheral accesses. bdirn o high drive external buffer direction. external transceiver direction control for the memory and peripheral data bus, mdata[31:0]. it is asserted low during any read transaction, and remains high during write transactions. boen[1:0] o high drive external buffer output enable. these signals provide two output enable controls for external data bus transceivers on the memory and peripheral data bus, mdata. boen[0] is asserted low during external device read transactions. boen[1] is asserted low during sdram read transactions. brn i sti external bus request. this signal is asserted low by an external master device to request ownership of the memory and peripheral bus. bgn o low drive external bus grant. this signal is asserted low by rc32351 to indicate that rc32351 has relinquished ownership of the local memory and peripheral bus to an external master. waitackn i sti wait or transfer acknowledge. when configured as wait, this signal is asserted low during a memory and peripheral device bus transaction to extend the bus cycle. when configured as transfer acknowledge, this signal is asserted low dur- ing a memory and peripheral device bus transaction to signal the completion of the transaction. csn[5:0] o [3:0] high drive [5:4] low drive device chip select. these signals are used to select an external device on the memory and peripheral bus during device transactions. each bit is asserted low during an access to the selected external device. csn[4] primary function: general purpose i/o, gpiop[16]. csn[5] primary function: general purpose i/o, gpiop[17]. table 1 pin descriptions (part 1 of 7)
6 of 42 may 25, 2004 idt 79rc32351 rwn o high drive read or write. this signal indicates if the transaction on the memory and peripheral bus is a read transaction or a write transaction. a high level indicates a read from an external device, a low level indicates a write to an external device. oen o high drive output enable. this signal is asserted low when data should be driven by an external device during device read transac- tions on the memory and peripheral bus. bwen[3:0] o high drive sdram byte enable mask or memory and i/o byte write enables. these signals are used as data input/output masks during sdram transactions and as byte write enable signals during device controller transactions on the memory and peripheral bus. they are active low. bwen[0] corresponds to byte lane mdata[7:0]. bwen[1] corresponds to byte lane mdata[15:8]. bwen[2] corresponds to byte lane mdata[23:16]. bwen[3] corresponds to byte lane mdata[31:24]. sdcsn[1:0] o high drive sdram chip select. these signals are used to select the sdram device on the memory and peripheral bus. each bit is asserted low during an access to the selected sdram. rasn o high drive sdram row address strobe . the row address strobe asserted low during memory and peripheral bus sdram transac- tions. casn o high drive sdram column address strobe. the column address strobe asserted low during memory and peripheral bus sdram transactions. sdwen o high drive sdram write enable. asserted low during memory and peripheral bus sdram write transactions. ckenp o low drive sdram clock enable. asserted high during active sdram clock cycles. primary function: general purpose i/o, gpiop[21]. sdclkinp i sti sdram clock input. this clock input is a delayed version of sysclkp. sdram read data is sampled into the rc32351 on the rising edge of this clock. atm interface atminp[11:0] i sti atm phy inputs. these pins are the inputs for the atm interface. atmiop[1:0] i/o low drive with sti atm phy bidirectional signals. these pins are the bidirectional pins for the atm interface. atmoutp[9:0] o low drive atm phy outputs. these pins are the outputs for the atm interface. txaddr[1:0] o low drive atm transmit address [1:0] . 2-bit address bus used for transmission in utopia-2 mode. txaddr[0] primary function: general purpose i/o, gpiop[22]. txaddr[1] primary function: general purpose i/o, gpiop[23]. rxaddr[1:0] o low drive atm receive address [1:0] . 2-bit address bus for receiving in utopia-2 mode. rxaddr[0] primary function: general purpose i/o, gpiop[24]. rxaddr[1] primary function: general purpose i/o, gpiop[25]. general purpose input/output gpiop[0] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: uart channel 0 serial output, u0soutp. gpiop[1] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: uart channel 0 serial input, u0sinp. gpiop[2] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function: uart channel 0 ring indicator, u0rin. 2nd alternate function: jtag boundary scan tap controller reset, jtag_trst_n. gpiop[3] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: uart channel 0 data carrier detect, u0dcrn. gpiop[4] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function: uart channel 0 data terminal ready, u0dtrn. 2nd alternate function: cpu or dma transaction indicator, cpup. name type i/o type description table 1 pin descriptions (part 2 of 7)
7 of 42 may 25, 2004 idt 79rc32351 gpiop[5] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: uart channel 0 data set ready, u0dsrn. gpiop[6] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: uart channel 0 request to send, u0rtsn. gpiop[7] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: uart channel 0 clear to send, u0ctsn. gpiop[8] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function: uart channel 1 serial output, u1soutp. 2nd alternate function: active dma channel code, dmap[3]. gpiop[9] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function: uart channel 1 serial input, u1sinp. 2nd alternate function: active dma channel code, dmap[2]. gpiop[10] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function: uart channel 1 data terminal ready, u1dtrn. 2nd alternate function: ice pc trace status, ejtag_pcst[0]. gpiop[11] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function: uart channel 1 data set ready, u1dsrn. 2nd alternate function: ice pc trace status, ejtag_pcst[1]. gpiop[12] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function: uart channel 1 request to send, u1rtsn. 2nd alternate function: ice pc trace status, ejtag_pcst[2]. gpiop[13] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function: uart channel 1 clear to send, u1ctsn. 2nd alternate function: ice pc trace clock, ejtag_dclk. gpiop[14] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. gpiop[15] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. gpiop[16] i/o high drive general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: memory and peripheral bus chip select, csn[4]. gpiop[17] i/o high drive general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: memory and peripheral bus chip select, csn[5]. gpiop[18] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: external dma device request, dmareqn. gpiop[19] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: external dma device done, dmadonen. gpiop[20] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: usb start of frame, usbsof. gpiop[21] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: sdram clock enable ckenp. gpiop[22] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: atm trans mit phy address, txaddr[0]. gpiop[23] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function: atm transmit phy address, txaddr[1]. 2nd alternate function: active dma channel code, dmap[0]. name type i/o type description table 1 pin descriptions (part 3 of 7)
8 of 42 may 25, 2004 idt 79rc32351 gpiop[24] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: atm receive phy address, rxaddr[0]. gpiop[25] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function: atm receive phy address, rxaddr[1]. 2nd alternate function: active dma channel code, dmap[1]. gpiop[26] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. gpiop[27] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: memory and peripheral bus address, maddr[22]. gpiop[28] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: memory and peripheral bus address, maddr[23]. gpiop[29] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: memory and peripheral bus address, maddr[24]. gpiop[30] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function: memory and peripheral bus address, maddr[25]. gpiop[31] i/o low drive with sti general purpose i/o. this pin can be configured as a general purpose i/o pin. 1st alternate function: dma finished, dmafin. 2nd alternate function: ejtag/ice reset, ejtag_trst_n. gpiop[32] i/o high drive general purpose i/o. this pin can be configured as an auxiliary general purpose i/o pin. gpiop[33] i/o low drive with sti general purpose i/o. this pin can be configured as an auxiliary general purpose i/o pin. gpiop[34] i/o high drive general purpose i/o. this pin can be configured as an auxiliary general purpose i/o pin. gpiop[35] i/o low drive with sti general purpose i/o. this pin can be configured as an auxiliary general purpose i/o pin. dma dmafin o low external dma finished. this signal is asserted low by the rc32351 when the number of bytes specified in the dma descriptor have been transferred to or from an external device. primary function: general purpose i/o, gpiop[31]. at re set, this pin defaults to primary function gpiop[31]. 2nd alternate function: ejtag_trst_n. dmareqn i sti external dma device request . the external dma device asserts this pin low to request dma service. primary function: general purpose i/o, gpiop[18]. at reset, this pin defaults to primary function gpiop[18]. dmadonen i sti external dma device done . the external dma device asserts this signal low to inform the rc32351 that it is done with the current dma transaction. primary function: general purpose i/o, gpiop[19]. at reset, this pin defaults to primary function gpiop[19]. usb usbclkp i sti usb clock. 48 mhz clock input used as time base for the usb interface. usbdn i/o usb usb d- data line. this is the negative differential usb data signal. usbdp i/o usb usb d+ data line. this is the positive differential usb data signal. usbsof o low drive usb start of frame. primary function: general purpose i/o, gpiop[20]. at re set, this pin defaults to primary function gpiop[20]. ethernet miicolp i sti mii collision detected. this signal is asserted by the ethernet phy when a collision is detected. miicrsp i sti mii carrier sense. this signal is asserted by the ethernet phy when either the transmit or receive medium is not idle. miimdcp o low drive mii management data clock. this signal is used as a timing reference for transmission of data on the management inter- face. name type i/o type description table 1 pin descriptions (part 4 of 7)
9 of 42 may 25, 2004 idt 79rc32351 miimdiop i/o low drive with sti mii management data. this bidirectional signal is used to transfer data between the station management entity and the ethernet phy. miirxclkp i sti mii receive clock. this clock is a continuous clock that provides a timing reference for the reception of data. miirxdp[3:0] i sti mii receive data. this nibble wide data bus contains the data received by the ethernet phy. miirxdvp i sti mii receive data valid. the assertion of this signal indicates that valid receive data is in the mii receive data bus. miirxerp i sti mii receive error. the assertion of this signal indicates that an error was detected somewhere in the ethernet frame cur- rently being sent in the mii receive data bus. miitxclkp i sti mii transmit clock. this clock is a continuous clock that provides a timing reference for the transfer of transmit data. miitxdp[3:0] o low drive mii transmit data. this nibble wide data bus contains the data to be transmitted. miitxenp o low drive mii transmit enable. the assertion of this signal indicates that data is present on the mii for transmission. miitxerp o low drive mii transmit coding error. when this signal is asserted together with miitxenp, the ethernet phy will transmit symbols which are not valid data or delimiters. ejtag jtag_tck i sti jtag clock. this is an input test clock, used to shift data into or out of the boundary scan logic. this signal requires an external resistor, listed in table 14. jtag_tdi i sti jtag data input. this is the serial data shifted into the boundary scan logic. this signal requires an external resistor, listed in table 14. this is also used to input ejtag_dintn during ejtag/ice mode. ejtag_dintn is an interrupt to switch the pc trace mode off. jtag_tdo o low drive jtag data output. this is the serial data shifted out from the boundary scan logic. when no data is being shifted out, this signal is tri-stated. this signal requires an external resistor, listed in table 14. this is also used to output the ejtag_tpc during ejtag/ice mode. ejtag_tpc is the non-sequential program counter output. jtag_tms i sti jtag mode select . this input signal is decoded by the tap controller to control test operation. this signal requires an external resistor, listed in table 14. ejtag_pcst[0] o low drive pc trace status. this bus gives the pc trace status information during ejtag/ice mode. ejtag/ice enable is selected during reset using the boot configuration and overrides the selection of the primary and alternate functions. this signal requires an external resistor, listed in table 14. primary function: general purpose i/o, gpiop[10]. 1st alternate function: uart channel 1 data terminal ready, u1dtrn. ejtag_pcst[1] o low drive pc trace status. this bus gives the pc trace status information during ejtag/ice mode. ejtag/ice enable is selected during reset using the boot configuration and overrides the selection of the primary and alternate functions. this signal requires an external resistor, listed in table 14. primary function: general purpose i/o, gpiop[11]. at re set, this pin defaults to primary function gpiop[11]. 1st alternate function: uart channel 1 data set ready, u1dsrn. ejtag_pcst[2] o low drive pc trace status. this bus gives the pc trace status information during ejtag/ice mode. ejtag/ice enable is selected during reset using the boot configuration and overrides the selection of the primary and alternate functions. this signal requires an external resistor, listed in table 14. primary function: general purpose i/o, gpiop[12]. 1st alternate function: uart channel 1 request to send, u1rtsn. ejtag_dclk o low drive pc trace clock. this is used to capture address and data during ejtag/ice mode. ejtag/ice enable is selected during reset using the boot configuration and overrides the selection of the primary and alternate functions. this signal requires an external resistor, listed in table 14. primary function: general purpose i/o, gpiop[13]. 1st alternate function: uart channel 1 clear to send, u1ctsn. name type i/o type description table 1 pin descriptions (part 5 of 7)
10 of 42 may 25, 2004 idt 79rc32351 ejtag_trst_n i sti ejtag test reset. ejtag_trst_n is an active-low signal for asynchronous reset of only the ejtag/ice controller. ejtag_trst_n requires an external pull-up on the board. ejtag/ice enable is selected during reset using the boot con- figuration and overrides the selection of the primary and alternate functions. this signal requires an external resistor, liste d in table 14. primary: general purpose i/o, gpiop[31] 1st alternate function: dma finished output, dmafin. jtag_trst_n i sti jtag test reset. jtag_trst_n is an active-low signal for asynchronous reset of only the jtag boundary scan control- ler. jtag_trst_n requires an external pull-down on the board that will hold the jtag boundary scan controller in reset when not in use if selected. jtag reset enable is selected during reset using the boot configuration and overrides the selection of the primary and alternate functions. primary function: general purpose i/o, gpiop[2]. 1st alternate function: uart channel 0 ring indicator, u0rin. debug instp o low drive instruction or data indicator . this signal is driven high during cpu instruction fetches and low during cpu data transac- tions on the memory and peripheral bus. cpup o low drive cpu or dma transaction indicator . this signal is driven high during cpu transactions and low during dma transactions on the memory and peripheral bus if cpu/dma transaction indicator enable is enabled. cpu/dma status mode enable is selected during reset using the boot configuration and overrides the selection of the primary and alternate functions. primary function: general purpose i/o, gpiop[4]. 1st alternate function: uart channel 0 data terminal ready u0dtrn. dmap[0] o low drive active dma channel code . dma debug enable is selected during reset using the boot configuration and overrides the selection of the primary and alternate functions. primary function: general purpose i/o, gpiop[23]. 1st alternate function: txaddr[1]. dmap[1] o low drive active dma channel code . dma debug enable is selected during reset using the boot configuration and overrides the selection of the primary and alternate functions. primary function: general purpose i/o, gpiop[25]. 1st alternate function: rxaddr[1]. dmap[2] o low drive active dma channel code . dma debug enable is selected during reset using the boot configuration and overrides the selection of the primary and alternate functions. primary function: general purpose i/o, gpiop[9]. 1st alternate function: u1sinp. dmap[3] o low drive active dma channel code . dma debug enable is selected during reset using the boot configuration and overrides the selection of the primary and alternate functions. primary function: general purpose i/o, gpiop[8]. 1st alternate function: u1soutp. uart u0soutp i sti uart channel 0 serial transmit. primary function: general purpose i/o, gpiop[0]. at re set, this pin defaults to primary function gpiop[0]. u0sinp i sti uart channel 0 serial receive. primary function: general purpose i/o, gpiop[1]. at re set, this pin defaults to primary function gpiop[1]. u0rin i sti uart channel 0 ring indicator. primary function: general purpose i/o, gpiop[2]. at reset, this pin defaults to primary function gpiop[2] if jtag reset enable is not selected during reset using the boot configuration. 2nd alternate function: jtag boundary scan reset, jtag_trst_n. u0dcrn i sti uart channel 0 data carrier detect. primary function: general purpose i/o, gpiop[3]. at re set, this pin defaults to primary function gpiop[3]. name type i/o type description table 1 pin descriptions (part 6 of 7)
11 of 42 may 25, 2004 idt 79rc32351 boot configuration vector the boot configuration vector is read into the rc32351 during cold reset. the vector defines parameters in the rc32351 that are essential to oper- ation when cold reset is complete. the encoding of boot configuration vector is described in table 2, and the vector input is illustrated in figure 6. u0dtrn o low drive uart channel 0 data terminal ready. primary function: general purpose i/o, gpiop[4]. at reset, this pin defaults to primary function gpiop[4] if cpu/dma sta- tus mode enable is not selected during reset using the boot configuration. 2nd alternate function: cpu or dma transaction indicator, cpup. u0dsrn i sti uart channel 0 data set ready. primary function: general purpose i/o, gpiop[5]. at re set, this pin defaults to primary function gpiop[5]. u0rtsn o low drive uart channel 0 request to send. primary function: general purpose i/o, gpiop[6]. at re set, this pin defaults to primary function gpiop[6]. u0ctsn i sti uart channel 0 clear to send. primary function: general purpose i/o, gpiop[7]. at re set, this pin defaults to primary function gpiop[7]. u0soutp o low drive uart channel 1 serial transmit. primary function: general purpose i/o, gpiop[8]. at reset, this pin defaults to primary function gpiop[8] if dma debug enable is not selected during reset using the boot configuration. 2nd alternate function: dma channel, dmap[3]. u1sinp i sti uart channel 1 serial receive. primary function: general purpose i/o, gpiop[9]. at reset, this pin defaults to primary function gpiop[9] if dma debug enable is not selected during reset using the boot configuration. 2nd alternate function: dma channel, dmap[2]. u1dtrn o low drive uart channel 1 data terminal ready. primary function: general purpose i/o, gpiop[10]. at reset, this pin defaults to primary function gpiop[10] if ice interface enable is not selected during reset using the boot configuration. alternate function: pc trace status bit 0, ejtag_pcst[0]. u1dsrn i sti uart channel 1 data set ready. primary function: general purpose i/o, gpiop[11]. at reset, this pin defaults to primary function gpiop[11] if ice interface enable is not selected during reset using the boot configuration. 2nd alternate function: pc trace status bit 1, ejtag_pcst[1]. u1rtsn o low drive uart channel 1 request to send. primary function: general purpose i/o, gpiop[12]. at reset, this pin defaults to primary function gpiop[12] if ice interface enable is not selected during reset using the boot configuration. 2nd alternate function: pc trace status bit 2, ejtag_pcst[2]. u1ctsn i sti uart channel 1 clear to send. primary function: general purpose i/o, gpiop[13]. at reset, this pin defaults to primary function gpiop[13] if ice interface enable is not selected during reset using the boot configuration. 2nd alternate function: pc trace clock, ejtag_dclk. 1. schmitt trigger input. name type i/o type description table 1 pin descriptions (part 7 of 7)
12 of 42 may 25, 2004 idt 79rc32351 signal name/description mdata[2:0] clock multiplier . this field specifies the value by which the system clock (clkp) is multiplied internally to generate the cpu pipeline clock. 0x0 - multiply by 2 0x1 - multiply by 3 0x2 - multiply by 4 0x3 - reserved 0x4 - reserved 0x5 - reserved 0x6 - reserved 0x7 - reserved mdata[3] endian. this bit specifies the endianness of rc32351. 0x0 - little endian 0x1 - big endian mdata[4] reserved. must be set to 0. mdata[5] debug boot mode . when this bit is set, the rc32351 begins executing from address 0xff20_0200 rather than 0xbfc0_0000 following a reset. 0x0 - regular mode (processor begins executing at 0xbfc0_0000) 0x1 - debug boot mode (processor begins executing at 0xff20_0200) mdata[7:6] boot device width . this field specifies the width of the boot device. 0x0 - 8-bit boot device width 0x1 - 16-bit boot device width 0x2 - 32-bit boot device width 0x3 - reserved mdata[8] ejtag/ice interface enable . when this bit is set, alternate 2 pin functions ejtag_pcst[2:0], ejtag_dclk, and ejtag_trst_n are selected. 0x0 - gpiop[31, 13:10] pins behaves as gpiop 0x1 - gpiop[31] pin behaves as ejtag_trst_n, gpiop[12:10] pins behave as ejtag_pcst[2:0], and gpiop[13] pin behaves as ejtag_dclk mdata[9] fast reset . when this bit is set, rc32351 drives rstn for 64 clock cycles, used during test only. clear this bit for normal operation. 0x0 - normal reset: rc32351 drives rstn for minimum of 4096 clock cycles 0x1 - fast reset: rc32351 drives rstn for 64 clock cycles (test only) mdata[10] dma debug enable . when this bit is set, alternate 2 pin function, dmap is selected. dmap provides the dma channel number during memory and peripheral bus dma transactions. 0x0 - gpiop[8, 9, 25, 23] pins behave as gpiop 0x1 - gpiop[8, 9, 25, 23] pins behave as dmap[3:0] mdata[11] hold sysclkp constant . for systems that do not require a sysclkp output and can instead use clkp, setting th is bit to a one causes the sysclkp output to be held at a constant level. this may be used to reduce emi. 0x0 - allow sysclkp to toggle 0x1 - hold sysclkp constant mdata[12] jtag boundary scan reset enable . when this bit is set, alternate 2 pin function, jtag_trst_n is selected. 0x0 - gpiop[2] pin behaves as gpiop 0x1 - gpiop[2] pin behaves as jtag_trst_n mdata[13] cpu / dma transaction indicator enable . when this bit is set, alternate 2 pin function, cpup is selected. 0x0 - gpiop[4] pin behaves as gpiop 0x1 - gpiop[4] pin behaves as cpup mdata[15:14] reserved . these pins must be driven low during boot configuration. table 2 boot configuration vector encoding
13 of 42 may 25, 2004 idt 79rc32351 logic diagram the following logic diagram shows the primary pin functions of the rc32351. figure 3 logic diagram 22 32 4 maddr[21:0] mdata[31:0] bwen[3:0] oen rwn 4 csn[3:0] waitackn brn bgn rasn casn sdwen 2 sdcsn[1:0] 2 boen[1:0] bdirn 12 2 10 atminp[11:0] atmiop[1:0] atmoutp[9:0] 36 gpiop[35:0] usbdp usbdn usbclkp miirxdp[3:0] 4 miirxdvp miirxerp miirxclkp miicrsp miicolp miitxdp[3:0] 4 miitxenp miitxerp miitxclkp miimdcp miimdiop jtag_tck jtag_tms jtag_tdi jtag_tdo clkp sysclkp coldrstn rc32351 miscellaneous signals usb interface ethernet interface jtag general purpose input/output atm interface memory and rstn sdclkinp debug logic diagram peripheral bus vcccore vcci/o vss power/ground vccp (pll) vssp (pll) (primary functions) instp
14 of 42 may 25, 2004 idt 79rc32351 clock parameters (ta = 0 c to +70 c commercial, vcc i/o = +3.3v 5%, v cc core and v cc p = +2.5v 5%) figure 4 clock parameters waveform parameter symbol reference edge rc32351 100mhz rc32351 133mhz units timing diagram reference min max min max internal cpu pipeline clock 1 frequency none 100 100 100 133 mhz figure 4 clkp 2,3,4 frequency none 25 50 25 67 mhz tperiod1 20 40 15 40 ns thigh1 10 ? 6 ? ns tlow1 10 ? 6 ? ns trise1 ? 3 ? 3 ns tfall1 ? 3 ? 3 ns tjitter ? 250 ? 250 ps 1 the cpu pipeline clock speed is selected during cold reset by the boot configuration vector (see table 2). 2 ethernet clock (miirxclkp and miitxclkp) frequency must be equal to or less than 1/2 clkp frequency. 3 usb clock (usbclkp) frequency must be less than clkp frequency. 4 atm utopia clock (rxclkp and txclkp) frequency must be equal to or less than 1/2 clkp frequency. table 3 clock parameters tlow1 thigh1 tperiod1 clkp trise1 tfall1 tjitter tjitter
15 of 42 may 25, 2004 idt 79rc32351 ac timing definitions below are examples of the ac timing c haracteristics used throughout this document. figure 5 ac timing definitions waveform symbol definition tperiod clock period. tlow clock low. amount of time the clock is low in one clock period. thigh clock high. amount of time the clock is high in one clock period. trise rise time. low to high transition time. tfall fall time. high to low transition time. tjitter jitter. amount of time the reference clock (or signal) edge can vary on either the rising or falling edges. tdo data out. amount of time after the reference clock edge that the output will become valid. the minimum time represents the d ata output hold. the maximum time represents the earliest time the designer can use the data. tzd z state to data valid. amount of time after the reference clock edge that the tri-stated output takes to become valid. tdz data valid to z state. amount of time after the reference clock edge that the valid output takes to become tri-stated. tsu input set-up. amount of time before the reference clock edge that the input must be valid. thld input hold. amount of time after the reference clock edge that the input must remain valid. tpw pulse width. amount of time the input or output is active. table 4 ac timing definitions tdz tzd tdo tpw tpw thld tsu tlow thigh thigh tperiod clock output signal 1 output signal 2 input signal 1 signal tjitter trise tfall tdo
16 of 42 may 25, 2004 idt 79rc32351 ac timing characteristics (ta = 0 c to +70 c commercial, vcc i/o = +3.3v 5%,v cc core = +2.5v 5%, v cc p = +2.5v 5%) signal symbol reference edge 100mhz 133mhz unit conditions timing diagram reference min max min max reset and system coldrstn tpw1 none 110 ? 110 ? ms figure 6 figure 7 trise1 none ? 5.0 ? 5.0 ns rstn 1 tdo2 clkp rising 4.0 10.7 4.0 10.7 ns mdata[15:0] boot configuration vector thld3 coldrstn rising 3?3?ns instp tdo clkp rising 5 8 5.0 8.0 ns cpup tdo clkp rising 3.5 7 3.5 7.0 ns dmap tdo clkp rising 3.5 6.6 3.5 6.6 ns dmareqn 2 tpw none (clkp+7) ? (clkp+7) ? ns dmadonen 2 tpw none (clkp+7) ? (clkp+7) ? ns dmafin tdo clkp rising 3.5 5.9 3.5 5.9 ns brn tsu clkp rising 1.6 ? 1.6 ? ns thld 0?0?ns bgn tdo clkp rising 3.3 5.8 3.3 5.8 ns 1 rstn is a bidirectional signal. it is treated as an asynchronous input. 2 dmareqn and dmadonen minimum pulse width equals the clkp period plus 7ns. table 5 reset and system ac timing characteristics
17 of 42 may 25, 2004 idt 79rc32351 figure 6 cold reset ac timing waveform boot vect sysclkp coldrstn rstn mdata[31:0] bdirn boen[0] >= 100 ms >=10ms >= 4096 clkp clock cycles or >= 64 clkp clock cycles * >= 4096 clkp clock cycles or >= 64 clkp clock cycles * * selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset). tpw1 tdo2 clkp 1 ffff_ffff thld3 1. coldrstn asserted by external logic. 2. the rc32351 asserts rstn, asserts boen[0] low, drives bdirn low, and tri-states the data bus in response. 3. external logic begins driving valid boot configuration vector on the data bus, and the rc32351 starts sampling it. 4. external logic negates coldrstn and tri-states the boot configuration vector on mdata[15:0]. the boot configuration vector mu st not be tri-stated before coldrstn is deasserted. the rc32351 stops sampling the boot configuration vector. 5. the rc32351 starts driving the data bus, mdata[31:0], deasserts boen[0] high, and drives bdirn high. 6. sysclkp may be held constant after this point if hold sysclkp constant is selected in the boot configuration vector. 7. rstn negated by rc32351. 8. cpu begins executing by taking mips reset exception, and the rc32351 starts sampling rstn as a warm reset input. 2 34 56 7 8 trise1
18 of 42 may 25, 2004 idt 79rc32351 figure 7 warm reset ac timing waveform active deasserted active clkp coldrstn rstn mdata[31:0] mem control signals >= 4096 clkp clock cycles or >= 64 clkp clock cycles * >= 4096 clkp clock cycles or >= 64 clkp clock cycles * (rstn ignored during this period to allow pull-up to drive signal high) * selection of 4096 or 64 cycles is selected by the boot configuration vector (fast reset). 1. warm reset condition caused by either rstn asserted, write to reset register, or bus transaction timer time-out. the rc32351 asserts rstn out- put low in response. 2. the rc32351 tri-states the data bus, mdata[31:0], and deasserts all memory control signals, such as rasn, casn, rwn, oen, etc . 3. the rc32351 deasserts rstn. 4. the rc32351 starts driving the data bus, mdata[31:0], again, but does not sample the rstn input. 5. cpu begins executing by taking a mips soft reset exception and also starts sampling the rstn input again. ffff_ffff 12 34 5
19 of 42 may 25, 2004 idt 79rc32351 signal symbol reference edge 100mhz 133mhz unit conditions timing diagram reference min max min max memory and peripheral bus - sdram access mdata[31:0] tsu1 sdclkinp rising 2.5 ? 2.5 ? ns figure 8 figure 9 figure 10 thld1 1.2 ? 1.2 ? ns tdo1 sysclkp rising 1.2 5.8 1.2 5.8 ns tdz1 ? 5.0 ? 5.0 ns tzd1 1.0 ? 1.0 ? ns maddr[20:2], bwen[3:0] tdo2 sysclkp rising 1.2 5.3 1.2 5.3 ns casn, rasn, sdcsn[1:0], sdwen tdo3 sysclkp rising 1.2 5.3 1.2 5.3 ns ckenp tdo4 sysclkp rising 1.2 5.3 1.2 5.3 ns bdirn tdo5 sysclkp rising 1.2 5.3 1.2 5.3 ns boen[1:0] tdo6 sysclkp rising 1.2 5.3 1.2 5.3 ns sysclkp rising tdo7 clkp rising 0.5 5.0 0.5 5.0 ns sdclkinp tperiod8 none 20 50 15 50 ns thigh8,tlow8 10 ? 6.0 ? ns trise8,tfall8 ? 3.0 ? 3.0 ns tdelay8 sysclkp rising 04.804.8 ns table 6 memory and peripheral bus ac timing characteristics (part 1 of 2)
20 of 42 may 25, 2004 idt 79rc32351 note: the rc32351 provides bus turnaround cycles to prevent bus contention when going from a read to write, write to read, and during external bus ownership. for example, there are no cycles wher e an external device and the rc32351 are both driving. see chapter 10, ?device controller,? chapter 11, ?synchronous dram controller,? and chapter 12, ?bus arbitration? in the rc32351 user reference manual. memory and peripheral bus - device access mdata[31:0] tsu1 clkp rising 2.5 ? 2.5 ? ns figure 11 figure 12 thld1 1.5 ? 1.5 ? ns tdo1 2.0 6.5 2.0 6.5 ns tdz1 ? 9.0 ? 9.0 ns tzd1 2.0 ? 2.0 ? ns waitackn, brn tsu clkp rising 2.5 ? 2.5 ? ns thld 1.5 ? 1.5 ? ns maddr[21:0] tdo2 clkp rising 2.0 6.0 2.0 6.0 ns tdz2 ? 9.0 ? 9.0 ns tzd2 2.0 ? 2.0 ? ns maddr[25:22] tdo3 clkp rising 2.5 6.5 2.5 6.5 ns tdz3 ? 9.0 ? 9.0 ns tzd3 2.0 ? 2.0 ? ns bdirn, boen[0] tdo4 clkp rising 2.0 6.0 2.0 6.0 ns tdz4 ? 9.0 ? 9.0 ns tzd4 2.0 ? 2.0 ? ns bgn, bwen[3:0], oen, rwn tdo5 clkp rising 2.0 6.0 2.0 6.0 ns tdz5 ? 9.0 ? 9.0 ns tzd5 2.0 ? 2.0 ? ns csn[3:0] tdo6 clkp rising 1.7 5.0 1.7 5.0 ns tdz6 ? 9.0 ? 9.0 ns tzd6 2.0 ? 2.0 ? ns csn[5:4] tdo7 clkp rising 2.5 6.0 2.5 6.0 ns tdz7 ? 9.0 ? 9.0 ns tzd7 2.0 ? 2.0 ? ns signal symbol reference edge 100mhz 133mhz unit conditions timing diagram reference min max min max table 6 memory and peripheral bus ac timing characteristics (part 2 of 2)
21 of 42 may 25, 2004 idt 79rc32351 figure 8 memory and peripheral bus ac timing waveform - sdram read access figure 9 sysclkp - sdclkinp relationship addr 1111 be's 1111 nop read nop 11 chip-sel 11 11 buffer enables 11 data tzd1 tdz1 tdo6 tdo6 tdo5 tdo5 tdo3 tdo3 tdo2 tdo2 thld1 tsu1 clkp sysclkp maddr[21:0] bwen[3:0] cmd[2:0]* sdcsn[1:0] bdirn boen[1:0] mdata[31:0] sdclkinp sdram cas latency tdo7 tdelay8 * note: cmd[2:0] = {rasn, casn, sdwen} rc32351 samples read data rc32351 sdram sram, eprom, etc. external sysclkp sdclkinp clkp memory bus tdelay8 rstn coldrstn vcc pull-up buffer
22 of 42 may 25, 2004 idt 79rc32351 figure 10 memory and peripheral bus ac timing waveform - sdram write access addr 1111 be's 1111 nop write nop 11 chip-sel 11 11 buff enable 11 data tdo1 tdo6 tdo5 tdo3 tdo3 tdo2 tdo2 clkp sysclkp maddr[21:0] bwen[3:0] cmd[2:0]* sdcsn[1:0] bdirn boen[1:0] mdata[31:0] tdo7 * note: cmd[2:0] = {rasn, casn, sdwen} sdram samples write data
23 of 42 may 25, 2004 idt 79rc32351 figure 11 memory and peripheral bus ac timing waveform - device read access addr[21:0] addr[25:22] 1111 data tdo4 tdo4 tdo4 tdo4 tzd1 tdz1 tdo5 tdo5 tdo6 tdo6 tdo3 tdo2 thld1 tsu1 clkp maddr[21:0] maddr[25:22] rwn csn[3:0] bwen[3:0] oen mdata[31:0] bdirn boen[0] waitackn rc32351 samples read data
24 of 42 may 25, 2004 idt 79rc32351 figure 12 memory ac and peripheral bus timing waveform - device write access addr[21:0] addr[25:22] 1111 byte enables 1111 data tdo4 tdo1 tdo5 tdo6 tdo5 tdo3 tdo2 clkp maddr[21:0] maddr[25:22] rwn csnx bwen[3:0] oen mdata[31:0] bdirn boen[0] waitackn
25 of 42 may 25, 2004 idt 79rc32351 signal symbol reference edge 100mhz 133mhz unit conditions timing diagram reference min max min max ethernet 1,2 miirxclkp, miitxclkp tperiod1 none 399.96 400.04 399.96 400.04 ns 10 mbps figure 13 thigh1,tlow1 140 260 140 260 ns trise1,tfall1 ? 3 ? 3 ns miirxclkp, miitxclkp tperiod1 none 39.996 40.004 39.996 40.004 ns 100 mbps thigh1,tlow1 14 26 14 26 ns trise1,tfall1 ? 2 ? 2 ns miirxdp[3:0], miirxdvp, miirxerp tsu2 miirxclkp rising 5?5?ns thld2 3 ? 3 ? ns miitxdp[3:0], miitxenp, miitxerp tdo3 miitxclkp rising 7 13 7 13 ns miimdcp tperiod4 none 30 ? 30 ? ns thigh4,tlow4 14 ? 14 ? ns trise4 ? 11 ? 11 ns tfall4 ? 8 ? 8 ns miimdiop tsu5 miimdcp rising 6?6?ns thld5 0.5 ? 0.5 ? ns tdo5 3 7 3 7 ns 1 ethernet clock (miirxclkp and miitxclkp) frequency must be equal to or less than 1/2 clkp frequency. 2 miicolp and miicrsp are asynchronous signals. table 7 ethernet ac timing characteristics
26 of 42 may 25, 2004 idt 79rc32351 figure 13 ethernet ac timing waveform tdo5 tdo5 tdo3 tdo3 thld5 tsu5 tlow4 tlow4 thigh4 tperiod4 tlow1 tlow1 thigh1 tperiod1 thld2 tsu2 tlow1 tlow1 thigh1 tperiod1 miirxclkp miirxdvp, miirxdp[3:0], miirxerp miitxclkp miitxenp, miitxdp[3:0], mmtxerp miimdcp miimdiop (output) miimdiop (input)
27 of 42 may 25, 2004 idt 79rc32351 figure 14 atm ac timing waveform signal symbol reference edge 100mhz 133mhz unit conditions timing diagram reference min max min max atm interface, utopia mode 1,2 1. atm utopia clock (rxclkp and txclkp) frequency must be equal to or less than 1/2 clkp frequency. 2. all utopia mode pins are multiplexed on the atm interface pins as described in table 9. rxclkp, txclkp 1 tperiod1 none ? 40 ? 40 ns 25 mhz utopia figure 14 thigh1,tlow1 16 ? 16 ? ns trise1,tfall1 ? 4 ? 4 ns rxclkp, txclkp 1 tperiod1 none ? 30 ? 30 ns 33 mhz utopia thigh1,tlow1 12 ? 12 ? ns trise1,tfall1 ? 3 ? 3 ns rxclkp, txclkp tperiod1 none ? 20 ? 20 ns 50 mhz utopia thigh,tlow1 8 ? 8 ? ns trise1,tfall1 ? 2 ? 2 ns txfulln tsu2 txclkp rising 2?2? ns thld2 2 ? 2 ? ns txdata[7:0], txsoc, txenbn, txaddr[1:0] tdo3 txclkp rising 4848 ns rxdata[7:0], rxemp- tyn, rxsoc tsu4 rxclkp rising 3?3? ns thld4 2 ? 2 ? ns rxaddr[1:0], rxenbn tdo5 rxclkp rising 3838 ns table 8 atm ac timing characteristics tdo5 tdo3 thld4 tsu4 tperiod1 tperiod1 thld2 tsu2 tperiod1 tperiod1 txclkp txfull txdata,txsoc,txenb,txaddr rxclkp rxdata, rxempty, rxsoc rxaddr, rxenb
28 of 42 may 25, 2004 idt 79rc32351 atm pin name utopia level 1 utopia level 2 atminp[0] rxdata[0] rxdata[0] atminp[1] rxdata[1] rxdata[1] atminp[2] rxdata[2] rxdata[2] atminp[3] rxdata[3] rxdata[3] atminp[4] rxdata[4] rxdata[4] atminp[5] rxdata[5] rxdata[5] atminp[6] rxdata[6] rxdata[6] atminp[7] rxdata[7] rxdata[7] atminp[8] rxclkp rxclkp atminp[9] rxemptyn rxemptyn atminp[10] rxsoc rxsoc atminp[11] txfulln txfulln atmiop[0] rxenbn rxenbn atmiop[1] txclkp txclkp atmoutp[0] txdata[0] txdata[0] atmoutp[1] txdata[1] txdata[1] atmoutp[2] txdata[2] txdata[2] atmoutp[3] txdata[3] txdata[3] atmoutp[4] txdata[4] txdata[4] atmoutp[5] txdata[5] txdata[5] atmoutp[6] txdata[6] txdata[6] atmoutp[7] txdata[7] txdata[7] atmoutp[8] txsoc txsoc atmoutp[9] txenbn txenbn gpiop[22] txaddr[0] gpiop[23] txaddr[1] gpiop[24] rxaddr[0] gpiop[25] rxaddr[1] table 9 atm i/o pin description
29 of 42 may 25, 2004 idt 79rc32351 signal symbol reference edge 100mhz 133mhz unit conditions timing diagram reference min max min max usb usbclkp 1 tperiod1 none 19.79 21.87 19.79 21.87 ns figure 15 thigh1,tlow1 8.3 ? 8.3 ? ns trise1,tfall1 ? 3 ? 3 ns tjitter1 ? 0.8 ? 0.8 ns 1/4th of the minimum source data jitter usbdn, usbdp trise2 4 20 4 20 n s universal serial bus specification (usbs) revision 1.1: figures 7.6 and 7.7. tfall2 4 20 4 20 ns usbs revision 1.1: figures 7.6 and 7.7. usbdn and usbdp rise and fall time matching 90 111.11 90 111.11 % usbs revision 1.1: note 10, section 7.1.2. data valid period tstate 60 ? 60 ? ns skew between usbdn and usbdp ? 0.4 ? 0.4 ns usbs revision 1.1: section 7.1.3 source data jitter ? 3.5 ? 3.5 ns usbs revision 1.1: table 7-6 receive data jitter ? 12 ? 12 ns source eop length tseop 160 175 160 175 ns receive eop length treop 82 ? 82 ? ns eop jitter -2 5 -2 5 ns full-speed data rate tfdrate 11.97 12.03 11.97 12.03 mhz average bit rate, usbs section 7.1.11. frame interval 0.9995 1.0005 0.9995 1.0005 ms usbs section 7.1.12. consecutive frame inter- val jitter ? 42 ? 42 ns without frame adjust- ment. ? 126 ? 126 ns with frame adjust- ment. 1 usb clock (usbclkp) frequency must be less than clkp frequency. table 10 usb ac timing characteristics
30 of 42 may 25, 2004 idt 79rc32351 figure 15 usb ac timing waveform signal symbol reference edge 100mhz 133mhz unit conditions timing diagram reference min max min max uart u0sinp, u0rin, u0dcdn, u0dsrn, u0ctsn, u1sinp, u1dsrn, u1ctsn tsu 1 clkp rising 5 ? ns thld 1 3? ns u0soutp, u0dtrn, u0rtsn, u1soutp, u1dtrn, u1rtsn tdo 1 clkp rising 1 12 ns 1 these are asynchronous signals and the values are provided for ate (test) only. table 11 uart ac timing characteristics tperiod1 thigh1 tr i s e 1 tlow1 tfall1 tseop tr e o p 90% 10% 90% 10% tstate usbclkp tjitter1 tr i s e 2 tfall2 tfdrate usbdn usbdp usbdn usbdp
31 of 42 may 25, 2004 idt 79rc32351 table 12 gpiop ac timing characteristics figure 16 gpiop ac timing waveform signal symbol reference edge 100mhz 133mhz unit conditions timing diagram reference min max min max gpiop gpiop[31:0] 1 tsu1 clkp rising 4 ? 4 ? ns figure 16 thld1 1.4 ? 1.4 ? ns tdo1 2 8 2 8 ns gpiop[35:32] 2 tsu1 3?3? ns thld1 1 ? 1 ? ns tdo1 3 8 3 8 ns 1 gpio[31:0] can be asynchronous signals; the values are provided for ate (test) only. 2 gpiop[35:32] are synchronous signals. gpiop (input) gpiop (output) clkp tsu1 thld1 tdo1 tdo1
32 of 42 may 25, 2004 idt 79rc32351 table 13 jtag ac timing characteristics figure 17 jtag ac timing waveform signal symbol reference edge 100mhz 133mhz unit conditions timing diagram reference min max min max ejtag and jtag jtag_tck tperiod1 none 100 ? 100 ? ns figure 17 thigh1,tlow1 40 ? 40 ? ns trise1,tfall1 ? 5 ? 5 ns ejtag_dclk 1 1. ejtag_dclk is equal to the internal cpu pipeline clock. tperiod2 none 10.0 10.0 7.5 10.0 ns thigh2,tlow2 2.5 ? 2.5 ? ns trise2,tfall2 ? 3.5 ? 3.5 ns jtag_tms, jtag_tdi, jtag_trst_n tsu3 jtag_tck rising 3.0 ? 3.0 ? ns thld3 1.0 ? 1.0 ? ns jtag_tdo tdo4 jtag_tck falling 2.0 12.0 2.0 12.0 ns tdo5 ejtag_dclk rising -0.7 2 2. a negative delay denotes the amount of time before the reference clock edge. 1.0 -0.7 2 1.0 ns jtag_trst_n tpw6 none 100 ? 100 ? ns tsu6 jtag_tck rising 2 ? 2 ? ns ejtag_pcst[2:0] tdo7 ejtag_dclk rising -0.3 2 3.3 -0.3 2 3.3 ns tperiod1 tfall1 tlow1 thigh1 trise2 tfall2 thigh2 tlow2 tsu3 thld3 tdo4 tperiod2 trise1 tdo5 tdo7 tsu6 tpw6 jtag_tck ejtag_dclk jtag_tms, jtag_tdi jtag_tdo ejtag_pcst jtag_trst_n tpc tdo tdo pcst ejtag tpc, tcst capture ejtag_trst_n
33 of 42 may 25, 2004 idt 79rc32351 table 14 shows the pin numbering for the standard ejtag connecto r. all the even numbered pins are connected to ground. multiple xing of pin functions should be considered when connecting ejtag_trst_n and ejtag_pcst. for details on using the jtag connector, see the jtag chapters in the rc32351 user reference manual. output loading for ac timing figure 18 output loading for ac timing pin signal rc32351 i/o termination 1 1. the value of the series resistor may depend on the actual printed circuit board layout situation. 1 ejtag_trst_n input 10 k ? pull-down resistor. a pull-down resistor will hold the ejtag controller in reset when not in use if the ejtag_trst_n function is selected with the boot configuration vector. refer to the user man- ual. 3 jtag_tdi input 10 k ? pull-up resistor 5 jtag_tdo output 33 ? series resistor 7 jtag_tms input 10 k ? pull-up resistor 9 jtag_tck input 10 k ? pull-up resistor 2 2. jtag_tck pull-up resistor is not required according to the jtag (ieee1149) standard. it is indicated here to prevent a floating cmos input when the ejtag connector is unconnected. 11 system reset input 10 k ? pull-up resistor is used if it is combined with the system cold reset control, coldrstn. 13 ejtag_pcst[0] output 33 ? series resistor 15 ejtag_pcst[1] output 33 ? series resistor 17 ejtag_pcst[2] output 33 ? series resistor 19 ejtag_dclk output 33 ? series resistor 21 debug boot input this can be connected to the boot configuration vector to control debug boot mode if desired. refer to table 2 on page 12 and the rc32351 user reference manual. 23 v cc i/o output used to sense the circuit board power. must be connected to the vcc i/o supply of the circuit board. table 14 pin numbering of the jtag and ejtag target connector 1.5v signal equivalent lump capacitance all high drive signals 50 pf 1 1. an equivalent load of 50 pf is derived from the tester load plus an external load. all low drive signals 25 pf rc32351 output . 50 ? 50 ? test point
34 of 42 may 25, 2004 idt 79rc32351 phase-locked loop (pll) the processor aligns the pipeline clock, pclock, to the master input clock (clkp) by using an internal phase-locked loop (pll) circuit that gener- ates aligned clocks. inherently, pll circuits are only capable of generating aligned clocks for master input clock (clkp) frequ encies within a limited range. pll analog filter the storage capacitor required for the phase-locked loop circuit is contained in the rc32351. however, it is recommended that t he system designer provide a filter network of passive components for the pll power supply. v cc p (pll circuit power) and v ss p (pll circuit ground) should be isolated from v cc core (core power) and v ss (common ground) with a filter circuit such as the one shown in figure 19. because the optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as starting points for further experim entation within your specific application. figure 19 pll filter circuit for noisy environments recommended operating temperature and supply voltage capacitive load deration refer to the rc32355 ibis model which can be found at the idt web site (www.idt.com). grade temperature vss 1 vssp 5 v cc i/o 2 v cc core 3 v cc p 4 commercial 0 c to +70 c ambient 0v 3.3v5% 2.5v5% 1 vss supplies a common ground. 2 vcci/o is the i/o power. 3 vcccore is the internal logic power. 4 vccp is the phase lock loop power. 5 vssp is the phase lock loop ground. table 15 temperature and voltage 10 f 0.1 f 100 pf vcc vss vccp vssp 10 ohm 1 1. this resistor may be required in noisy circuit environments. rc32351
35 of 42 may 25, 2004 idt 79rc32351 power-on rampup the 2.5v core supply (and 2.5v v cc pll supply) can be fully powered without the 3.3v i/o s upply. however, the 3.3v i/o supply cannot exceed the 2.5v core supply by more than 1 volt during power up. a sust ained large power difference could potentially damage the part. inp uts should not be driven until the part is fully powered. specifically, the input high voltages should not be applied until the 3.3v i/o supply i s powered. there is no special requirement for how fast v cc i/o ramps up to 3.3v. however, all timing references are based on a stable v cc i/o. dc electrical characteristics (t ambient = 0 c to +70 c commercial , vcc i/o = +3.3v 5%, v cc core and v cc p = +2.5v 5% ) para- meter min max unit pin numbers conditions low drive output with schmitt trigger input (sti) i ol 7.3 ? ma 1-4,6-8,10-16,18,20-25,27-29,32,33,35-37, 39-42,44,46-48,50,52,53,56,58-60,62-69, 71-77,82-85,87-94,96-99,101-105,167, 205-208 v ol = 0.4v i oh -8.0 ? ma v oh = (v cc i/o - 0.4) v il ?0.8v ? v ih 2.0 (v cc i/o + 0.5) v? v oh v cc - 0.4 ? v? high drive output with standard input i ol 9.4 ? ma 49,51,54,55,106-108,110,112-117,119, 121,123-128,130,132-137,139,141,143, 150,152,154-159,161,163-166,168-170, 172,174-179,181,185-190,192,194-200, 202,204 v ol = 0.4v i oh -15 ? ma v oh = (v cc i/o - 0.4) v il ?0.8v ? v ih 2.0 (v cc i/o + 0.5) v? v oh v cc - 0.4 ? v? clock drive output i ol 39 ? ma 183 v ol = 0.4v i oh -24 ? ma v oh = (v cc i/o - 0.4) capacitance c in ? 10 pf all pins ? leakage i/o leak ?20 a all pins ? table 16 dc electrical characteristics
36 of 42 may 25, 2004 idt 79rc32351 usb electrical characteristics power consumption note: this table is based on a 2:1 cpu bus (pclock to clkp) clock ratio. table 18 rc32351 power consumption parameter min max unit conditions usb interface v di differential input sensitivity -0.2 v i(d+)-(d-)i v cm differential input common mode range 0.8 2.5 v v se single ended receiver threshold 0.8 2.0 v c in transceiver capacitance 20 pf i li hi-z state data line leakage -10 10 s0v < v in < 3.3v usb upstream/downstream por t v oh static output high 2.8 3.6 v 15km + 5% to gnd [7] v ol static output low 0.3 v z o usb driver output impedance 28 44 ? including r ext = 20 ? table 17 usb interface characteristics parameter 100mhz 133mhz unit conditions typical max. typical max. i cc i/o 60 110 80 130 ma i cc core normal mode 300 350 400 450 ma c l = 0 t a = 25 o c vccp = 2.625v (for max. values) v cc core = 2.625v (for max. values) v cc i/o = 3.46v (for max. values) vccp = 2.5v (for typical values) v cc core = 2.5v (for typical values) v cc i/o = 3.3v (for typical values) standby mode 1 1. riscore 32300 cpu core enters standby mode by executing wait instructions; however, other logic continues to function. standby mode reduces power consumption by 0.6 ma per mhz of the cpu pipeline clock, pclock. 240 290 320 370 ma power dissipation normal mode 0.95 1.30 1.26 1.63 w standby mode 1 0.80 1.09 1.06 1.42 w
37 of 42 may 25, 2004 idt 79rc32351 power curve the following graph contains a power curve that s hows power consumption at various bus frequencies. note: the system clock (clkp) can be multiplied by 2, 3, or 4 to obtain the cpu pipeline clock (pclock) speed. figure 20 typical power usage absolute maximum ratings symbol parameter min 1 1. functional and tested operating conditions are given in table 15. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. max 1 unit v cc i/o i/o supply voltage -0.3 4.0 v v cc core core supply voltage -0.3 3.0 v v cc p pll supply voltage -0.3 3.0 v vimin input voltage - undershoot -0.6 ? v vi i/o input voltage gnd v cc i/o+0.5 v ta, commercial ambient operating temperature 0 70 degrees c tstg storage temperature -40 125 degrees c table 19 absolute maximum ratings typical power curve 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 25 30 35 40 45 50 55 60 65 system bus speed (mhz) power (w @ 3.3v io & 2.5v core) 2x
38 of 42 may 25, 2004 idt 79rc32351 package pin-out ? 208-pin pqfp the following table lists the pin numbers and signal names for the rc32351. pin function alt pin function alt pin function alt pin function alt 1 atmoutp[0] 53 jtag_tdo 105 bgn 157 mdata[28] 2 atmoutp[1] 54 gpiop[16] 1 106 csn[0] 158 mdata[13] 3 atminp[02] 55 gpiop[17] 1 107 csn[1] 159 mdata[29] 4 atmoutp[2] 56 gpiop[18] 1 108 csn[2] 160 vcc i/o 5 vss 57 vss 109 vcc i/o 161 mdata[14] 6 atmoutp[3] 58 jtag_tck 110 csn[3] 162 vss 7 atminp[03] 59 gpiop[19] 1 111 vss 163 mdata[30] 8 atmoutp[4] 60 gpiop[20] 1 112 oen 164 mdata[15] 9 vcc i/o 61 vcc i/o 113 rwn 165 mdata[31] 10 atmoutp[5] 62 gpiop[21] 1 114 bdirn 166 clkp 11 atminp[04] 63 jtag_tdi 115 boen[0] 167 waitackn 12 atmoutp[6] 64 gpiop[22] 1 116 boen[1] 168 maddr[00] 13 atmoutp[7] 65 gpiop[23] 2 117 bwen[0] 169 maddr[11] 14 atminp[05] 66 gpiop[24] 1 118 vcc i/o 170 maddr[01] 15 atmoutp[8] 67 jtag_tms 119 bwen[1] 171 vcc i/o 16 atmoutp[9] 68 gpiop[25] 2 120 vss 172 maddr[12] 17 vss 69 gpiop[26] 121 bwen[2] 173 vss 18 atminp[06] 70 vss 122 vcc core 174 maddr[02] 19 vcc core 71 gpiop[27] 1 123 bwen[3] 175 maddr[13] 20 gpiop[00] 1 72 coldrstn 124 mdata[00] 176 maddr[03] 21 gpiop[01] 1 73 gpiop[28] 1 125 mdata[16] 177 maddr[14] 22 atminp[07] 74 gpiop[29] 1 126 mdata[01] 178 maddr[04] 23 gpiop[02] 2 75 gpiop[30] 1 127 mdata[17] 179 maddr[15] 24 gpiop[03] 1 76 gpiop[31] 2 128 mdata[02] 180 vcc i/o 25 atminp[08] 77 usbclkp 129 vcc i/o 181 maddr[05] 26 vcc i/o 78 vcc i/o 130 mdata[18] 182 vcc core 27 gpiop[04] 2 79 usbdn 131 vss 183 sysclkp 28 gpiop[05] 1 80 usbdp 132 mdata[03] 184 vss 29 atminp[09] 81 vss 133 mdata[19] 185 maddr[16] 30 vccp 1 82 miicrsp 134 mdata[04] 186 maddr[06] 31 vssp 1 83 miicolp 135 mdata[20] 187 maddr[17] 32 atminp[10] 84 miitxdp[0] 136 mdata[05] 188 maddr[07] 33 gpiop[06] 1 85 miitxdp[1] 137 mdata[21] 189 maddr[18] 34 vss 86 vcc core 138 vcc core 190 maddr[08] 35 gpiop[07] 1 87 miitxdp[2] 139 mdata[06] 191 vcc i/o 36 atminp [11] 88 miitxdp[3] 140 vcc i/o 192 maddr[19] 37 gpiop[08] 2 89 miitxenp 141 mdata[22] 193 vss table 20: 208-pin qfp package pin-out (part 1 of 2)
39 of 42 may 25, 2004 idt 79rc32351 alternate pin functions table 21 alternate pin functions 38 vcc core 90 miitxclkp 142 vss 194 maddr[09] 39 gpiop[09] 2 91 miitxerp 143 mdata[07] 195 maddr[20] 40 gpiop[10] 2 92 miirxerp 144 mdata[23] 196 maddr[10] 41 gpiop[11] 2 93 miirxclkp 145 sdclkinp 197 maddr[21] 42 gpiop[12] 2 94 miirxdvp 146 mdata[08] 198 casn 43 vcc i/o 95 vcc i/o 147 mdata[24] 199 rasn 44 gpiop[13] 2 96 miirxdp[0] 148 mdata[09] 200 sdwen 45 vss 97 miirxdp[1] 149 mdata[25] 201 vcc i/o 46 gpiop[14] 98 miirxdp[2] 150 mdata[10] 202 sdcsn[0] 47 gpiop[15] 99 miirxdp[3] 151 vcc i/o 203 vss 48 gpiop[35] 100 vss 152 mdata[26] 204 sdcsn[1] 49 gpiop[34] 101 miidcp 153 vss 205 atminp[00] 50 gpiop[33] 102 miidiop 154 mdata[11] 206 atmiop[0] 51 gpiop[32] 103 rstn 155 mdata[27] 207 atmiop[1] 52 instp 104 brn 156 mdata[12] 208 atminp[01] 1 vccp and vssp are the phase lock loop (pll) power and ground. pll power and ground should be supplied through a special filter circuit. pin primary alt #1 alt #2 pin primary alt #1 alt #2 20 gpiop[00] u0soutp 55 gpiop[17] csn[5] 21 gpiop[01] u0sinp 56 gpiop[18] dmareqn 23 gpiop[02] u0rin jtag_trst_n 59 gpiop[19] dmadonen 24 gpiop[03] u0dcrn 60 gpiop[20] usbsof 27 gpiop[04] u0dtrn cpup 62 gpiop[21] ckenp 28 gpiop[05] u0dsrn 64 gpiop[22] txaddr[0] 33 gpiop[06] u0rtsn 65 gpiop[23] txaddr[1] dmap[0] 35 gpiop[07] u0ctsn 66 gpiop[24] rxaddr[0] 37 gpiop[08] u1soutp dmap[3] 68 gpiop[25] rxaddr[1] dmap[1] 39 gpiop[09] u1sinp dmap[2] 71 gpiop[27] maddr[22] 40 gpiop[10] u1dtrn ejtag_pcst[0] 73 gpiop[28] maddr[23] 41 gpiop[11] u1dsrn ejtag_pcst[1] 74 gpiop[29] maddr[24] 42 gpiop[12] u1rtsn ejtag_pcst[2] 75 gpiop[30] maddr[25] 44 gpiop[13] u1ctsn ejtag_dclk 76 gpiop[31] dmafin ejtag_trst_n 54 gpiop[16] csn[4] pin function alt pin function alt pin function alt pin function alt table 20: 208-pin qfp package pin-out (part 2 of 2)
40 of 42 may 25, 2004 idt 79rc32351 package drawing - 208-pin qfp
41 of 42 may 25, 2004 idt 79rc32351 package drawing - page two
42 of 42 may 25, 2004 idt 79rc32351 corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: rischelp@idt.com phone: 408-284-8208 ordering information valid combinations 79rc32t351 -100dh 208-pin qfp package, commercial temperature 79rc32t351 -133dh 208-pin qfp package, commercial temperature 79rcxx yy xxxx 999 a a operating voltage device type speed package temp range/ process t 100 blank commercial temperature (0c to +70c ambient) 100 mhz pipeline clk 2.5v +/-5% core voltage integrated core processor product type 79rc32 32-bit embedded microprocessor 208-pin qfp dh 133 351 133 mhz pipeline clk

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