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1998, 1999 data sheet 4-bit single-chip microcontroller for infrared remote control transmission description the m pd66p04b is a microcontroller for infrared remote control transmitters which is provided with a one-time prom as the program memory. because users can write programs for the m pd66p04b, it is ideal for program evaluation and small-scale production of the application systems using the m pd6604. when reading this document, also refer to the m pd6604 data sheet (u11281e). features ? program memory (one-time prom) : 1002 10 bits ? data memory (ram) : 32 4 bits ? built-in carrier generation circuit for infrared remote control ? 9-bit programmable timer : 1 channel ? command execution time : 16 m s (when operating at f osc = 500 khz: rc oscillation) ? stack level : 1 level (stack ram is for data memory rf as well.) ? i/o pins (k i/o ) : 8 units ? input pins (k i ) : 4 units ? sense input pin (s 0 ) : 1 unit ?s 1 /led pin (i/o) : 1 unit (when in output mode, this is the remote control transmission display pin.) ? power supply voltage : v dd = 2.2 to 3.6 v ? operating ambient temperature : t a = C40 to +85 c ? oscillator frequency : f osc = 300 khz to 1 mhz ? poc circuit application infrared remote control transmitter (for av and household electric appliances) because the m pd66p04b uses an rc oscillation system clock, its accuracy and stability are lower than the models using ceramic oscillation. in applications where the clock accuracy and stability pose a problem, use the m pd61p34b (ceramic oscillation type). mos integrated circuit m pd66p04b document no. u13596ej2v1ds00 (2nd edition) date published august 2000 n cp(k) printed in japan the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
2 m pd66p04b data sheet u13596ej2v1ds00 ordering information part number package m pd66p04bgs 20-pin plastic sop (7.62 mm (300)) m pd66p04bgs-gjg 20-pin plastic ssop (7.62 mm (300)) pin configuration (top view) 20-pin plastic sop (7.62 mm (300)) ? m pd66p04bgs 20-pin plastic ssop (7.62 mm (300)) ? m pd66p04bgs-gjg (1) normal operating mode caution round brackets ( ) indicate the pins not used in the prom programming mode. l : connect each of these pins to gnd via a pull-down resistor. (2) prom programming mode 1 2 3 4 5 6 7 8 9 10 k i/o6 k i/o7 s 0 s 1 /led rem v dd osc out osc in gnd reset 20 19 18 17 16 15 14 13 12 11 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 d 6 d 7 clk (l) v dd osc out osc in gnd v pp d 5 d 4 d 3 d 2 d 1 d 0 md 3 md 2 md 1 md 0
3 m pd66p04b data sheet u13596ej2v1ds00 block diagram list of functions item m pd66p04b rom capacity 1002 10 bits one-time prom ram capacity 32 4 bits stack 1 level (shared with rf of ram) i/o pin key input (k i ) : 4 pins key i/o (k i/o ) : 8 pins key expansion input (s 0 , s 1 ) : 2 pins remote control transmitter display output (led) : 1 pin (shared with s 1 pin) number of keys 32 keys 48 keys (when expanded by key expansion input) 96 keys (when expanded by key expansion input and diode) clock frequency rc oscillation f osc = 300 to 500 khz f osc = 500 khz to 1 mhz note instruction execution time 16 m s (at f osc = 500 khz) carrier frequency f osc , f osc /2, f osc /8, f osc /12, f osc /16, f osc /24, no carrier (high level) timer 9-bit programmable timer : 1 channel poc circuit internal supply voltage v dd = 2.2 to 3.6 v operating ambient ? t a = C40 to +85 c temperature ? t a = C20 to +70 c (when poc circuit used) package ? 20-pin plastic sop (7.62 mm (300)) ? 20-pin plastic ssop (7.62 mm (300)) note it is necessary to design the application circuit so that the reset pin goes low at a supply voltage of less than 2.2 v. k i0 -k i3 k i/o0 -k i/o7 s 0 , s 1 /led port k i port k i/o port s 4 8 2 4 8 2 one- time prom ram system control carrier generator 9-bit timer cpu core reset osc in osc out v dd gnd rem s 1 /led
4 m pd66p04b data sheet u13596ej2v1ds00 table of contents 1. pin functions ................................................................................................................ ......... 5 1.1 normal operating mode ....................................................................................................... ............. 5 1.2 prom programming mode ....................................................................................................... ........ 6 1.3 input/output circuits of pins ............................................................................................... ....... 7 1.4 dealing with unused pins .................................................................................................... ............ 8 1.5 notes on using k i pin at reset ........................................................................................................ 8 2. differences between m pd6604 and m pd66p04b .......................................................... 9 3. writing and verifying one-time prom (program memory) .................................. 10 3.1 operating mode when writing/verifying program memory .......................................................... 10 3.2 program memory writing procedure ............................................................................................ .. 11 3.3 program memory reading procedure ............................................................................................ .12 4. electrical specifications ............................................................................................... 13 5. characteristic curve (reference values) .............................................................. 19 6. applied circuit example ................................................................................................... 21 7. package drawings ............................................................................................................. .22 8. recommended soldering conditions .......................................................................... 24 appendix a. development tools ........................................................................................ 25 appendix b. example of remote-control transmission format .......................... 26
5 m pd66p04b data sheet u13596ej2v1ds00 1. pin functions 1.1 normal operating mode pin no. symbol function output format when reset 1k i/o0 -k i/o7 cmos high-level output 2 push-pull note 1 15-20 3s 0 high-impedance (off mode) 4s 1 /led cmos push-pull high-level output (led) 5 rem cmos push-pull low-level output 6v dd 7 osc out high-impedance 8 osc in (oscillation stopped) low level (oscillation stopped) 9 gnd 10 reset 11-14 k i0 -k i3 note 2 input (low-level) notes 1. be careful about this because the drive capability of the low-level output side is held low. 2. in order to prevent malfunction, do not input a high level signal to pins k i0 to k i3 (leaving these pins open is possible, however, when these pins are left open, do not disconnect any connected pull-down resistors) when reset is released (when reset pin changes from low level to high level, or poc is released due to supply voltage startup). these pins refer to the 8-bit i/o ports. i/o switching can be made in 8-bit units. in input mode, a pull-down resistor is added. in output mode, they can be used as the key scan output of the key matrix. refers to the input port. can also be used as the key return input of the key matrix. in input mode, the availability of the pull-down resistor of the s 0 and s 1 ports can be specified by software in terms in 2-bit units. if input mode is canceled by software, this pin is placed in off mode and enters the high-impedance state. refers to the i/o port. in input mode (s 1 ), this pin can also be used as the key return input of the key matrix. the availability of the pull-down resistor of the s 0 and s 1 ports can be specified by software in 2-bit units. in output mode (led), it becomes the remote control transmission display output (active low). when the remote control carrier is output from the rem output, this pin outputs the low level from the led output synchronously with the rem signal. refers to the infrared remote control transmission output. the output is active high. carrier frequency: f osc , f osc /8, f osc /12, high-level, f osc /2, f osc /16, f osc /24 (usable on software) refers to the power supply. these pins are used for rc oscillation. refers to the ground. normally, this pin is a system reset input. by inputting a low level, the cpu can be reset. when resetting with the poc circuit a low level is output. a pull-up resistor is incorporated. these pins refer to the 4-bit input ports. they can be used as the key return input of the key matrix. the use of the pull-down resistor can be specified by software in 4-bit units.
6 m pd66p04b data sheet u13596ej2v1ds00 1.2 prom programming mode pin no. symbol function i/o 1, 2 d 0 -d 7 8-bit data input/output when writing/verifying program memory i/o 15-20 3 clk clock input for updating address when writing/verifying program input memory 6v dd power supply. C supply +6 v to this pin when writing/verifying program memory. 7 osc out clock necessary for writing program memory. connect a resistor C 8 osc in (r = 47 k w ) and a capacitor (c = 27 pf) to these pins. input 9 gnd gnd C 10 v pp supplies voltage for writing/verifying program memory. C apply +12.5 v to this pin. 11-14 md 0 -md 3 input for selecting operation mode when writing/verifying program memory. input
7 m pd66p04b data sheet u13596ej2v1ds00 1.3 input/output circuits of pins the input/output circuits of the m pd66p04b pins are shown in partially simplified forms below. (1) k i/o0 -k i/o7 (4) s 0 (5) s 1 /led note the drive capability is held low. (2) k i0 -k i3 (3) rem (6) reset p-ch n-ch note n-ch v dd output latch input buffer data output disable selector n-ch input buffer pull-down flag standby release p-ch n-ch v dd output latch carrier generator data off mode pull-down flag n-ch input buffer standby release p-ch n-ch n-ch v dd rem output latch input buffer output disable pull-down flag standby release n-ch p-ch poc circuit internal reset signal other than poc input buffer v dd
8 m pd66p04b data sheet u13596ej2v1ds00 1.4 dealing with unused pins the following connections are recommended for unused pins in the normal operation mode. table 1-1. connections for unused pins pin connection inside the microcontroller outside the microcontroller k i/o input mode open output mode high-level output rem s 1 /led output mode (led) setting s 0 off mode setting directly connected to gnd k i reset note built-in poc circuit open note if the circuit is an applied one requiring high reliability, be sure to design it in such a manner that the reset signal is entered externally. caution the i/o mode and the terminal output level are recommended to be fixed by setting them repeatedly in each loop of the program. 1.5 notes on using k i pin at reset in order to prevent malfunction, do not input a high level signal to pins k i0 to k i3 (leaving these pins open is possible, however, when these pins are left open, do not disconnect any connected pull-down resistors) when reset is released (when reset pin changes from low level to high level, or poc is released due to supply voltage startup).
9 m pd66p04b data sheet u13596ej2v1ds00 2. differences between m pd6604 and m pd66p04b table 2-1 shows the differences between the m pd6604 and m pd66p04b. the only differences among these models are the program memory, supply voltage, system clock frequency, oscillation stabilization wait time, and poc circuit (mask option), and the cpu function and internal peripheral hardware are the same. the electrical characteristics also differ slightly. for the electrical characteristics, refer to the data sheet of each model. table 2-1. differences between m pd6604 and m pd66p04b (1) when poc circuit (mask option) is provided to m pd6604 item m pd66p04b m pd6604 rom one-time prom mask rom oscillation stabilization wait time ? on releasing stop mode by release 260/f osc 36/f osc condition ? on releasing stop or halt mode by 284/f osc to 340/f osc 60/f osc to 116/f osc reset input and at reset v pp pin and operating mode select pin provided not provided electrical specifications some electrical specifications, such as data retention voltage and current consumption, differ. for details, refer to data sheet of each model. (2) when poc circuit (mask option) is not provided to m pd6604 item m pd66p04b m pd6604 rom one-time prom mask rom oscillation stabilization wait time ? on releasing stop mode by release 260/f osc 36/f osc condition ? on releasing stop or halt mode by 284/f osc to 340/f osc 60/f osc to 116/f osc reset input and at reset v pp pin and operating mode select pin provided not provided poc circuit incorporated not provided supply voltage v dd = 2.2 to 3.6 v v dd = 1.8 to 3.6 v (t a = C40 to +85 c) (t a = C40 to +85 c) system clock frequency ?f osc = 300 to 500 khz ?f osc = 300 to 500 khz ?f osc = 500 khz to 1mhz note ? f osc = 300 khz to 1 mhz (v dd = 2.2 to 3.6 v) electrical specifications some electrical specifications, such as data retention voltage and current consumption, differ. for details, refer to data sheet of each model. note it is necessary to design the application circuit so that the reset pin goes low when the supply voltage is less than 2.2 v.
10 m pd66p04b data sheet u13596ej2v1ds00 3. writing and verifying one-time prom (program memory) the program memory of the m pd66p04b is a one-time prom of 1002 10 bits. to write or verify this one-time prom, the pins shown in table 3-1 are used. note that no address input pin is used. instead, the address is updated by using the clock input from the clk pin. table 3-1. pins used to write/verify program memory pin name function v pp supplies voltage when writing/verifying program memory. apply +12.5 v to this pin. v dd power supply. supply +6 v to this pin when writing/verifying program memory. clk inputs clock to update address when writing/verifying program memory. by inputting pulse four times to clk pin, address of program memory is updated. md 0 -md 3 input to select operation mode when writing/verifying program memory. d 0 -d 7 inputs/outputs 8-bit data when writing/verifying program memory. osc in , osc out clock necessary for writing program memory. connect a resistor (r = 47 k w ) and a capacitor (c = 27 pf) to these pins. 3.1 operating mode when writing/verifying program memory the m pd66p04b is set in the program memory write/verify mode when +6 v is applied to the v dd pin and +12.5 v is applied to the v pp pin after the m pd66p04b has been in the reset status (v dd = 5 v, v pp = 0 v) for a specific time. in this mode, the operating modes shown in table 3-2 can be set by setting the md 0 through md 3 pins. connect all the pins other than those shown in table 3-1 to gnd via pull-down resistor. table 3-2. setting operation mode setting of operating mode operation mode v pp v dd md 0 md 1 md 2 md 3 +12.5 v +6 v h l h l clear program address to 0 l h h h write mode l l h h verify mode h h h program inhibit mode : dont care (l or h)
11 m pd66p04b data sheet u13596ej2v1ds00 3.2 program memory writing procedure the program memory is written at high speed in the following procedure. (1) pull down the pins not used to gnd via resistor. keep the clk pin low. (2) supply 5 v to the v dd pin. keep the v pp pin low. (3) supply 5 v to the v pp pin after waiting for 10 m s. (4) wait for 2 ms until oscillation of the clock connected across the osc in and osc out pins stabilizes. (5) set the program memory address 0 clear mode by using the mode setting pins. (6) supply 6 v to v dd and 12.5 v to v pp . (7) set the program inhibit mode. (8) write data to the program memory in the 1-ms write mode. (9) set the program inhibit mode. (10) set the verify mode. if the data have been written to the program memory, proceed to (11). if not, repeat steps (8) through (10). (11) additional writing of (number of times of writing in (8) through (10): x) 1 ms. (12) set the program inhibit mode. (13) input a pulse to the clk pin four times to update the program memory address (+1). (14) repeat steps (8) through (13) up to the last address. (15) set the 0 clear mode of the program memory address. (16) change the voltages on the v dd and v pp pins to 5 v. (17) turn off power. the following figure illustrates steps (2) through (13) above. repeated x time reset oscillation stabilization wait time write verify additional write address increment data input hi-z hi-z hi-z data output data input hi-z v pp v dd gnd v dd +1 v dd gnd clk v pp d 0 -d 7 md 0 md 1 md 2 md 3 v dd
12 m pd66p04b data sheet u13596ej2v1ds00 3.3 program memory reading procedure (1) pull down the pins not used to gnd via resistor. keep the clk pin low. (2) supply 5 v to the v dd pin. keep the v pp pin low. (3) supply 5 v to the v pp pin after waiting for 10 m s. (4) wait for 2 ms until oscillation of the clock connected across the osc in and osc out pins stabilizes. (5) set the program memory address 0 clear mode by using the mode setting pins. (6) supply 6 v to v dd and 12.5 v to v pp . (7) set the program inhibit mode. (8) set the verify mode. data of each address is output sequentially each time the clock pulse is input to the clk pin four times. (9) set the program inhibit mode. (10) set the program memory address 0 clear mode. (11) change the voltage on the v dd and v pp pins to 5 v. (12) turn off power. the following figure illustrates steps (2) through (10) above. reset oscillation stabilization wait time hi-z hi-z v pp v dd gnd v dd +1 v dd gnd clk v pp d 0 -d 7 md 0 md 1 md 2 md 3 data output data output "l" v dd
13 m pd66p04b data sheet u13596ej2v1ds00 4. electrical specifications absolute maximum ratings (t a = +25 c) parameter symbol test conditions rating unit power supply voltage v dd C0.3 to +7.0 v v pp C0.3 to +13.5 v input voltage v i k i/o , k i , s 0 , s 1 , reset C0.3 to v dd + 0.3 v output voltage v o C0.3 to v dd + 0.3 v high-level output current i oh note rem peak value C30 ma rms C20 ma led peak value C7.5 ma rms C5 ma one k i/o pin peak value C13.5 ma rms C9 ma total of led and k i/o pins peak value C18 ma rms C12 ma low-level output current i ol note rem peak value 7.5 ma rms 5 ma led peak value 7.5 ma rms 5 ma operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c note work out the rms with: [rms] = [peak value] duty. caution product quality may suffer if the absolute rating is exceeded for any parameter, even momen- tarily. in other words, an absolute maxumum rating is a value at which the possibility of psysical damage to the product cannnot be ruled out. care must therefore be taken to ensure that the these ratings are not exceeded during use of the product. recommended power supply voltage range (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit power supply voltage v dd f osc = 300 to 500 khz 2.2 3.0 3.6 v f osc = 500 khz to 1 mhz note 2.2 3.0 3.6 v note it is necessary to design the application circuit so that the reset pin goes low when the supply voltage is less than 2.2 v.
14 m pd66p04b data sheet u13596ej2v1ds00 dc characteristics (t a = C40 to +85 c, v dd = 2.2 to 3.6 v) parameter symbol test conditions min. typ. max. unit high-level input voltage v ih1 reset 0.8 v dd v dd v v ih2 k i/o 0.65 v dd v dd v v ih3 k i , s 0 , s 1 0.65 v dd v dd v low-level input voltage v il1 reset 0 0.2 v dd v v il2 k i/o 0 0.3 v dd v v il3 k i , s 0 , s 1 0 0.15 v dd v high-level input i lh1 k i 3 m a leakage current v i = v dd , pull-down resistor not incorporated i lh2 s 0 , s 1 3 m a v i = v dd , pull-down resistor not incorporated low-level input leakage i ul1 k i v i = 0 v C3 m a current i ul2 k i/o v i = 0 v C3 m a i ul3 s 0 , s 1 v i = 0 v C3 m a high-level output voltage v oh1 rem, led, k i/o i oh = C0.3 ma 0.8 v dd v low-level output voltage v ol1 rem, led i ol = 0.3 ma 0.3 v v ol2 k i/o i ol = 15 m a 0.4 v high-level output current i oh1 rem v dd = 3.0 v, v oh = 1.0 v C5 C9 ma i oh2 k i/o v dd = 3.0 v, v oh = 2.2 v C2.5 C5 ma low-level output current i ol1 k i/o v dd = 3.0 v, v ol = 0.4 v 30 70 m a v dd = 3.0 v, v ol = 2.2 v 100 220 m a built-in pull-up resistor r 1 reset 25 50 100 k w built-in pull-down resistor r 2 reset 2.5 5 15 k w r 3 k i , s 0 , s 1 75 150 300 k w r 4 k i/o 130 250 500 k w data hold power supply v dddr in stop mode 1.2 3.6 v voltage supply current note i dd1 operating f osc = 1.0 mhz, v dd = 3 v 10 % 0.6 1.2 ma mode f osc = 455 khz, v dd = 3 v 10 % 0.5 1.0 ma i dd2 halt mode f osc = 1.0 mhz, v dd = 3 v 10 % 0.5 1.0 ma f osc = 455 khz, v dd = 3 v 10 % 0.4 0.8 ma i dd3 stop mode v dd = 3 v 10 % 1.0 8.0 m a v dd = 3 v 10 %, t a = 25 c 1.0 2.0 m a note the poc circuit current and the current flowing in the built-in pull-up resistor are not included.
15 m pd66p04b data sheet u13596ej2v1ds00 ac characteristics (t a = C40 to +85 c, v dd = 2.2 to 3.6 v) parameter symbol test conditions min. typ. max. unit instruction execution time t cy 15.9 27 m s note 1 7.9 27 m s k i , s 0 , s 1 high-level width t h 10 m s when canceling standby mode halt mode 10 m s stop mode note 2 m s reset low-level width t rsl 10 m s notes 1. when using at f osc = 500 khz or higher, it is necessary to design the application circuit so that the reset pin goes low when the supply voltage is less than 2.2 v. 2. 10 + 260/f osc remark t cy = 8/f osc (f osc : system clock oscillator frequency) poc circuit note 1 (t a = C20 to +70 c) parameter symbol test conditions min. typ. max. unit poc-detected voltage note 2 v poc 1.8 2.0 2.2 v poc circuit current i poc 1.2 1.5 m a notes 1. operates effectively under the conditions of f osc = 300 to 500 khz. 2. refers to the voltage with which the poc circuit cancels an internal reset. if v poc < v dd , the internal reset is canceled. from the time of v poc 3 v dd until the internal reset takes effect, lag of up to 1 ms occurs. when the period of v poc 3 v dd lasts less than 1 ms, the internal reset may not take effect. system clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.2 to 3.6 v) parameter symbol test conditions min. typ. max. unit oscillator frequency f osc 300 455 500 khz note 300 455 1000 khz note when using at f osc = 500 khz or higher, it is necessary to design the application circuit so that the reset pin goes low when the supply voltage is less than 2.2 v. recommended oscillator constant (t a = C40 to +85 c, v dd = 2.2 to 3.6 v) parameter symbol test conditions min. typ. max. unit capacity of oscillation c 22 27 33 pf capacitor oscillation resistance r 47 k w an external circuit example osc in osc out c r
16 m pd66p04b data sheet u13596ej2v1ds00 prom programming mode dc programming characteristics (t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v) parameter symbol test conditions min. typ. max. unit high-level input voltage v ih1 other than clk 0.7 v dd v dd v v ih2 clk v dd C0.5 v dd v low-level input voltage v il1 other than clk 0 0.3 v dd v v il2 clk 0 0.4 v input leakage current i li v in = v il or v ih 10 m a high-level output voltage v oh i oh = C1 ma v dd C1.0 v low-level output voltage v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 30 ma v pp supply current i pp md 0 = v il , md 1 = v ih 30 ma cautions 1. keep v pp to within +13.5 v including overshoot. 2. apply v dd before v pp and turns it off after v pp .
17 m pd66p04b data sheet u13596ej2v1ds00 ac programming characteristics (t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v) parameter symbol note1 test conditions min. typ. max. unit address setup time note 2 (vs. md 0 )t as t as 2 m s md 1 setup time (vs. md 0 )t m1s t oes 2 m s data setup time (vs. md 0 )t ds t ds 2 m s address hold time note 2 (vs. md 0 - )t ah t ah 2 m s data hold time (vs. md 0 - )t dh t dh 2 m s md 0 -? data output float delay time t df t df 0 130 ns v pp setup time (vs. md 3 - )t vps t vps 2 m s v dd setup time (vs. md 3 - )t vds t vcs 2 m s initial program pulse width t pw t pw 0.95 1.0 1.05 ms additional program pulse width t opw t opw 0.95 21.0 ms md 0 setup time (vs. md 1 - )t mos t ces 2 m s md 0 ? data output delay time t dv t dv md0 = md1 = v il 1 m s md 1 hold time (vs. md 0 - )t m1h t oeh t m1h +t m1r 3 50 m s2 m s md 1 recovery time (vs. md 0 )t m1r t or 2 m s program counter reset time t pcr C10 m s clk input high-, low-level width t xh , t xl C 0.125 m s clk input frequency f x C 8 mhz initial mode set time t i C2 m s md 3 setup time (vs. md 1 - )t m3s C2 m s md 3 hold time (vs. md 1 )t m3h C2 m s md 3 setup time (vs. md 0 )t m3sr C when program memory is read 2 m s address note 2 ? data output delay time t oad t acc when program memory is read 2 m s address note 2 ? data output hold time t had t oh when program memory is read 0 130 ns md 3 hold time (vs. md 0 - )t m3hr C when program memory is read 2 m s md 3 ? data output float delay time t dfr C when program memory is read 2 m s reset setup time t res C10 m s oscillation stabilization wait time note 3 t wait C2ms notes 1. equivalent symbol of the corresponding m pd27c256a (the m pd27c256a is a maintenance product.) 2. the internal address signal is incremented at the falling edge of the third clock of clk. 3. connect a resistor (r = 47 k w ) and a capacitor (c = 27 pf) between the osc in and osc out pins.
18 m pd66p04b data sheet u13596ej2v1ds00 program memory write timing program memory read timing t m3s t pcr t m1s t m1h t pw t m1r t mos t opw t m3h data input data output data input data input t ds t dh t dv t df t ds t dh t xl t xh t vps t vds t wait t res t t hi-z hi-z hi-z hi-z hi-z t ah t as v pp v dd gnd v dd +1 v dd gnd clk v pp v dd d 0 -d 7 md 0 md 1 md 2 md 3 t m3sr t pcr data output t dv t mad t vds t i hi-z hi-z "l" t m3hr v pp v dd gnd v dd +1 v dd gnd clk v pp d 0 -d 7 md 0 md 1 md 2 md 3 t dad t xl data output t dfr t xh t wait t res t vps v dd
19 m pd66p04b data sheet u13596ej2v1ds00 5. characteristic curve (reference values) i ol vs v ol (rem, led) low-level output current i ol [ma] low-level output voltage v ol [v] i oh vs v oh (rem) high-level output current i oh [ma] high-level output voltage v oh [v] i oh vs v oh (led) high-level output current i oh [ma] high-level output voltage v oh [v] 10 0.6 1.8 2.4 3 1.2 9 8 7 6 5 4 3 2 1 0 ?0 v dd ? 0.6 v dd ? 1.8 v dd ? 2.4 v dd ? 3 v dd ? 1.2 ?8 ?6 ?4 ?2 ?0 ? ? ? ? 0 v dd ?0 v dd ? 0.6 v dd ? 1.8 v dd ? 2.4 v dd ? 3 v dd ? 1.2 ? ? ? ? ? ? ? ? ? 0 v dd (t a = 25 c, v dd = 3.0 v) (t a = 25 c , v dd = 3.0 v) (t a = 25 c , v dd = 3.0 v) i dd vs v dd power supply current i dd [ma] power supply voltage v dd [v] (t a = 25 c) 1100 1000 900 800 700 600 500 400 1.2 2.4 3.0 4.2 3.6 1.8 f osc vs v dd oscillator frequency fosc [khz] power supply voltage v dd [v] (c = 27 pf, t a = 25 c) r = 47 k w r = 22 k w 1.2 1.0 0.8 0.6 0.4 0.2 0 1.8 2.4 3.0 1 mhz operating mode 1 mhz halt mode 455 khz operating mode 455 khz halt mode 3.6 4.2 2.2
20 m pd66p04b data sheet u13596ej2v1ds00 i ol vs v ol ( k i/o ) low-level output current i ol [ a] low-level output voltage v ol [v] i oh vs v oh ( k i/o ) high-level output current i oh [ma] high-level output voltage v oh [v] 320 0.6 1.8 2.4 3 1.2 0 ?5 v dd ? 0.6 v dd ? 1.8 v dd ? 2.4 v dd ? 3 v dd ? 1.2 0 v dd 280 240 200 160 120 80 40 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? (t a = 25 c, v dd = 3.0 v) (t a = 25 c, v dd = 3.0 v) m
21 m pd66p04b data sheet u13596ej2v1ds00 6. applied circuit example example of application to system ? remote-control transmitter (40 keys; mode selection switch accommodated) ? remote-control transmitter (48 keys accommodated) remark when the poc circuit is used effectively, it is not necessary to connect the capacitor enclosed in the dotted lines. k i/o6 k i/o7 s 0 s 1 /led rem v dd osc out osc in gnd reset k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0 key matrix 8 5 = 40 keys mode selection switch + + r c k i/o6 k i/o7 s 0 s 1 /led rem v dd osc out osc in gnd reset k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 k i3 k i2 k i1 k i0 key matrix 8 6 = 48 keys + + r c
22 m pd66p04b data sheet u13596ej2v1ds00 7. package drawings (1) m pd66p04bgs 110 11 20 s - 3 item millimeters a b c e f g h j 12.7 0.3 1.27 (t.p.) 1.8 max. 1.55 0.05 7.7 0.3 0.78 max. 0.12 1.1 m 0.1 0.1 n p20gm-50-300b, c-7 p3 + 7 note each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. d 0.42 + 0.08 - 0.07 k 0.22 + 0.08 - 0.07 l 0.6 0.2 0.10 detail of lead end i 5.6 0.2 m p g c b d e f n 20-pin plastic sop (7.62 mm (300)) s m h k l j i a
23 m pd66p04b data sheet u13596ej2v1ds00 (2) m pd66p04bgs-gjg 20 11 110 s s 20-pin plastic ssop (7.62 mm (300)) note each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. item millimeters c 0.575 max. b 6.7 0.3 a 0.65 (t.p.) e 0.125 0.075 f 2.0 max. g 1.7 0.1 h 8.1 0.3 m 0.12 n 0.10 i 6.1 0.2 j 1.0 0.2 l 0.5 0.2 k 0.15 + 0.10 - 0.05 p3 + 7 - 3 d 0.32 + 0.08 - 0.07 p20gm-65-300b-4 k l g p dm b j detail of lead end n a i m f e c h
24 m pd66p04b data sheet u13596ej2v1ds00 8. recommended soldering conditions carry out the soldered packaging of this product under the following recommended conditions. for details of the soldering conditions, refer to information material semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than the recommended conditions, please consult one of our nec sales representatives. table 8-1. soldering conditions for surface-mount type m pd66p04bgs : 20-pin plastic sop (7.62 mm (300)) m pd66p04bgs-gjg: 20-pin plastic ssop (7.62 mm (300)) soldering method soldering condition recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 secs. max. (210 c min.), ir35-00-2 number of times: twice max. vps package peak temperature: 215 c, time: 40 secs. max. (200 c min.), vp15-00-2 number of times: twice max. wave soldering solder bath temperature: 260 c max., time: 10 secs. max., ws60-00-1 number of times: once, preheating temperature: 120 c max. (package surface temperature.) partial heating pin temperature: 300 c or less ; time: 3 secs or less (for each side of the device) caution do not use two or more soldering methods in combination (except partial heating).
25 m pd66p04b data sheet u13596ej2v1ds00 appendix a. development tools a prom programmer, program adapter, and emulator are provided for the m pd66p04b. hardware prom programmer (af-9706 note , af-9708 note , af-9709 note ) this prom programmer supports the m pd66p04b. by connecting a program adapter to this prom programmer, the m pd66p04b can be programmed. note these are products of ando electric. for details, consult ando electric (03-3733-1163). program adapter (pa-61p34, pa-61p34bmc) it is used to program the m pd66p04b in combination with af-9706, af-9708, or af-9709. emulator (eb-6133 note ) it is used to emulate the m pd66p04b. note this is a product of naito densei machida mfg. co., ltd. for details, consult naito densei machida mfg. co., ltd. (044-822-3813). software assembler (as6133) ? this is a development tool for remote control transmitter software. part number list of as6133 host machine os supply medium part number pc-9800 series ms-dos tm (ver. 5.0 to ver. 6.2) 3.5-inch 2hd m s5a13as6133 (cpu: 80386 or more) ibm pc/at tm compatible ms-dos (ver. 6.0 to ver. 6.22) 3.5-inch 2hc m s7b13as6133 pc dos tm (ver. 6.1 to ver. 6.3) caution although ver.5.0 or later has a task swap function, this function cannot be used with this software.
26 m pd66p04b data sheet u13596ej2v1ds00 appendix b. example of remote-control transmission format (in the case of nec transmission format in command one-shot transmission mode) caution when using the nec transmission format, please apply for a custom code at nec. (1) rem output waveform (from <2> on, the output is made only when the key is kept pressed.) remark if the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (led) can be reduced by sending the reader code and the stop bit from the second time. (2) enlarged waveform of <1> (3) enlarged waveform of <3> rem output 9 ms 13.5 ms 0 4.5 ms 1100 2.25 ms 1.125 ms 0.56 ms (4) enlarged waveform of <2> rem output 58.5 to 76.5 ms 108 ms 108 ms < 1 > < 2 > rem output 13.5 ms leader code 9 ms 4.5 ms custom code 8 bits custom code' 8 bits data code 8 bits data code 8 bits 27 ms 18 to 36 ms 58.5 to 76.5 ms stop bit 1 bit < 3 > rem output 9 ms 11.25 ms 2.25 ms 0.56 ms stop bit leader code
27 m pd66p04b data sheet u13596ej2v1ds00 (5) carrier waveform (enlarged waveform of each codes high period) (6) bit array of each code caution to prevent malfunction with other systems when receiving data in the nec transmission format, not only fully decode (make sure to check data code as well) the total 32 bits of the 16-bit custom codes (custom code, custom code) and the 16-bit data codes (data code, data code) but also check to make sure that no signals are present. rem output 8.77 s 9 ms or 0.56 ms carrier frequency : 38 khz 26.3 s m m c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 0 ' c 0 or c o c 1 ' c 1 or c 1 c 2 ' c 2 or c 2 c 3 ' c 3 or c 3 c 4 ' c 4 or c 4 c 5 ' c 5 or c 5 c 6 ' c 6 or c 6 c 7 ' c 7 or c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 = = = = = = = = data code data code custom code' custom code leader code
28 m pd66p04b data sheet u13596ej2v1ds00 [memo]
29 m pd66p04b data sheet u13596ej2v1ds00 [memo]
30 m pd66p04b data sheet u13596ej2v1ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
31 m pd66p04b data sheet u13596ej2v1ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
m pd66p04b ms-dos is either a registered trademark or a trademark of microsoft corporation in the united states and/ or other countries. pc/at and pc dos are trademarks of ibm corp. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of july, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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