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elan microelectronics corp. page 1 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 240 channel common driver for dot matrix stn liquid crystal display with high voltage drive EM65H137 contents 1. general description 2 2. feature 2 3. applications 2 4. pin configurations (package) 3 5. functional block diagram 3 6. pin descriptions 4 7. function description 7 8. absolute maximum rating 10 9. dc electrical characteristics 11 10. ac electrical characteristics 12 11. timing diagrams 13 12. application circuit 14
elan microelectronics corp. page 2 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 general description the EM65H137 is a 240-channel common driver which drives a dot matrix stn liquid crystal panel. by changing the mode, this can be applied to 240- and 200- and 160- channel output. through the use of a 43v high-voltage cmos process technology, a high-voltage drive of +21.5 v and -21.5 v, centering on vm is possible. -21.5v is generated from max +21.5v with built-in switching circuit and external capacity. 3 v is used for logic drive. this device is used together with the segment driver em65h130 or em65h134. feature display duty: up to 1 / 240 lcd drive voltage: 43 v max built-in 240 bits bi-directional shift register built-in switching circuit (to generate -21.5v) number of lcd drive circuit: 240 operating voltage: 2.5 to 5.5 v intermediate voltage i/f built-in alternating signal generation circuit pin programmable, output mode change: 240-output mode 200-output mode 160-output mode built-in display-off function: when /dspof is ?l?, all lcd drive output remain at the vm level. flex tcp applications pda dictionary message display product
elan microelectronics corp. page 3 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 pin configurations (package) vlcdl vhl vml vll veel veo c1 c2 eio2 fr rst frs4 frs3 frs2 frs1 frs0 vdd m1 m0 /doc dspof amp dir vss lp clp m/s eio1 veer vlr vmr vhr vlcdr c1 c2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . c239 c240 top view EM65H137 tcp package 273 ----------------------------------------------------------------------------------------------241 1---------------------------------------------------------------------------------------------------------------------240 figure1. tcp package pin arrangement functional block diagram liquid crystal display driver circuit 240-bits bidirectional shift register level shifter 3 3 240 c1 to c240 vhr,vmr,vlr fr /d spo f 240 bits level shifter 240 vhl,vml,vll alternating signal generating circuit /r st frs0~frs4 clock control & data direction control switch circuit clp amp veo c1,c2 e i o 2 e i o 1 d i r m 1 d m s m 0 l p vlcdr,l veer,l v d d v s s / d o c figure 2. system block diagram
elan microelectronics corp. page 4 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 pin descriptions table 1. pin arrangement pin no. symbol i/o description 1 to 240 c1?c240 o lcd driver output 241,273 vlcdr, vlcdl - 242,272 vhr, vhl - 243,271 vmr, vml - 244,270 vlr, vll - 245,269 veer, veel - power supply for lcd driver 246 265 eio1 eio2 i/o serial data input / output pin 247 dms i controls the display-off function and display-off signal output from /doc pin. 248 clp i built-in switching circuit clock input. 249 lp i shift clock input for segment mode 250 vss i ground (0v) 251 dir i display data shift direction selection 252 swc i built-in switching circuit on-off control. 253 /dspof i control input for deselect output level 254 /doc o display off control pin for segment driver. 256 255 m1 m0 i mode select for the number of lcd drive output pins. 257 vdd i power supply for logic system 258~262 frs0~frs4 i this pin specifies the cycle of the alternating signal, fr signal in the unit of the number of lines(lp signal) 263 rst i setting this pin to initializes the fr signal circuit 264 fr i/o ac-converting signal input for lcd driver waveform 265 c2 - capacitance 266 c1 - capacitance 267 veo o voltage output of built-in switching circuit
elan microelectronics corp. page 5 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 table 2. pin descriptions symbol i/o connect to description vlcdl, r veel, r i power supply lcd driver output vhl,r vml,r vll,r i power supply power supply for lcd driver level select level : vh,vl non-select level : vm vdd vss i power supply power supply for internal logic system veo o vee when using built-in switching circuit to generate vee, vm voltage is point of reference. vlcd - vm voltage is reversed and output as vee. if switching circuit not used, set this pin to open, don?t connect to any pin c1 c2 - - when using built-in switching circuit to generate vee, should be connected, or it don?t connect. lp i controller shift clock for bi-directional shift register, data is shifted on the falling edge of the clock fr i/o controller or open ac signal for lcd drive the lcd driver output voltage level can be set by line latch output signal and fr signal it can be produced by internal function of frs0~frs4 fr s0 fr s1 fr s2 fr s3 fr s4 i vdd/vss this pin specifies the cycle of the alternating signal, fr signal in the unit of the number of lines. the number of lines, which is an integer from 2 to 31, is specified as follows. usually, specify the number of lines within a range from 10 to 31. when the EM65H137 is driven by an external alternating signal, specify the number of lines as zero. m0 m1 i vdd/vss switch terminals for the number of lcd drive output pins. m0 m1 description(dir=?h?) h h 240 output (c1-c240) h l 200 output (c21-c220) l h 160 output (c41-c200) l l prohibited eio1 eio2 i controller data input/output shift for bi-directional shift register dir eio1 eio2 h output input l input output clp i lp/vss when using built-in switching circuit and generating vee, this pin connect lp pin. if built-in switching circuit is not used, clp must be fixed to vss. /rst i controller /rst description h normal status l initializes the fr signal circuit /dspof i controller control signal for output deselect level B when the signal is low the output (c1 ? c240) of lcd driver be set to level vm the internal register is not cleared B when the signal is high, returns to the normal status. dms i vdd/vss display-off function mode selection. dms description h when /dspof is low level, c1-c240 set vm level. l until 16 times serial data is into eio, c1-c240 set vm level.
elan microelectronics corp. page 6 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 continuous table 2 symbol i/o connect to description /doc o - display off control pin for segment driver., when using dms is low level , /doc pin should be connected to segment lsi display off control pin. when dms=?h? , /dspof=?h?, /doc output ?h? level /dspof=?l? , /doc output ?l? level. when m/s = ?l?,. until 16 times serial data is into dio, c1-c240 set to vm level. dir i vdd/vss directional selection of bi-directional shift register dir m0 m1 shift direction h h h c1 to c240 l h h c240 to c1 h h l c21 to c220 l h l c220 to c21 h l h c41 to c200 l l h c200 to c41 x l l prohibited x: don?t care swc i vdd/vss built-in switch circuit control when using built-in switching circuit, this pin must be fixed to vdd, or this pin must be fixed to vss c1 to c240 o lcd panel lcd driver output. by a combination of the display data and the fr signal, when /dspof is set to vdd, either vh, vl, or vm is selected and transmitted to the output circuit.
elan microelectronics corp. page 7 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 function description . clock control and data direction control this circuit controlled the input/output data of bi-directional pins, direction of data shift and display off function for segment driver (/doc signal) . line shift register this is 240-bits shift register circuit. the shift direction is determined by dir pin. the first data is from eio1 and eio2 pin, shifts data from the data input pin on the falling edge of the lp signal. . level shifter the logic voltage signal is boost to the lcd driver voltage level, and output to the driver block. . 3-level driver drive the lcd driver output pins from the line shift register data, selecting one of 3 levels (vh, vm, vl) based on the fr and /dspof signals . alternating signal generating circuit this circuit generate fr signal for lcd driver to suppress cross-talk. the number of lines, which is an integer from 2 to 31, is specified by frs0~frs5. when the EM65H137 is driven by an external alternating signal, specify the number of lines as zero. . switch circuit a high voltage driver of vh and vl centering on vm, vh is generated from vh with built-in switch circuit and external capacity. . relation between fr, data input and liquid crystal display driver output voltage level, explain as following table 3: table 3. liquid crystal display driver output voltage level fr latch data /dspof driver output voltage level h h h vl h l h vm l h h vh l l h vm x x l vm vl elan microelectronics corp. page 8 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 . relationship between the display data and driver output pin table 4. . relationship between the display data and driver output pin dir m0 m1 data transfer direction eio 1 eio 2 h h c1 c240 h l c21 c220 h l h c41 c200 output input h h c240 c1 h l c220 c21 l l h c200 c41 input output x l l prohibited x x x: don?t care . example of power supply circuit dc/dc converter +21.5v vdd=3.0 to 5 v 2.7 to 5.5 v vss vdd v0 vm v1 vss segment driver (em65h134) (em65h130) common driver (EM65H137) vh veo vl vee c1 c2 + - + - + - external capacitor (ca,cb) (2.2~4.7uf) ca cb vlcd vm vdd vss figure 3. power supply circuit example
elan microelectronics corp. page 9 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 . precaution when connecting or disconnecting the power. this lsi has a high voltage lcd driver, so it may be permanently damaged by a high current which may flow if a voltage is supplied to the lcd driver power supply while the logic system power supply is floating. when connecting or disconnecting the power supply, show the following recommend sequence. 0ms 0ms 0ms 0ms 0ms 0ms 0ms vcc vlcd,vh vm vee,vl /dspof input signal clock, or data undefine initialization figure 4.sequence for connecting or disconnecting the power supply
elan microelectronics corp. page 10 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 absolute maximum rating table 5 absolute maximum ratings parameter symbol conditions applicable pins ratings unit supply voltage (1) vdd vdd -0.3 to +7.0 v vlcd vlcdl, vlcdr -0.3 to +25.0 v supply voltage (2) vee veel, veer -20.0 to +0.3 v input voltage (1) v i logic input pin -0.3 to vdd+0.3 v input voltage (2) vh vhl, vhr -0.3 to vlcd v input voltage (3) vm vml, vmr -0.3 to +5.0 v input voltage (4) vl vll, vlr +0.3 to vee v operating temperature topr -30 to +75 storage temperature tstg ta=25 referenced to vss (0v) -45 to +125
elan microelectronics corp. page 11 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 dc electrical characteristics table 6.dc characteristics of common mode (vss=0v, vdd=+2.5 to 5.5v, ta = -20~85c) parameter symbol conditions applicable pins min. typ. max. unit v ih 0.8v dd v input voltage v il lp, dir, fr, m1, m0, eio1, eio2, /dspof, frs0-4, /rst, dms , /doc , clp , swc 0.2v dd v v oh i oh = -0.4ma v dd -0.4 v output voltage v ol i ol = +0.4ma eio 1 , eio 2 , fr , /doc +0.4 v i lih v i =v dd +5 a input leakage current i lil v i =v ss lp, dir, fr, m1, m0, eio1, eio2, /dspof, frs0-4, /rst, dms , /doc , clp , swc -5 a output resistance r on i on =150ua c1-c240 0.7 2.0 k stand-by current i stb *1 v ss 2.0 a consumed current (1) i dd *2 v dd 10 40 a consumed current (2) i dd *3 v dd 20 50 a consumed current(3) i lcd *2 v 0 20 35 a note: 1. v dd = +5v, vlcd-vee=40v, v i = v ss 2. v dd = +3.3v, vlcd-vee=40v, v i = v ss , f lp =19.2khz, f fr =1.5khz. 3. v dd = +5v, vlcd-vee=40v, v i = v ss , f lp =19.2khz, f fr =1.5khz.
elan microelectronics corp. page 12 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 ac electrical characteristics table 7. ac characteristics of common driver timing 1, vcc=2.5 to 5.5v, vlcd-vee=15 to 43v, ta=-30~+75 item symbol pin name min. max. unit. note. clock cycle time tcyc lp 400 -- ns lp high-level width tcwh lp 25 -- ns lp low-level width tcwl lp 370 -- ns lp rising time tr lp -- 30 ns lp falling time tf lp -- 30 ns data setup time tds eio1, eio2, lp 100 -- ns data hold time tdh eio1, eio2, lp 0 -- ns data output delay time tdd eio1, eio2, lp -- 150 ns *1 fr output delay time tmd fr, lp -- 150 ns *1 fr setup time tms fr, lp 20 -- ns fr hold time tmh fr, lp 20 -- ns /doc delay time 1 tdoc1 /dspof, /doc -- 300 ns *2 /doc delay time 2 tdoc2 eio1, eio2, /doc -- 300 ns *2 table 8. ac characteristics of common driver timing 2, vcc=2.5 to 5.5v, vlcd-vee=15 to 43v, ta=-30~+75 item symbol pin name min. max. unit. note. output delay time 1 tpd1 c(n), fr -- 1.2 us *2 table 9. ac characteristics of common driver timing 3, vcc=2.5 to 5.5v, vlcd-vee=15 to 43v, ta=-30~+75 item symbol pin name min. max. unit. note. output delay time 2 tpd2 c(n), fr -- 1.2 us *2 notes: *1.defined by connecting the load circuit shown in next figure *2.defined by connecting the load circuit shown in next figure test point *1:30pf *2:100pf figure 5. load circuit
elan microelectronics corp. page 13 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 timing diagrams t f t r t cw h t cyc t ds t dh t dd t md t pd1 lp eio1 eio2 eio1 eio2 fr c (n) (a) ac characteristics of common driver timing 1 t mh t ms lp fr (during input) (b) ac characteristics of common driver timing 2 t doc1 t doc2 /dspof eio1 eio2 (during input) /doc (c) ac characteristics of common driver timing 3 figure 6. ac timing
elan microelectronics corp. page 14 Yx????? , ??S??}?D?? all rights strictly reserved, any portion in this paper shall not be repro duced, copied without permission. ??? 1.2 ? / l? 2001/7/16 application circuit lcd panel 320 * 3 *240 1/240 duty eio2 eio1 dir cc1~cc4 /dspof d0~d7 fr xck lp v1l,r vml,r v0l,r vdd gnd em 65h134 eio2 eio1 dir cc1~cc4 /dspof d0~d7 fr xck lp v1l,r vml,r v0l,r vdd gnd em 65h134 (n 0 . 1) eio2 eio1 dir cc1~cc4 /dspof d0~d7 fr xck lp v1l,r vml,r v0l,r vdd gnd em 65h134 (n 0 . 4) (n 0 . 2) seg1 seg2 seg3 seg240 seg239 seg238 ----------------------------- seg241 seg242 seg243 seg480 seg479 seg478 ----------------------------- seg721 seg722 seg723 seg960 seg959 seg958 ----------------------------- ~~~~~~~~~~~~~~~~~ ~ vdd vdd vdd s240 ~ s1 s240 ~ s1 s240 ~ s1 c1 ~ c240 lp clp /rst /dspof amp m/s /doc fr frs0~frs4 vhl,r vml,r dir vll,r lcd controller power supply circuit eio1 eio2 vlcdl,r gnd veel,r veo vdd c1 c2 correction circuit figure 7. application circuit

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