View EM65H134_2385282.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

elan microelectronics corp. page 1 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 240 channel segment driver for dot matrix stn liquid crystal display with low voltage drive EM65H134 contents 1. general description 2 2. feature 2 3. applications 2 4. pin configurations (package) 3 5. functional block diagram 4 6. pin des criptions 5 7. function description 7 8. absolute maximum rating 16 9. dc electrical characteristics 18 10. ac electrical characteristics 20 1 1 . timing diagrams 21 1 2 . application circuit 22
elan microelectronics corp. page 2 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 general description the EM65H134 is a 2 40 - channel segment lcd driver lsi, which drives a dot matrix stn liquid crystal display at low power. the EM65H134 operates with a low 5v lcd drive voltage and a low 3v logic voltage. the EM65H134 includes shadowing correction circuit in order to improve i mage quality. the EM65H134 is packaged in a fine pitch slim tcp( slim type carrier package) technology, it is deal for substantially decreasing the size of lcd module frame. feature - duty cycle: up to 1/300 - lcd drive voltage: 3.5 to 5.5 v - 240 lcd drive circuits - operating voltage: 2.7 to 5.5 v - eight data bits - shift clock speed ?x 25 mhz max/3 v ?x 40 mhz max/5 v - shadowing correction circuit - display - off function - slim - tcp ?x output lead pitch: 70 g m ?x user area: 5.5mm - automatic genera tion of the chip enable signal - standby function applications - pda - dictionary - message display product
elan microelectronics corp. page 3 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 p in configuration s 1 s 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . s 2 3 9 s 2 4 0 EM65H134 top view 267--------------------------------------------------------------------------------------------241 1----------------------------------------------------------------------------------------------------------------------240 d i r e i o 1 / d s p o f d i 0 d i 1 d i 2 d i 3 d i 4 d i 5 d i 6 d i 7 x c k l p f r e i o 2 c c 1 c c 2 c c 3 c c 4 v s s v 1 r v 0 r v m r v m l v 0 l v 1 l v d d note: the pin configuration is lsi chip, not tcp. figure1. pin configuration
elan microelectronics corp. page 4 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 functional block diagram 240 bits 3-level driver (liquid crystal display driver circuit) correction circuit line latch circuit shift register data latch .... fr /dspof 3 3 8 8 8 8 8 8 8 240 240 data shift and arithmetic circuit lp xck dir eio2 eio1 v 0r v 0l 240 239 2 1 , ........, .......... .......... ,......... , s s s s 8 240 di0~di7 cc1~cc4 dd v ss v v 1r , v mr , v 1l , v ml , 8 figure 2. block diagram
elan microelectronics corp. page 5 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 pin descriptions table1 pin description symbol pin no. i/o connected to functions v dd 264 i power supply power supply for internal logic connects to +2.7 to +5.5v v ss 244 i gnd connect to ground v 0r , v 0l v mr , v ml v 1 r , v 1l 266,242 267,241 256,243 i power supply power supply for lcd driver level ensure that the voltage are set such that v 1 EM65H134 in input state ?a the input pin of the fist EM65H134 must connect to vss ?a the other input pin must connect to the output pin of previous EM65H134. dir eio 1 eio 2 h output input l input output
elan microelectronics corp. page 6 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 table1 pin description (continous) cc1 248 i rising crosstalk correction signal.the v1 level output is reset to vm level when cc1 is high. cc2 247 i falling crosstalk correction signal.the v0 level output is reset to vm level when cc2 is high. cc3 246 i waveform distortion non - selected (black) data correction signal.the present output pin (non - selected)and t he next output pin (non - selected) are reset to the vm level when cc3 is high. cc4 245 i waveform distortion selected (white) data correction signal.the present output pin (selected)and the next output pin (selected) are reset to the vm level when cc4 is high. s 1 - s 240 1 to 240 o lcd drive r output. one of two levels is output according to the combination of the fr signal and display data, when /dspof is in v dd
elan microelectronics corp. page 7 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 function descriptions - shift register the 30 - bit shift register genera te latch signal for data latch circuit at the falling edge of xck signal. the shift direction is selected by dir signal. - data latch it latches the data on the 8 bits data bus(di0 to di7) and output the data to line latch. it is controlled by shift regis ter. - line latch all 240 bits, which have been read into the data latch are simultaneously latched at the falling edge of the lp signal then output to the correction circuit and 3 - level driver. - 3 - level driver drive lcd panel from driver output pins, selecting one of three levels ( v 0 , v m , v 1 ) based on the line latch data, correction circuit(cc1 to cc4) and /dspof. - correction circuit this circuit corrects the shadowing volume. 1.the circuit compares the crosstalk correction signals (cc1 and cc2) from the external circuits and present output, and determines whether the effective value is increased due to crosstalk. if the effective value is increased, the output level is reset to the vm level. 2.the circuit compares the output data to the next output da ta. if there are no data changes due to the waveform distortion correction signal (cc3 and cc4), the output level is reset to vm level. the reset period can be adjusted by using cc1 to cc4. the correction needed depends on each output pin. - data shift an d arithmetic circuit the data shifter shifts the destinations of data output when necessary. the arithmetic circuit performs operations for the data and fr signal. lp fr segment common figure 3. fr ?b lp ?b output timing
elan microelectronics corp. page 8 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 relation between fr ?b latch data ?b /dspof and output level table 2 lcd driver output voltage level fr latch data /dspof driver output voltage level h h h v 0 h l h v 1 l h h v 1 l l h v 0 ? ? l v m v ss ?? v 1 < v m < v 0 h:v dd l:v ss ? :d on?|t care relationship between the display data and driver output and data output destination table 3 relationship between the display data and driver output figure of clock dir ei o1 ei o2 data input 1 st 2 nd 3 rd ? 28 th 29 th 30 th di 0 s 8 s 16 s 24 ? s 224 s 232 s 240 di 1 s 7 s 15 s 23 ? s 223 s 231 s 239 di 2 s 6 s 14 s 22 ? s 222 s 230 s 238 di 3 s 5 s 13 s 21 ? s 221 s 229 s 237 di 4 s 4 s 12 s 20 ? s 220 s 228 s 236 di 5 s 3 s 11 s 19 ? s 229 s 227 s 235 di 6 s 2 s 10 s 18 ? s 228 s 226 s 234 l input output di 7 s 1 s 9 s 17 ? s 227 s 225 s 233 di 0 s 233 s 225 s 217 ? s 17 s 9 s 1 di 1 s 234 s 226 s 218 ? s 18 s 10 s 2 di 2 s 235 s 227 s 219 ? s 19 s 11 s 3 di 3 s 236 s 228 s 220 ? s 20 s 12 s 4 di 4 s 237 s 229 s 221 ? s 21 s 13 s 5 di 5 s 238 s 230 s 222 ? s 22 s 14 s 6 di 6 s 239 s 231 s 223 ? s 23 s 15 s 7 h output input di 7 s 240 s 232 s 224 ? s 24 s 16 s 8
elan microelectronics corp. page 9 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 data output destination the direction of data latch and the chip enable input/output pin can be select by dir signal. d4 d7 d6 d5 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 s1 s2 s3 s4 s5 s6 s7 s8 s233 s234 s235 s236 s237 s238 s239 s240 first data last data dir=vss ,enable input: eio1 ,enable output: eio2 d3 d0 d1 d2 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 s1 s2 s3 s4 s5 s6 s7 s8 s233 s234 s235 s236 s237 s238 s239 s240 last data first data dir=vdd ,enable input: eio2 ,enable output: eio1 figure 4. data output destinatio n operating timing figure 4 shows the 8 - bit data - latch timing when dir=gnd; that is, when the eio1 pin is a chip - enable input and the eio2 pin is a chip - enable output. when shl=v cc, the eio1 pin is a chip - enable output and the eio2 pin is a chip - enable i nput. when a low chip - enable signal is input via the eio1 pin, the EM65H134 is first released from the data - standby state, then, at the falling edge of the following xck pulse, it is released entirely from the standby state and starts latching data. it s imultaneously latches eight bits of data at the falling edge of each xck pulse. when it has latched 232 bits of data, it sets the eio2 signal to low. when it has latched 240 bits of data, it automatically stops and enters the standby state, initiating the next EM65H134, provided its eio2 pin is connected to the eio1 pin of the next EM65H134. the EM65H134 output one line of data from the s1 to s240 pins at the falling edge of each lp pulse. data d1 is output from s1, and d240 from s240 when shl=gnd, and d1 is output from s240, and d240 from s1 when dir= v cc.
elan microelectronics corp. page 10 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 eo (no.2) eo (no.3) lp xck ei (no.1) eo (no.1) di0 di7 d8 d1 d9 d16 eo (no.10) d240 d233 1 2 3 29 30 31 299 300 301 s1~s240 no.1 latch data no.2 latch data no.3 latch data no.10 latch data line dir=vss figure 5. data latch timing
elan microelectronics corp. page 11 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 correction circuit the EM65H134 include shadowing correction circuits. there are two types of shadowing: one caused by crosstalk, a nd the other by waveform distortion. in both types, image quality can be improved by correction circuits cc1, cc2, cc3, and cc4. (1) cc1 and cc2(shadowing caused by crosstalk) (a) (b) fr waveform at (a) waveform at (b) showing section white black black black black white white white white white seg com seg com (normally black panel) corresponding sections figure 6. shadowing caused by crosstalk when a ruled line is displayed, noise occurs in the common vm level in the lcd panel due to the segment change of a solid background in fr reverse. this is because many segments display the solid background and are simultaneously changed, affecting the common vm level (creating crosstalk). the effective voltage for section (a) in the solid background becomes low. on the other hand, the effective voltage for section (b) becomes high. shadowing occurs in the corresponding sections due to the different voltages. the em65h 134s compare the crosstalk correction signals cc1 and cc2 and the present output, and determine whether the effective value is increased by the crosstalk. if increased, the output level is reset to the vm, which corrects the effective voltages in (a) and ( b) and suppresses the shadowing. figure 8 shows an example of the crosstalk - correction - signal external circuit. the basic potentials of a comparator (vm+ ? v and vm ?e? v ? ) a r e c o r r e c t e d a c c o r d i n g t o t h e s h a d o w i n g l e v e l f o r o u t p u t correction while cc1 and cc2 are high. cc1 corrects the rising crosstalk, and cc2 corrects the falling crosstalk.
elan microelectronics corp. page 12 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 before correction after correction w a v e f o r m i n s e c t i o n ( a ) w a v e f o r m i n s e c t i o n ( b ) vm seg waveform cc1 cc2 seg waveform vm vm seg waveform seg waveform vm effective voltage decreased effective voltage increased effective voltage correction vm+ v vm- v' figure 7. effective voltage cor rection cc1 cc2 vm power supply vm+ v vm- v' comparator power supply circuit figure8. cc1 and cc2 external circuit
elan microelectronics corp. page 13 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 (2) cc3 and cc4(shadowing caused by waveform distortion) (a) (b) waveform at (a) waveform at (b) white black black white white white seg com seg com (normally black panel) corresponding sections black black fr reversed figure 9. shadowing caused by waveform distortion when the background is displayed in graysc ale (for example, in a checker pattern), many segment levels are changed in section (a) but not in section (b). the effective voltage for section (a) becomes low because distortion occurs in the segment output waveform due to driver or panel impedance. on the other hand, the effective voltage for section (b) becomes high because the waveform is changed only slightly. shadowing occurs in the corresponding sections due to the different voltages. the EM65H134 compare the present output data and the next outpu t data. if the data is not changed, the output level is reset to the vm, which corrects the effective voltages in (a) and (b). the high width is corrected according to the shadowing level for output correction while cc3 and cc4 are high. cc3 corrects the n on - selected output pin (black background), and cc4 corrects the selected output pin (white background).
elan microelectronics corp. page 14 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 before correction after correction w a v e f o r m i n s e c t i o n ( a ) w a v e f o r m i n s e c t i o n ( b ) cc3 cc4 seg waveform seg waveform effective voltage decreased effective voltage correction vm seg waveform seg waveform vm vm vm seg waveform vm figure 10. effective voltage correction by waveform distortion
elan microelectronics corp. page 15 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 (b)v0 reset (v0->vm) fr lp xck di0~di7 cc1 cc2 cc3 cc4 data latch line latch compared result for correction circuit (a)v1 reset (v1->vm) (d)v1 reset (v1->vm) (c)v0 reset (v0->vm) segment output: n-1 m m n m n+1 m-1 m n n-1 n-2 n-3 n-4 * * * last data (m n ) (n) (m n-1 ) calculate result (m) ( ) ( ) next output data (n) (m n ) (n) (m n ) next output data (m n-1 ) current output data (m) (m n-1 ) current output data (m) (n) (m n ) next output data (n) (m n ) next output data (n) (m n ) next output data (n) (m n ) next output data (m n-1 ) current output data (m) (m n-1 ) current output data (m) (m n-1 ) current output data (m) (m n-1 ) current output data (m) vm vm vm vm * : invalid vm reset (correction) figure 11 . compared result for correction circuit the correction circuit compares the present output data (line latch) and the next output data (data latch). depending on the compared result, the circuit resets the high width of cc3 to the vm for the output withou t a data change if the data is the non - selected output ((c) in figure 12). the circuit resets the high width of cc4 to the vm if the data is the selected output ((d) in figure 12). cc3 and cc4 are input after the last valid data is transferred. cc1 forcibl y resets the v1 output to for the high width ((a) in the figure 12). cc2 forcibly resets the v0 output to vm for the high width ((b) in figure 12). therefore, shadowing caused by waveform distortion is corrected with cc3 or cc4 (non - selected or selected), and shadowing caused by crosstalk is corrected with cc1 or cc2 (in the v0 or v1 direction). note: the high period from cc1 to cc4 should be matched with the shadowing level.
elan microelectronics corp. page 16 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 absolute maximum ratings table 4 absolute maximum ratings parameter symbol condit ions applicable pins ratings unit supply voltage (1) v dd v dd *1,*2 - 0.3 to +7.0 v supply voltage (2) v 0 v 0l , v 0r *1,*2 - 0.3 to +7.0 v input voltage(1) v i1 xck, lp,dir,fr, eio 1 , eio 2 , di 0 - 7 ,/dspof, cc1 to cc4 *1 - 0.3 to v dd +0.3 v input voltage(2) v i2 v ml ,v mr ,v 1l ,v 1r *1,*2 - 0.3 to v 0 +0.3 v operating temperature t opr - 30to +75 j storage temperature t stg referenced to v ss (0v) - 55 to +110 j note ?g 1 . if the lsi is used beyond the above maximum ratings , it may be permanently d amaged . i t s h o u l d a l w a y s b e u s e d w i t h i n i t ? s s p e c i f i e d o p e r a t i n g r a n g e f o r n o r m a l o p e r a t i o n t o prevent malfunctions or degraded reliabilility. 2. as show in figur e11, user should conform to the following turn on/off sequence for the power and signal. othe rwise, the lsi will malfunction or will be permanently damaged. in addition, the lsi reliability will be affected. /dspof vm v1 vm v1 2.7 v 2.7 v 0 ms 0 ms 0 ms 0 ms 0 ms 0 ms input-signal colck data v0 v dd signal-undefined period initialization period (at least one frame) ( 0 ms : minimun specification ) figure 12. turn on/off timing
elan microelectronics corp. page 17 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 3. turn on the power: (1) turn on the power in the order of gnd - vdd, gnd - v0, and vm/ v1. then ground the /dspof pin. (2) the lcd forcibly outputs the vm level by the displayoff function. (3) even an input signal disturbed immediately after vdd is applied, the displayoff function has priority. (4) input the specific signal to initialize the registers i n the driver. the initialization period must be at lease one frame. (5) the preparation for the normal display is completed. apply the vdd level to the /dspof pin to cancel the displayoff function. at this time, the level of pin v0, vm and v1 must rise to the specific potential. 4. turn off the power: the procedure is basically the reverse of that used to turn on the power. (1) ground the /dspof pin. (2) turn off the lcd power in the order of vm/v1 and gnd - v0. (3) ground vdd and an input signal. at this time, the level of pin v0, vm and v1 must fall to 0v. since the displayoff function stops when vdd fall to 0v, the lcd may output a level other than vm. therefore, a display failure may occur when the power is turn off or on.
elan microelectronics corp. page 18 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 dc characteristics table 5 dc characteristics 1 ( v ss = gnd=0v, v dd = +2.7 to +4.5v, v 0 - vss= 3.5 to 5.5v, t a = - 3 0 ~ + 7 5 c ) parameter symbol conditions applicable pins min type max unit v ih 0.7 v dd v dd v input voltage v il d i 0 - d i 7 , xck, lp,dir,fr,ei o 1 , ei o 2 , /dspof, cc1 to cc4 0 0 .3 v dd v v oh i oh = - 0.4ma v d d - 0. 4 v output voltage v ol i ol =+0.4ma ei o 1 , ei o 2 +0.4 v input leakage current (1) i il1 v i =v dd - v ss d i 0 - d i 7 , xck, lp, dir, fr, md, ei o 1 , ei o 2 , /dspof - 5 +5 ua input leakage current (2) i il2 v i =v 0 - v ss v ml ,v mr ,v 1l ,v 1r - 100 +100 ua v 0r ,v ol 0.5 1.0 v mr ,v ml 1.0 2.0 output resistance r on *1 i o n = 150ua v 1r ,v 1l y 1 - y 240 0.5 1.0 k [ stand - by current i stb *2 *3 vi = v dd v dd 0.4 1.0 ma consumed current i dd *2 *3 v dd 1.0 6.0 ma consumed current i 0 *2 vi = vss v dd =3v f xck =25mhz f lp =100khz f fr =4khz v 0l , v 0r 0.4 1.0 ma table 6 dc characteristics 2 ( v ss =gnd = 0v, v dd = 4.5v to 5.5v, v 0 - vss= 3.5 to 5.5v, t a = - 3 0 ~ + 7 5 c ) parameter symbol conditions applicable pins min type max unit v ih 0.7 v dd v dd v input voltage v il d i 0 - d i 7 , xck, lp,dir,fr,ei o 1 , ei o 2 , /dspof, cc1 to cc4 0 0.3 v dd v v oh i oh = - 0.4ma v d d - 0. 4 v output voltage v ol i ol =+0.4ma ei o 1 , ei o 2 +0.4 v input leakage current (1) i il1 v i =v dd - v ss d i 0 - d i 7 , xck, lp, dir, fr, md, ei o 1 , ei o 2 , /dspof - 5 +5 ua input leakage current (2) i il2 v i =v 0 - v ss v ml ,v mr ,v 1l ,v 1r - 100 +100 ua v 0r ,v ol 0.5 1.0 v mr ,v ml 1.0 2.0 output resistance r on *1 i o n = 150ua v 1r ,v 1l y 1 - y 240 0.5 1.0 k [ stand - by current i stb *2 *3 vi = v dd v dd 1.0 2.0 ma consumed current i dd *2 *3 v dd 3.0 15 ma consumed current i 0 *2 vi = vss v dd =5v f xck =40 mhz f lp =160khz f fr =6khz v 0l , v 0r 0.4 2.0 ma
elan microelectronics corp. page 19 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 note : 1. indicate the resistance between one of thwe pins y1~y240 and one of the voltage supply pins,when loa d current is applied to the y pins. defined under the following conditions: v0 - vss = 5.5v; vm = (v0=v1)/2; v1 = vss+1 v1 should be near the ground level, vm should be near the middle voltage between v1 and v0. v1should be within the range of ? v = 2.5v0, which is the range within which r on , t h e l c d d r i v e r c i r c u i t ? s o u t p u t impedance, is stable. see figure 13 2. input and output are excluded. when a cmos input is left floating, excess the current flows from the power supply through the input circ uit. to avoid this, vih and vil must be used at vdd and vss, respectively. 3. vi = enable input,. when dir = vss, vi = eio1. when dir = v dd , vi = eio2 4. the voltage of each signal is show in figure 14 v0 vm v1 gnd v = 0.25 v0 figure 13.relationship between driver output waveform and each level voltage segment voltage segment waveform common waveform common voltage vh(38.0v) v dd (3.3v) vm(3.0v) gnd(0.0v) vl(-32.0v) normal display period normal display period display- off period display- off period vm(3.0v) v dd (3.3v) gnd(0.0v) v1(1.0v) v0 (5.0v) figure 14. signal voltage
elan microelectronics corp. page 20 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 ac electrical characteristic table 7 ac electrical characteristics 1 ( v ss = gnd=0v, v dd = 2.7 to 4.5v , v 0 - vss = 3.5 to 5.5v, t a = 30~7 5 c ) parameter symbol condition min typ max unit shift clock period t wck 40 ns s h i f t c l o c k ? h ? p u l s e w i d t h t wckh 15 ns s h i f t c l o c k ? l ? p u l s e w i d t h t wckl 15 ns data setup time t ds 10 ns data hold time t dh 10 ns l a t c h p u l s e ? h ? p u l s e w i dth t wlph 30 ns shift and latch clock set up time t s 20 ns shift and latch clock hold time t h 50 ns shift and latch clock rise time t r 30 ns shift and latch clock fall time t f 30 ns fr set up time t fs 20 ns fr hold time t fh 20 ns output delay time t d c l =100pf 500 ns cc setup time t ccs 20 ns cc hold time t cch 20 ns table 8 ac electrical characteristics 2 ( v ss =gnd = 0v, v dd = 4.5 to 5.5v , v 0 - vss = 3.5 to 5.5v, t a = 30~7 5 c ) parameter symbol condition min typ max unit shift clock period t wck 25 ns s h i f t c l o c k ? h ? p u l s e w i d t h t wckh 10 ns s h i f t c l o c k ? l ? p u l s e w i d t h t wckl 10 ns data setup time t ds 6 ns data hold time t dh 6 ns l a t c h p u l s e ? h ? p u l s e w i d t h t wlph 25 ns shift and latch clock set up time t s 20 ns shift and latch clock hold time t h 50 ns shift and latch clock rise time t r 20 ns shift and latch clock fall time t f 20 ns fr set up time t fs 20 ns fr hold time t fh 20 ns o utput delay time t d c l =100pf 500 ns cc setup time t ccs 20 ns cc hold time t cch 20 ns notes: 1. the load must be less than 10 pf between the eio1 and eio2 connections of the EM65H134s. 2. connect the load circuit as shown in figure 15. test point 100 pf figure 15. load circuit for output delay time
elan microelectronics corp. page 21 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 timing diagram di0~di7 0.8 v 0 0.7 v dd 0.3 v dd t d 0.2 v 1 lp s (n) xck 0.7 v dd 0.3 v dd 0.3 v dd 0.7 v dd t r t f t w ckh t w ckl t w ck t ds t dh 0.3 v dd 0.7 v dd xck lp t s t h 0.7 v dd 0.3 v dd fr t fs t fh t wlph 0.3 v dd 0.7 v dd xck lp t cch cc3 cc4 t ccs 0.3 v dd 0.3 v dd last first correct the waveform by cc3 and cc4 after xck fetches the last data. complete correction before data from the next line is output at the falling edge of lp. figure 16. ac characteristics
elan microelectronics corp. page 22 ?????|3?v?y?q??1qla?|3--?q , ?d?g??--?3\?ia?|l??|l??a??l?|?|? all rights strictly reserved, any portion in this paper shall not be reproduced, copied without permission. ???|?ot?a?|??g 1.2 ??|?a? / o|?H?g 2001/ 7 / 16 application circuit lcd panel 320 * 3 *240 1/240 duty eio2 eio1 dir c c 1 ~ c c 4 / d s p o f d 0 ~ d 7 f r x c k l p v 1 l , r v m l , r v 0 l , r v d d g n d EM65H134 eio2 eio1 dir c c 1 ~ c c 4 / d s p o f d 0 ~ d 7 f r x c k l p v 1 l , r v m l , r v 0 l , r v d d g n d EM65H134 (n0. 1) eio2 eio1 dir c c 1 ~ c c 4 / d s p o f d 0 ~ d 7 f r x c k l p v 1 l , r v m l , r v 0 l , r v d d g n d EM65H134 (n0. 4) (n0. 2) s e g 1 s e g 2 s e g 3 s e g 2 4 0 s e g 2 3 9 s e g 2 3 8 ----------------------------- s e g 2 4 1 s e g 2 4 2 s e g 2 4 3 s e g 4 8 0 s e g 4 7 9 s e g 4 7 8 ----------------------------- s e g 7 2 1 s e g 7 2 2 s e g 7 2 3 s e g 9 6 0 s e g 9 5 9 s e g 9 5 8 ----------------------------- ~~~~~~~~~~~~~~~~~ ~ vdd vdd vdd s240 ~ s1 s240 ~ s1 s240 ~ s1 c 1 ~ c 2 4 0 lp clp /rst /dspof amp m/s /doc fr frs0~frs4 vhl,r vml,r d i r vll,r lcd controller power supply circuit e i o 1 e i o 2 v l c d l , r g n d v e e l , r v e o v d d c 1 c 2 correction circuit figure 17. application circuit

▲Up To Search▲

Price & Availability of EM65H134

	To Download EM65H134 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .