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EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 1 general description the EM65240 is a 240-channel lcd driver lsi used to drive large scale dot matrix lcd panels, like pda, personal computers and workstations. which is made by power cmos high voltage process technology. through the use of tcp technology, it is deal for substantially decreasing the size of lcd module frame. this product can function as a common and a segment driver, which is used for liquid crystal dot matrix display. in common driver mode, it can be selected in single mode and dual mode by a mode pin (md), data input/output pins are bi-directional, four data shift direction are pin selectable. in segment driver mode, it can be selected 4-bit parallel input mode or 8-bit parallel input mode by a mode pin (md). features both common mode and segment mode - display duty application: up to 1/480 duty - supply voltage for the logic system: +2.5 to +5.5v - supply voltage for lcd driver: +15 to +42v - number of lcd driver outputs: 240 - low output impedance - low power consumption - cmos silicon process (p-type silicon substrate) - 268 pin tcp (tape carrier package) package: EM65240u common mode - shift clock frequency: 4.0mhz (max.) (v dd =+2.5 to +5.5) - built-in 240 bits bi-directional shift register (divisible into 120bits*2) - available in a single mode or in a dual mode - data input/output pins are bi-directional, four data shift direction are pin selectable. - shift register circuit reset function when /dspof active
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 2 segment mode - shift clock frequency: 20mhz(max.) (v dd =+ 5v 10%) 15mhz(max.) (v dd =+ 3.5v to + 4.5v ) 12mhz(max.) (v dd =+ 2.5v to + 3.0v ) - adopts a data bus system - 4-bits/8-bits parallel input mode are selected by md pin - automatic transfer function of an enable signal - automatic counting function which, in the chip select, causes the internal clock to be stopped by automatically counting 240 of input data - line latch circuit reset function when /dspof active pin configuration v 0l v 12l v 43l v 5l vdd s/c eio2 di0 di1 di2 di3 di4 di5 di6 di7 xck /dspof lp eio1 fr dir md test1 vss v 5r v 43r v 12r v 0r y 240 y 239 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . y 2 y 1 chip surface 241 ------------------------------------------------------------------------------------------------------268 240---------------------------------------------------------------------------------------------------------------------1 figure1 pin configuration
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 3 table 1 pin designation pin no. symbol i/o description 1 to240 y 1 ? y 240 o lcd driver output 241,268 v ol ,v or - power supply for lcd driver 242,267 v 12l ,v 12r - power supply for lcd driver 243,266 v 43l ,v 43r - power supply for lcd driver 244,265 v 5l ,v 5r - power supply for lcd driver 245 v dd - power supply for logic system 246 s/c i segment/common mode selection 247 259 eio 2 eio 1 i/o input /output for chip select or data of shift register 248 to 254 255 di 0 ? di 6 di 7 i display data input for segment mode dual mode data input for common mode 256 xck i display data shift clock input for segment mode 257 /dspof i control input for non-select output level 258 lp i latch pulse input/shift clock input for shift register 260 fr i ac-converting signal input for lcd driver waveform 261 dir i display data shift direction selection 262 md i mode selection input 263 test 1 i test mode selection input 264 v ss - ground (0 v)
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 4 pin descriptions segment mode table2 pin description of segment mode symbol i/o connected to functions v dd i power supply power supply for internal logic connects to +2.5 to +5.5v v ss i gnd connect to ground v 0r v 0l v 12r v 12l v 34r v 34l v 5r v 5l i power supply power supply for lcd driver level B normally the bias voltage used is set by resistor divider B ensure that the voltage are set such that v ss Q v 5 EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 5 segment mode (continuous) directional selection for reading display data dir data read direction l y 240 to y 1 h y 1 to y 240 dir i controller /dspof i controller control signal for output deselect level B the input signal is level-shifted from logic voltage level to lcd driver voltage level and controls lcd drive circuit B when the signal is low the output (y 1 ? y 240 ) of lcd drive be set to level v 5 the contents of line latch are reset but read the display data in the data latch regardless of condition of /dspof B when this signal return to high, the operation returns to the normal status. fr i controller ac signal for lcd driver B input a frame inversion signal B the lcd driver output voltage level can be set by line latch output signal and fr signal mode selection md mode selection h 4-bit parallel input l 8-bit parallel input md i controller
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 6 segment mode (continuous) input/output for chip selection B in output state after 240-bit of data have been read set to ?l? then set to ?h? B in input state the chip is selected when ei is set to ?l? then 240-bit of data have been read the ship is deselected dir eio 1 eio 2 h input output l output input eio 1 eio 2 i/o controller y 1 -y 240 o lcd driver output. B one of four levels is output according to the combination of the fr signal and display data test 1 i test mode selection B during normal operation connect to v ss
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 7 common mode table3 pin description of common mode symbol i/o connected to functions v dd i power supply power supply for internal logic connects to +2.5 to +5.5v v ss i gnd connect to ground v 0r ,v 0l v 12r ,v 12l v 34r ,v 34l v 5r ,v 5l i power supply power supply for lcd driver level B normally the bias voltage used is set by resistor divider B ensure that the voltage are set such that v ss Q v 5 EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 8 common mode (continuous) /dspof i controller control signal for output deselect level B the input signal is level-shifted from logic voltage level to lcd driver voltage level and controls lcd drive circuit B when the signal is low the output (y 1 ? y 240 ) of lcd drive be set to level v 5 the contents of shift register are reset not read B when this signal return to high, the operation returns to the normal status. fr i controller ac signal for lcd drive B input a frame inversion signal B the lcd driver output voltage level can be set by shift register output signal and fr signal md i controller mode selection md mode selection h dual mode l single mode s/c i controller selection of segment mode/common mode s/c mode selection h segment mode l common mode di 7 i controller dual mode data input B in dual mode data can input from 121 st bit di 0 -di 6 i v ss or v dd not used xck i v ss or open not used y 1 -y 240 o lcd driver output. B one of four voltage levels is output according to the data of shift register and fr signal test 1 i test mode select B during normal operation connect to v ss
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 9 block diagram 7 0 240 bits 4-level driver (liquid crystal display driver circuit) 240 bits level shift 240bits line latch (segment mode) shift register (common mode) data latch control level shifter l l l l v v v v 5 43 12 0 , , , 240 239 2 1 , ........, .......... .......... ,......... , y y y y 8bits*2 data latch .... 7 di fr /dspof 4 4 8 16 16 16 16 16 16 16 16 16 240 240 test circuit sp convesion & data control (4 to 8 or 8 to 8) ~ di di 8 dd ss v v active control clock control lp xck r d i md c s / 1 test 2 1 eio eio r r r r v v v v 5 43 12 0 , , , figure 2 block diagram
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 10 functional descriptions . active control in case of segment mode, controls the selection or deselection of the chip. following a lp signal, and after the chip select signal is input, a select signal is generated internally until 240 bits of data have been read in. once data input has been completed, a select signal for cascade connection is output, and the chip is non-selected. in case of common mode, controls the input/output data of bi-directional pins. . sp conversion & data control in case of segment mode, keep input data which are 2 clocks of xck at 4-bit parallel mode into latch circuit, or keep input data which are 1 clock of xck at 8-bits parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at a time. . data latch control in case of segment mode, selects the state of the data latch which reads in the data bus signals. the shift direction is controlled by the control logic, for every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. . data latch in case of segment mode, latches the data on the data bus. the latched state of each lcd driver output pin is controlled by the control logic and the data latch control, 240 bits of data are read in 30 sets of 8 bits. . line latch / shift register in case of segment mode, all 240 bits, which have been read into the data latch are simultaneously latched on the falling edge of the lp signal, and output to the level shifter block. in case of common mode, shifts data from the data input pin on the falling edge of the lp signal. . level shifter the logic voltage signal is level-shifted to the lcd driver voltage level, and output to the driver block. . 4-level driver drive the lcd driver output pins from the line latch/shift register data, selecting one of 4 levels (v 0 , v 12 , v 43 , v 5 ) based on the s/c, fr and /dspof
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 11 . control logic controls the operation of each block. in case of segment mode, when a lp signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. once the selection signal has been output, operation of the data latch and data transmission are controlled, 240 bits of data are read in, and the chip is deselected. in case of common mode, controls the direction of data shift. .test circuit the circuit for the test. during normal operation, it doesn?t act. relation between fr latch data /dspof and output level table 4 lcd driver output voltage level (a) segment mode fr latch data /dspof driver output voltage level h h h v 0 h l h v 12 l h h v 5 l l h v 43 x x l v 5 v ss Q v 5 < v 43 < v 12 < v 0 h:v dd l:v ss x : don?t care (b) common mode fr latch data /dspof driver output voltage level h h h v 5 h l h v 12 l h h v 0 l l h v 43 x x l v 5 v ss Q v 5 < v 43 < v 12 < v 0 h:v dd l:v ss x : don?t care
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 12 relationship between the display data and driver output pin table 5 relationship between the display data and driver output pin (a)segment mode (4-bit parallel mode) figure of clock md dir eio 1 eio 2 data input 1 st 2 nd 3 rd ? 38 th 39 th 60 th di 0 y 4 y 8 y 12 ? y 232 y 236 y 240 di 1 y 3 y 7 y 11 ? y 231 y 235 y 329 di 2 y 2 y 6 y 10 ? y 230 y 234 y 238 h h input output di 3 y 1 y 5 y 9 ? y 229 y 233 y 237 di 0 y 237 y 233 y 229 ? y 9 y 5 y 1 di 1 y 238 y 234 y 230 ? y 10 y 6 y 2 di 2 y 239 y 235 y 231 ? y 11 y 7 y 3 h l output input di 3 y 240 y 236 y 232 ? y 12 y 8 y 4 (b) segment mode (8-bit parallel mode) figure of clock md dir eio1 eio2 data input 1 st 2 nd 3 rd ? 28 th 29 th 30 th di 0 y 8 y 16 y 24 ? y 224 y 232 y 240 di 1 y 7 y 15 y 23 ? y 223 y 231 y 239 di 2 y 6 y 14 y 22 ? y 222 y 230 y 238 di 3 y 5 y 13 y 21 ? y 221 y 229 y 237 di 4 y 4 y 12 y 20 ? y 220 y 228 y 236 di 5 y 3 y 11 y 19 ? y 229 y 227 y 235 di 6 y 2 y 10 y 18 ? y 228 y 226 y 234 l h input output di 7 y 1 y 9 y 17 ? y 227 y 225 y 233 di 0 y 233 y 225 y 217 ? y 17 y 9 y 1 di 1 y 234 y 226 y 218 ? y 18 y 10 y 2 di 2 y 235 y 227 y 219 ? y 19 y 11 y 3 di 3 y 236 y 228 y 220 ? y 20 y 12 y 4 di 4 y 237 y 229 y 221 ? y 21 y 13 y 5 di 5 y 238 y 230 y 222 ? y 22 y 14 y 6 di 6 y 239 y 231 y 223 ? y 23 y 15 y 7 l l output input di 7 y 240 y 232 y 224 ? y 24 y 16 y 8 (c) common mode md dir data transfer direction eio 1 eio 2 di 7 y 1 ~y 120 h y 121 ~y 240 input output input y 240 ~ y 121 h (dual) l y 120 ~ y 1 output input input h y 1 ~y 240 input output x l (single) l y 240 ~ y 1 output input x h:v dd l:v ss x :don?t care
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 13 connection example of plural segment driver case of dir=?l? di 2 eio 1 eio r d i xck lp md fr di 0 ~di 7 2 eio 1 eio r d i xck lp md fr di 0 ~di 7 2 eio 1 eio r d i xck lp md fr di 0 ~di 7 xck lp md fr 7 0 ~ di ss v 240 y 1 y 240 y 1 y 240 y 1 y figure 3 segment mode of dir=?l? case of dir=?h? 2 eio 1 eio r d i xck lp md fr di 0 ~di 7 2 eio 1 eio r d i xck lp md fr di 0 ~di 7 2 eio 1 eio r d i xck lp md fr di 0 ~di 7 xck lp md fr 7 0 ~ di di dd v 240 y 1 y 240 y 1 y 240 y 1 y ss v figure 4 segment mode of dir=?h?
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 14 connection of plural common driver single mode dir=?l? lp ss dd v or v ss v fr /dspof 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y di first last figure 5 single mode dir=?l? single mode dir=?h? lp dd v ss dd v or v ss v fr /dspof 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y first last 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y di figure 6 single mode dir=?h?
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 15 connection of plural common driver dual mode dir=?l? lp ss v ss dd v or v dd v fr /dspof 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y 1 di 1 first 2 last 120 y 121 y 2 di 2 first 1 last figure 7 dual mode dir=?l ? dual mode dir=?h? lp dd v ss dd v or v ss v fr /dspof 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y 1 first 2 last 2 eio 1 eio lp di7 md dir /dspof fr 240 y 1 y 1 di 120 y 121 y 2 di 2 first 1 last figure 8 dual mode dir=?h?
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 16 timing chart of 4-device cascade connection of segment driver eo (device b) eo (device c) fr lp xck 7 0 ~ di di device a device b device c device d ei (device a) eo (device a) n123 1 1 1 n n n n 222 33 3 n:4-bit parallel mode 60 8-bit parallel mode 30 top data last data l figure 9 timing chart of 4-device cascade connection of segment driver power supply circuit for liquid crystal drive precaution when connecting or disconnecting the power this lsi has a high-voltage lcd driver, so it may be permanently damaged by a high current which may flow if a voltage is supplied to the lcd driver power supply while the logic system power supply is floating. . we recommend you connecting the serial resistor (50~100 ) or fuse to the lcd drive power v 0 of the system as a current limiter. and set up the suitable of the resistor in consideration of lcd display grade.
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 17 when connecting the power supply, show the following recommend sequence. dd v ss v dd v ss v ss v dd v dd v 0 v /dspof figure 10 drive by operational amplifier in graphic displays, the size of the liquid crystal becomes larger and the display duty ratio becomes smaller, so the stability of liquid crystal drive level is more important than a small display system. since the liquid crystal for graphic display is large and has many picture elements, the load capacitance becomes large. the high impedance of power supply for liquid crystal drive produce distortion in the drive waveforms, and degrades display quality. for the reason, the liquid crystal drive level impedance should be reduced with operational amplifiers. range of operating voltage: v0 it is necessary to set the voltage for v0 within the vdd operating voltage range shown in the diagram below. operating voltage range 2.0 2.5 10 20 30 40 42 3.0 4.0 5.0 5.5 vdd (v) v0(v) figure 11
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 18 absolute maximum ratings table 6 absolute maximum ratings parameter symbol conditions applicable pins ratings unit supply voltage (1) v dd v dd -0.3 to +7.0 v v 0 v 0l , v 0r -0.3 to +45.0 v v 12 v 12l , v 12r -0.3 to v 0 +0.3 v v 43 v 43l , v 43r -0.3 to v 0 +0.3 v supply voltage (2) v 5 v 5l , v 5r -0.3 to v 0 +0.3 v input voltage v i di 0-7 , xck, lp, dir, fr, md, s/c, eio 1 , eio 2 , /dspof,test 1 -0.3 to v dd +0.3 v storage temperature t stg t a =25 reference d to v ss (0v) -45 to +125 recommended operation conditions table 7 recommended operation conditions parameter symbol conditions applicable pins min. typ. max . unit supply voltage (1) v dd v dd +2.5 +5.5 v supply voltage (2) v 0 reference d to v ss (0v) v 0l , v 0r +15 +42 v operating temperature t opr -20 +85
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 19 dc characteristics segment mode table 8 dc characteristics of segment mode (v ss = v 5 = 0v, v dd = +2.5 to +5.5v, v 0 = +15 to +42v, t a = -20~+85c) parameter symbo l conditions applicable pins min type max unit v ih 0.8v d d v input voltage v il di 0 -di 7 , xck, lp,dir,fr,m d, s/c,eio 1 , eio 2 , /dspof 0.2v d d v v oh i oh =-0.4ma v dd -0. 4 v output voltage v ol i ol =+0.4ma eio 1 , eio 2 +0.4 v i lih v i =v dd +10 ua input leakage current i lil v i =v ss di 0 -di 7 , xck, lp, dir, fr, md, s/c,eio 1 , eio 2 , /dspof -10 ua v 0 =+40 v 1.0 1.5 v 0 =+30 v 1.5 2.0 output resistance r on | v on | =0.5v v 0 =+20 v y 1 - y 240 2.0 2.5 k stand-by current i stb *1 v ss 75.0 ua consumed current (deselectio n) i dd1 *2 v dd 2.0 ma consumed current (selection) i dd2 *3 v dd 12.0 ma consumed current i 0 *4 v 0 1.5 ma note : 1. v dd = +5v, v 0 = +42v, v i = v ss 2. v dd = +5v, v 0 = +42v, f xck = 20mhz, no-load, ei = v dd the input data is turned over by data taking clock (4-bit parallel input mode) 3. v dd = +5v, v0 = +42v, f xck = 20mhz, no-load, ei = v ss the input data is turned over by data taking clock (4-bit parallel input mode) 4. v dd = +5v, v0 = +42v, f xck = 20mhz, f lp = 41.6khz, f fr = 80hz, no-load the input data is turned over by data taking clock (4-bit parallel input mode)
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 20 common mode table 9 dc characteristics of common mode (vss = v5 = 0v, vdd = +2.5 to 5.5v, v0 = +15 to +42v, ta = -20~85c) parameter symbo l conditions applicable pins min typ e max unit v ih 0.8v dd v input voltage v il di 0 -di 7 , xck, lp,dir,fr,m d, s/c,eio 1 , eio 2 , /dspof 0.2v d d v v oh i oh = -0.4ma v dd -0.4 v output voltage v ol i ol = +0.4ma eio 1 , eio 2 +0.4 v i lih vi=v dd di 0 -di 7 , xck, lp, dir, fr, md, s/c, /dspof +10 ua input leakage current i lil v i =v ss di 0 -di 7 , xck, lp, dir, fr, md, s/c,eio 1 , eio 2 , /dspof -10 ua v 0 =+40 v 1.0 1.5 v 0 =+30 v 1.5 2.0 output resistance r on | v on | =0.5v v 0 =+20 v y 1 - y 240 2.0 2.5 k input pull-down current i pd v i =v dd xck,eio 1 ,eio 2 , di 7 100.0 ua stand-by current i stb *1 v ss 75.0 ua consumed current (1) i dd *2 v dd 120.0 ua consumed current(2) i 0 *2 v 0 240.0 ua note: 1. v dd = +5v, v 0 = +42v, v i = v ss 2. v dd = +5v, v 0 = +42v, f lp = 41.6khz, f fr = 80hz, 1/480 duty, no-load
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 21 ac electrical characteristic segment mode 1 table 10 ac electrical characteristics of segment mode 1 (v ss = v 5 = 0v, v dd = +4.5 to +5.5v , v 0 = +15 to +42v, t a = -20~85c) parameter symbol condition min typ max unit shift clock period *1 t wck t r ,t f Q 10ns 50 ns shift clock ?h? pulse width t wckh 15 ns shift clock ?l? pulse width t wckl 15 ns data setup time t ds 10 ns data hold time t dh 12 ns latch pulse ?h? pulse width t wlph 15 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 30 ns latch pulse rise to shift clock rise time t ls 25 ns latch pulse fall to shift clock fall time t lh 25 ns input signal rise time *2 t r 50 ns input signal fall time *2 t f 50 ns enable setup time t s 10 ns /dspof removal time t sd 100 ns /dspof ?l? pulse time t wdl 1.2 us output delay time (1) t d c l =15pf 30 ns output delay time (2) t pd1 t pd2 c l =15pf 1.2 us output delay time (3) t pd3 c l =15pf 1.2 us notes: 1. take the cascade connection into consideration. 2. (t wck ? t wckh ? t wckl ) / 2 is maximum in the case of high speed operation.
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 22 segment mode 2 table 11 ac electrical characteristics of segment mode 2 (v ss = v 5 = 0v, v dd = +3.0 to +4.5v , v 0 = +15 to +42v, t a = -20~8c) parameter symbol condition min typ max unit shift clock period *1 t wck t r ,t f Q 10ns 66 ns shift clock ?h? pulse width t wckh 23 ns shift clock ?l? pulse width t wckl 23 ns data setup time t ds 15 ns data hold time t dh 23 ns latch pulse ?h? pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 50 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns input signal rise time *2 t r 50 ns input signal fall time *2 t f 50 ns enable setup time t s 15 ns /dspof removal time t sd 100 ns /dspof ?l? pulse time t wdl 1.2 us output delay time (1) t d c l =15pf 41 ns output delay time (2) t pd1 t pd2 c l =15pf 1.2 us output delay time (3) t pd3 c l =15pf 1.2 us notes: 1. take the cascade connection into consideration. 2. ( twck ? t wckh ? t wckl ) / 2 is maximum in the case of high speed operation.
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 23 segment mode 3 table 12 ac electrical characteristics of segment mode 3 (v ss = v 5 = 0v, v dd = +2.5 to +3.0v , v 0 = +15 to +42v, t a = -20~85c) parameter symbol condition min typ max unit shift clock period *1 t wck t r ,t f Q 10ns 82 ns shift clock ?h? pulse width t wckh 28 ns shift clock ?l? pulse width t wckl 28 ns data setup time t ds 20 ns data hold time t dh 23 ns latch pulse ?h? pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 65 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns input signal rise time *2 t r 50 ns input signal fall time *2 t f 50 ns enable setup time t s 15 ns /dspof removal time t sd 100 ns /dspof ?l? pulse time t wdl 1.2 us output delay time (1) t d c l =15pf 57 ns output delay time (2) t pd1 t pd2 c l =15pf 1.2 us output delay time (3) t pd3 c l =15pf 1.2 us notes: 1. take the cascade connection into consideration. 2. (t wck ? t wckh ? t wckl ) / 2 is maximum in the case of high speed operation.
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 24 common mode table 13 ac electrical characteristics of common mode (v ss = v 5 = 0v, v dd = +2.5 to +5.5v, v 0 = +15 to +42v, t a = -20~+85c) parameter symbol condition min typ max unit shift clock period t wlp t r ,t f Q 20ns 250 ns v dd =+5.0v 10% 15 ns shift ?h? pulse width t wlph v dd =+2.5v~+4.5v 30 ns data setup time t su 30 ns data hold time t h 50 ns input signal rise time *2 t r 50 ns input signal fall time *2 t f 50 ns /dspof removal time t sd 100 ns /dspof ?l? pulse time t wdl 1.2 us output delay time (1) t dl c l =15pf 200 ns output delay time (2) t pd1 ,t pd2 c l =15pf 1.2 us output delay time (3) t pd3 c l =15pf 1.2 us
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 25 timing diagrams timing characteristics of segment mode lp xck 7 0 di di ? /dspof wdl t sd t last data top data dh t ds t wck t r t f t ls t sl t wckh t lh t ld t wlph t wckl t figure 12 lp xck ei eo s t d t 1 2 n n:4-bit parallel mode 60 8-bit parallel mode 30 figure 13 fr lp /dspof 240 1 ~ y y 3 pd t 2 pd t 1 pd t figure 14
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 26 timing characteristics of common mode lp 2 eio 1 eio /dspof () 7 di wlp t f t wlph t r t su t h t dl t wdl t sd t figure 15 fr lp /dspof 240 1 ~ y y 3 pd t 2 pd t 1 pd t figure 16
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 27 application circuit eio1 md fr s/c lp dir di0-di7 /dspof xck eio2 eio1 md s/c fr dir lp di0-di7 /dspof eio2 xck eio1 md s/c fr dir lp di0-di7 /dspof eio2 xck eio1 md fr s/c lp dir di0-di7 /dspof xck eio2 eio1 md fr s/c lp dir di0-di7 /dspof xck eio2 0 v ee v 1 v 2 v 3 v 4 v 960*480 dot matrix lcd panel com1 com2 . . . . . . . . . . . . . . . . . . . com479 com480 yd fr lp /dspof xck lcd controller xd0-xd7 EM65240*2 seg960 seg959 . . . . . . . . . . . . . . . . . . . . . seg2 seg1 5 v dd v ss v current limitter r (n-4)r r r r c 50~100 duty a when a n bias n 1 , 1 1 , 1 + = EM65240*4 figure 17 application circuit of 960*480 dot matrix lcd panel
EM65240 240 com/seg dot matrix lcd driver * this specification are subject to be changed without notice. 4.8.2002 28 eio1 md fr s/c lp dir di0-di7 /dspof xck eio2 eio1 md s/c fr dir lp di0-di7 /dspof eio2 xck eio1 md s/c fr dir lp di0-di7 /dspof eio2 xck eio1 md fr s/c lp dir di0-di7 /dspof xck eio2 eio1 md fr s/c lp dir di0-di7 /dspof xck eio2 0 v ee v 1 v 2 v 3 v 4 v 1920*480 dot matrix lcd panel com1 com2 . . . . . . . . . . . . . . . . . . . com479 com480 yd fr lp /dspof xck lcd controller xd0-xd7 EM65240*2 EM65240*8 seg1920 seg1919 . . . . . . . . . . . . . . . . . . . . . seg2 seg1 5 v dd v ss v current limitter r (n-4)r r r r c 50~100 duty a when a n bias n 1 , 1 1 , 1 + = figure 18 application circuit of 1920*480 dot matrix lcd panel

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