ds030 (v1.5) april 4, 2000 1 introduction the spartan ? family of proms provide an easy-to-use, cost-effective method for storing spartan device configura- tion bitstreams. when the spartan device is in master serial mode, it gen- erates a configuration clock that drives the spartan prom. a short access time after the rising clock edge, data appears on the prom data output pin that is connected to the spartan device din pin. the spartan device generates the appropriate number of clock pulses to complete the configuration. once configured, it disables the prom. when a spartan device is in slave serial mode, the prom and the spartan device must both be clocked by an incom- ing signal. for device programming, either the xilinx alliance or the foundation series development systems compiles the spartan device design file into a standard hex format which is then transferred to most commercial prom pro- grammers. spartan prom features configuration one-time programmable (otp) read-only memory designed to store configuration bitstreams for spartan, spartan-xl, and spartan-ii fpga devices simple interface to the spartan device requires only one user i/o pin programmable reset polarity (active high or active low) low-power cmos floating gate process available in 5v and 3.3v versions available in compact plastic 8-pin dip, 8-pin voic, or 20-pin soic (xc17s40 only) packages. programming support by leading programmer manufacturers. design support using the xilinx alliance and foundation series software packages. 0 spartan family of proms ds030 (v1.5) april 4, 2000 05* product specification r spartan fpga configuration bits compatible spartan prom xcs05 53,984 xc17s05 xcs05xl 54,544 xc17s05xl xcs10 95,008 xc17s10 xcs10xl 95,752 xc17s10xl xc2s15 197,728 xc17s15xl xcs20 178,144 xc17s20 xcs20xl 179,160 xc17s20xl xcs30 247,968 xc17s30 xcs30xl 249,168 xc17s30xl xc2s30 336,768 xc17s30xl xcs40 329,312 xc17s40 xcs40xl 330,696 xc17s40xl xc2s50 559,232 xc17s50xl xc2s100 781,248 xc17s100xl xc2s150 1,040,128 xc17s150xl xc2s200 1,335,872 xc17s200xl
r spartan family of proms 2 ds030 (v1.5) april 4, 2000 pin description table 1: spartan prom pinouts pin name 8-pin pdip & voic 20-pin soic pin description data 1 1 data output, 3-stated when either ce or oe are inactive. during pro- gramming, the data pin is i/o. note that oe can be programmed to be either active high or active low. clk 2 3 each rising edge on the clk input increments the internal address counter, if both ce and oe are active. reset/oe (oe/reset ) 38 when high, this input holds the address counter reset and 3-states the data output. the polarity of this input pin is programmable as ei- ther reset/oe or oe/reset . to avoid confusion, this document describes the pin as reset/oe , although the opposite polarity is possible on all devices. when reset is active, the address counter is held at zero, and the data output is 3-stated. the polarity of this input is programmable. the default is active high reset, but the preferred option is active low reset , because it can be driven by the fpgas init pin. the polarity of this pin is controlled in the programmer interface. this input pin is easily inverted using the xilinx hw-130 programmer soft- ware. third-party programmers have different methods to invert this pin. ce 4 10 when high, this pin disables the internal address counter, 3-states the data output, and forces the device into low-i cc standby mode. gnd 5 11 gnd is the ground connection. v cc 7, 8 18, 20 the v cc pins are to be connected to the positive voltage supply.
r ds030 (v1.5) april 4, 2000 3 spartan family of proms controlling proms connecting the spartan device with the prom: the data output of the prom drives the din input of the lead spartan device. the master spartan device cclk output drives the clk input of the prom. the reset /oe input of the prom is driven by the init output of the spartan device. this connection assures that the prom address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a v cc glitch. other methods ? such as driving reset /oe from ldc or system reset ? assume that the prom internal power-on-reset is always in step with the fpga ? s internal power-on-reset, which may not be a safe assumption. the ce input of the prom is driven by the done output of the spartan device, provided that done is not permanently grounded. otherwise, ldc can be used to drive ce , but must then be unconditionally high during user operation. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary supply current of 10 ma maximum. fpga master serial mode summary the i/o and logic functions of the configurable logic block (clb) and their associated interconnections are estab- lished by a configuration program. the program is loaded either automatically upon power up, or on command, depending on the state of the spartan device mode pin. in master serial mode, the spartan device automatically loads the configuration program from an external memory. the spartan prom has been designed for compatibility with the master serial mode. upon power-up or reconfiguration, the spartan device enters the master serial mode when the mode pin is low. data is read from the prom sequentially on a single data line. synchronization is provided by the rising edge of the temporary signal cclk, which is generated during configu- ration. master serial mode provides a simple configuration inter- face. only a serial data line and two control lines are required to configure the spartan device. data from the prom is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of cclk. if the user-programmable, dual-function din pin on the spartan device is used only for configuration, it must still be held at a defined level during normal operation. the spar- tan family takes care of this automatically with an on-chip default pull-up resistor. programming the fpga with counters unchanged upon completion when multiple-configurations for a single spartan device are stored in a prom, the oe pin should be tied low. upon power-up, the internal address counters are reset and con- figuration begins with the first program stored in memory. since the oe pin is held low, the address counters are left unchanged after configuration is complete. therefore, to reprogram the fpga with another program, the done line is pulled low and configuration begins at the last value of the address counters. this method fails if a user applies reset during the spar- tan device configuration process. the spartan device aborts the configuration and then restarts a new configura- tion, as intended, but the prom does not reset its address counter, since it never saw a high level on its oe input. the new configuration, therefore, reads the remaining data in the prom and interprets it as preamble, length count etc. since the spartan device is the master, it issues the neces- sary number of cclk pulses, up to 16 million (2 24 ) and done goes high. however, the spartan device configura- tion will be completely wrong, with potential contentions inside the spartan device and on its output pins. this method must, therefore, never be used when there is any chance of external reset during configuration.
r spartan family of proms 4 ds030 (v1.5) april 4, 2000 figure 1: master serial mode. the one-time-programmable spartan prom supports automatic loading of configuration programs. an early done inhibits the prom data output one cclk cycle before the spartan fpga i/os become active. din cclk init done spartan prom data 3.3v clk ce spartan master serial (low resets the address pointer) ds030_01_040400 cclk (output) din dout (output) oe/reset mode 4.7k v cc v cc v pp
r ds030 (v1.5) april 4, 2000 5 spartan family of proms standby mode the prom enters a low-power standby mode whenever ce is asserted high. the output remains in a high imped- ance state regardless of the state of the oe input. programming the spartan family proms the devices can be programmed on programmers supplied by xilinx or qualified third-party vendors. the user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. the wrong choice can permanently damage the device. important: always tie the two v cc pins together in your application. notes: 1. the xc17s00 reset input has programmable polarity 2. tc = terminal count = highest address value. tc+1 = address 0. figure 2: simplified block diagram (does not show programming circuit) table 2: truth table for xc17s00 control inputs control inputs internal address outputs reset ce data i cc inactive low if address < tc: increment if address > tc: don ? t change active 3-state active reduced active low held reset 3-state active inactive high not changing 3-state standby active high held reset 3-state standby eprom cell matrix address counter ce data oe output clk v cc gnd ds030_02_011300 tc oe reset/ oe/ reset or
r spartan family of proms 6 ds030 (v1.5) april 4, 2000 xc17s05, xc17s10, xc17s20, xc17s30, xc17s40 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. operating conditions note : during normal read operation both v cc pins must be connected together. dc characteristics over operating condition symbol description value units v cc supply voltage relative to gnd ? 0.5 to +7.0 v v in input voltage relative to gnd ? 0.5 to v cc +0.5 v v ts voltage applied to 3-state output ? 0.5 to v cc +0.5 v t stg storage temperature (ambient) ? 65 to +150 c t sol maximum soldering temperature (10 s @ 1/16 in.) +260 c symbol description min max units v cc commercial supply voltage relative to gnd (t a = 0 c to +70 c) 4.75 5.25 v industrial supply voltage relative to gnd (t a = ? 40 c to +85 c) 4.50 5.50 v symbol description min max units v ih high-level input voltage 2.0 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = ? 4 ma) commercial 3.86 v v ol low-level output voltage (i ol = +4 ma) 0.32 v v oh high-level output voltage (i oh = ? 4 ma) industrial 3.76 v v ol low-level output voltage (i ol = +4 ma) 0.37 v i cca supply current, active mode (at maximum frequency) 10.0 ma i ccs supply current, standby mode xc17s05, xc17s10, xc17s20, xc17s30 50.0 a xc17s40 100.0 a i l input or output leakage current ? 10.0 10.0 a c in input capacitance (v in = gnd, f = 1.0 mhz) 10.0 pf c out output capacitance (v in = gnd, f = 1.0 mhz) 10.0 pf
r ds030 (v1.5) april 4, 2000 7 spartan family of proms xc17s05xl, xc17s10xl, xc17s15xl, xc17s20xl, xc17s30xl, xc17s40xl, xc17s50xl, xc17s100xl, xc17s150xl, xc17s200xl absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. operating conditions note : during normal read operation both v cc pins must be connected together. dc characteristics over operating condition symbol description value units v cc supply voltage relative to gnd ? 0.5 to +4.0 v v in input voltage with respect to gnd ? 0.5 to v cc +0.5 v v ts voltage applied to 3-state output ? 0.5 to v cc +0.5 v t stg storage temperature (ambient) ? 65 to +150 c t sol maximum soldering temperature (10 s @ 1/16 in.) +260 c symbol description min max units v cc commercial supply voltage relative to gnd (t a = 0 c to +70 c) 3.0 3.6 v industrial supply voltage relative to gnd (t a = ? 40 c to +85 c) 3.0 3.6 v symbol description min max units v ih high-level input voltage 2.0 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = ? 3 ma) 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 v i cca supply current, active mode (at maximum frequency) 5.0 ma i ccs supply current, standby mode 50.0 a i l input or output leakage current ? 10.0 10.0 a c in input capacitance (v in = gnd, f = 1.0 mhz) 10.0 pf c out output capacitance (v in = gnd, f = 1.0 mhz) 10.0 pf
r spartan family of proms 8 ds030 (v1.5) april 4, 2000 ac characteristics over operating condition notes: 1. ac test load = 50 pf 2. guaranteed by design, not tested. 3. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. reset/oe ce clk data t ce t oe t lc t sce t sce t hce t hoe t cac t oh t df t oh t hc ds0306_03_011300 t cyc symbol description min max units t oe reset/oe to data delay 45 ns t ce ce to data delay 60 ns t cac clk to data delay 80 ns t oh data hold from ce , reset/oe , or clk (2) 0ns t df ce or reset/oe to data float delay (2,3) 50 ns t cyc clock periods 100 ns t lc clk low time (2) 50 ns t hc clk high time (2) 50 ns t sce ce setup time to clk (to guarantee proper counting) 25 ns t hce ce hold time to clk (to guarantee proper counting) 0 ns t hoe reset/oe hold time (guarantees counters are reset) 25 ns
r ds030 (v1.5) april 4, 2000 9 spartan family of proms ordering information valid ordering combinations * in development spartan 5v spartan 5v spartan 3.3v spartan 3.3v spartan3.3v xc17s05pd8c xc17s20pd8c xc17s05xlpd8c xc17s20xlpd8c xc17s50xlpd8c xc17s05vo8c xc17s20vo8c xc17s05xlvo8c xc17s20xlvo8c xc17s50xlso20c xc17s05pd8i xc17s20pd8i xc17s05xlpd8i xc17s20xlpd8i xc17s50xlpd8i xc17s05vo8i xc17s20vo8i xc17s05xlvo8i xc17s20xlvo8i xc17s50xlso20i xc17s10pd8c xc17s30pd8c xc17s10xlpd8c xc17s30xlpd8c xc17s100xlpd8c xc17s10vo8c xc17s30vo8c xc17s10xlvo8c xc17s30xlvo8c xc17s100xlso20c xc17s10pd8i xc17s30pd8i xc17s10xlpd8i xc17s30xlpd8i xc17s100xlpd8i xc17s10vo8i xc17s30vo8i xc17s10xlvo8i xc17s30xlvo8i xc17s100xlso20i xc17s40pd8c xc17s15xlpd8c xc17s40xlpd8c xc17s150xlpd8c xc17s40so20c xc17s15xlvo8c xc17s40xlso20c xc17s150xlso20c xc17s40pd8i XC17S15XLPD8I xc17s40xlvo8c* xc17s150xlpd8i xc17s40so20i xc17s15xlvo8i xc17s40xlpd8i xc17s150xlso20i xc17s40xlso20i xc17s40xlvo8i* xc17s200xlpd8c xc17s200xlso20c xc17s200xlpd8i xc17s200xlso20i xc17s20xl vo8 c operating range/processing c=commercial ( t a = 0 c to +70 c) i = industrial ( t a = ? 40 c to +85 c) package type pd8 = 8-pin plastic dip vo8 = 8-pin plastic small-outline thin package so20 = 20-pin plastic small-outline package device number xc17s05 xc17s05xl xc17s10 xc17s10xl xc17s15xl xc17s20 xc17s20xl xc17s30 xc17s30xl xc17s40 xc17s40xl xc17s50xl xc17s100xl xc17s150xl xc17s200xl
r spartan family of proms 10 ds030 (v1.5) april 4, 2000 marking information due to the small size of the prom package, the complete ordering part number cannot be marked on the package. the xc prefix is deleted and the package code is simplified. device marking is as follows. note: when marking the device number on the xl parts, an l is used in place of an xl. revision control date revision revision 7/14/98 1.1 cosmetic edits for pages 1 , 2 , 3 & 4 . 9/8/98 1.2 clarified the spartan fpga and prom interface by removing references to ceo pin. re- moved the esd notation in absolute maximum table since it is now included in xilinx ? s reliability monitor report. 01/20/00 1.3 added additional spartan-xl parts, changed sprom to prom. 02/18/00 1.4 changed device ordering numbers, added 4.7k resistor to oe/reset in figure 1. 04/04/00 1.5 added xc17s200xl prom for spartan xc2s200. 17s20l v c operating range/processing c = commercial ( t a = 0 c to +70 c) i = industrial ( t a = ? 40 c to +85 c) package type p = 8-pin plastic dip v = 8-pin plastic small-outline thin package s = 20-pin plastic small-outline package device number xc17s05 xc17s05l xc17s10 xc17s10l xc17s15l xc17s20 xc17s20l xc17s30 xc17s30l xc17s40 xc17s40l xc17s50l xc17s100l xc17s150l xc17s200l
|
