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application note digital video encoder module system: 7128mod2 an 97085
abstract module system: 7128mod2 philips semiconductors application note an 97085 2 philips electronics n.v. 1998 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copy- right owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other indu- strial or intellectual property rights. this application note is intended to provide application support for philips digital video decoders and encoders. it contains a description of one evaluation board as well as i2c-bus programming of the respective device. the digital video decoder converts an analog video input signal into a digital output signal. this signal can be processed by a wide range of applications and fed to the digital video encoder, which delivers analog video signals to tv receivers or video cassette recorders. this note gives a detailed description of the schematics and some hints how to design the pcb (printed circuit board) with mixed analog and digital signal processing.
keywords philips semiconductors author: digital video encoder application note an 97085 3 application note digital video encoder module system: 7128mod2 dietmar speller mpc-e, hamburg, germany digital video encoder (denc) saa7128/29 SAA7138/39 saa7120/21 saa7126/27 i2c-bus multimedia date: 5th december 1997 an 97085
summary module system: 7128mod2 philips semiconductors application note an 97085 4 this application note is intended to provide application support for philips digital video decoders and encoders. it contains a description of one evaluation board as well as i2c-bus programming of the respective device. the digital video decoder converts an analog video input signal into a digital output signal. this signal can be processed by a wide range of applications and fed to the digital video encoder, which delivers analog video signals to tv receivers or video cassette recorders. this note gives a detailed description of the schematics and some hints how to design the pcb (printed circuit board) with mixed analog and digital signal processing.
module system: 7128mod2 philips semiconductors 5 application note an 97085 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. digital video encoder module 7128mod2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 input- and output- connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.1 vg96 input connector on 7128mod2 . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.2 cvbs subclick connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.3 scart connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 i2c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 i2c eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6 clock- and synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.7 jumperlist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. interfacing input data with a y-module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. tips for a pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 analog and digital signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 iic bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5. software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 programming tables for saa7128/29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 summary of registerfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. appendix: schematics and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1.1 top sheet of 7128mod2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1.2 connector in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.3 connector out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.4 SAA7138/39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.5 saa7128/29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.6 output filter 1..6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.7 5mhz lowpass filter1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.8 5mhz lowpass filter2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.9 5mhz lowpass filter3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1.10 5mhz lowpass filter4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.11 5mhz lowpass filter5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.12 5mhz lowpass filter6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.13 i2c - eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1.14 supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.2 layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2.1 top placement of 7128mod2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2.2 routing of top layer of 7128mod2 . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2.3 top solder mask of 7128mod2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2.4 bottom placement of 7128mod2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.2.5 bottom layer of 7128mod2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.2.6 bottom solder mask of 7128mod2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.2.7 ground plane layer of 7128mod2 (mid layer1) . . . . . . . . . . . . . . . . . . . . 51 6.2.8 routing of power supply layer of 7128mod2 (mid layer2) . . . . . . . . . . . . . . 52
6 module system: 7128mod2 philips semiconductors application note an 97085
module system: 7128mod2 philips semiconductors 7 application note an 97085 1. introduction the digital video decoder/encoder modules provide the basis to evaluate various philips digital video decoders and encoders and give the opportunity to simply insert the modules into customized applications and systems. on the following pages the assembly and function of a digital video encoder module is shown. the module can operate in stand alone mode (colourbar generator) as well as extension to other systems like pci-bridges, mpeg decoders or video input/output systems. the module has a socket for an i2c-bus eeprom (e.g. pcf 8582, pcf8594, pcf8598, x24164) in order to store data for initialization and for simple control functionality operated by a (future) microcontroller module. software for ibm compatible personal computers enables access to all features and settings of the devices. it handles the i2c-bus via a printer port adaptor. this adaptor and a fitting cable is part of the accessory. this modular concept was designed to combine different video decoders with various video encoders. some modules (e.g. the 7128mod2) can be configured for several devices and packages without the necessity of having a new pcb. this could be achieved by using multiple footprints for one ic and some configurational parts. for interfacing a 96-pin module connector is used. the modules need a 5v analog and a 5v digital supply voltage. a respective power connector is placed at each backend (encoder-) module whereas frontend modules are supplied via the 96-pin module connector. if necessary, an internal voltage regulator generates the required 3.3v onboard. alternatively it is also possible to bypass the regulators on some encoder modules and connect 3.3v supply directly to the respective pins. you can find a fitting power connector cable as a part of the accessory as well. 2. digital video encoder module 7128mod2 the digital encoder module 7128mod2 contains the philips digital encoder saa7128/29, SAA7138/39, saa7120/21or saa7126/27 (the even-numbered types include macrovision pay-per-view copy protection, while the odd-numbered types do not). all listed encoders are cmos 3.3v devices with 3.3v input stages but differ (among others) in following features: saa7128/29 pal/ntsc/secam encoder with six dacs for cvbs(csync), vbs(cvbs), c(cvbs), r(cr), g(y), b(cb) (signals in brackets optionally) and a 54mhz double speed multiplexed d1 interface. it features also a versatile fader for fading of two data streams (at double speed port mp) against each other. qfp44 package. SAA7138/39 pal/ntsc/secam encoder with six dacs for cvbs(csync), vbs(cvbs), c(cvbs), r(cr), g(y), b(cb) (signals in brackets optionally) and a 54mhz double speed multiplexed d1 interface. it features also a versatile fader for fading of two data streams (at double speed port mp or through the additional port dp) against each other. qfp64 package. saa7120/21 pal/ntsc encoder with three dacs for c vbs, y, c. qfp44 package. saa7126/27 pal/ntsc encoder with four dacs for cvbs(csync, vbs), r(cr, c), g(y, vbs) and b(cb, cvbs) (si gnals in brackets optionally) and a 54mhz double speed multiplexed d1 interface. qfp44 package. the digital data is fed via the 96-pin input connector. the circuits accept ccir compatible yuv data with 720 active pixels per line in 4:2:2 multiplexed formats, for example mpeg decoded data. for interfacing an ecl - ttl converter can be used (accessory). at a 54mhz (double speed) multiplexed d1 input port the circuits accept two ccir compatible cbycr data streams for example mpeg decoded data with overlay, whereas one datastream is
8 module system: 7128mod2 philips semiconductors application note an 97085 latched at the rising, the other one at the falling clock edge. therefore a special y-module is designed (available jan. 98). this y-module will provide two input module connectors with multiplexer, an eprom with ccir 656 data and a centronic interface to generate a 54mhz interlaced data stream (see chapter 3.). after passing the analog postfilters (to be be disabled with jumper) the output signal is available simultaneously as cvbs, y/c ( and rgb) at the respective connectors (scart for c vbs, y/c, rgb and additionally a subclick connector for cvbs output). an adaptor from scart to mini din and cinch is part of the accessory. to prevent a wrong termination, be sure that the cvbs0 signal is not switched to the cvbs output connector and the scart output (cvbs output or rgb-sync) at the same time (jp14, jp15). fig.1 location of ics, jumpers and connectors on the 7128mod2 pcb fig.1 shows the location of ics, jumpers and connectors on the application module 7128mod2. the function of the used connectors is described on page 10. the function of jumpers is shown in a jumper list on page 16. abc dil20 spare 71__mod2 v1.0 dil8 dgnd agnd a0 a1 a2 u5 cvbs us new old +5vd dgnd +5va agnd -5va 27 mhz reset cvbs c filter off || filter on = y r b g scart filter source resn switch extern i2c 5v 3,3v u4 saa7120/21 saa7126/27 saa7128/29 SAA7138/39 philips mpc-e/pd october 1997 termllc_2 termllc_1 cvbs1 cvbs2 s5/o10 sa llcb clkout llca llcout llc_1 xclk llc_2 hs to rcv2 vs rcv1 odd cvbs1 cvbs2 cvbs0 y/c / rgb y/c / cvbs rgb active y/c saa7126/27 i2c eeprom i2c-con
module system: 7128mod2 philips semiconductors 9 application note an 97085 2.1 power supply the +5v analog and digital power supply should be kept separate at the power connector. analog and digital ground must be connected once near the power supply units. a negative voltage (-5v) is one part of the mpc module system supply voltages but is not necessary for this application. all supply voltages are available at the vg96 input connector according to the pinning on page 10. 2.2 reset there are two different ways to reset the device: using this module in conjunction with a mpc decoder module, preferably the reset not generated by the deco- der should be used (jp26 = extern). therefore a dedicated pin exists at the vg96 input connector. in case of a stand alone operation (e.g. colourbar generator) or in conjunction with other systems the reset push-button can be used (jp26 = switch). during reset (resn = low) and after reset is released, all digital i/o stages are set to input mode, pal-black- burst on cvbs, vbs and c; all analog outputs are set to high impedance. a reset forces the i2c-bus interface to abort any running bus transfer and sets register 3a to 03h, register 61 to 06h and registers 6bh and 6eh to 00h. all other control registers are not influenced by a reset.
10 module system: 7128mod2 philips semiconductors application note an 97085 2.3 input- and output- connectors 2.3.1 vg96 input connector on 7128mod2 table 1 pinning of the vg96 module input connector (bottom view) *: only for SAA7138/39 in a b c 32 -5v analog 31 gnd analog 30 +5v analog 29 gnd digital 28 27 +5v digital 26 25 sda resn scl 24 vp7 23 vp6 clkout* 22 vp5 21 vp4 20 vp3 llc_2* 19 vp2 18 vp1 17 vp0 llc_1 16 odd 15 14 13 rtci 12 vs 11 hs 10 source* 9 8mp7 ttxrq 7mp6 ttx 6 mp5 rcv2 5 mp4 rcv1 4mp3 3mp2 2mp1 1mp0
module system: 7128mod2 philips semiconductors 11 application note an 97085 table 2 description of signals on the vg96 module input connector *: only for SAA7138/39 signal specification sda i 2 c-bus serial data. scl i 2 c-bus serial clock. resn reset not input (active low). after reset is applied, all digital i/os are in input mode; pal-blackburst on cvbs, vbs and c; rgb outputs set to lowest voltage. the i2c-bus receiver waits for the start condition. mp (7..0) double speed 54mhz mpeg port. input for ccir 656 style multiplexed cb, y, cr data. data are sampled at the rising and falling clock edge; data sampled on the rising edge then are sent to the encoding part of the device, data sampled on the falling edge are sent to the rgb part of the device (or vice versa, depending on programming) dp* (7..0) data port input for ccir 656 style multiplexed cb, y, cr data. llc_1 line-locked clock input 1; this is the 27mhz master clock (via jp13a) llc_2* line-locked clock input 2; this is the alternative source for the 27mhz master clock (via jp13) clkout* line-locked clock output, this is the buffered output for the selected 27mhz master clock (via jp13a) source* fast switch between dp and mp port. if the fader is bypassed, a high selects mp port, a low selects dp port. hs horizontal synchronous signal for synchronization via rcv2. vs vertical synchronous signal for synchronization via rcv1 (jp9). odd odd/even field i dentification, for synchronization via rcv1 (jp9). rcv1 raster control 1, this pin provides or receives a vs, fs or fseq signal. rcv2 raster control 2, this pin provides an hs pulse of programmable length or receives an hs pulse. rtci real time control input. if the llc clock is provided by a digital video decoder like saa7111a, supporting this function. rtci should be con- nected to the rtco pin of the respective decoder to get information con- cerning actual subcarrier, pal-id, and more, depending on the video decoder. ttxrq teletext request output, indicating when the bit stream is requested. ttx teletext bit stream input.
12 module system: 7128mod2 philips semiconductors application note an 97085 2.3.2 cvbs subclick connector this is the output for the cvbs signal that passed the 5mhz lowpass filter and the jp14 (cvbs_out). this jumper selects the cvbs output (cvbs0 or opti onally cvbs1,2 at y/c lines). a simultaneous load at this conne- xctor and the scart connector should be avoided. 2.3.3 scart connector fig.2 output connector the figure above shows the analog output circuit with subclick- and scart- connector. the main cvbs line should not be switched to both subclick and scart (cvbs output or csync) at the same time. the saa7128/ 29 and SAA7138/39 offer additional c vbs outputs on y and c pins as option (jp14). to enable rgb input to a scart tv plug, close jp16. in this case jp17 must be in position rgb saa7120/21: this device provides no other signals than cvbs and y/c one time so the jumper configuration is jp14 = cvbs0 and jp17 = y/c. saa7126/27: this device provides c vbs and y/c or rgb si gnals at the respective connectors. for y/c output jp31 and jp32 must be closed. a cvbs0 cvbs1 cvbs2 rgb y / c "place side by side" y / c cvbs ycout1 ycout0 rgbout1 rgbout0 rgbout2 p4 scart cvbs out 19 cvbs gnd 17 red 15 red gnd 13 grn 11 grn gnd 9 bl 7 bl gnd 5 l out 3 r out 1 cvbs in 20 st rgb gnd 18 st rgb 16 d2b gnd 14 d2b 12 d2b 10 ctrl i/o 8 l in 6 lr gnd 4 r in 2 gnd 21 p3 cvbs_con 1 2 1 2 jp16 rgb active 1 2 jp15 1 3 2 jp17 1 3 2 jp14 1 3 2 cvbsout ycout[1..0] rgbout[2..0] vdd a
module system: 7128mod2 philips semiconductors 13 application note an 97085 2.4 i2c-bus two i2c-bus slave addresses are selected: 88h: low at pin sa 8ch: high at pin sa systems running in a 3.3v environment probably require the same voltage for the i2c-bus. in this case, jp29 must be changed from default position to 3.3v in order to adjust the i2c supply voltage. a new single master interface with the ic 74hc9114d can be used then, it replaces the former single master interface with the ic 74ls05, which is only suited for 5v. the new interface operates on the i2c-bus from 1.8v to 5v. please note that there are no additional pullup resistors on this board, thus supply of the i2c-bus is provided once at the (single master-) i2c-bus interface. on this backend module, two connectors can be used for i2c-bus control (alternative). the first one is a 6pin mini din connector with the pinning shown on the right side of fig.3. in order to consider different existing pinnings, the stoko connector has a combined footprint for the standards old, new and us. please note that modules from the philips application lab. hamburg use the norm new while the default configuration of the mpc module system is old. fig.3 pinning of i2c-stoko and mini-din connector 2.5 i2c eeprom a dil 8 socket on each module is provided for adding an eeprom with i2c interface. it can be used to store data for initialization and simple control functionality operated by a (future) microcontroller module. several eeprom types can be assembled depending on their memory size (e.g. pcf8582, pcf8594, pcf8598, x24164). additio- nally, the i2c-bus device address can be adapted by using the jumper 1..3 (eep-adr). combi-footprint vcc gnd scl sda sda vcc gnd scl vcc sda gnd scl new old us (top view) gnd scl sda gnd vcc (solder view)
14 module system: 7128mod2 philips semiconductors application note an 97085 2.6 clock- and synchronization signals there are two operating modes for the encoder on this board. in master mode, v- and h- signals are output of the rcv1 and rcv2 pins in order to synchronize an external source (e.g. memory or teletext). in slave mode the synchronization signals h and v are generated out of the frame sync code embedded into the ccir-656 data stream or fed to the encoder via rcv1 and rcv2 (after passing jp23 and jp24). the configura- tion of rcv1 and rcv2 (direction, polarity etc.) is handled in reg. 6bh (some information about register- functions can be found on page 25). after a reset the rcv pins are programmed as inputs. regardless of master or slave mode operation, the system clock llc can come from external or from the chips own oscillator. figures 4 and 5 show the respective jumper to configure clock direction. when an external clock is received, jp27 and jp28 allow termination of llc_1 and llc_2 by adding a 240r resistor to ground. in addition to this, series resistors (22r) terminate these clock lines. fig.4 clock switching for SAA7138/39 possible applications are: - the internal oscillator provides the master clock by connecting xclk and llc1 (or llc2). the buffered clock signal at pin llcout is switched to vg96 pin llc for other circuits. - an external oscillator can clock the device via vg96 pin clk2_in and jp13. like in the first case, the buffe- red clock signal at pin llcout is switched to vg96 pin llc for other circuits. - an external oscillator can clock an external device (e.g. mpeg decoder). the clock signal comes in via clk2_in and out via the buffered clock output llcout and the vg96 pin clkout. abc saa 7138/39 llc2 xclk llc1 llcout clk2 in (b20) llc (b17) clk out (b23) jp13 jp13a
module system: 7128mod2 philips semiconductors 15 application note an 97085 fig.5 clock switching for saa7128/29 (26/27, 20/21) if types other than SAA7138/39 are being used,only jumper (jp13) is essential. in master mode the internal osci- llator generates the clock at pin xclk and jumper (jp13) is used to connect the device and external circuits via llc_1. the shown shortcut is done by a 0r resistor. in slave mode this jumper must be open. abc saa 7128/29 saa 7126/27 saa 7120/21 xclk llc1 llc_1 (b17) shortcut
16 module system: 7128mod2 philips semiconductors application note an 97085 2.7 jumperlist table 3 jumperlist 7128mod2 jumper name description jp1,2 c 5mhz lowpass filter 1 on/off jp3,4 y 5mhz lowpass filter 2 on/off jp5,6 cvbs 5mhz lowpass filter 3 on/off jp7,8 b 5mhz lowpass filter 4 on/off jp9,10 g 5mhz lowpass filter 5 on/off jp11,12 r 5mhz lowpass filter 6 on/off jp13 xclk/clk2in handles clock direction together with jp13a jp 13a clock i/o (5 pins) handles clock directions acc. to fig. jp14 cvbs out co nnects default c vbs1 or opt. cvbs2,3 to subclick jp15 y/c / cvbs scart output: cvbs0 or y jp16 rgb active activates rgb input of e.g. tv if closed jp17 y/c / rgb scart output: red or c jp18 a0 eeprom address a0 jp19 a1 eeprom address a1 jp20 a2 eeprom address a2 jp21 s5/o10 cvbs2 closed: cvbs2 out; open: for y/c out (c-path) jp22 s5/o10 cvbs1 closed: cvbs1 out; open: for y/c out (y-path) jp23 hs to rcv2 connects hs line to rcv2 device-pin jp24 odd/vs connects odd line or vertical sync to rcv1 device-pin jp25 sa i2c slave address select, closed = 88h, open = 8ch jp26 resn selects source for reset not signal (push-b./inp.conn.) jp27 termllc_1 termination of 1st llc line with 240r jp28 termllc_2 termination of 2nd llc line with 240r jp29 iic 5v/3v supply voltage for i2c-bus (default: 5v) jp30 source fast switch input port (only for SAA7138/39) jp31 y/c saa7126 y/c output from saa7126/27 (c-path) jp32 y/c saa7126 y/c output from saa7126/27 (y-path)
module system: 7128mod2 philips semiconductors 17 application note an 97085 3. interfacing input data with a y-module the following drawings show some principal ways how to connect a chameleon digital video encoder to one or two video/overlay data sources. within saa7128/29 (eventually within a device indicated here as SAA7138/39), the two video data streams can be directed separately to rgb outputs and y/c/cvbs outputs. a hard keying or versatile chroma keying and fading is available for combing both data streams mode 1: clock llc comes from saa7111a (or a similar philips digital video decoder), the saa7128/29 video encoder is slaved to the sync code (frame sync) embedded into the ccir-656 data stream from saa7111a. output h - sync and v- sync from saa7128/29 master a memory controller and memory for output of overlay data. memory con- troller and associated memory can also be considered to be represented by the osd/overlay part of an mpeg decoder. the two data streams, one from saa7111a, the second from the overlay generator, are multiplexed to a physical 54 mhz data stream, using llc as a control signal for the external multiplexer. mode 2: the on-chip llc clock generator of saa7128/29 is used to clock the mpeg decoder and the memory, providing osd/overlay signals. both mpeg decoder and separate overlay source are slaves of saa7128/29 h- and v- syncs. this seems to be a rather uncommon configuration, in practice mode 3 will be more of interest. mode 3: llc clock is coming from the on-chip crystal oscillator of saa7128/29, which should be able to be fine-tuned in a certain range. (llc could also come from an external oscillator of similar properties). the mpeg decoder is sla- ved to saa7128/29 w.r.t. h- sync and v- sync. a 54 mhz multiplexed data stream, carrying e.g. video with overlay data at the rising clock edge and video wit- hout overlay data at the falling clock edge, is directly fed to the 54 mhz input port of saa7128/29. mode 4: as the device indicated here SAA7138/39 has two separate 8 bit d1 ports, ?mp' and ?vp', external demultiplexing is not necessary. the video decoder saa7111a is master for the video encoder w.r.t. llc clock and h-sync and v-sync (embed- ded frame sync in the ccir-656 data coming out of the video decoder and going into vp input). the encoder-internal clock chip buffers the clock as llcout for the osd/overlay source. SAA7138/39 is sync master for the osd/overlay source, which is sending its data to the mp input. again, this configuration seems to be uncommon (for test purposes, only), and mode 5 should be focused on the more. mode 5: again, the video decoder saa7111a is clock and sync master for SAA7138/39, providing clock llc to clock input llc_1, and video and sync via input port vp. through h- and v- sync coming out of SAA7138/39, additional osd/overlay data can be taken from the mpeg decoder in order to overlay it to the (digitized) analog video. in this case, llcout for the mpeg decoder is derived from llc_1. the osd/overlay data can come with the rising or falling edge of llcout or with both edges. if the active video source is mpeg video, the saa7111a video decoder will idle, and clock for SAA7138/39 is llco, fed to the llc_2 input of the encoder-internal clock multiplexer. for this operational mode, also the on- chip crystal oscillator instead of an external oscillator could be used.
18 module system: 7128mod2 philips semiconductors application note an 97085 interfacing 54mhz data via y-module with saa7128/29 operating as a clock slave / master (mode1 + 2) i saa7111a memory control memory centronics eprom mp2 mp1 27mhz data (8bit) llc 54mhz multiplexed data (8bit) rcv1,2 h( 1 ), v llc saa7128/29 ( 2 ) ( 1 ): delayed via 74 574 ( 2 ): delayed via 74 240 mux mpeg decoder memory control memory centronics eprom mp2 mp1 mpeg decoded data llc 54mhz multiplexed data (8bit) rcv1,2 h( 1 ), v llc saa7128/29 ( 2 ) ( 1 ): delayed via 74 574 ( 2 ): delayed via 74 240 h, v mux
module system: 7128mod2 philips semiconductors 19 application note an 97085 interrfacing 54mhz data via y-module with saa7128/29 operating as a clock master (mode 3) interfacing 54mhz data via y-module with SAA7138/39 operating as a clock slave (mode 4) mpeg decoder memory control memory centronics eprom mp1 mpeg decoded data 54mhz multiplexed 8bit llc 54mhz multiplexed data 8bit rcv1,2 h( 1 ), v llc saa7128/29 ( 1 ): delayed via 74 574 h, v mux saa7111a memory control memory centronics eprom mp2 mp: 27mhz data 8bit rcv1,2 h( 1 ), v SAA7138/39 ( 1 ): delayed via 74 574 llc vp: 27mhz data 8bit llc_1 llcout 27mhz data 8bit mux
20 module system: 7128mod2 philips semiconductors application note an 97085 interfacing 54mhz data via y-module with SAA7138/39 operating as a clock slave (mode 5) saa7111a memory control memory centronics eprom mp1 mp: 27/54mhz data 8bit rcv1,2 h( 1 ), v SAA7138/39 ( 1 ): delayed via 74 574 llc vp: 27mhz data 8bit llc_1 llcout 27mhz data 8bit mpeg decoder 27/54mhz mpeg decoded data h, v llci llco llc_2 mux
module system: 7128mod2 philips semiconductors 21 application note an 97085 4. tips for a pcb layout 4.1 analog and digital signal processing - use separate ground planes for analog and digital supply in one layer (no overlapping!) - use separate supply planes for analog and digital with the same shape (or smaller) as ground (no overlap of analog supply with digital ground and vice versa!) - if there are different (asynchronous) clock domains, use separate ground and supply planes (place the analog areas not in a direct neighborhood; separate the clock domains) - always use the inner layers for ground and supply planes (no signal layer in between!) - try to keep digital signals away from analog areas - place analog areas close to the border of a pcb - avoid long tracks for analog signals - place decoupling capacitors (22nf to 100nf) close to the power pins of the ics - prepare several provisions for connecting places for analog and digital ground on the pcb for further optimization on the final board. 4.2 iic bus always supply the i2c-bus with pull-up resistors, but avoid too high currents. the values of resistors rp and rs depend on the following parameters: - supply voltage - bus capacitance - number of connected devices (input current + leakage current) please see i2c-bus specification (e.g. chapter 10.1 in the philips data handbook: maximum and minimum values of resistors rp and rs). 4.3 application information application environment of all possible encoders on this board is shown at the end of the datasheet of the respective device.
22 module system: 7128mod2 philips semiconductors application note an 97085 5. software the enclosed disk contains the latest version of the universal register debugger software (urd) and some files and macros for easy debugging philips encoders and decoders in conjunction with the i2c-bus parallel port adaptor. for this module please open the file saa7128.urd to get a default setup as described on the following page. the information will be transmitted by clicking the wd (write default) push button. to change this setting (e.g. for ntsc or secam encoding) there exist macros as shown on pages page 24 and following. the program is caused to perform a macro operation by clicking the push button right in front of the macro name. for editing single values use +/- on your keyboard and then click wn (write now). you can find further details concerning the software in the doc-file on the disk.
module system: 7128mod2 philips semiconductors 23 application note an 97085 5.1 programming tables for saa7128/29 saa7128/29: init data pal slave: 88h or 8ch sub data sub data reg 26h 0dh reg 5ch afh reg 27h 00h reg 5dh 2dh reg 28h 1fh reg 5eh 3fh reg 29h 1fh reg 5fh 3fh reg 2ah 75h reg 60h 7bh reg 2bh 3fh reg 61h 02h reg 2ch 06h reg 62h 46h reg 2dh 3fh reg 63h cbh reg 38h 1ah reg 64h 8ah reg 39h 1ah reg 65h 09h reg 3ah 13h reg 66h 2ah reg 42h 00h reg 67h 77h reg 43h 68h reg 68h 41h reg 44h 10h reg 69h 88h reg 45h 97h reg 6ah 41h reg 46h 4ch reg 6bh 12h reg 47h 18h reg 6ch 02h reg 48h 9bh reg 6dh 20h reg 49h 93h reg 6eh a0h reg 4ah 9fh reg 6fh b4h reg 4bh ffh reg 70h 41h reg 4ch 7ch reg 71h c3h reg 4dh 34h reg 72h 00h reg 4eh 3fh reg 73h 3eh reg 4fh 17h reg 74h b8h reg 50h 00h reg 75h 1eh reg 51h 83h reg 76h 15h reg 52h 83h reg 77h 16h reg 53h 80h reg 78h 15h reg 54h 8ch reg 79h 16h reg 55h 0fh reg 7ah 2bh reg 56h c3h reg 7bh d9h reg 57h 06h reg 7ch 80h reg 58h 02h reg 7dh 00h reg 59h 80h reg 7eh 00h reg 5ah 34h reg 7fh 00h reg 5bh 7dh the table shows a default setup for the saa7128/29. with following settings: 8-bit input data format working as clock slave detection of sync. signals (h, v) out of datastream output format = pal wss, ttx and closed caption disabled internal colour bar off (luts programmed to 100% colourbar not listed registers must be programmed to 00h to activate the programmable colour bar generator the msb of register 3ah must be set to 1. bold signed registers must be edited for changing the output format (ntsc, secam) the most important changes e.g. concerning output format are shown in the next tables.
24 module system: 7128mod2 philips semiconductors application note an 97085 table 4 changes for ntsc and secam the tables show the registers that are changed when performing a macro function. saa7182/83: changes for ntsc slave: 88h or 8ch saa7182/83: changes for secam slave: 88h or 8ch sub data sub data reg 5ah reg 5ah reg 5bh reg 5bh reg 5ch reg 5ch reg 5dh reg 5dh reg 5eh reg 5eh reg 5fh reg 5fh reg 61h reg 61h reg 62h reg 62h reg 63h reg 63h reg 64h reg 64h reg 65h reg 65h reg 66h reg 66h reg 6ch reg 6ch reg 6dh reg 6dh reg 6eh reg 6eh reg 7ah reg 7ah reg 7bh reg 7bh
module system: 7128mod2 philips semiconductors 25 application note an 97085 5.2 summary of registerfunctions in the following table the usage of registers is described in order to get a quick view of the most important functions and give help for programming the device. the table does not contain whole information about the function or determination of values but should give background information. the subaddress is the location according to the described function but not exclusive in every case. for further details see chapter slave recei- ver in the datasheet. table 5 registers of the saa7128/29 function subadr description status byte (read only) 00h null 01h - 25h always program with 00h in order to avoid unexpected effects wide screen signal 26h - 27h wsson enables or disables completely the wss encoding; for meaning of the individual bits refer to the table given in ets-300 294 real time control 28h if rtce is set to high, real time control (rtc) of the generated subcar- rier frequency is enabled. rtc should be used whenever the clock for the video encoder is generated by a digital line-locked video decoder to ensure stable encoding phase for clean colors. from a decoder supporting the new function deccol, a flag indicating that color was detected can be received if deccol=high. if decfis=high, the field frequency information detected by a decoder can be received. burst start / end 28h - 29h the begin and the end of the color burst can be adjusted in a certain range at an accuracy of llc clock cycles; the suggested defaults should be used copy generation 2ah - 2ch cg19-cg0: lsbs of the respective bytes are encoded immediately after run-in, the msbs of the respective bytes have to carry the crcc bits, in accordance with the definition of copy generation management system encoding format. cgen set low disables the insertion. output port control 2dh all dac outputs can be set individually to high impedance through bits btri (blue or cb), gtr (green or y), rtri( red or cr) ytri( vbs or cvbs), cvbstri (cvbs or csync). if cvbsen0 is set low, the c si gnal is directed to the dac normally used for this signal; if cvbsen0 is set high, a cvbs si gnal is directed to this dac as an alternative. if cvbsen1 is set low, the vbs signal is directed to the dac normally used for this signal; if cvbsen1 is set high, a cvbs si gnal is directed to this dac as an alternative. null 2eh - 37h always program with 00h in order to avoid unexpected effects gain luma and gain colour diff. of rgb 38h - 39h common practice is to set gy=gcd in order to adjust both luminance con- trast and color saturation, when rgb output mode is chosen. the suggested nominal values given in the datasheet are based on the proposed external resistor circuitry (23 ohm series, 75 ohm load).
26 module system: 7128mod2 philips semiconductors application note an 97085 input port control 1 3ah (0, 1): setting these bits high for straight binary data, inverts the msb inter- nally for correct processing; setting these bits low passes the data as it is. (2): when this bit is set low, a cvbs signal is directed to the dac normally used for this signal; if it is set low, a composite sync only is directed to this dac as alternative. (3): when this bit is set high, the color dematrix is by-passed, and video input is only up-sampled to 27 mhz data rate for output instead of rgb. (4): when this bit is set high, in slave mode the encoder is triggered by an embedded frame sync code within the ccir-656 data input. if the embed- ded frame sync is not available, this bit must be set low and appropriate signals have to be provided at rcv1 and rcv2 inputs. (6): SAA7138/39 only: this bit set low enables the fader function; if it is set high, two input signals can be hard-keyed via the pin source. (7): setting this bit high decouples the video input and inserts a test signal defined by eight color-programmable bars, e.g. a 100/75 color bar. key colour 42h - 4dh two 24 bit (true color) color ranges key1 and key2 are defined, which together with the weighting factors fade1 and fade2 determine the yuv color range of the first input signal to be blended with the second input signal. fade 4eh - 50h fade1, fade2 and fade3 are 6 bit multiplicators, defining the trans- parancy of the two input signals. while fade1 and fade3 operate in the yuv color space defined through the borders of the key color parameters, fade3 blends the color stored in the internal lut against one of the input signals. if cfadev is set high, the first input signal (mp1) at port mp is mixed enti- rely with the color stored in the internal lut, using fade3 as multiplicator, regardless of the defined keying range. if cfadev is set high, the second input signal (mp2) at port mp is mixed entirely with the color stored in the internal lut, using fade3 as multipli- cator, regardless of the defined keying range. look up table for key colour 51h - 53h true color value of the internal lookup table that is used for blending if a color within color range key2 is detected in the first i nput signal. input port control 2 54h if edge1 set low, data of the first input signal at mp port are sampled at the rising clock edge, otherwise at the falling clock edge. if edge2 set low, data of the second input signal at mp port are sampled at the rising clock edge, otherwise at the falling clock edge. only SAA7138/39:if vpsel set low, fader input vp is fed with data app- lied to dp port, if vpsel set high, fader input vp is fed with data applied to mp2 input . if delin set low, data at dp port are by-passing the fader; if delin set high, data of mp2 are by-passing the fader. if rgbin set low and delin set low, data to the rgb processor come from the dp port; if rgbin set low and delin set high, data to the rgb processor are mp2 data; if rgbin set high, the output of the fader is fed data to the rgb processor. function subadr description
module system: 7128mod2 philips semiconductors 27 application note an 97085 video programming system data inser- tion 54h - 59h vpsen set to high enables the insertion of data for video programming system. five bytes vps5, vps11, vps12, vps13, and vps14 can be loaded acc. to the specification of vps chroma phase 5ah this register defines the absolute subcarrier phase w.r.t. the synchroniza- tion pulse scheme. although in practice the absolute subcarrier phase is almost never relevant, values for the most common standards ntsc-m and european pal are given. please note that the value is different when the internal color bar function is active. gain_u, gain_v 5bh - 5eh these registers directly influence the amplitude of the internal color diffe- rence baseband signals and thus of the generated subcarrier for quadra- ture modulated standards (for secam, the frequency deviation is influenced!) usually, the nominal settings given in the datasheet should be used; in case that an analog post filter contributes noticeable attenuation around the subcarrier frequency, both gainu and gainv should be enlarged accordingly. note that the sign bit (0=positive, 1=negative) is located in 5dh for gainu and in 5eh for gainv. black level 5dh this parameter adds a certain offset to the luminance signal w.r.t. to the sync tip, but leaves the peak-peak amplitude unaffected. real time control 5dh - 5eh if decoe=high, the odd/even information can be received from a deco- der supporting this function. if decph=high, a subcarrier oscillator phase reset initiated on the decoder side will reset the phase of the encoder oscillator. blanking level 5eh - 5fh this parameter adds a certain offset to the luminance blanking level w.r.t. the sync tip. note that this parameter has to be set twice, i.e. outside (5eh) and inside (5fh) the vertical blanking interval. usually, both blankings are identical. null 60h always program with 00h in order to avoid unexpected effects standard control 61h (0): configures the internal pixel counter either to 858 pixels/line (high) or 868 pixels/line (low) (1): this bit set to high enables the pal specific process of inverting the v color difference component line by line. (2): usually set to high for standard-compliant chroma bandwidth; in some cases (e.g. for best s-video quality), it can be set to low. (3): this bit set to high enables the secam processing; it overrides bit pal (4): this bit selects one of two possible gain factors for the luminance black-to-white amplitude; when set to high, luminance is adjusted for 92.5 ire output amplitude, and when set to low for 100 ire output amplitude. (5): only relevant when rtce bit is high; usually set to low. (6): if set to high, internally a constant code corresponding to the lowest possible output voltage at the dacs for cvbs, y/c is applied. (7): if set to high,internally a constant code corresponding to the lowest possible output voltage at the dacs for r, g, b is applied. function subadr description
28 module system: 7128mod2 philips semiconductors application note an 97085 real time control enable 62h if rtce is set to high, real time control (rtc) of the generated subcar- rier frequency is enabled. rtc should be used whenever the clock for the video encoder is generated by a digital line-locked video decoder to ensure stable encoding phase for clean colors. burst amplitude 62h these registers directly influence the amplitude of the color burst for qua- drature modulated standards (for secam, the amplitude of the color burst cannot be modified!) usually, the nominal settings given in the datasheet should be used; in case that an analog post filter contributes noticeable attenuation around the subcarrier frequency, this parameter should be enlarged accordingly. subcarrier fre- quency 63h - 66h the subcarrier frequency is synthesized by a 32 bit discrete time oscilla- tor; all four bytes are fully programmable line 21 encoding 67h - 6ah closed caption and extended data service bytes to be downloaded inclu- ding parity bit at the msb position of each byte. rcv-port control 6bh handles input- or output signal of rcv1 and rcv2 pins (see correspon- ding table in the datasheet). although the usual definition for master mode stands for trigger i/os to be switched to output, the device allows for a kind of mixed mode as to be sla- ved by a frame sync applied to pin rcv1 and simultaneously to output a horizontal pulse on pin rcv2. h-trigger control 6ch - 6dh sets the horizontal trigger phase related to signal on rcv1 or rcv2. if a vertical sync is applied to rcv1, an additional horizontal sync at rcv2 is needed to adjust the position of video horizontally. v- trigger control 6dh sets the vertical trigger phase related to the input signal on rcv1; value vtrig - counting half lines - should be even, only. field length control 6eh interlaced operation or two different non-interlaced modes are selectable for 525/60 signals or 625/50 signals. luma delay 6eh depending on ldel1 and ldl0 bits, an extra delay of the luminance signal portion (for vbs or cvbs) can be added in order to com pensate for group delay distortions of the analog post filter. phase reset mode of the colour subcar- rier generator 6eh these two bits should exactly be set acc. to the table in the datasheet. for ntsc signals, both two-line reset or four-field reset are possible. blckon 6eh this bit set to low ensures normal operation, while set to high forces the all signals to blanking level. v-blanking definition 6eh setting this bit to low will define the vertical blanking interval by the values loaded into registers fal and lal; if this bit is set to high, the vertical blanking intervall is forced acc. to ccir-624 (50hz) or acc. to rs170a (60hz) individual line 21 encoding 6fh two bits enabling field-dependent insertion of closed caption/ eyxtended data. teletext enable 6fh for any line with teletext insertion, this bit must be set to high, as it is a master switch. the actual selection for activated text lines is made below. function subadr description
module system: 7128mod2 philips semiconductors 29 application note an 97085 line select for clo- sed caption or exten- ded data 6fh this parameter selects one out of 32 possible position for closed caption encoding; usually it is line 21 for ntsc corresponding to 11h. start / end rcv2 70h - 72h these registers define start and end of a pulse repeating at line frequency: note that if start is greater than end, the pulse will be inverted. start / delayttxrq 73h - 74h every high-state of the signal at pin ttxrq - depending on the chosen text format - initiates the transfer of a new teletext bit stream bit; as this bit stream must match to the internal pixel counter, the start of the first request pulse is programmable by ttxhd to accomodate to indiviual lat- encies of the bit stream source. ttxhs is an internally needed parameter and should be taken as given in the datasheet. vsync shift 75h in master mode (rcv1 and rcv2 as outputs), sometimes the phase of the horizontal pulse on rcv2 must be shifted against the phase of the ver- tical sync pulse on rcv1 in steps of 27 mhz clock cycles. this can be accomblished with this parameter in 3 steps. csync advanced 75h in order to compensate for shorter propagation of rgb signals through a tv scart input, the alternative csync signal on the (usually) cvbs dac can be advanced up to 31 llc clock cycles. ttx odd / even request vs/ve 76h-79h, 7ch for the odd and even field, the lines to carry teletext information can be determined individually. note that it is possible to nearly use the complete inactive and the com- plete active fields for teletext insertion instead of video. first / last active line 7ah - 7ch these parameters define the vertical blanking interval if bit sblbn = low. main purpose is to widen the range for active video input, as the input data are ignored during the lines that are dedicated to belong to the vertical blanking interval. e.g., time code could be inserted through the video input port when fal is programmed to start before the normal first active line. ttx mode 7ch ttxo set to low enables the universal ttx protocol: at every rising edge of ttxrq a single ttx bit is requested. ttxo set to high enables the older ttx protocol for compatability rea- sons: the encoder provides a high state window of ttxrq, and the length of the window depends on the chosen text standard. depending on the selected field frequency (bit fise), the teletext stan- dard is being selected through ttx60 null 7dh always program with 00h in order to avoid unexpected effects disable ttx line 7eh - 7fh starting with line line 8, ending with line 23 inclusive, each of these lines can be disabled for teletext insertion (the respective bit set to high), although enabled by the global window definitions for teletext. this can be useful in order to allow e.g. other information entering through the video input to be inserted between lines containing teletext. function subadr description
30 module system: 7128mod2 philips semiconductors application note an 97085 6. appendix: schematics and layout the schematics (made in orcad) can be delivered on request. for a board layout gerber files are available.
3 1 module system: 7128mod2 philips semiconductors application note an 97085 6.1 schematic 6.1.1 top sheet of 7128mod2 tuesday, april 02, 1996 1 1 a4 114 friday, october 10, 1997 o:\orcad_97\chameleon\7128mod2_iba.dsn saa7128/29 38/39 module philips mpc-e speller ti t le size document number rev date: sheet of modif y : path designer eeprom eeprom sda scl vdd5 conn_in conn_in vddan vdd vdda scl sda resn mp[7..0] sync[3..0] rcv[2..1] ttx ttxrq vp[7..0] clk[3..0] source saa7128/29 38/39 saa7128/29 38/39 sda scl resn cvbs mp[7..0] sync[3..0] yc[1..0] rgb[2..0] vdd5 ttx ttxrq rcv[2..1] vp[7..0] clk[3..0] source vdd3,3 vdda3,3 supply supply vdd vdda vdd5 vdd3,3 vdda3,3 output filter output filter yc[1..0] ycout[1..0] cvbs cvbsout rgb[2..0] rgbout[2..0] conn_out conn_out vddan vdd vdda ycout[1..0] cvbsout scl sda rgbout[2..0] vdd3,3 vddan vdd vdda vp[7..0] clk[3..0] vdd5 rgb[2..0] rcv[2..1] mp[7..0] yc[1..0] sync[3..0] cvbs vdda3,3 vdd3,3 vdd scl sda ycout[1..0] rgbout[2..0] vdda vddan
32 module system: 7128mod2 philips semiconductors application note an 97085 6.1.2 connector in tuesday, april 02, 1996 1 1 a4 814 friday, october 10, 1997 o:\orca d_97\cha meleon\7128mod2_iba .dsn conn_in philips mpc-e spel ler tit le size docum ent n umber rev date: sheet of modif y : path des igner d a d a d a d odd hs vs rtco "clk0 -> llc1 clk1 -> llc2 clk2 -> llcout c lk3 -> xc lk " clk2 in xclk jp13a jp13a source dgnd vd d vd da vd dan vdd vdda vddan vdd vdda vddan llca sy nc0 sy nc1 sy nc2 rcv1 rcv2 vdd vdda vddan sy nc3 mp2 mp4 mp1 mp5 mp0 mp6 mp7 mp3 vp6 vp7 vp0 vp5 vp1 vp4 vp2 vp3 llcb clkout llc a clkout llc b clk1 clk0 clk2 clk3 source source p1a modul in-con96 a32 a31 a30 a29 a28 a27 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 p1b mo dul in-co n96 b32 b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 p1c modul in-con96 c32 c31 c30 c29 c28 c27 c26 c25 c24 c23 c22 c21 c20 c19 c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 tp tp tp tp tp tp tp tp tp tp jp30 1 2 jp13 1 3 2 mp[7..0] resn scl sync[3..0] rcv[2..1] ttx ttxrq vdd vdda vddan sda vp[7..0] clk[3..0] source
33 module system: 7128mod2 philips semiconductors application note an 97085 6.1.3 connector out tuesday , april 02, 1996 1 1 a4 914 thursday, october 09, 1997 o:\orcad_97\chameleon\7128mod2_iba.dsn conn_out philips mpc-e speller tit le size document number rev date: sheet of modif y : path designer a a d d a cvbs0 cvbs1 cvbs2 rgb y / c "place side by side" y / c cvbs ycout1 ycout0 rgbout1 rgbout0 rgbout2 p4 scart cvbs out 19 cvbs gnd 17 red 15 red gnd 13 grn 11 grn gnd 9 bl 7 bl gnd 5 l out 3 r out 1 cvbs in 20 st rgb gnd 18 st rgb 16 d2b gnd 14 d2b 12 d2b 10 ctrl i/o 8 l in 6 lr gnd 4 r in 2 gnd 21 p5 i2c 4pcon vcc 1 sda 2 scl 4 gnd 3 p6 i2c 6pcon sda 3 scl 4 vcc 2 vcc 1 gnd 6 nc 5 u2 i2c 4pcon_new sda 1 vcc 2 scl 4 gnd 3 u1 i2c 4pcon_us vcc 1 gnd 2 sda 4 scl 3 p2 5pconn 1 1 2 2 3 3 4 4 5 5 p3 cvbs_con 1 2 1 2 jp16 rgb active 1 2 jp15 1 3 2 jp17 1 3 2 jp14 1 3 2 jp29 1 3 2 cvbsout sda scl vdda vddan ycout[1..0] rgbout[2..0] vdd3,3 vdd
34 module system: 7128mod2 philips semiconductors application note an 97085 6.1.4 SAA7138/39 tuesday, april 02, 1996 1 1 a4 13 14 friday, october 10, 1997 o:\orcad_97\chameleon\7128mod2_iba.dsn saa7128/29 38/39 philips mpc-e spell er title size document number rev date: sheet of modif y : path designer d d a d d d d d a mp7 mp6 mp5 mp4 mp3 mp2 mp1 mp0 vdd3,3 vdd5 vdd 3,3 vdd 5 syn c 3 syn c 1 syn c 0 sync2 vd d3,3 vdd3,3 clk3 yc1 yc0 rgb1 rgb0 rgb2 clk2 clk0 clk1 vp6 vp2 vp7 vp4 vp3 vp0 vp1 vp5 rcv2 rcv1 clk0 clk1 clk2 clk3 vdd3,3 vdda3,3 vdda3,3 vdd 3,3 r17 4k7 s1 reset c25 100n c26 100n r23 0 r13 open r14 4k7 r15 4k7 r16 4k7 r18 4k7 c21 10p l13 10 c22 1n c23 100n c24 100n r21 240r r20 22r cp1 22 + c20 10p y1 27mhz r22 240r r19 22r u5 saa 7138/39 chameleon_64 saa 7138/39 res 47 scl 58 sda 59 rcv2 12 rcv1 11 vdd3 56 vss1 9 ttx 61 ttxrq 60 mp 7 13 mp 6 14 mp 5 15 sa 29 res 33 res 19 res 16 mp 4 20 mp 3 21 mp 2 22 mp 1 23 mp 0 24 vdd2 25 vss2 26 rtci 27 ap 7 sp 6 resn 57 b (cb) 40 vdda4 53 vdda3 42 vdda2 39 vdda1 36 g (y) 37 r (cr) 34 c (cvbs) 35 cvbs (csync) 41 vssa2 44 vssa1 30 vp0 5 res 48 res 32 res 50 res 49 llc1 8 vddi2c 28 llc2 17 llcout 18 source 31 vdd1 10 vss3 55 vp1 4 vp2 3 vp3 2 vp4 1 vp5 64 vp6 63 vp7 62 xtal 52 xtali 51 vssa3 45 vbs (cvbs) 38 vssa4 46 xclk 54 res 43 c31 100n c33 100n c32 100n jp23 hs 1 2 jp25 sa 1 2 jp27 termllc1 1 2 jp28 termllc2 1 2 jp24 odd / vs 1 3 2 jp26 resn 1 3 2 l16 open sda mp[7..0] vdd5 scl rcv[2..1] sync[3..0] vdd3,3 vdda3,3 ttx cvbs yc[1..0] rgb[2..0] resn vp[7..0] source clk[3..0] ttxrq
35 module system: 7128mod2 philips semiconductors application note an 97085 6.1.5 saa7128/29 tuesday, september 02, 1997 1 1 a4 12 14 tuesday, october 07, 1997 o:\orcad_97\chameleon\7128mod2_iba.dsn saa7 128/29 38/39 philips mpc-e/pd speller tit le size doc ument number rev date: sheet of modif y : path designer u4 saa 7128/29 chameleon_44 ap 3 sp 2 ttx 44 mp7 9 mp6 10 mp3 13 mp5 11 sa 21 resn 40 cvbs (csync) 30 vbs (cvbs) 27 c (cvbs) 24 llc 4 scl 41 sda 42 mp4 12 mp2 14 mp1 15 mp0 16 rcv1 7 rcv2 8 xtal 34 xtali 35 vss1 5 vdd2 17 vdd3 39 vdd1 6 vssa2 32 ttxrq 43 rtci 19 vssa1 22 res. 1 vdda1 25 vdda2 28 vdda3 31 vdda4 36 vss2 18 g (y) 26 vddi2c 20 vss3 38 r (cr) 23 b (cb) 29 xclk 37 vssa3 33
36 module system: 7128mod2 philips semiconductors application note an 97085 6.1.6 output filter 1..6 wednesday, april 03, 1996 1 1 a4 11 14 thursday, october 09, 1997 o:\orcad_97\chameleon\7128mod2_ib a .ds n output filter philips mpc speller tit le size document number rev date: sheet of modif y : pat h d es igner a 5mhz lowpass filter1 fin fout b 5mhz lowpass filter2 fin fout c 5mhz lowpass filter3 fin fout d 5mhz lowpass filter4 fin fout e 5mhz lowpass filter5 fin fout f 5mhz lowpass filter6 fin fout ycout1 ycout0 rgbout2 rgbout1 rgbout0 yc1 yc0 yc1 yc0 rgb1 rgb0 rgb2 r6 10r r8 10r r9 4,7r r10 22r r12 22r r7 10r r5 10r r11 22r jp21 5 r 1 2 jp22 5 r 1 2 jp31 y/c 1 2 jp32 s aa 7126/27 1 2 cvbs ycout[1..0] cvbsout rgb[2..0] rgbout[2..0] yc[1..0]
37 module system: 7128mod2 philips semiconductors application note an 97085 6.1.7 5mhz lowpass filter1 wednesday, april 03, 1996 1 1 a4 214 thursday, october 09, 1997 o:\orcad_97\chameleon\7128mod2_iba.dsn 5mhz lowpass filter1 philips mpc speller ti t le size document number rev date: sheet of modif y : path designer a c2 390p c3 560p c1 120p l1 2 h7 l2 2 h7 jp1 jmpin 1 2 jp2 jmpout 1 2 fout fin
38 module system: 7128mod2 philips semiconductors application note an 97085 6.1.8 5mhz lowpass filter2 wednesday, august 20, 1997 1 1 a4 314 thursday, october 09, 1997 o:\orcad_97\chameleon\7128mod2_iba.dsn 5mhz lowpass filter2 philips mpc-e/pd speller tit le size document number rev date: sheet of modif y : path designer a c5 390p c6 560p c4 120p l3 2 h7 l4 2h7 jp3 jmpin 1 2 jp4 jmpout 1 2 fout fin
39 module system: 7128mod2 philips semiconductors application note an 97085 6.1.9 5mhz lowpass filter3 wednesday, april 03, 1996 1 1 a4 414 thursday, october 09, 1997 o:\orcad_97\chameleon\7128mod2_iba.dsn 5mhz lowpass filter3 philips mpc speller ti t le size document number rev date: sheet of modif y : path designer a c8 390p c9 560p c7 120p l5 2 h7 l6 2 h7 jp5 jmpin 1 2 jp6 jmpout 1 2 fout fin
40 module system: 7128mod2 philips semiconductors application note an 97085 6.1.10 5mhz lowpass filter4 wednesday, august 27, 1997 1 1 a4 514 thursday, october 09, 1997 o:\orcad_97\chameleon\7128mod2_iba.dsn 5mhz lowpass filter4 philips mpc-e/pd speller tit le size document number rev date: sheet of modif y : path designer a l8 2h7 jp7 jmpin 1 2 c10 120p c12 560p c11 390p jp8 jmpout 1 2 l7 2 h7 fout fin
41 module system: 7128mod2 philips semiconductors application note an 97085 6.1.11 5mhz lowpass filter5 wednesday, august 27, 1997 1 1 a4 614 thursday, october 09, 1997 o:\orcad_97\chameleon\7128mod2_iba.dsn 5mhz lowpass filter5 philips mpc-e/pd speller ti t le size document number rev date: sheet of modif y : path designer a c13 120p jp10 jmpout 1 2 c14 390p l10 2 h7 jp9 jmpin 1 2 c15 560p l9 2h7 fout fin
42 module system: 7128mod2 philips semiconductors application note an 97085 6.1.12 5mhz lowpass filter6 wednesday, august 27, 1997 1 1 a4 714 thursday, october 09, 1997 o:\orcad_97\chameleon\7128mod2_ib a.ds n 5mhz lowpass filter6 philips mpc-e/pd speller title size document number rev date: sheet of modif y : path designer a c17 390p c18 560p c16 120p l11 2 h7 l12 2 h7 jp11 jmpin 1 2 jp12 jmpout 1 2 fout fin
43 module system: 7128mod2 philips semiconductors application note an 97085 6.1.13 i 2c - eeprom monday, march 04, 1996 1 1 a4 10 14 thursday, october 09, 1997 o:\orcad_97\chameleon\7128mod2_iba.dsn eeprom philips mpc-e speller title size document number rev date: sheet of modif y : path designer d c19 3.3n u3 pcf8598e eeprom sda 5 scl 6 vdd 8 vss 4 a0 1 a2 3 a1 2 ptc 7 r1 10k r2 10k r3 10k r4 56k jp20 a2 1 2 jp19 a1 1 2 jp18 a0 1 2 sda vdd5 scl
44 module system: 7128mod2 philips semiconductors application note an 97085 6.1.14 supply monday, march 04, 1996 1 1 a4 14 14 thursday, october 09, 1997 o:\orca d_97\cha meleon\7128mod2_ib a.ds n supply philips mpc-e speller tit le size document number rev date: sheet of modif y : path d esigner a d d a d ferrit ferr it c27 470n cp2 47 + r24 0 l14 ferrit 2.2 p9 dgnd gnd tp p10 agnd gnd tp r25 0 cp7 47 + l15 ferrit 2.2 reg2 lm3940 vi 1 vo 3 gnd 2 c29 470n c30 100n cp4 100 + c28 100n reg1 lm3940 vi 1 vo 3 gnd 2 cp3 100 + vdda vdd vdd3,3 vdd5 vdda3,3
45 module system: 7128mod2 philips semiconductors application note an 97085 6.2 layout 6.2.1 top placement of 7128mod2
46 module system: 7128mod2 philips semiconductors application note an 97085 6.2.2 routing of top layer of 7128mod2
47 module system: 7128mod2 philips semiconductors application note an 97085 6.2.3 top solder mask of 7128mod2
48 module system: 7128mod2 philips semiconductors application note an 97085 6.2.4 bottom placement of 7128mod2
49 module system: 7128mod2 philips semiconductors application note an 97085 6.2.5 bottom layer of 7128mod2
50 module system: 7128mod2 philips semiconductors application note an 97085 6.2.6 bottom solder mask of 7128mod2
51 module system: 7128mod2 philips semiconductors application note an 97085 6.2.7 ground plane layer of 7128mod2 (mid layer1)
52 module system: 7128mod2 philips semiconductors application note an 97085 6.2.8 routing of power supply layer of 7128mod2 (mid layer2)
module system: 7128mod2 philips semiconductors 53 application note an 97085

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