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zilog w orldwide h eadquarters ? 910 e. h a milton avenue ? campbell, ca 95008 telephone: 408.558.8500 ? fax: 408.558.8300 ? www.zilog.com z90t366 rom and z90t361 otp ezvision 64 kword television con- troller with osd product specification ps005901-1100
ps005901-1100 this publication is subject to replacement by a later edition. to determine whether a later edition exists, or to request copies of publications, contact zilog worldwide headquarters 910 e. hamilton avenue campbell, ca 95008 telephone: 408.558.8500 fax: 408.558.8300 www.zilog.com windows is a registered trademark of microsoft corporation. document disclaimer ? 2000 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. except with the express written approval zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 iii table of contents 1 overview ........................................................................................... 1 1.1 block diagram ................................................................................. 3 1.2 pin assignments .............................................................................. 4 1.3 pin descriptions ............................................................................... 5 1.4 development tools .......................................................................... 7 2 operation .......................................................................................... 8 2.1 cpu description .............................................................................. 8 2.2 memory (rom and ram) .............................................................. 14 2.3 clock circuit description ................................................................ 16 2.4 reset conditions ........................................................................... 18 2.5 power management ....................................................................... 20 2.6 i/o port configurations .................................................................. 20 2.7 interrupts ........................................................................................ 22 2.8 timers ............................................................................................ 23 2.9 adc ............................................................................................... 24 2.10 pulse width modulation ................................................................. 26 2.11 i2c interface .................................................................................. 27 2.12 on-screen display (osd) ............................................................. 32 2.13 cursor ............................................................................................ 39 2.14 color palette assignment .............................................................. 43 2.15 other functions ............................................................................. 44 3 register groups .............................................................................. 46 3.1 register description ...................................................................... 47 3.2 bank0 (i/o ports, i2c interface, pll frequency, cursor) control registers .................................................................. 48 3.3 bank1 (control registers) ............................................................. 53 3.4 bank2 (pwm registers) ................................................................ 67 3.5 bank3 (on screen display [osd] registers) .................................. 69
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 iv 4 instruction set ................................................................................. 81 4.1 instruction summary ...................................................................... 81 4.2 instruction operands ..................................................................... 84 4.3 instruction format .......................................................................... 86 4.4 instruction bit codes ...................................................................... 87 4.5 instruction format examples ......................................................... 91 4.6 instruction timing .......................................................................... 97 4.7 instruction op codes ..................................................................... 98 5 system design considerations ..................................................... 169 6 electrical characteristics ............................................................... 171 6.1 dc peripherals ............................................................................ 172 6.2 ac characteristics ....................................................................... 174 6.3 analog rgb ............................................................................. 175 7 packaging ..................................................................................... 176 8 ordering information ..................................................................... 178
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 v list of figures 1 block diagram.............................................................................................. 3 2 52-pin sdip pinout ...................................................................................... 4 3 code development environment ................................................................. 7 4 ar register format ...................................................................................12 5 ram, rom, and pointer architecture ........................................................14 6 rom map ...................................................................................................15 7 ram allocation ..........................................................................................16 8 clock switching block diagram (8 -16 mhz) .............................................17 9 32 khz oscillator recommended circuit ...................................................17 10 bidirectional port pins ................................................................................21 11 bidirectional pins multiplexed with i2c port ...............................................21 12 bidirectional pins multiplexed with adc inputs .........................................22 13 ir capture register block diagram ...........................................................23 14 z90t361/6 adc block diagram .................................................................25 15 adc data packing .....................................................................................26 16 master mode ..............................................................................................30 17 slave mode ................................................................................................31 18 data flow ..................................................................................................33 19 blank and r, g, b outputs in digital mode ................................................33 20 r, g, and b outputs in analog (palette) mode ..........................................34 21 character expansion .................................................................................35 22 table settings ............................................................................................37 23 cursor ........................................................................................................39 24 programmable palette control at ar register ..........................................43 25 ir capture register input ..........................................................................44 26 loop filter pin configuration .....................................................................44 27 pipeline execution .....................................................................................97 28 system block diagram .............................................................................170 29 recommended application schematics ..................................................175 30 52-pin sdip package dimensions ..........................................................176
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 vi list of tables 1 z90t366 or z90t361 pin description ......................................................... 5 2 internal registers ........................................................................................ 9 3 status register ........................................................................................... 9 4 ram pointer loop description .................................................................. 10 5 additional control registers ..................................................................... 13 6 reset conditions ...................................................................................... 18 7 adc inputs typical range ....................................................................... 24 8 master i2c bus bit rates ......................................................................... 27 9 master i2c bus interface commands ....................................................... 28 10 slave i2c bus interface commands ......................................................... 29 11 character expansion register .................................................................. 36 12 attribute assignment ................................................................................. 38 13 cursor parameters ................................................................................... 40 14 memory allocation for cursor bitmap ....................................................... 41 15 fixed palette color assignment ............................................................... 43 16 r4(1) settings .................................................................................. 45 17 register summary .................................................................................... 46 18 bank assignments .................................................................................... 47 19 register1, bank0, cursor palette ............................................................. 48 20 register2, bank0, pll frequency data register ..................................... 48 21 register3, bank0, i2c interface register ................................................. 50 22 register5, bank0, port 1 data register .................................................... 51 23 register4, bank0, port 0 data register .................................................... 51 24 register6, bank0, port 0 direction register ............................................. 52 25 register7, bank0, port 1 direction register ............................................. 52 26 register0, bank1, clamp position register .............................................. 53 27 register1, bank1, speed control register ............................................... 55 28 register2, bank1, wdt/stop (write only) and 9-bit counter (read only) control register ....................................... 58 29 register3, bank1, standard control register ........................................... 58 30 register4, bank1, adc control register .................................................. 60 31 register5, bank1,timer control register ................................................. 61 32 register6, bank1, clock switch control register ..................................... 63 33 register7, bank1, interrupts/wdt/smr control register ........................ 66 34 interrupt priority ........................................................................................ 67
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 vii 35 register0Cregister5, bank 2, pwm 1C6 registers .................................. 67 36 register6, bank 2, shadow control register ........................................... 68 37 register7, bank 2, cgrom offset register ........................................... 69 38 register0Cregister1, bank 3, write operation, shift registers ............... 70 39 register0Cregister2, bank 3, read operation, character multiple registers ............................................................. 70 40 register2, bank 3, attributes register, write operation .......................... 71 41 register3, bank 3, write operation, attribute data register .................... 73 42 register3, bank 3, read operation, attributes register ........................ 73 43 register 3, bank 3, display character format for attribute data register, osd mode write operation ........................ 74 44 register 3, bank 3, control character format for attribute data register, osd mode write operation ........................ 75 45 register 3, bank 3, display character format for attribute data register, write operation ccd mode ........................ 76 46 register 3, bank 3, control character format for attribute data register, ccd mode, write operation ....................... 76 47 register4, bank 3, osd control register ................................................ 77 48 register5, bank 3, capture register, read operation ............................. 78 49 register6, bank 3, palette control register ............................................. 79 50 register7, bank 3, output palette control register ................................. 80 51 instruction format mnemonics ................................................................. 81 52 accumulator modification instructions ...................................................... 82 53 arithmetic instructions .............................................................................. 82 54 bit manipulation instructions ..................................................................... 82 55 load instructions ...................................................................................... 83 56 logical instructions ................................................................................... 83 57 program control instructions .................................................................... 83 58 rotate and shift instructions ..................................................................... 83 59 instruction operand summary .................................................................. 84 60 instruction mnemonics/operands ............................................................. 85 61 condition code bits .................................................................................. 87 62 accumulator modification bits ................................................................... 88 63 flag modification bits ................................................................................ 89 64 register pointer/ data pointer bits ........................................................... 90 65 register bits ............................................................................................. 90 66 general instruction format ....................................................................... 93 67 accumulator modification format ............................................................. 93 68 flag modification format ........................................................................... 94
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 viii 69 direct internal addressing format ............................................................ 95 70 short immediate addressing format ........................................................ 95 71 long immediate addressing format ......................................................... 96 72 jump and call instruction formats ........................................................... 96 73 instruction op codes ................................................................................ 98 74 instruction descriptions .......................................................................... 103 75 instruction format mnemonics ............................................................... 103 76 absolute maximum and minimum ratings ............................................. 171 77 dc characteristics .................................................................................. 171 78 r, g, and b analog output ..................................................................... 172 79 adc0/small range* ............................................................................... 173 80 ac characteristics .................................................................................. 174 81 adc1-adc4/full range .......................................................................... 174 82 rgb voltage specification ..................................................................... 175 83 rgb time specification .......................................................................... 175 84 controlling dimensions ........................................................................... 177
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 1 z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd 1 overview the ezvision z90t366 and z90t361 are the rom and one-time programmable (otp) versions of a television controller with on-screen display (osd) that contains 64 kwords of program memory and 1 kword of ram. zilogs ezvision z90t366 tv controller with on-screen display (osd) is a highly-integrated solution for television design. the z90t366 boasts a high-speed 16-bit, advanced digital signal processor (dsp) and powerful osd engine. flexible and sophisticated, the osd includes video display attributes, semi-transparency, programmable color palettes, and a hardware cursor for easy user interface. the z90t366 supports parental control, closed captioning, and extended data system (xds). the z90t366 is an ideal choice for mainstream television sets for both pal and ntsc standards. the z90t36x family consists of the following two basic devices: the z90t366 masked rom the z90t361 one time programmable (otp) device in addition, zilog provides a comprehensive development suite for television system developers including an emulator capable of otp programming, osd evaluation board, c-compiler, application programmer interface (api), zilogs developer studio (zds) software, and graphics user interface (gui) osd screen design tools. these tools enable tv developers to work ef?ciently and effectively to bring new products to market. the ezvision z90t361 is the otp controller used to develop code and prototypes for speci?c television applications or initial limited production. program rom and character generation rom (cgrom) in the z90t361 are both programmable. the ezvision z90t366 incorporates the rom code developed by the customer with the z90t361. customer code is masked into both program rom and cgrom.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 2 the z90t366 television controller with osd is based on zilogs z89c00 processor core. the z89c00 is a 16-bit, fractional, twos complement cmos digital signal processor (dsp). most instructions are accomplished in a single clock cycle. this processor features a 24-bit arithmetic logic unit (alu) and a 24-bit accumulator. the processor also contains a six-level stack and three vectored interrupts. the z90t366 contains 64 kwords of program rom and 1 kword of on-chip data ram. program rom space can hold an unlimited number of characters with a 16x16, 16x18, and 16x20 programmable matrix in relocated character generation rom (cgrom), which is only restricted by the available rom. in addition, the z90t366 contains four external register banks with eight registers each. additional control registers (ar) are available to control new peripherals like palette banks and memory management. an internal 24-mhz/2 system clock has a phase lock loop (pll) driven by an external 32.768-khz crystal. six-channels of 4-bit analog to digital converters (adc) support the following: analog control front panel buttons audio level input vertical blank interval (vbi) data capture six pulse width modulator (pwm) outputs allow low-cost digital-to-analog conversion. the pwms have 8-bit resolution to control video and audio attributes. a master/slave i 2 c (inter integrated circuit) bus interface provides serial system interconnect to common peripheral functions. twenty-four programmable i/o pins provide ?exibility for other digital input/output functions. an ir (infrared) remote capture register facilitates reliable remote data capture. on-chip horizontal synchronization (h sync ) and vertical synchronization (v sync ) circuits generate a video time base (typically used for vcr and set-top applications) in the absence of an available video signal. micro-programmable osd generation logic provides ?exibility to tailor osd features and functions. in addition to normal osd functions, closed caption is supported in accordance with fcc report and order on gen docket no. 91-1, dated april 12, 1991. expanded data service (xds) capability is supported as well. the z90t366 is packaged in a 52-pin sdip package.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 3 figure 1 is a block diagram of the internal structure of the chip. figure 2 illustrates the pin locations, and table 1 describes the function of each pin. 1.1 block diagram figure 1 block diagram adc0 adc1 adc2 adc3 adc4 adc5 4-bit adc port00 port02 port03 port04 port05 port06 port07 port08 port09 port0a port0b port0c port0d port10 port11 port12 port13 port14 port15 port16 port17 port18 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 ir osd engine xtal1 xtal2 lpf hsync vsync reset cpu core ram 1 rom addr rom data address data i 2 cmc1 i 2 cmd1 i 2 cmc2 i 2 cmd2 otp/ rom reg addr/data ir in control port 1 i 2 c port 0x r g b ovl sovl pwm
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 4 1.2 pin assignments figure 2 52-pin sdip pinout for simplicity, both the z90t366 and z90t361 will be referred to as the z90t366. port03 port0b/i2cmc1 port0c/i2cmd1 port0d port12/i2cmd2 port11/i2cmc2 port0e port10/r0 adc5 gnd vcc cvi/adc0 lpf agnd port04/adc0 port13/g1 port14/b0 port05/adc3 hsync vsync port00/adc2 port17/adc1 port15/b1 irin port16/sclk port18/g0 pwm5 port0a port09 pwm4 pwm3 port08/r1 pwm2 pwm1 vcc gnd port0f/sovl ovl b g r avcc agnd xtal2 xtal1 reset port02 pwm6 vcc gnd port07/csync port06/counter z90t366 or z90t361 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 5 1.3 pin descriptions table 1 z90t366 or z90t361 pin description symbol pin # function direction port03 1 port 03 i/o port0b/i 2 cmc1 2 port 0b or master1 i 2 c clock i/o port0c/i 2 cmd1 3 port 0c or master1 i 2 c data i/o port0d 4 port 0d i/o port12/i 2 cmd2 5 port 12 or master2 i 2 c data i/o port11/i 2 cmc2 6 port 11 or master1 i 2 c clock i/o port0e 7 port 0e i/o port10/r0 8 port 10 or digital rgb output, red i/o adc5 9 adc5 input i gnd 10 digital ground power vcc 11 digital vcc power cvi/adc0 12 adc0 input or composite video input ai lpf 13 loop ?lter ai/ao agnd 14 analog ground power port04/adc0 15 port 04 or adc0 input i/o or ai port13/g1 16 port 13 or digital rgb output, green i/o port14/b0 17 port 14 or digital rgb output, blue i/o port05/adc3 18 port 05 or adc3 input i/o or ai hsync 19 horizontal sync i/o vsync 20 vertical sync i/o port00/adc2 21 port 00 or adc2 input i/o or ai port17/adc1 22 port 17 or adc1 input i/o or ai port15/b1 23 port 15 or digital rgb output, blue i/o irin 24 infrared remote capture input i port16/sclk 25 port 16 or internal process sclk i/o port18/g0 26 port 18 or digital rgb output, green i/o port06/cntr 27 port 06 or counter input i/o
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 6 port07/csync 28 port 07 or composite sync output i/o gnd 29 digital ground power vcc 30 digital vcc power pwm6 31 8-bit pwm output o port02 32 port 02 i/o reset 33 reset i xtal1 34 crystal oscillator input ai xtal2 35 crystal oscillator output ao agnd 36 analog ground power avcc 37 analog vcc power r 38 osd video output to drive red o/ao g 39 osd video output to drive green o/ ao b 40 osd video output to drive blue o/ao ovl 41 osd overlay output o port0f/sovl 42 port 0f or osd semi-transparency overlay output i/o gnd 43 digital ground power vcc 44 digital vcc power pwm1 45 8-bit pwm output o pwm2 46 8-bit pwm output o port08/r1 47 port 08 or digital rgb output, red i/o pwm3 48 8-bit pwm output o pwm4 49 8-bit pwm output o port09 50 port 09 i/o port0a 51 port 0a i/o pwm5 52 8-bit pwm output o table 1 z90t366 or z90t361 pin description (continued) symbol pin # function direction
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 7 1.4 development tools the z90t361 requires zilogs z90369zem emulator with its proprietary zilog developer studio (zds) software for programing. to view code effects, the emulator uses a zilog on-screen display (zosd) board that connects directly to a television screen. refer to figure 3. figure 3code development environment develop code on pc z90379 z90t361 z90369 in-circuit emulation kit zosd board converts to video display download code to z90379 ice chip program the z90t361 otp review code on tv display z9034600zco
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 8 2 operation 2.1 cpu description the z89c00 core is a high-performance dsp that has a modi?ed harvard-type architecture with separate program and data memories. the design has been optimized for processing power. the z89c00 used in the z90t366 device has been modi?ed. the multiplier is disabled. however, the x and y registers in the multiplier are still available and can be used as general-purpose registers. refer to zilogs z89c00 documentation. alu the 24-bit alu has two input ports, one of which is connected to the output of the 24-bit accumulator. the other input is connected to the 24-bit p-bus; the upper 16 bits are connected to the 16-bit d-bus. instruction timing several instructions are executed in one machine cycle. lenghty immediate instructions and jump or call instructions are executed in two machine cycles. when the program memory is referenced in internal ram indirect mode, it requires three machine cycles. an additional machine cycle is required if the program counter (pc) is selected as the destination of a data transfer instruction. this only occurs with a register indirect branch instruction. hardware stack a six-level hardware stack is connected to the d-bus to hold subroutine return addresses or data. the call instruction pushes pc+2 onto the stack. the ret instruction returns the contents of the stack to the program counter. cpu registers the z90t366 has 11 physical internal registers and four banks of eight external registers. in addition, it has nine virtual registers. the 11 internal registers are de?ned in table 2, and the status register is de?ned in table 3.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 9 internal registers x and y are 16-bit general purpose registers. a is a 24-bit accumulator. the output of the alu is sent to this register. when 16-bit data are transferred into this register, it goes into the 16 msbs and the least table 2 internal registers register register de?nition size x general purpose register 16 bits y general purpose register 16 bits a accumulator 24 bits sr status register 16 bits pn:b six ram address pointers 8 bits each pc program counter 16 bits table 3 status register bit/field bit position r/w description n 15 r alu negative ov 14 r alu over?ow z 13 r alu zero c 12 r carry reserved 11 r reserved reserved 10 r reserved reserved 9 r reserved op 8 r/w over?ow protection ie 7 r/w interrupt enable register bank selector 6,5 r/w 00 register bank 0 01 register bank 1 10 register bank 2 11 register bank 3 sfd 4,3 r/w short form direct bits rpl 2-0 r/w ram pointer loop size
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 10 signi?cant eight bits are set to zero. only the upper 16 bits are transferred to the destination register when the accumulator is selected as a source register in transfer instruction. sr is the status register that contains the alu status and the control bits listed in table 3. the status register is always read in its entirety. s15-s12 are set/reset by the hardware and can only be read through software. they are set or reset by the alu after an operation. s8-s0 can be written by software. s8, if 0 (reset), allows the hardware to over?ow. if s8 is set, the hardware clamps at maximum positive or negative values instead of over?owing. s7 enables interrupts. s6Cs5 are used for short form direct addresses, which are described below. the de?nitions of s2-s0 are listed in table 4. pn:b are the pointer registers for accessing data ram. (n= 0, 1, 2 refer to the pointer number) (b = 0, 1 refers to ram bank 0 or 1). they can be read from or written to directly and can point directly to locations in data ram or indirectly to program memory. pc is the program counter. when this register is assigned as a destination register, one nop machine cycle is automatically added to adjust the pipeline timing. table 4 ram pointer loop description s2 s1 s0 loop size 0 0 0 256 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 11 external registers the z90t366 module is capable of accessing eight external registers directly using only the three external register address signals that are normally available. two user bits (status register s6-s5) are combined with the register address signals to provide the ability to address four banks of eight registers each. the registers most critical for speed are located together in bank 3. in this speci?cation, all external registers are referred to rx(y) where: x is a register number within a register bank; y is a bank number; and z is a bit ?eld number an external register bank can be selected by setting bits 6 and 5 in the status register to de?ne the bank, then specifying the address of the register on the external register address bus. external registers reside on the chip and are used to control the operation of all the peripheral modules in the device. by reading or writing to the ?elds in the external registers, the user can interact with the peripheral devices on the chip. virtual registers bus is a read-only register that, when accessed, returns the contents of the d- bus. it is a virtual register. (physical ram does not exist on the chip.) dn:b these eight data pointers refer to possible locations in ram that can be used as pointers to locations in program memory. the programmer decides which location to choose two bits from in the status register and which two bits in the operand. this means only the lower 16 possible locations in ram can be speci?ed. at any one time there are eight usable pointers, four per bank, and the four pointers are in consecutive locations in ram. for example, if s3/s4 = 01 in the status register, then d0:0/d1:0/d2:0/d3:0 refers to locations 4/5/6/7 in ram bank 0. when the data pointers are being written to, a number is actually being loaded to data ram, so they can be used as a limited method for writing to ram. additional control registers (ar) additional control registers (ar) control new peripheral blocks like palette banks and memory management. to activate ars, r0(1) must be set to 1. ars can note:
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 12 be disabled by setting r0(1) = 0, (por) for software backward compatibility or if access to ram location 1ffh is required. the 128 eight-bit control registers (referred as ar or arx) use ram- mapped i/o access. location 1ffh in ram is used to address up to 128 byte- width ars. the ar number and written data are encoded into the data ?eld as illustrated in figure 4. figure 4 ar register format when writing to address 1ffh, the data write bit (dwb) and ar number are latched, depending on whether the dwb data ?eld is either written to the selected port (latched) or discarded (not latched). the ar number and corresponding data are read after reading from the previously latched dwb address 1ffh. to write to the ar, the data must be written to address 1ffh; dwb must be set to 1, the port number must be speci?ed in bits 8C14, and actual data must be speci?ed in bits 0C7. example ld a, #(%8000 | 29 <<8 | %57); write 57 (hex) into the ar29 ld %1ff, a; the dwb and port number are latched for further reading if necessary. to read from the ar, the address must be previously latched by writing it to address 1ffh with dwb set to 0. bits 0C7 have no meaning. because the bits are not going to be written in this mode, only the port number is latched. example ld a, #(%0 | 30<<8 | %0); dwb=0, latch ar30, data is not written ld %1ff, a; ld a, %1ff; read from ar30-%1exx, where xx is current content at least one cycle delay (nop) is required between two consecutive accesses to the ar. if access is performed by a two-cycle instruction, no delay is necessary. external memory must exhibit access times of less than 60 ns. table 5 lists the additional control registers. 15 14 8 7 0 data ar number dwb
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 13 table 5 additional control registers ar # name bit position data function 0 palette_8 76------ --543210 dh ddh reserved palette8/color0r1r0g1g0b1b0 1 palette_8 76------ --543210 dh ddh reserved palette8/color1r1r0g1g0b1b0 2 palette_8 76------ --543210 dh ddh reserved palette8/color2r1r0g1g0b1b0 3 palette_8 76------ --543210 dh ddh reserved palette8/color3r1r0g1g0b1b0 4 palette_8 76------ --543210 dh ddh reserved palette8/color4r1r0g1g0b1b0 5 palette_8 76------ --543210 dh ddh reserved palette8/color5r1r0g1g0b1b0 6 palette_8 76------ --543210 dh ddh reserved palette8/color6r1r0g1g0b1b0 7 palette_8 76------ --543210 dh ddh reserved palette8/color7r1r0g1g0b1b0 8C15 palette_9 76543210 ddh same as ar 0C7 for palette9 16C23 palette_10 76543210 ddh same as ar 0C7 for palette10 24C31 palette_11 76543210 ddh same as ar 0C7 for palette11 32C39 palette_12 76543210 ddh same as ar 0C7 for palette12 40C47 palette_13 76543210 ddh same as ar 0C7 for palette13 48C55 palette_14 76543210 ddh same as ar 0C7 for palette14 56C63 palette_15 76543210 ddh same as ar 0C7 for palette15 64C123 reserved 124 pglocation0 7------- -6------ --543210 0 1 0 1 ddh page0 is located internallyCpor page0 is located externally internal rom is enabledCpor internal rom is disabled (low power consumption) page0external (physical) page number 125 pglocation1 7------- -6------ --543210 0 1 0 1 ddh page1 is located internallyCpor page1 is located externally reserved page1external (physical) page number 126 pglocation2 76543210 ddh same as above for page2
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 14 ram addressing the addresses in ram can be speci?ed in one of three ways: ram, rom, pointers. refer to figure 5. figure 5 ram, rom, and pointer architecture 2.2 memory (rom and ram) the z90t366 has 64k words of read only memory (rom) and 1k words of random access memory (ram). 127 pglocation3 76543210 ddh same as above for page3 table 5 additional control registers (continued) ar # name bit position data function 00h p0:1 p1:1 p2:1 p0:0 p1:0 37 h 256 x 16-bit 256 x 16- bit ram pointers ffh @p1:0 37h 0321h 00h d0:0 d1:0 d2:0 d3:0 0321h d0:1 d1:1 d2:1 d3:1 ram 0 ram1 data pointers internal rom 8000h 0321h 0000h 0321h 1234h @ d 0:1 @@p1:0 s4/s3 = 01 64kx16-bit ff h 04h ram pointers p2:0
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 15 rom the 64k words mask rom is designed to provide storage for both program codes and character set graphic pixel matrices (cgrom). the address boundary between these applications is dependent on the storage required for character graphics. the program rom (pgmrom) section can, in theory, be accessed anywhere in the addressable rom space; however, because cgrom usually starts at location 0000h, program rom resides in the higher address locations. the maximum available rom space for program memory depends on the rom reserved for cgrom (for an application). cgrom can be placed anywhere in the 64k rom address space by setting the cgrom address offset register r7(2). this offset is added to the character address before accessing rom. by modifying the cgrom offset, several fonts can be accessed (limited by rom size only). when reset, r7(2) =0 (no offset) for backward compatibility with existing software. refer to figure 6. figure 6 rom map cgrom-bank 0 (n characters) scan lines 1-16 0000h 10 * nh 1000h 1200h 14 00h fffch fffdh fffeh ffffh int0 vector int1 vector int2 vector reset vector program rom up to 4k cgrombank 0, scan lines 17, 18 or bank 1, or program rom cgrombank 0, scan lines 19, 20 or bank1 or program rom 4k up to 4.5k up to 5k 64k program rom or cgrom 13ff h fffbh 11ffh 0fffh 10 * nh-1
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 16 ram the 1k words ram is organized in four banks of 256 words consisting of 16 bits each. bank1.0 is always accessible. bank0.0 is mapped to other bank(s); only one page from 0.x is active through bit selection. see figure 7. figure 7 ram allocation 2.3 clock circuit description the processor is able to operate from several clock sources: primary phase lock loop vco source (pvco) secondary phase lock loop (svco) 32.768-khz oscillator clock (osc) in addition, the processor clock can be halted temporarily to select the clock source or access rom without disrupting normal operation of the processor. an external crystal controls the internal 32.768-khz oscillator. the crystal is used as the clock reference for the internal phase locked loop (pll). the pll provides the internal pvco clock for processor operation. the system clock (sclk) is generated internally by dividing the frequency of an appropriate oscillator (pvco) by 2. the frequency of the sclk after power on reset (por) is 12.058 mhz. the sclk signal can be sent to the port16 output pin under software control by setting bit 9 in register r3(1). the svco must be used as the system clock when the osd is generated. the clock switch control register r6(1) de?nes the source of the sclk for the z90t366 core. the block diagram in figure 8 represents the clock switch circuit. bank1.0 bank0.0 256 words 256 words 256 bank0.1 bank0.2 256
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 17 clock switching is not recommended. this feature is only for advanced users. figure 8 clock switching block diagram (8 -16 mhz) clock switching is discouraged. it is only for advanced users. input/drive circuits the 32 khz oscillator circuit in figure 9 is suggested for proper clock operation. figure 9 32 khz oscillator recommended circuit note: 32.768-khz oscillator 12 mhz pvco 12-mhz svco pll pll filter switch1 switch2 switch3 sclk divider r6(1)<5> r6(1)<4> r1(1)<0> 0 1 0 1 0 1 2 2 2 svco/pvco no_switch fast/slow note: ee 6h c/ 6h eh ) ? 32.768 khz 68 k ? xtal1 xtal2 z90t361/6
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 18 2.4 reset conditions reset conditions including addresses and registers are listed in table 6. table 6 reset conditions addr register ----------------------------- reset condition ------------------------- comments 1514131211109876543 210 r0(0) reserved xxxxxxxxxxxxxxx x not available r1(0) cursor palette x x 0 0 xxxxxxxxxxx x cursor palette gauge r2(0) pll_freq 001000000111000 0 pll frequency control r3(0) i 2 c_int 000001 xxxxxxxxx xi 2 c interface register r4(0) port0 xxxxxxxxxxxxxxx x 16-bit i/o port 0 r5(0) port1 xxxxxxxxxxxxxxx x 9-bit i/o port 1 r6(0) dir0 111111111111111 1 16-bit port 0 direction r7(0) dir1 xxxxxxx 11111111 1 9-bit port 1 direction r0(1) clamp_pos 111100000 xxxxxx x position of video clamp pulse r1(1) sclk_freq x 0000000xxx0000 0 stop/sleep/normal mode r2(1) 9-bit cntr xxxxxxxxx 000000 0 stop and wdt, 9- bit counter r3(1) standard_ctl 00000000000xxx0 0 output h/vsync/ blink control r4(1) adc_ctl 000000000000xxx x a/d converter control r5(1) cap_1s_ctl xxxx00xxxxxxxxx xc ounter timers control r6(1) clock_ctl 000000000001xxx x clock control (switch vco/dot) r7(1) wdt_smr_ctl xxxxxxxx0xxxxxx xsmr and wdt control/interrupt
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 19 addr register ----------------------------- reset condition ------------------------- comments 1514131211109876543 210 r0(2) pwm_data1 00000000 xxxxxxx x 8-bit pwm 1 data r1(2) pwm_data2 00000000 xxxxxxx x 8-bit pwm 2 data r2(2) pwm_data3 00000000 xxxxxxx x 8-bit pwm 3 data r3(2) pwm_data4 00000000 xxxxxxx x 8-bit pwm 4 data r4(2) pwm_data5 00000000 xxxxxxx x 8-bit pwm 5 data r5(2) pwm_data6 00000000 xxxxxxx x 8-bit pwm 6 data r6(2) shadow ctrl 00000000 xxxxxxx xshado w color ctrl r7(2) cgrom offset 000000000000000 0cgr om offset register r0(3) hi_x2_hi_x3 xxxxxxxxxxxxxxx xchara cter multiple/ current data r1(3) lo_x2_mid_x3 xxxxxxxxxxxxxxx xchara cter multiple/ next or previous data r2(3) ch_x1_lo_x3 xxxxxxxxxxxxxxx xchara cter multiple/ character graphics attribute r3(3) attr_data xxxxxxxxxxxxxxx xchara cter attribute/ video ram data r4(3) osd_cntl xxxxxxxxxxxxxxx x on screen display control r5(3) cap_data xxxxxxxxxxxxxxx xca pture register data r6(3) palette_color 000000000000000 0 display palette color/underline color r7(3) output palette 000000000000000 0o utput palette table 6 reset conditions (continued)
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 20 2.5 power management there are two low-power operating modes for z90t366: sleep mode and stop mode. sleep mode in sleep mode, the controller uses the 32.768-khz clock for the sclk to reduce power consumption. stop mode in stop mode, the processor is suspended, and the power consumption is minimized. 2.6 i/o port configurations user control can be monitored either through the front panel keypad scanning port or the 16-bit remote control capture register. two input/output port blocks are available for general-purpose digital i/o application. each port bit can be programmed to be either an input or output port. to conserve the device pin count, some port pins are mapped to provide i/o to the adc converter block and i 2 c interface block. the 24 con?gurable i/o pins are general-purpose pins for functions such as serial data i/o, led on/off control, key scanning, power control and monitoring, and i 2 c serial data communications. port 0 and 1 directions are de?ned in r6(0) and r7(0), respectively. r4(0) and r5(0) are data registers for both ports 0 and 1 . figure 10, figure 11, and figure 12 indicate i/o con?guration and sharing with other functional units. port01 must be con?gured as an input in the user mode even though it is not called out in the device speci?cation. note:
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 21 figure 10 bidirectional port pins figure 11 bidirectional pins multiplexed with i 2 c port v cc pad direction 1in 0out output input 20 ? v cc pa d direction 1- in 0- out input 20 ? i 2 c output output
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 22 figure 12 bidirectional pins multiplexed with adc inputs 2.7 interrupts the z90t366 has three external interrupt signals. there are four interrupt sources as follows: horizontal sync (h sync ) vertical sync (v sync ) ir capture timer external event (port09) } multiplexed all interrupts are vectored. the capture timer and port09 are multiplexed to the same interrupt. interrupt priorities are programmable. each interrupt can be masked by setting ?elds in the external registers. when the z90t366 receives an interrupt request from one of the interrupt sources, it executes the interrupt service routine directly for that source. external register r7(1) controls interrupts. v cc pa d direction 1in 0out output input 20 ? analog mux
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 23 2.8 timers watch-dog timer the watch-dog timer resets the cpu when it times out. external register r7(1) controls the watch-dog timer. real time clock a clock timer, in real time, generates ticks every 1000, 250, 62.5 or 15.625 ms. external register r5(1) controls the real time clock. ir capture timer a capture timer measures time between edges of the ir signal. this timer can be programmed to measure timing from rising-to-rising, falling-to-rising, rising-to- falling, or falling-to-falling edges. the ir capture timer is controlled by external register r5(1). figure 13 is a block diagram of the ir capture register structure. figure 13ir capture register block diagram cap_glitch cap_edge glitch filter prescaler edge detector capture time capture register capture flags ir cap_speed r5(1)<1:0> halt capture timer r5(1)<6> captured data r5(3) falling edge is captured reset r5(1) rising edge is captured/ reset r5(1) timeout/ reset r5(1)
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 24 2.9 adc this function employs a 4-bit resolution, ?ash a-to-d converter. the six-to-one analog input multiplexor and conversion start circuits are controlled by the user program. the 4-bit conversion result is available to be read by the cpu at the end of each conversion. one input channel (adc0) is dedicated for quantizing vbi (vertical blanking interval) data for subsequent digital signal processing. another channel, adc5, is typically used for v sync separation from the composite tv signal. these channels (adc0 and adc5) feature a special video clamp circuit that provides dc restoration of the composite video input signal. typical vbi applications include line 21 closed caption, electronic data services, and starsight telecast. the range of adc0 and adc5 is from 1.5 to 2.0 v. the four remaining channels of adc (adc1, adc2, adc3, and adc4) are general purpose. they are typically used for tuner automatic frequency control and analog key entry. the range of adc1Cadc4 is from 0 to 5.0 v. the 4-bit adc in the z90t366 features six multiplexed inputs. the allowed range for input signals differs for various adc inputs according to table 7. reference voltages that have been generated internally de?ne the maximum range of the input signal for the adc. nominal values are as follows: ref+ = 2.0 v refC = 1.5 v @ v cc = 5.0 v table 7 adc inputs typical range input range (v) clamping typical application cvi/adc0 1.5C2.0 yes (refC) ccd sampling input adc1/port17 0C5.0 no afc input adc2/port00 0C5.0 no key scanning input adc3/port05 0C5.0 no key scanning input adc4/port04 0C5.0 no key scanning input adc5 1.5C2.0 yes (ref+) v sync decoder sampling input
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 25 for other v cc values, the reference voltages must be prorated as follows: ref+ = 0.4 * v cc refC = 0.3 * v cc the maximum sampling rate of the adc converter is 3 mhz. it takes 4 sclk cycles for valid output data from the adc to become available. this is especially important if the application uses the single-shot mode. the adc exhibits monotonous conversion characteristics with a nonlinearity of less than 0.5 lsb. adc0. the adc has a range of 0.5v (from 1.5v to 2.0v) and is directly multiplexed to the input of the adc. the remaining adc inputs (ranging from 0v to 5v) use agnd and av cc voltage as a reference. figure 14 is a block diagram of the adc inner structure, and figure 15 illustrates adc input circuits. . figure 14 z90t361/6 adc block diagram analog converter 6 to1 mux refC ref+ clamp clamp adc0 (ccd decoder) adc1/port17 adc2/port00 adc3/port05 adc5 (v sync decoder) 4 z90t366 adc4/port04 to digital
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 26 adc data packing up to four 4-bit adc data samples can be packed into one 16-bit word without software overhead. if r4(1)<9> = 1, every reading of r4(1) returns the result, where the high 12 bits are the three previous adc samples and the low 4 bits are the current one, as illustrated in figure 15. figure 15 adc data packing the following routine shows adc packing: ld sr,%#20; select regbank1 ld a,ext4; turn adc data packing mode on or a, #%0200; set r4(1)<9> ld ext4, a; ld a, ext4; read ?rst adc sample, a = %0005 ld a, ext4; read second adc sample, a = %005e ld a, ext4; read third adc sample, a = %05e7 ld a, ext4; read forth adc sample, a= %5e74 ld a, ext4; read ?fth adc sample, ?rst sample is thrown away, a = %e741 the adc is controlled by the external register r4(1). 2.10 pulse width modulation pulse width modulation (pwm) is used in conjunction with external low-pass ?lters to perform digital-to-analog conversion. six pwms (8-bit resolution each) generate signals for the control for video and sound attributes. in case of a chassis employing a frequency synthesis tuner, these pwms can also control video or sound attributes. pwms can also be used to acknowledge tones for remote or keyboard commands. each pwm circuit features a data register whose contents are set under program control. the data in the register determines the ratio of pwm high to pwm low time. pwm data registers are not initialized when reset. in order to eliminate a potential glitch on a pwm output, it is recommended to initialize pwm data registers before enabling the vcos. adc sample (t) adc sample (t-1) adc sample (t-2) adc sample (t-3) 0 3 4 7 8 11 12 15
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 27 external registers r0(2) to r5(2) are data registers for pwm1 to pwm6 accordingly. 2.11 i 2 c interface there are two hardware modules that support standard i 2 c bus protocol according to the i 2 c bus speci?cation published by philips in 1992, titled i 2 c peripherals for microcontrollers data handbook . the ?rst module, the master, can be con?gured for fast (400 khz) or slow (100 khz) bit rates and can be used in applications with a single master. the z90t366 adds two additional non-standard bit rates (50 khz and 10 khz) and an additional multiplexed master port that is controlled by the i 2 cm_mux control bit. table 8 lists the bit rates for the master i 2 c bus. to suppress possible problems on both data (sda) and clock (scl) lines, digital ?lters are available for all inputs of the i 2 c bus interface. these ?lters exhibit a time constant equal to 3t sclk = 250 ns. if the master i 2 c interface is enabled, corresponding i/os, port11 and port12, must be assigned as outputs. master and slave modules cannot be used simultaneously because of the shared i 2 c data register (see the register 3(0) data ?eld). the software activates i 2 c modules by writing appropriate commands into the control register. to control the i 2 c bus interface, the control register r3(0) toggle bit must point to an appropriate interface (master or slave). m_disable or s_disable bits allow either the master or slave i 2 c interface to be disabled so as not to interfere with any activity associated with the port pins. at power-on reset (por), both i 2 c interfaces are enabled. to use the i 2 c interface, table 8 master i 2 c bus bit rates mode i 2 c mode bit rate actual bit rate lo/slow 0C10 khz 10 khz hi/slow 0C50 khz 44 khz lo/fast slow 0C100 khz 91 khz hi/fast fast 0C400 khz 334 khz
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 28 the corresponding port pin (multiplexed with the i 2 c data and clock) must be con?gured as an output, while m_disable or s_disable bits must be reset to 0 . external register r3(0) controls the i 2 c. table 9 lists the master i 2 c bus interface commands. table 10 lists the slave i 2 c bus interface commands. figure 16 and figure 17 are ?ow charts of the master and slave modes. table 9 master i 2 c bus interface commands command notes/function 0 0 0 this command sends a start bit, followed by an address byte speci?ed in the data ?eld (bits <7:0>), then fetches an acknowledgment in bit <0>. this command initializes communication and generates 9 scl cycles. 0 0 1 this command sends one byte of data speci?ed in the data ?eld (bits <7:0>), then fetches an acknowledgment in bit <0>. this command is used in a write frame and generates 9 scl cycles. 0 1 0 this command sends bit <7> as an acknowledgment (ack = 0, nak = 1), then receives a data byte. this command is used in a read frame when the next data byte is expected and generates 9 scl cycles. received data appears in the data ?eld (bits <7:0>). 0 1 1 this command sends bit <7> as an acknowledgment (ack = 0, nak = 1). this command is used in a read frame to terminate data transfer and generates one scl cycle. 1 0 0 1 0 1 a null operation. this command must be used with a reset bit and/or a toggle bit . using the reset and/or toggle bits with any other command interferes with the logic of the i 2 c interface. 1 1 0 this command receives one data byte. it is used in a read frame to receive the ?rst data byte after the address byte is transmitted. it generates 8 scl cycles. 1 1 1 this command sends a stop bit and generates one scl cycle.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 29 table 10 slave i 2 c bus interface commands command notes/function 0 0 0 reserved . c annot be used. 0 0 1 this command sends bit <7> as an acknowledgment (ack = 0 only), then receives one data byte. this command is used in a write frame and requires 9 scl cycles. received data is read as a data ?eld (bits <7:0>). 0 1 0 this command sends one byte of data speci?ed in a data ?eld (bits <7:0>), then fetches an acknowledgment in bit <0>. this command is used in a read frame and requires 9 scl cycles. 0 1 1 reserved. cannot be used. 1 0 0 1 0 1 a null operation. this command must be used with a reset bit and/or toggle bit . using the reset and/or toggle bits with any other command interferes with the logic of the i 2 c interface. 1 1 0 this command sends a bit <7> as a not acknowledgment (nak = 1 only) in a write or read frame. this command terminates i 2 c communication and requires one scl cycle. the sulfonamide bit is automatically reset when a busy bit <9> goes low. this command sends a bit <7> as an acknowledgment (ack = 0 only) in a read frame and requires one scl cycle. the send data command (010) must be executed next. this command acknowledges an address byte in a read frame. 1 1 1 reserved . c annot be used.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 30 figure 16 master mode start read r3(0)<8> busy ==0? yes no write r3(0) {0000,0xxx,addr,r/w} no busy==1 write frame read frame send a start bit followed by a 7-bit address byte yes write r3(0) {1100,0xxx,xxxx,xxxx} busy==1? more bytes yes no to send? write r3(0) {0010,0xxx,data} (send data byte) yes no (ask slave to send data byte) read r3(0)<0> (read ack bit) r3(0)<0>==0? yes no (nak) no (ack) busy==1? yes read r3(0) {xxxx,xxxx,data} (read data byte) yes no receive more bytes? write r3(0) {0100,0xxx,0xxx,xxxx} (acknowledge data byte) write r3(0) {0110,0xxx,0xxx,xxxx} (ack data byte) write r3(0) {0110,0xxx,1xxx,xxxx} (nak data byte) no busy==1? yes write r3(0) {1110,0xxx,xxxx,xxxx} (send a stop bit) note: shaded blocks are executed in software
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 31 if a stop condition is detected at any point, the hardware resets the slave bit (r3(0)) and releases the i 2 c bus. figure 17 slave mode start start condition detected yes no address matches yes no set slave moder3(0) hold the bus stretch clock (nak master) write r3(0) {1100,0xxx,1xxx,xxxx} read r3(0)<0> ack master ignore master write frame read frame r3(0)<0>=1 r3(0)<0>=0 reset slave busyr3(0)<9> (send data) write r3(0) {0100,0xxx,data} read r3(0)<0> no (nak) yes (ack) hold the bus stretch clock (ack master) write r3(0) 0010,0xxx,0xxx,xxxx (get data) read r3(0) goto ack master slave = 1,busy = 0 r3(0) yes no r3(0) yes no r3(0) yes no reset r3(0)<9> set r3(0)<9> (r/w bit) (ack master) write r3(0) {1100,0xxx,0xxx,xxxx} ack==0? (nak master) write r3(0) 1100,0xxx,1xxx,xxxx reset r3(0) slave = 1,busy = 0 slave = 1,busy = 0 note: shaded blocks are executed in software wait here for send first byte command wait for ack from master hold the bus stretch clock
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 32 2.12 on-screen display (osd) the z90t366 provides sophisticated on-screen display features. on-screen display has the following two modes: osd used to generate tv control osd ccd used to display closed caption information osd mode provides access to the full set of control attributes including latched and unlatched attributes. unlatched attributes can be modi?ed on a character-by- character basis. control characters change latched attributes. any 256-character set can be displayed with many display attributes, including underlining, italics, blinking, eight foreground and background colors, character position offset delay, and background transparency. a 16-bit display character represents foreground color, background color, and underline attributes, which can be modi?ed character by character. in addition, the z90t361 supports eight ?xed plus eight programmable color palettes out of 64 colors, independent left and right shadows with color control. shadows are available on transparent and nontransparent backgrounds. semi-transparency is supported on a character-by- character basis. a characters pixel array is stored as 16, 18, or 20 words in character generation rom (cgrom). additional hardware provides the capability to display characters at two and three times normal size. the smoothing logic contained in the on-screen display improves the appearance of two and three times normal size characters. shadows can be activated to improve the visibility of characters by adding a border (one pixel wide) on each side. the z90t366 provides rgb signals and a video blank signal. rgb outputs are available in two modes: digital and analog. in digital mode, the output rgb signals correspond to a primary colors palette. analog mode supports 15 different palettes, which can be chosen under software control. in analog mode, each rgb output is generated by a 2-bit digital-to-analog converter. the user can switch the 2-bit digital inputs of the digital-to-analog converter to port pins (port10, port13, port14, port15, port18 and port08) under software control by setting bit9 in register r3(1). video synchronization is normally obtained from h_flyback and v_flyback but can be generated by the z90t366 and driven to the external de?ection unit using the bidirectional h sync and v sync ports when external video synchronization signals are not present. osd is completely software controlled. hardware supports the optimum generation of the character-based osd; however, the cpu can bypass it and
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 33 generate pixels and attributes directly. the block diagram in figure 18 illustrates the osd data ?ow. figure 19 and figure 20 indicate the r, g, b, and blank output circuits. figure 18 data flow figure 19 blank and r, g, b outputs in digital mode shift register r g b memory rd r3(3) r4(3) r3(3) r0(3) r1(3) r2(3) r0(3) r1(3) r2(3) r6(3) r7(3) cpu video ram osd:at7ch8 or attr15 ccd:char7 orattr7 cgrom pixels: 1x 2x 3x full attrib attribute p a l e t t e s 3 x d a c v cc pa d p n output
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 34 figure 20 r, g, and b outputs in analog (palette) mode closed caption data capture closed-caption text can be decoded directly from the composite video signal using the processors digital signal processing capabilities and displayed on the screen. the character representation in this mode provides simple attribute control by inserting control characters. each word of video ram speci?es two displayed characters. the 4-bit ?ash a/d converter, with proper clamping, provides the ability to receive the composite video signal directly and process the closed-caption text embedded in the signal. signal processing can be applied directly to the signal to improve decoder performance. cgrom relocation cgrom can be placed anywhere in the 64k rom address space by setting the cgrom address offset register r7(2). this offset is added to the cgrom address before accessing the rom. by modifying the cgrom offset, several v cc v cc pa d r 3 kohms i 800 ma i / 2 r,g or b <1> r,g or b <0> v cc i / 4
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 35 fonts can be accessed (limited only by rom size). when reset, r7(2) = 0 (no offset), making the z90t366 backward-compatible with existing osd control software. the character scan line from cgrom addressed by the character register is fetched and stored into the cgrom capture register. if a pixel is set to 1 , it displays the foreground color. if a pixel is set to 0 , it displays the background color. the scan line can be stretched by the character multiplier to be two or three times normal character size by duplicating each bit in the word. controlling character expansion the character size can be stretched to two or three times the size of the scan line. hardware fetches data from cgrom and stretches the data to be read from registers r0(3), r1(3), and r2(3). figure 21 is a block diagram of the structure of the character expansion multiplexor, and table 11 lists bit functions. figure 21 character expansion cgrom data capture register character expansion multiplexor char_mult_mid char_mult_high char_mult_low rom data processor external bus control x1, x2, x3 r0(3) r1(3) r2(3) 16 16 48 16 16 16
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 36 displayed data formats the z90t366 hardware supports the following two different data formats: osd mode, r4(3) = 1 supports a standard osd with full set of features. ccd mode, r4(3) = 0 supports reduced features which comply with the recommendations of the fcc on closed caption support. in ccd mode, the background color of the characters cannot be changed and is always preset to black . osd mode in osd mode, each character occupies a 16-bit word in vram. there are two possible character formats de?ned: a display character and a control character. the code stored in display character format de?nes a character code and up to 7 attributes of the character. the control character de?nes latched attributes and is presented on-screen as a space character. the combination of display and control characters provides versatile osd generation. smoothing is supported for double-size (x2) and triple-size (x3) characters only. ccd mode in ccd mode, each character occupies 8 bits (one byte) in vram. the ccd characters must be mapped into a 16-bit vram data ?eld. the hardware supports compressed placement of characters in vram. each word in vram is represented by a high byte and a low byte. a currently active byte is selected by r4(3). the format and data representation in both bytes is exactly the same. there are two possible character formats de?ned: a display character and a control character. the code stored in display character format de?nes a table 11 character expansion register capture register contents char_mult_high char_mult_mid char_mult_low x1 operation abcdefghijklmnop x2 operation aabbccddeeffgghh iijjkkllmmnnoopp x3 operation aaabbbcccdddeeef ffggghhhiiijjjkk klllmmmnnnoooppp
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 37 character code. the control character de?nes up to ?ve attributes (foreground color, italic, underline, blinking, and transparent). it is presented on screen as a space character. the combination of display and control characters provides the basis for a speci?ed range of attributes de?ned by fcc speci?cations for ccd. shadows shadows, if enabled, are active on both transparent and nontransparent backgrounds. two bits in the attributewr and attributerd registers, (r2(3)<1:0> and r3(3)<1:0>), control the type of shadow. refer to figure 22. figure 22 table settings the smoothing attribute has been moved to r7(3)<5>. the bit assignment in the latched attribute follows the bit assignment in r2(3). the left and right shadow colors are independently controlled by r6(2) and r6(2). the smoothing control bit r7(3)<5> must be set to a 1 in order to activate fringing. semi-transparent both semi-transparency (pin name sovl) and transparency (pin name ovl) attributes are supported. the semi-transparency mode can be enabled through either latched or unlatched attributes. latched attributes remain set until they are reset. unlatched attributes remain set for only one character, which means the attribute must be constantly refreshed on a character-by-character basis. background foreground right shadow left shadow r2(3)<1:0>, r3(3)<1:0> function 00 no shadows 01 left shadow 10 right shadow 11 both shadows
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 38 activation to activate semi-transparency output, two bits must be set properly. port 0f must be in output mode [r6(0) = 0], and the sovl/port0f control bit must be in sovl mode [r3(1)<6> = 1]. latched semi-transparency the latched semi-transparency attribute is controlled by bit [r2(3)<6>]. unlatched semi-transparency the unlatched semi-transparency attribute is controlled by bit [r3(3)<8>]. this bit has one of four possible assignments depending on how it is set up in [r7(3)<7:6>]. the four assignments are underline, semi-transparency, blinking, and cgrom bank select. notes: 1. the semi-transparency signal (sovl), when active, is only valid with the background color. with the foreground color, sovl is inactive. therefore, characters do not take on a semi-transparent appearance (only the background does). this condition allows characters to be read without interference. 2. if both the transparency (background and foreground color are equal) and semi-transparency are activated, the ovl signal is high, and the sovl signal is low. attribute assignment depending on r7(3)<7:6>, bit 8 of the attribute_data register, r3(3) (in character mode) can be assigned to control either 1st underline, semi-transparency, blinking, or cgrom bank select, as indicated in table 12. table 12 attribute assignment r7(3)<7:6> r3(3)<8> 00 1st underline (por) 01 semi-transparency 10 blinking 11 cgrom bank1 select
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 39 2.13 cursor the cursor buffer ( a one-line pixel buffer) is loaded via the dma on every line where the cursor is displayed (no software support is required). horizontal size is programmable at 16, 32, or 48 pixels wide, and vertical size is programmable from 1 to 63 lines per ?eld. the color depth is 2 bits per pixel, 3 programmable colors and the transparency. depending on r1(0), the cursors colors can be selected either from a current palette (r1(0) = 0) or from palette #6 (r1(0) = 1). refer to table 15. the cursor image is stored in rom as a bitmap. the number of cursors is limited by available rom size. the cursor is positioned by initializing cursor parameters in the beginning of every ?eld. initialization occurs by setting the cursor_info_load bit r7(3)<4> to 1 , then writing sequentially to the r3(3) 16-bit parameters (color, hparam, vparam and caddr, respectively). the cursor buffer is loaded from rom at the leading edge of h sync wherever the horizontal line requires a cursor. this process halts the cpu for 3/5/7 cycles depending on the cursors horizontal size. the cursor bitmap address pointer (caddr) is incremented automatically. though the cursor can be displayed anywhere on the screen, limiting the cursor to the osd area is best. outside of the osd area, the cursor can jitter or become distorted. the cursor bitmap is organized as pixel data placed sequentially in the rom. the data format is described below. for the interlaced mode, even and odd cursor bitmaps must be de?ned separately. proper selection occurs during the cursor initialization at the beginning of every ?eld. see figure 23, table 13, and table 14. figure 23cursor 48 pixels max 63 lines max (01) color 1 (10) color 2 (11) color 3 (00) transparent horizontal position (x: 1C1023) vertical position (y: 1C1023) focus (x,y) (2*63 in progressive scan mode)
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 40 example ld sr,%#60 ; select regbank3 or ext7,#%0010; enable cursor_info_load ld ext3,#(3*64 + 7*8 + 2); load ccolor: color3 = 3, color2 = 7, color1 = 2 ld ext3,#(2*1024 + 120); load hparam: hsize = 2 (32 pixels), hpos = 120 ld ext3,#(28*1024 + 55); load vparam: vsize = 28, vpos = 55 ld ext3,#%6000; load caddrcursor bitmap address and ext7,#%ffef; disable cursor_info_load, ready for osd table 13 cursor parameters parameter reg ?eld bit position data description caddr caddr fedcba9876543210 d cursor bitmap address (pointer to cursor bitmap in rom) vparam vsize fedcba---------- 1C63 vertical size (lines in one ?eld) vpos ------9876543210 1C1023 vertical position (lines in one ?eld) hparam n/a fedc------------ n/areserved hsize ----ba---------- 00 01 10 11 no cursor 16 pixels wide 32 pixels wide 48 pixels wide hpos ------9876543210 1C1023 horizontal position (pixels from trailing edge of hsync) ccolor n/a fedcba9--------- n/areserved color3 -------876------ 0C7 cursor color 2 assignment color2 ----------543--- 0C7 cursor color 1 assignment color1 -------------210 0C7 cursor color 0 assignment
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 41 table 14 memory allocation for cursor bitmap 16 pixels wide mode addrn: l0_p15_b0, l0_p14_b0, l0_p13_b0, ... , l0_p1_b0, l0_p0_b0 addrn+1: l0_p15_b1, l0_p14_b1, l0_p13_b1, ... , l0_p1_b1, l0_p0_b1 addrn+2: l1_p15_b0, l1_p14_b0, l1_p13_b0, ... , l1_p1_b0, l1_p0_b0 addrn+3: l1_p15_b1, l1_p14_b1, l1_p13_b1, ... , l1_p1_b1, l1_p0_b1 .................................................. addrn+2n: ln_p15_b0, ln_p14_b0, ln_p13_b0, ... , ln_p1_b0, ln_p0_b0 addrn+2n+1: ln_p15_b1, ln_p14_b1, ln_p13_b1, ... , ln_p1_b1, ln_p0_b1 32 pixels wide mode addrn: l0_p31_b0, l0_p30_b0, l0_p29_b0, ... , l0_p17_b0, l0_p16_b0 addrn+1: l0_p31_b1, l0_p30_b1, l0_p29_b1, ... , l0_p17_b1, l0_p16_b1 addrn+2: l0_p15_b0, l0_p14_b0, l0_p13_b0, ... , l0_p1_b0, l0_p0_b0 addrn+3: l0_p15_b1, l0_p14_b1, l0_p13_b1, ... , l0_p1_b1, l0_p0_b1 addrn+4: l0_p31_b0, l0_p30_b0, l0_p29_b0, ... , l0_p17_b0, l0_p16_b0 addrn+5: l0_p31_b1, l0_p30_b1, l0_p29_b1, ... , l0_p17_b1, l0_p16_b1 .................................................. addrn+4n: ln_p31_b0, ln_p30_b0, ln_p29_b0, ... , ln_p17_b0, ln_p16_b0 addrn+4n+1: ln_p31_b1, ln_p30_b1, ln_p29_b1, ... , ln_p17_b1, ln_p16_b1 addrn+4n+2: ln_p15_b0, ln_p14_b0, ln_p13_b0, ... , ln_p1_b0, ln_p0_b0 addrn+4n+3: ln_p15_b1, ln_p14_b1, ln_p13_b1, ... , ln_p1_b1, ln_p0_b1 48 pixels wide mode addrn: l0_p47_b0, l0_p46_b0, l0_p45_b0, ... , l0_p13_b0, l0_p32_b0 addrn+1: l0_p47_b1, l0_p46_b1, l0_p45_b1, ... , l0_p33_b1, l0_p32_b1 addrn+2: l0_p31_b0, l0_p30_b0, l0_p29_b0, ... , l0_p17_b0, l0_p16_b0 addrn+3: l0_p31_b1, l0_p30_b1, l0_p29_b1, ... , l0_p17_b1, l0_p16_b1 addrn+4: l0_p15_b0, l0_p14_b0, l0_p13_b0, ... , l0_p1_b0, l0_p0_b0 addrn+5: l0_p15_b1, l0_p14_b1, l0_p13_b1, ... , l0_p1_b1, l0_p0_b1 addrn+6: l0_p47_b0, l0_p46_b0, l0_p45_b0, ... , l0_p33_b0, l0_p32_b0 addrn+7: l0_p47_b1, l0_p46_b1, l0_p45_b1, ... , l0_p33_b1, l0_p32_b1 ..................................................
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 42 where addrn+6n: ln_p47_b0, ln_p46_b0, ln_p45_b0, ... , ln_p33_b0, ln_p32_b0 addrn+6n+1: ln_p47_b1, ln_p46_b1, ln_p45_b1, ... , ln_p33_b1, ln_p32_b1 addrn+6n+2: ln_p31_b0, ln_p30_b0, ln_p29_b0, ... , ln_p17_b0, ln_p16_b0 addrn+6n+3: ln_p31_b1, ln_p30_b1, ln_p29_b1, ... , ln_p17_b1, ln_p16_b1 addrn+6n+4: ln_p15_b0, ln_p14_b0, ln_p13_b0, ... , ln_p1_b0, ln_p0_b0 addrn+6n+5: ln_p15_b1, ln_p14_b1, ln_p13_b1, ... , ln_p1_b1, ln_p0_b1 lx_py_bz = line x, pixel y, bit z; line 0 = ?rst (top) cursors line; pixel 0 = ?rst (left) cursors pixel bit 1, bit 0 = most and least signi?cant bits of the cursors color de?ned as 00 = transparent 01 = color 1 10 = color 2 11 = color 3 table 14 memory allocation for cursor bitmap (continued)
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 43 2.14 color palette assignment the z90t366 features a total of 16 color palettes, 8 of which are ?xed and 8 of which are programmable. palettes are selected by setting r7(3)<3:0>. fixed palettes are de?ned in table 15. programmable palettes (8C15) are mapped to ar0Car63 (8 registers per palette). the register and bit assignments for palette # 11 are listed in figure 24. programmable palettes are grouped into 2 banks (palettes 8C11 and 12C15). palettes in the bank cannot be modi?ed if another palette from the same bank is displayed. an interleaving palette bank access must be created if on-the-?y palette modi?cations are required. one palette bank is used to display four colors, and the other bank is used for updates. see figure 24. figure 24 programmable palette control at ar register table 15 fixed palette color assignment (color0 is black; color7 is white) palette description color1 color2 color3color4 color5 color6 rgbrgbrgbrgbrgbrgb 0 digital rgb 00 00 11 00 11 00 00 11 11 11 00 00 11 00 11 11 11 00 1 analog rgb 00 00 11 00 11 00 00 11 11 11 00 00 11 00 11 11 11 00 2 greyscale_1 01 01 01 10 10 10 11 11 11 00 00 00 01 01 01 10 10 10 3 greyscale_2 00 00 00 01 01 01 01 01 01 10 10 10 10 10 10 11 11 11 4 rgb_cyan_2grey 00 00 11 00 11 00 00 11 11 11 00 00 01 01 01 10 10 10 5 rgb_magenta_2grey 00 00 11 00 11 00 01 01 01 11 00 00 11 00 11 10 10 10 6 rgb_yellow_2grey 00 00 11 00 11 00 01 01 01 11 00 00 10 10 10 11 11 00 7 starsight 00 11 11 10 11 10 10 10 10 11 01 01 11 11 10 11 11 00 color1 0 1 2 3 4 5 b g r color2 0 1 2 3 4 5 b g r color3 0 1 2 3 4 5 b g r color4 0 1 2 3 4 5 b g r color5 0 1 2 3 4 5 b g r color6 0 1 2 3 4 5 b g r ar25 ar26 ar27 ar28 ar29 ar30 color7 0 1 2 3 4 5 b g r ar31 color0 0 1 2 3 4 5 b g r ar24 6 7 n/a 6 7 n/a 6 7 n/a 6 7 n/a 6 7 n/a 6 7 n/a 6 7 n/a 6 7 n/a
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 44 2.15 other functions video and sound attribute control basic receiver functions such as color and volume can be controlled directly by six 6-bit pulse-width modulated ports. infrared capture function the infrared remote control data capture feature uses a capture register to hold the time value from one transition of ir data to the next. software periodically checks and reads the capture status and the value if a new capture occurs. subsequent decoding and command passing of the received ir signal is under software control. figure 25 illustrates the ir input circuit. figure 25 ir capture register input loop filter the loop filter pin con?guration is represented in figure 26. figure 26 loop filter pin con?guration pa d ir input 20 ? v cc pa d 20 ? pd positive out pd negative out to vco driver v cc v cc
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 45 hardware accelerated 4-bit and 8-bit shifts hardware-accelerated byte and nibble shifts signi?cantly reduce software overhead. shifts are created by assigning one particular ram location (%1fe) a special meaning. depending on the r4(1) settings, data read from this address are either unmodi?ed, rotated 4 bits left, 4 bits right, or byte swapped. see table 16. example ld sr,#%20 ; select regbank1 ld a,ext4 ; turn hardware-supported shift mode on and a, #%9fff ; or a, #%4000 ; ld ext4, a ; select 4-bit right rotate ld a, #%3ed7 ; load a = 3ed7h ld %1fe, a ; write a to the ram ld a, %1fe ; a = 73edh ld a,ext4 ; turn hardware-supported rotate mode on or a,#%6000 ; ld ext4, a ; select byte swap ld a, %1fe ; a = d73eh table 16 r4(1) settings r4(1) function 00 direct (unmodi?ed)Cpor 01 4-bit left rotate 10 4-bit right rotate 11 byte swap
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 46 3 register groups table 17 provides a summary of the registers in external banks. table 17 register summary bank bank sub address read register write register description bank0 7 dir1 9-bit i/o port 1 direction control 6 dir0 16-bit i/o port 0 direction control 5 port1 9-bit i/o port 1 4 port0 16-bit i/o port 0 3i 2 c_int i 2 c interface register 2 pll_freq pll frequency control 1 write control register cursor palette gauge write control register 0 reserved reserved bank1 7 wdt_smr_ctl/interrupt smr and wdt control and interrupt 6 clock_ctl clock control (switch vco/dot) 5 cap_1s_ctl counter timers control 4 adc_ctl a/d converter control 3 standard_ctl output h/vsync/blnk control 2 9-bit counter stop/wdt stop and wdt instructions, 9-bit counter 1 sclk_freq stop/sleep/normal mode 0 clamp_pos de?nes position of video clamp pulse bank2 7 cgrom offset register cgrom offset register 6 shadow control register de?nes right and left shadow color 5 pwm_data6 8-bit pwm 6 data 4 pwm_data5 8-bit pwm 5 data 3 pwm_data4 8-bit pwm 4 data 2 pwm_data3 8-bit pwm 3 data 1 pwm_data2 8-bit pwm 2 data 0 pwm_data1 8-bit pwm 1 data
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 47 3.1 register description the register ?le in the z90t366 is organized into four banks that can be selected by writing to bits 5 and 6 (register bank selector bits) in the status register of the z90t366 core. all registers are mapped into an external register space; each bank consists of 8 registers. the status register is available to read or write at any time. the appropriate bank of registers must be selected before accessing the register. the software must keep track of which register bank is accessible at any time. refer to table 18 for register bank assignments. bank3 7 output palette output palette 6 palette_color display palette color/underline color 5 capture_data i 2 c slave addr. capture register data 4 osd_control on screen display control 3 attribute_data vram_data character attribute/video ram data 2 ch_x1_lo_x3 cg_attribute character multiple/character graphics attribute 1 lo_x2_mid_x3 cg_nxt_prv character multiple/next or previous data 0 hi_x2_hi_x3 cg_current character multiple/current data table 18 bank assignments bank status register bank functions bank0 xxxx xxxx x00x xxxx b i/o ports, i 2 c interface, pll frequency, cursor bank1 xxxx xxxx x01x xxxx b control registers bank2 xxxx xxxx x10x xxxx b pwm1Cpwm5 bank3 xxxx xxxx x11x xxxx b osd, palette control table 17 register summary (continued) bank bank sub address read register write register description
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 48 3.2 bank0 (i/o ports, i 2 c interface, pll frequency, cursor) control registers table 19 de?nes the bits for register1, r1(0) cursor palette control register. table 20 de?nes the bits for register2, r2(0) pll frequency data register. table 19 register1, bank 0, cursor palette bit 15 14 1312 11 10 9 8 r/w reserved reserved r/w r/w r/w r/w r/w r/w reset x x 0 0 x x x x bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxx x note: r = read w = write x = indeterminate reg field bit position r w data description reserved fe-------------- reserved cursor palette --d------------- rw1 0 palette #6 (recommended) current palettepor pgwritenen ---c------------ rw1 0 page write enable page write disablepor pagewrite ----ba9876543210 r w xxxx pagewrite# table 20 register2, bank 0, pll frequency data register bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w reserved r/w r/w reset 00100000 bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 01110000 note: r = read w = write x = indeterminate
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 49 if the master i 2 c interface is enabled, the corresponding i/os, port11 and port12 must be assigned as outputs. (the z90t366 does not have pins to support a slave interface.) the vco, dot, and sclk frequency are de?ned as the following: f vco = f dot = f sclk = xtal * (256 + pll data ) therefore, xtal = 32.768 khz at por, the pll frequency data register is preset to 70h, which corresponds to the vco frequency of 12.058 mhz. the pll_data ?eld can be loaded with any value from 00h. this value corresponds to an sclk = 256*xtal up to ffh, which corresponds to an sclk = 511*xtal. table 21 through table 25 describe the bits in registers 3 through 7. reg field bit position r w data description m_disable f--------------- rw 1 0 i 2 c master interface disabled i 2 c master interface enabledCpor s_disable -e-------------- rw 1 0 i 2 c slave interface disabled i 2 c slave interface enabledCpor i 2 cm_mux --d------------- rw 1 0 select i 2 msd2, i 2 msc2Cpor select i 2 msd1, i 2 msc1 i 2 c_out_ resistance ---c------------ rw 1 0 600 ? output resistance normal cmos port output resistanceCpor i 2 c_speed _range ----b----------- rw 1 0 low speed range (10 khz, 50 khz) high speed range (100 khz, 400 khz)Cpor reserved -----a---------- reserved p46/ hsync2 ------9--------- r w 10 hsync logic takes input from hsync pinCpor. this bit must always be set to 0 . p07/ csync -------8-------- rw 1 0 composite sync output p07 i/oCpor pll_data --------76543210 r w d pll divider = 256 + d
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 50 data written to r3(0) requires 4 cycles before being applied. consecutive writings to these bits require at least a 6-cycle delay. the received data is available for reading only when the busy bit is reset to a 0. when por, the speed of the i 2 c interface is set to low. table 21 register3, bank 0, i 2 c interface register bit 15 14 1312 11 10 9 8 r/w w w w r/w w r/w r/w r/w reset 000001xx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position r w data description command fed------------- w d see table 9 and table 10 for a full description. toggle ---c------------ r w 1 0 1 0 slave interface master interfaceCpor condition toggle active i 2 c interface no effect reset ----b----------- w1 0 reset slave i 2 c interface if bit =1 reset master i 2 c interface if bit =0 no effect slave_mode -----a---------- r1 0 slave mode is active (por condition) slave mode is inactive slavebusy ------9--------- r1 0 slave i 2 c interface is busy slave i 2 c interface is idle masterbusy -------8-------- r1 0 master i 2 c interface is busy master i 2 c interface is idle data --------76543210 rw xx xx received data data to be sent
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 51 table 22 register4, bank 0, port 0 data register bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position r w data description port_data fedcba9876543210 r w xxxx xxxx if a port is con?gured in input mode, enter the input data onto the port pins. if a port is con?gured in output mode, then the data is written directly to the port data. table 23 register5, bank 0, port 1 data register bit 15 14 1312 11 10 9 8 r/w reserved reserved reserved reserved reserved reserved reserved r/w reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position r w data description reserved fedcba9--------- reserved port_data -------876543210 r w xxxx xxxx if a port is con?gured in input mode, enter the input data onto the port pins. if a port is con?gured in output mode, then the data is written directly to the port data.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 52 table 24 register6, bank 0, port 0 direction register bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 note: r = read w = write x = indeterminate reg field bit position r w data description port_direction fedcba9876543210 r w xxxx 1: input mode for corresponding bit 0: output mode for corresponding bit table 25 register7, bank 0, port 1 direction register bit 15 14 1312 11 10 9 8 r/w reserved reserved reserved reserved reserved reserved reserved r/w reset xxxxxxx1 bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 note: r = read w = write x = indeterminate reg field bit position r w data description reserved fedcba9--------- reserved port_direction -------876543210 r w xxxx 1: input mode for corresponding bit 0: output mode for corresponding bit
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 53 3.3 bank1 (control registers) table 26 through table 33 provide bit functions for bank 1 control registers. table 26 register0, bank 1, clamp position register bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w reserved reserved reserved reset 11110000 bit 76543210 r/w reserved r/w r/w r/w r/w r/w r/w r/w reset 0 xxxxxxx note: r = read w = write x = indeterminate reg field bit position r w data description disable_clamp_1 f--------------- rw 1 0 adc0 clamp generation is disabled adc0 clamp generation is enabled disable_clamp_2 -e-------------- rw 1 0 adc5 clamp generation is disabled adc5 clamp generation is enabled disable_tip_clamp --d------------- rw 1 0 adc0 tip clamp is disabledC por adc0 tip clamp is enabled counter_input ---c------------ rw 1 0 counter takes input from p06C por counter takes input from internal hsync separator arenable ----b----------- rw 1 0 ar enabled ar disabledCpor reserved -----a987------- reserved position ---------6543210 r w xx position of clamp pulse (from leading edge of the h- flyback)
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 54 at por the disable_clamp bit is set to 1 . the clamp pulse is generated if enabled (bit ) and the sclk frequency is switched back to pvco. the svco/pvco ?ag in r6(1) must be reset to 0 before the current h sync , regardless of whether the svco is enabled or disabled. the clamp position is de?ned by the position ?eld. the width of the clamp pulse cannot be modi?ed and is set to 1s. the value that can be assigned to the position ?eld must be >10h and <7fh. the time interval between the leading edge of the h-flyback and the beginning of the clamp pulse can be calculated from the following equation: t delay positio n 1 t sclk --------------- ?? ?? position 82ns ==
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 55 when a por, smr, or wdt reset occurs, both the fast_enable and fast/slow are reset to 0 . this event corresponds to an sclk frequency of 32.768 khz. table 27 register1, bank 1, speed control register bit 15 14 1312 11 10 9 8 r/w reserved r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 r/w w w w r/w r/w r/w r/w r/w reset x x x 00000 note: r = read w = write x = indeterminate reg field bit position r w data description reserved f--------------- reserved mode selection -e-------------- rw 1 0 standard interlace mode (single scan) double scan -por h_shift --dcba98-------- r w d horizontal delay* por = 0 1xhsync --------7------- w1 0 1xhsync connected to port03 1xhsync is 2xhsync/2-por skip_hsync ---------6------ w1 0 skip next hsync do not skip next hsync frame_start ----------5----- w1 0 field start initializaiton no effect osd_black -----------4--- rw 1 0 next output line is osd next output line is black line_buffer_mode ------------3--- rw 1 0 interlaced(osd/black) progressive (osd/osd)-por 2x_rgb -------------2-- rw 1 0 double rgb output normal rgb output-por fast_enable --------------1- rw 1 0 pvco/svco enabled pvco/svco disabledCpor fast_slow ---------------0 rw 1 0 sclk is 12.058 mhz sclk is 32.768 khzCpor note: * 1 step = 4 pixels
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 56 to switch from a 32.768 khz sclk to 12 mhz, use the following procedure: 1. be sure the registerer bank is set to bank 1 with the following settings. ctl_bank equ %0020 ld sr, #ctl_bank 2. set the h_position ?eld r6(1)<3:0> to a nonzero value. hsynch_delay_min equ %0001 ld clk_control, #hsynch_delay_min 3. enable the primary and secondary vcos by setting by fast_enable bit r1(1)<1> to 1 . vco_enable equ %0002 ld sclk_freq, #vco_enable 4. wait one second for the 12 mhz pll to stabilize (about 33,000 clock cycles at 32.768 khz). the delay depends on the external pll ?lter and can vary signi?cantly. ld a, #11000 vco_delay: sub a, #1 jp nz, vco_delay 5. switch the sclk to a fast clock by setting fast/slow bit r(1)<0> to 1 . vco_enable equ %0002 fast_clk equ %0001 ld sclk_freq,#(vco_enable|fast_clk) the following code is the complete code to switch from 32.768 khz clock to 12 mhz clock: ctl_ban equ %0020 vco_enable equ %0002 fast_clk equ %0001 hsynch_delay_min equ %0001 ; ; set register bank to bank 1
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 57 ; ld clk_control, #hsynch_delay_min ; ; change the system clock rate from 32 khz up to 12 mhz ; before switching over ; 11000 * 3 * 32?ec ~= 1 second ; ld a, #11000 vco_delay: sub a, #1 jp nz, vco_delay ld sclk_freq, #(vco_enable | fast_clk) ; to switch from the 12 mhz sclk to 32.768 khz, use the following procedure: 1. switch the sclk to a 32.768 khz clock (set fast/slow bit r1(1)<0> to 0 ). 2. wait for more than r2(0)<7:0> + 256 clock cycles (approximately 32 s) for the sclk to be switched. 3. set the hsync_delay ?eld r6(1)<3:0> to 0fh . 4. disable the primary and secondary vcos (set the fast_enable bit r1(1)<1> to 0 ). if r1(1)<3> is set to 1 (interlaced osd/black), the interleaving of osd and black can be controlled by writing 1 or 0 into r1(1)<4>; this must be done once every v sync .
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 58 when a por, smr or a wdt reset occurs, the wdt is disabled. the wdt can be reenabled only after the pvco and svco are enabled, and the part is switched into a fast mode (sclk = 12 mhz). when switching the part into a slow mode (sclk = 32.768 khz), the wdt halts. to return to fast mode, the wdt must be initialized again. table 28 register2, bank1, wdt/stop (write only) and 9-bit counter (read only) control register bit 15 14 1312 11 10 9 8 r/w rrrrrrrr reset xxxxxxxx bit 76543210 r/w r reserved reserved reserved reserved reserved w w reset x 0000000 note: r = read w = write x = indeterminate reg field bit position r w data description counter_value fedcba987------- r counter on port06 value reserved ---------65432-- reserved wdt_instr --------------1- w1 0 wdt enable, wdt reset no effect stop_instr ---------------0 w1 0 stop no effect table 29 register3, bank 1, standard control register bit 15 14 1312 11 10 9 8 r/w w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 x x x 0 0 note: r = read w = write x = indeterminate
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 59 reg field bit position r w data description counter_ reset f--------------- w1 0 reset counter on port06 no effect counter_on/off -e-------------- rw 1 0 counter on port06 is on counter is offCpor condition mask_hvsync --d------------- rw 1 0 disable hvsync output hvsync in/outCpor condition char_size_16_18/20 ---c------------ rw 1 0 16x20 character matrix 16x16 or 16x18 character matrixC por bank0_sel ----ba---------- rw 00 01 10 11 ram bank 00Cpor ram bank 01 ram bank 02 reserved rgbc/port1 ------9--------- rw 1 0 sclk, r1, r0, g1, g0, b1, b0 p16,p08,p10,p13,p18,p15,p14 i 2 c_hi/lo_speed -------8-------- rw 1 0 hi speed (400/50 khz) lo speed (100/10 khz)Cpor cgrom bank --------7------- rw 1 0 bank1 is selected (starts @1000h) bank0 is selected (starts @0000h) sovl/port0f ---------6------ rw 1 0 semi-transparency p0f output osd_on/off ----------5----- rw 1 0 osd is enabled osd is disabledCpor rgb_polarity -----------4---- rw 1 0 negative positive positive/negative ------------3--- rw 1 0 negative hvsync in output mode positive hvsync in output mode sync/ovl -------------2-- rw 1 0 hvovl outputs hvsync outputs 25/30_hz and hv_polarity --------------10 rw 10 00 11 01 internal mode only (tv standard) 50 hz/625 lines support 60 hz/525 lines supportCpor external mode only (hv polarity) positive negative
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 60 two bits de?ne the polarity of the hvsync signals. bit <3> de?nes the polarity of the signals when they are con?gured as outputs (it does not affect internal hv C sync signals). bit <1> de?nes the polarity of the external hv C sync signals which affect the device synchronization. 1. the composite sync is active in internal mode only. 2. when using the internally-generated composite sync signal, be sure the sclk is set to 12.09 mhz (r2(0)<7:0> = 71h). this action helps ensure the best hsync frequency approximation. table 30 register 4, bank 1, adc control register bit 15 14 1312 11 10 9 8 r/w reserved r/w r/w r/w r/w r/w r/w reserved reset 00000000 bit 76543210 r/wr/wr/wr/wr/wrrrr reset 0000 xxxx note: r = read w = write x = indeterminate reg field bit position r w data description reserved f--------------- reserved hw_shift -ed------------- rw 00 01 10 11 direct (unmodi?ed)Cpor 4-bit shift left 4-bit shift right byte swap hsync_edge* ---c------------ rw 1 0 hsync is leading edge active hsync is trailing edge activeCpor adc_ref ----b----------- rw 1 0 all adcs use av cc and agnd as reference voltage all adcs use 2.0v and 1.5v as reference voltageCpor adc_select -----a---------- rw 1 0 adc4, adc5 select adc0, adc1, adc2, adc3 selectC por condition note:
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 61 adc0 has a signal range from 1.5 to 2.0 v. this ?eld is always connected to the composite video input pin and can be clamped to a refC voltage (1.5v). adc1, adc2, adc3, and adc4 have a signal range from 0 to 5.0 v. adc5 features a signal range from 1.5 to 2.0 v. for this ?eld, the input signal can be clamped to a ref+ voltage (2.0v). to use the i/o pin as an adc input, the corresponding port must be set up as an input (refer to r4(0) and r6(0)). adcdata- packing ------9--------- rw 1 0 adc data packing is on adc data packing is offpor reserved -------8-------- reserved adcspeed --------76------ rw 00 01 10 11 single conversionCpor condition sclk/4 sclk/6 sclk/8 adcsource ----------54---- rw 00 01 10 11 adc0 (cvi)/adc4 (p04)Cpor adc1 (p17)/adc5 adc2 (p00) adc3 (p05) adcdata ------------3210 r adc data note: *if hsync is leading edge active (r4(1) = 1),the actual interrupt is delayed from the leading edge of hsync by 72 cycles (~6 s @12 mhz). table 31 register5, bank 1, timer control register bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w reserved reserved r/w r/w reset xxxx00xx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position r w data description
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 62 reg field bit position r w data description capint_r f--------------- r w 1 0 1 0 rising edge is captured no rising edge is captured reset ?ag no effect capint_f -e-------------- r w 1 0 1 0 falling edge is captured no falling edge is captured reset ?ag no effect tout_1s --d------------- r w 1 0 1 0 timeout of 1s timer no timeout of 1s timer reset ?ag no effect tout_cap ---c------------ r w 1 0 1 0 timeout of capture timer no timeout of capture timer reset ?ag no effect reserved ----ba---------- reserved speed_1s ------98-------- rw 00 01 10 11 1s 250 ms 62.5 ms 15.625 ms port09/ cap_int* --------7------- rw 1 0 int2 source is port09 int2 source is capture timer cap_halt* ---------6------ rw 1 0 capture timer is halted capture timer is running cap_edge* ----------54---- rw 00 01 10 11 no capture capture on rising edge only capture on falling edge only capture on both edges cap_glitch* ------------32-- rw 00 01 10 11 glitch ?lter is disabled <8tsclk is ?ltered out <32tsclk is ?ltered out <128tsclk is ?ltered out
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 63 cap_speed * --------------10 rw 00 01 10 11 sclk/4 sclk/8 sclk/16 sclk/32 * resetting a capture timer flag does not modify capture counter or capture register data. when the glitch filter is enabled, the duration of the pulse is decreased by the cap_glitch value. table 32 register6, bank 1, clock switch control register bit 15 14 1312 11 10 9 8 r/w reserved reserved reserved reserved reserved reserved reserved reserved reset 00000000 bit 76543210 r/w reserved reserved r/w r/w r/w r/w r/w r/w reset 0001 xxxx note: r = read w = write x = indeterminate reg field bit position r w data description reserved fedcba9876------ reserved svco/pvco ----------5----- r w 1 0 1 0 sclk = svco (?ag) sclk = pvco (?ag) por switch sclk to pvco no effect no_switch -----------4---- rw 1 0 sclk = pvco, no clock switchingpor clock switching is enabled h_position ------------3210 r w d de?nes delay of h sync interrupt by 4x sclk cycles reg field bit position r w data description
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 64 h_position the h_position ?eld must be set to f. the actual horizontal position adjustment is controlled by r1(1). no_switch the no_switch bit determines if the system clock is permanently set to the primary vco (pvco) or allowed to switch between pvco and the secondary vco (svco). this bit is set to 1 (no clock switching) at power up reset. after the system has been switched to fast (12 mhz) clock both signals feeding into this switch must be pvco before the switch setting is changed. otherwise a short system clock can result which causes the processor to run at a higher frequency than speci?ed. the instruction fetched from memory, at the location with the out-of-spec frequency, can be corrupted! to ensure safe clocks, the following practices are recommended: 1. set the no_switch to the required setting before switching from the 32.768 khz to the fast (12 mhz) clock and leave it there permanently. 2. use the following procedure when changing from switching vco to permanent pvco while running from the fast clock: - simultaneously set the h_position delay to 0x0, while leaving the no_switch enabled (0), and the svco/pvco left as (0). - wait a minimum of 80 clock cycles to ?ush any h sync out of the system. - simultaneously switch svco/pvco to pvco (write 1 into r6(1)<5>), while leaving the no_switch enabled (0), and the h_position delay at 0x0. - wait 3 system clock cycles to be sure that the clock has had time to switch to pvco. - switch no_switch to no clock switch (write 1 into r6(1)<6>). the h_position can be set to none-zero at this time as well. 3. use the following procedure when changing from permanent pvco to switching vco while running from the fast clock. - simultaneously set the h_position delay to 0x0, while leaving the no_switch disabled (1), and the svco/pvco setting as dont care (0). caution:
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 65 - wait a minimum of 80 clock cycles to ?ush residual h-sync out of the system. - simultaneously switch svco/pvco to pvco (write 1 into r6(1)<5>), while leaving the no_switch disabled (1), and the h_position delay at 0x0. - wait 3 system clock cycles to be sure that the clock has had time to switch to pvco. - switch no_switch to clock switching is enabled (write 0 into r6(1)<6>). the h_position can be set to none-zero at this time as well. svco/pvco the svco/pvco bit when read back determines the current setting of the system clock. writing a 1 to this bit switches the system clock from its current setting to pvco. this switch has a glitch ?lter that removes random voltage spikes. it must be changed back to pvco. the z90t366 switches to the svco automatically when it receives an h-sync interrupt. this mechanism exists to synchronize the system clock exactly with the h-sync trailing edge. the result is a sharp start of the osd, jitter free. an example of a typical svco/pvco switching follows: 1. system clock is set to pvco. 2. h-sync interrupt occurs. (the system clock has automatically been set to the svco). osd code is executed inside of the h-sync interrupt service routine (isr). 3. before leaving the isr, the user switches the clock back to pvco. the clamp pulse (de?ned in r0(1)) is generated only if the svco/pvco switch is set to pvco before receiving an h sync . the software provides the correct switch setting before every h sync . table 33 lists the interrupt/wdt for the wst/smr control register.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 66 the ?nal result of the stop-mode recovery (smr) is reset. ports selected for smr must be assigned as inputs, while the other smr ports must be assigned as outputs exhibiting an inactive value. if any smr source is active, and the stop mode is executed, the part resets immediately. table 33 register7, bank 1, interrupts/wdt/smr control register bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx bit 76543210 r/w r r/w r/w r/w r/w r/w r/w r/w reset 0 xxxxxxx note: r = read w = write x = indeterminate reg field bit position r w data description int_priority fed------------- r w x see table 34. int_mask ---cba---------- r w 1xx 0xx x1x x0x xx1 xx0 int2 is enabled int2 is disabled int1 is enabled int1 is disabled int0 is enabled int0 is disabled wdtspeed ------98-------- rw 00 01 10 11 1.83 ms 7.68 ms 31.12 ms 124.8 ms smr?ag --------7------- r0 1 no stop-mode recoveryCpor stop-mode recovery smr polarity ---------6------ rw 0 1 or of all smr sources nand of all smr sources smrsource smr5 smr4 smr3 smr2 smr1 smr0 ----------543210 ----------5----- -----------4---- ------------3--- -------------2-- --------------1- ---------------0 r w xx bit which corresponds to a 1 in xx binary representation is active p09 p14 p13 p12 p11 p10
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 67 all core interrupts are set to interrupt0 >interrupt1 > interrupt2. these priorities cannot be changed and are embedded into the core. however, z90t366 architecture provides ?exibility to change the priority of the interrupts by switching the interrupt sources between interrupt inputs of the z90t366 core. the correspondence between h sync , v sync and 1s/cap interrupts sources, and int0, int1, and int2 interrupts inputs of the z90t366 are listed in table 34. 3.4 bank2 (pwm registers) table 35 lists the bits for the pwm registers. table 34 interrupt priority int_priority field h sync is switched to: v sync is switched to: 1s/cap is switched to: 0 0 0 int0 int1 int2 0 0 1 int0 int2 int1 0 1 0 int1 int0 int2 0 1 1 int2 int0 int1 1 0 0 int1 int2 int0 1 0 1 int2 int1 int0 table 35 register0Cregister5, bank 2, pwm 1C6 registers bit 15 14 1312 11 10 9 8 r/w reserved reserved reserved reserved reserved reserved reserved reserved reset 00000000 bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position r w data description reserved fedcba98-------- reserved pwm_data --------76543210 r w xx 8-bit pwm data
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 68 all of the pwms feature push-pull. outputs from all pwms are staged by one pvco clock. the repetition frequency of the pwm output signals can be calculated from the following equation: when reset, pwm_data registers are not initialized; however, pwm output is set to 0 . because the pwm is clocked with pvco, it is better to initialize the pwm_data before enabling pvco. table 36 lists the bits for the shadow control register. table 37 lists the bits for the cgrom offset register. table 36 register6, bank 2, shadow control register bit 15 14 1312 11 10 9 8 r/w reserved reserved r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 r/w reserved reserved reserved reserved reserved reserved reserved reserved reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position r w data description reserved fe-------------- reserved lshadow-color --dcb----------- r w xx left shadow color-por = 0 rshadow-color -----a98-------- r w xx right shadow color-por = 0 reserved --------76543210 reserved f pwm f pvco 8 256 - - - - - - - - - - - 12mhz 2048 - - - - - - - - - - 6khz ===
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 69 3.5 bank3 (on screen display [osd] registers) table 38 lists the r0(3)- r2(3) character multiplier registers (read operation). table 39 lists the r0(3)Cr1(3) shift registers (write operation). table 40 lists the r2(3) attributes register (write operation). table 37 register7, bank 2, cgrom offset register bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 note: r = read w = write x = indeterminate reg field bit position r w data description cgoffset fedcba9876543210 r w xxxx cgrom offset, por=0
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 70 table 38 register0Cregister2, bank 3, read operation, character multiple registers bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg name cgrom data reg add description cgrom_x2_hi cgrom_x3_hi ffeeddccbbaa9988 fffeeedddcccbbba r0(3) high word of double size character r4(3)<6> = 0 high word of triple size character r4(3)<6> = 1 cgrom_x2_lo cgrom_x3_mid 7766554433221100 aa99988877766655 r1(3) low word of double size character r4(3)<6> = 0 middle word of triple size character r4(3)<6> = 1 cgrom_x1 cgrom_x3_lo fedcba9876543210 5444333222111000 r2(3) single size character r4(3)<6> = 0 low word of triple size character r4(3)<6> = 1 table 39 register0Cregister1, bank 3, write operation, shift registers bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg name cgrom data reg address description current_reg fedcba9876543210 r0(3) current line shift register next/previous_reg fedcba9876543210 r1(3) next/previous line shift register
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 71 registers r1(3) and r0(3) must be loaded with video data one time every 16 cycles. to support smoothing, register r1(3) must be updated every 16 cycles. the current line register is loaded ?rst, followed by next/previous register during the next cycle. the next/previous register is loaded only if smoothing/fringing attributes are activated for the current character. if neither register is loaded, the space character is displayed. there is no difference between loading 0000h into either register or not loading at all. table 40 register2, bank 3, attributes register, write operation bit 15 14 1312 11 10 9 8 r/w reserved r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position data description reserved f--------------- reserved background color -edc------------ 000 001 010 011 100 101 110 111 black blue green cyan red magenta yellow white foreground color not palette mode ----ba9--------- same as background mode palette selection palette mode ----ba---------- 00 01 10 11 palette0 palette1 palette2 palette3 2nd_underline palette mode ------9--------- 1 0 second underline is active second underline is not active 1st_underline -------8-------- 1 0 first underline is active first underline is not active
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 72 if both the background and foreground colors of a character are set to be the same, the characters background is displayed as transparent. the attributes register must be loaded 8 cycles after the current line register r0(3) is loaded. loading the attributes register enables the osd logic during the next 16 cycles. if the attributes register is not loaded, there is no active osd, even if the current line register r0(3) is loaded. see table 41. shift_video --------7------- 1 0 video signal is delayed by 8 pixels standard character positioning semi-transparent ---------6------ 1 0 semi-transparent background background color de?ned by background color ?eld blinking ----------5----- 1 0 blinking character not blinking character italic -----------4---- 1 0 italic character not italic character color_delay ------------32-- 00 01 10 11 character color changes instantly color changes with 4 pixels delay color changes with 8 pixels delay color changes with 12 pixels delay shadowing --------------10 00 01 10 11 no shadowing left shadow right shadow both shadows reg field bit position data description note:
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 73 the data read from the attribute register is a combination of attribute ?elds from the most recently displayed character and control character codes loaded into the attribute_data register. character codes are fetched from video ram and must be loaded into the attribute_data register r3(3). bit of the attribute_data register (during a read) indicates whether the most recent character was a control or displayed character. the data read from the attribute_data register must be directly loaded into attribute register r2(3). refer to table 42. loading vram data into an attribute_data register initializes a cgrom access cycle. four clock cycles after the ld instruction, the z90t366 halts for three clock cycles to fetch the data from cgrom and latch it into a cgrom data capture register. after the cgrom data is latched, core operations are resumed. when a control character code is loaded into the attribute_data register, the cgrom data from address 0000 hex is fetched. therefore, zilog recommends placing a table 41 register3, bank 3, read operation, attributes register bit 15 14 1312 11 10 9 8 r/w reserved r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position data description same as r2(3) read operation table 42 register3, bank 3, write operation, attribute data register bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position data description vram_data fedcba9876543210 xxxx character code fetched from vram
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 74 space character at location 0000 hex in cgrom. refer to table 43 through table 46 for the various vram data formats loaded in r3(3). table 43 register 3, bank 3, display character format for attribute data register, osd mode write operation bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position data description control bit f--------------- 0 display character background color* -edc------------ 000 001 010 011 100 101 110 111 black blue green cyan red magenta yellow white foreground color (not palette mode) ------ba9------- d same as background_color foreground palette (palette mode) --------ba------ 00 01 10 11 palette 0 (de?ned in r6(3)<8C6> palette 1 (de?ned in r6(3) palette 2 (de?ned in r6(3)<5C3> palette 3 (de?ned in r6(3)<2C0> second underline (palette mode) -------9--------- 1 0 second underline attribute is active second underline attribute is inactive attribute8 -------8-------- 1 0 selected attribute (r7(3),<76>) is active selected attribute (r7(3),<76>) is inactive character code --------76543210 d de?nes the character in cgrom note: *if both the background and foreground colors of a character are set to be the same, the character? background is displayed as transparent.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 75 smoothing is supported for double size (x2) and triple size (x3) characters only. at reset, the background color in osd mode is black. foreground color, background color, blinking and italic attributes are delayed by 3/4 character. the smoothing attribute is enabled. table 44 register 3, bank 3, control character format for attribute data register, osd mode write operation bit 15 14 1312 11 10 9 8 r/w r/w reserved reserved reserved reserved reserved reserved reserved reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxx1 note: r = read w = write x = indeterminate reg field bit position data description control bit f--------------- 1 control character reserved -edcba98-------- reserved shift_video --------7------- 1 0 video signal is delayed by 8 pixels standard character positioning transparent ---------6------ 1 0 transparent background background color de?ned by background color ?eld blinking ----------5----- 1 0 blinking character not blinking character italic -----------4---- 1 0 italic character not italic character color_delay ------------32-- 00 01 10 11 character color changes instantly color changes with 4 pixels delay color changes with 8 pixels delay color changes with 12 pixels delay shadowing --------------10 00 01 10 11 no shadowing left shadow right shadow both shadows
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 76 table 45 register 3, bank 3, display character format for attribute data register, write operation ccd mode bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position data description control bit 7------- 0 display character character code -6543210 de?nes the character in cgrom. table 46 register 3, bank 3, control character format for attribute data register, ccd mode, write operation bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position data description control bit 7------- 1 control character transparent -6------ 1 0 transparent background background color de?ned by background color ?eld blinking --5----- 1 0 blinking character not blinking character italic ---4---- 1 0 italic character not italic character
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 77 in ccd mode, each character occupies 8 bits (one byte) in vram. the ccd characters must be mapped into a 16-bit vram data ?eld. the hardware supports compressed character placement in vram. each word in vram is represented by high byte and low byte. a currently active byte is selected by r4(3). the format and data representation for both bytes is the same. there are two possible character formats de?ned: a display character and a control character. the code stored in display character format de?nes a character code. the control character de?nes up to seven attributes of the next character and is presented on screen as a space character. combining display and control characters generates of a ccd osd according to fcc speci?cation. refer to table 47. foreground color ----321- 000 001 010 011 100 101 110 111 black blue green cyan red magenta yellow white first underline -------0 1 0 underline attribute is active underline attribute is inactive table 47 register4, bank 3, osd control register bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position r w data description underline fe-------------- rw 1x 0x x1 x0 second underline is active second underline is inactive first underline is active first underline is inactive reg field bit position data description
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 78 the underline ?eld must be set by ?rmware when scan lines that contain underline information are displayed. the underline bits are anded with the second and ?rst underline active ?elds of data loaded into attribute register r2(3), causing the screen character to be underlined. the italic shift ?eld de?nes a delay of video data. it is used to generate italic characters. the ?rmware decrements by 1 (the value of the italic_shift ?eld) for each consecutive line. the video signal is delayed only for characters that have the r2(3)<4> (italic) bit set to 1 . table 48 lists the bits for the capture register. osd/ccd --d------------- rw 1 0 osd mode ccd mode ccd_top/btm ---c------------ rw 1 0 the upper byte in vram is used the lower byte in vram is used italic_shift ----ba98-------- r w x de?nes delay of the character blink_off/on --------7------- rw 0 1 blinking character is displayed blinking character is not displayed (hidden) mpx_bus ----------65---- rw 00 01 10 11 x1 character size x2 character size x3 character size reserved cgrom scan_line -----------43210 r w de?nes cgrom addressing table 48 register5, bank 3, capture register, read operation bit 15 14 1312 11 10 9 8 r/w rrrrrrrr reset xxxxxxxx bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r reset xxxxxxxx note: r = read w = write x = indeterminate reg field bit position r w data description
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 79 in read mode, r5(3) returns the 16-bit captured data from the irin pin. in write mode, the 7-bit i 2 c slave interface address must be put in bit 7-1. table 49 lists the bits for the palette control register. at por the palette control register is reset to 0 . table 50 lists the bits for the output palette control register. reg field bit position r w data description cap_data fedcba9876543210 r 16-bit captured data i2c_saddr --------7654321- wi 2 c slave interface address table 49 register6, bank 3, palette control register bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 note: r = read w = write x = indeterminate reg field bit position r w data description palette f--------------- rw 1 0 palette mode is active palette mode is inactive underline color -edc------------ r w 000 001 010 011 100 101 110 111 black blue green cyan red magenta yellow white palette1 ----ba9--------- r w same as underline color palette0 -------876------ r w same as underline color palette3 ----------543--- r w same as underline color palette2 -------------210 r w same as underline color
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 80 at por the output palette register is set to 0 for digital output. table 15 is the look-up table for the color palettes. table 50 register7, bank 3, output palette control register bit 15 14 1312 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 note: r = read w = write x = indeterminate reg field bit position r w data description blank_delay fedc------------ r w d vblank and svblank delay value%00Cpor condition background_on/off ----b----------- rw 1 0 master background is on master background is offCpor condition background_color -----a98-------- r w d de?nes the color of the master background (same as the palette) attrselect --------76------ rw 00 01 10 11 1st underlinepor semi-transparency blinking cgrom bank select smoothing ----------5----- rw 0 1 smoothing logic disabledpor smoothing logic enabled cursor write enable -----------4---- r w0 1 return 0 cursor parameters write disabledpor cursor parameters write enabled palette # ------------3210 r w palette number
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 81 4 instruction set the processor instruction set consists of 30 basic instructions. it has been optimized for high code density and reduced execution time. single-cycle instruction execution is possible on most instructions. the format for op codes and addressing modes is provided in the following tables but is normally not required. the assembler removes the burden of hand constructing the instruction format. by translating the mnemonics. system designers can access the instruction format when debugging. 4.1 instruction summary the dsp instruction set can be broken down into the following types of instructions: accumulator modi?cation arithmetic bit manipulation load logical program control rotate and shift instruction format mnemonics are in table 51. table 52 through table 58 list other instructions. table 51 instruction format mnemonics mnemonic description a address am accumulator modi?cation b ram bank cc condition code const exp constant expression d destination address dest destination value fm flag modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 82 op op code rp register pointer s source address src source value table 52 accumulator modi?cation instructions mnemonic operands instruction abs , a absolute value cp a, comparison dec , a decrement inc , a increment neg , a negate table 53 arithmetic instructions mnemonic operands instruction add a, add cp a, compare sub a, subtract table 54 bit manipulation instructions mnemonic operands instruction ccf none clear carry flag cief none clear interrupt enable flag copf none clear over?ow protection flag scf none set carry flag table 51 instruction format mnemonics (continued) mnemonic description
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 83 sief none set interrupt enable flag sopf none set over?ow protection flag table 55 load instructions mnemonic operands instruction ld , load pop pop push push table 56 logical instructions mnemonic operands instruction and a, logical and or a, logical or xor a, logical exclusive or table 57 program control instructions mnemonic operands instruction call a call procedure jp a jump ret none return table 58 rotate and shift instructions mnemonic operands instruction rl , a rotate left table 54 bit manipulation instructions mnemonic operands instruction
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 84 4.2 instruction operands to access the operands for the dsp, use the register pointers, data pointers, hardware registers, direct addressing, immediate data and memory. there are nine distinct types of instruction operands. table 59 and table 60 describe these instructions. rr , a rotate right sll , a shift left logical sra , a shift right arithmetic table 59 instruction operand summary symbolic name syntax description pn:b register pointer dn:b data pointer x, y, pc, sr, extn, a, bus hardware registers @a accumulator indirect direct address expression # long (16-bit) immediate # short (8-bit) immediate value @pn:b @pn:b+ @pn:b+loop @pn:b-loop indirect addressing of ram @dn:b @dn:b @@pn:b @@pn:b+ @@pn:b+loop @@pn:b-loop indirect addressing of rom table 58 rotate and shift instructions mnemonic operands instruction
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 85 the register pointer mode is used for loading the pointer with the appropriate ram address. this address references the ram location that stores the requested data. the pointer can also be used to store 8-bit data when used as a temporary register. the pointers are connected to the lower 8 bits of the d-bus. instruction 1 loads pointer 2, ram bank0 with the value f2h . the register indirect mode is used for indirect access to ram. as noted in instruction 2, the register indirect address method is used to get the operand to multiply it with the accumulator. the data-pointer mode is used as an indirect addressing method similar to @p2:0 . the data pointers access the lower 16 bits of each ram bank. instruction 7 uses indirect addressing to push information onto the stack. pointer or data registers can be used to access program memory. both are commonly used to reference program memory. instructions 5 and 6 display this addressing method. either pointer is automatically incremented to assist in transferring sequential data. another method of indirect addressing is using the accumulator to store the address. instruction 2 describes how to use this method. the absolute ram address is used in the direct mode. a range between 0 and 511 (000h to 1ffh) is allowed. the accumulator is used in conjunction with this method as a source or destination operand. instruction 7 displays the accumulator as the destination. this instruction indicates a long immediate load. a 16-bit word can be copied directly from the operand into the speci?ed register or memory. instruction 3 uses this method. this instruction can only be used for immediate transfer of 8-bit data in the operand to the speci?ed ram pointer. table 60 instruction mnemonics/operands # instruction mnemonic/operand representation 1 ld p2:0, #%f2 ld , 2 ld a, @p2:0 ld , 3 ld x, @a ld , 4 ld y, #%3cf5 ld , 5 sub a, @@p2:0 sub a, 6 or a, @d2:0 or a, 7 add a, %f2 add a, 8 push d1:1 push
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 86 4.3 instruction format the instruction format that speci?es to the processor the action to be taken consists of the op code, destination, source, and other special bits. the assembler makes this operation transparent by providing mnemonics. occasionally, the instruction format and development code can assist in debugging. examples to clarify the various instruction formats and explain how speci?c bit patterns are developed and evaluated are provided below. most instructions require one 16-bit word containing the information necessary for the processor to execute the instruction correctly. this process requires one clock cycle for execution. immediate addressing, immediate operands, jump and call instructions require two 16-bit words (two clock cycles). each instruction type has a unique op code and format to differentiate various instructions. different operations also have unique formats. the variables a, op, b, d, s, cc, am, fm, rp are used in the instruction format to depict bits determined by the active instruction. addition and inc formats the op code and format for an instruction differ to allow the processor to differentiate between the instructions. for example, the addition instruction requires that two operands be de?ned in the instruction. add a, the inc (increment) instruction requires that a condition and modi?cation code be speci?ed. inc a 1514131211109876543210 100000110000 ssss op code ram bank condition code modi?cation code 1514131211109876543210 1001000001001010 op code condition code modi?cation code
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 87 inc and sll formats the inc and sll instructions have the same op code with an accumulator modi?cation format. the least signi?cant four bits, the modi?cation code, determine the type of operation the accumulator performs. inc a sll a 4.4 instruction bit codes the values in a series of bits in a register form patterns called bit codes . types of bit codes include the following: condition codes accumulator modi?cation code flag modi?cation codes source/destination field designators register pointer/data pointer the following tables list the options available and their corresponding instructions. condition codes table 61 lists the condition codes that are used in accumulator modi?cation, call , and jump instructions. 1514131211109876543210 1001000000000100 op code condition code modi?cation code 1514131211109876543210 1001000000000011 op code condition code modi?cation code table 61 condition code bits bit code mnemonic code value condition code value condition code 00000 f false
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 88 accumulator modi?cation codes accumulator modi?cation codes determine the type of modi?cation made to the value in the accumulator. see table 62. condition codes are also used with call, and jump instructions. 00001 unused 00010 nu0 ui0 is set to 0 not user zero 00011 nu1 ui1 is set to 0 not user one 00100 nc c is set to 0 no carry 00101 nz z is set to 0 not zero (not equal) 00110 nov ov is set to 0 no over?ow 00111 pl n is set to 0 plus (not negative) 01xxx unused 10000 ttrue 10001 unused 10010 u0 ui0 is set to 1 user zero 10011 u1 ui1 is set to 1 user one 10100 c c is set to 1 carry 10101 z z is set to 1 zero (equal) 10110 ov ov is set to 1 over?ow 10111 mi n is set to 1 minus (negative) 11xxx unused table 62 accumulator modi?cation bits bit code mnemonic operation 0000 rr rotate right 0001 rl rotate left table 61 condition code bits (continued) bit code mnemonic code value condition code value condition code
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 89 flag modi?cation codes flag modi?cations initialize or set/reset bits to accommodate interrupts, over?ows, and carrys. see table 63. source/destination field designators register pointers and data pointers provide convenient access to data. the pointers are a source or destination ?eld in instructions. speci?c bit codes are listed in table 64. the register pointer offers optional incrementing or decrementing. this option is speci?ed by the following instruction: ld a, @p2:1+ 0010 sr shift right 0011 sl shift left 0100 inc increment 0101 dec decrement 0110 neg negate 0111 abs absolute table 63 flag modi?cation bits bit code mnemonic operation flag value xx10 ccf clear carry c 0 xx11 scf set carry c 1 x1x0 cief clear interrupt enable ie 0 x1x1 sief set interrupt enable ie 1 1xx0 copf clear over?ow protection op 0 1xx1 sopf set over?ow protection op 1 table 62 accumulator modi?cation bits bit code mnemonic operation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 90 data pointers are automatically incremented when accessing program memory (for example, ld a, @d0:0 ) and do not require an incrementing option. code in xx11 format is designated for a data pointer when source or destination format is used. additional source or destination designators include the other hardware registers provided by the processor. to determine if a data pointer, register pointer or a register is used as a source or destination is discussed in the next section. table 65 lists the bit code for mnemonic register names. table 64 register pointer/ data pointer bits bit code mnemonic 00xx nop 01xx +1 10xx -1/loop 11xx +1/loop xx00 p0:0 or p0:1 xx01 p1:0 or p1:1 xx10 p2:0 or p2:1 0011 d0:0 or d0:1 0111 d1:0 or d1:1 1011 d2:0 or d2:1 1111 d3:0 or d3:1 table 65 register bits bit code mnemonic 0000 bus 0001 x 0010 y 0011 a 0100 sr
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 91 4.5 instruction format examples refer to the following examples indicating how bit codes are used in an instruction format. instruction format accumulator modi?cation format 0101 stack 0110 pc 0111 reserved 1000 ext0 1001 exti 1010 ext2 1011 ext3 1100 ext4 1101 ext5 1110 ext6 1111 ext7 1514131211109 8 76543210 opopopopopopopb dddd ssss op code ram bank destination source 1514131211109876543210 op op op op op op op cc cc cc cc cc am am am am op code condition code acc modi?cation table 65 register bits (continued) bit code mnemonic
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 92 notes: 1. the variables a, op, b, d, s, cc, am, fm, rp are used in the instruction format to depict bits determined by the instruction. 2. the general instruction format requires an op code, ram bank bit, destination and source addresses. for example, ld a, @p2:1+ load instruction format the op code ( 0000001 ) provides a unique signature for the ld command. the processor uses this signature to determine the instruction format. the ram bank bit is high (equal to 1) because of the instruction de?nition b=1 (pn:b) . the destination bit code is 0011 which corresponds to the accumulator. the source 0110 corresponds to the +1 option and p2:0 or p2:1 . the ram bank bit indicates that the processor loaded the accumulator with the operand designated by pointer 2 bank1 ( p2:1 ). source and destination ?elds can be accessed from the register pointers, data pointers, or registers. the op code speci?es the type of source and destination. an op code of 0000101 speci?es that the source is an indirect address to program memory ( @@p0.0 or @d0:0 ) and the destination is a register. instruction format listing instruction formats and applicable instructions are listed in table 66 through table 72. notes: 1. several instructions provide various addressing modes to obtain operands; therefore, the same instruction can have several different formats depending on the addressing mode. 2. the variables a, op, b, d, s, ce, am, fm, rp are used in the instruction format to depict bits determined by the speci?c instruction used. 1514131211109 8 76543210 0000001 1 00110110 op code ram bank destination source
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 93 general instruction format accumulator modi?cation format 1514131211109 8 76543210 opopopopopopop b dddd ssss op code ram bank destination source table 66 general instruction format mnemonic operands bit code hex add a, @p0:0 1000001 0 0000 0000 8200 and a, d1:1 1100110 1 0000 0111 ab07 cp a,x 0110000 0 0000 0001 6001 ld a,p 0000000 0 0011 0111 0037 pop x 0000000 0 0001 0101 0015 push d0:0 0000001 0 0101 0011 0253 ret 0000000 0 0110 0101 0065 sub a,@d1:1 0010101 1 0000 0111 2b07 xor a,p2:0 1111001 0 0000 0010 f202 1514131211109876543210 op op op op op op op cc cc cc cc cc am am am am op code condition code acc modi?cation table 67 accumulator modi?cation format mnemonic operands bit code hex representation abs z, a 1001000 10101 0111 9157 dec a 1001000 00000 0101 9005
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 94 flag modi?cation format direct internal addressing format inc nz, a 1001000 00101 0100 9054 neg a 1001000 00000 0110 9006 rr nu0, a 1001000 00010 0000 9020 rl pl, a 1001000 00111 0001 9071 sll c, a 1001000 10100 0011 9143 sra u1, a 1001000 10011 0010 9132 1514131211109876543210 op op op op op op op cc cc cc cc cc fm fm fm fm op code condition code flag modi?cation table 68 flag modi?cation format mnemonic bit code hex representation ccf 1001010 00000 0010 9402 cief 1001010 00000 0100 9404 copf 1001010 00000 1000 9408 scf 1001010 00000 0011 9403 sief 1001010 00000 0101 9405 sopf 1001010 00000 1001 9409 1514131211109876543210 op op op op op op op aaaaaaaaa op code 9-bit internal address table 67 accumulator modi?cation format mnemonic operands bit code hex representation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 95 short immediate addressing format long immediate addressing format table 69 direct internal addressing format mnemonic operands bit code hex representation add a, %ff 1000011 011111111 86ff and a, 255 1010011 011111111 a6ff cp a, 255 0110011 011111111 66ff ld 0000111 000010010 0e12 1514131211109876543210 op op op op op rp rp rp aaaaaaaa op code register pointer 8-bit immediate address/data table 70 short immediate addressing format mnemonic operands bit code hex representation ld p1:1, #%fa 00011 101 11111010 1dfa 1514131211109 8 76543210 opopopopopopop b dddd ssss op code ram bank destination source 1514131211109 8 76543210 aaaaaaa a aaaaaaaa 16-bit address/data
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 96 jump and call instruction formats table 71 long immediate addressing format mnemonic operands hex representation add a, #%1234 8800 1234 and a, #% 26a4 a800 26a4 ld x, #%6ffc 0810 6ffc push #%c32c 0850 c32c sub a, #%2444 2800 2444 xor a,#%afc2 e800 afc2 1514131211109876543210 1000110cccccccccc ssss op code condition code not used 1514131211109876543210 aaaaaaaaaaaaaaaa 16-bit address table 72 jump and call instruction formats mnemonic operands hex representation call end 4800 0004 jp u1, end 4d30 0004
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 97 4.6 instruction timing the dsp can be executed with single cycle instructions using independent data memory and program memory buses in the system architecture and pipeline instructions. this method allows the instruction fetch and execution cycles to overlap. figure 27 illustrates the execution sequence. the ?rst instruction takes two clock cycles to execute; subsequent executions occur in a single cycle. all instruction fetch cycles have the same machine timing regardless of whether external or internal memory is used. because the dsp contains a two-level pipeline, the jump and call instructions do not disrupt the execution process. in two-word instructions, the second word is fetched while the ?rst word is executing. because the processor knows that the instruction is a jump or call , the second word is transferred to the program counter and the correct address is fetched into the pipeline. there is no disruption or pipeline ?ushing. the pipeline ?ow is affected when the program counter is the destination for a load. because the load ( ld ) instruction is a single word instruction, the next instruction is fetched during load execution. to compensate for the instruction in the pipeline, that instruction is executed as a nop . figure 27 pipeline execution fetch the second instruction execute the first instruction execute the second instruction fetch the first instruction
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 98 4.7 instruction op codes table 73 summarizes essential information about the instruction set. table 73 instruction op codes inst description op code synopsis operands words cycles examples abs absolute value 1001000 abs[,] ,a 1 1 abs nc, a 1001000 a 1 1 abs a add addition 1001001 add, a, 1 1 add a, p0:0 1000001 a, 1 1 add a, d0:0 1000100 a, 2 2 add a, #%1234 1000101 a, 1 3 add a, @@p0:0 1000011 a, 1 1 add a, %f2 1000001 a 1 1 add a, @p1:1 1000000 a, 1 1 add a, x and bitwise and 1011001 and , a, 1 1 and a, p2:0 1010001 a, 1 1 and a, d0:1 1010100 a, 2 2 and a, #%1234 1010101 a, 1 3 and a, @@p1:0 1010001 a, 1 1 and a, %2c 1010001 a, 1 1 and a, @p1:2+loop 1010000 a, 1 1 and a, ext3 call subroutine call 0010100 call ,
, 2 2 call sub1 0010100 2 2 call z, sub2 ccf clear carry flag 1001010 ccf none 1 1 ccf cief clear carry flag 1001010 cief none 1 1 cief copf clear op flag 1001010 copf none 1 1 copf
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 99 cp comparison cp, 0111001 a, 1 1 cp a, p0:0 0110001 a, 1 1 cp a, d3:1 0110101 a, 1 3 cp a, @@p0:0 0110011 a, 1 1 cp a, %ff 0110001 a, 1 1 cp a, @p2:1+ 0110000 a, 1 1 cp a, stack 0110100 a, 2 2 cp a, #%ffcf dec decrement 1001000 dec [,] , a 1 1 dec nz, a 1001000 a 1 1 dec a inc increment 1001000 inc [,] , a 1 1 inc pl, a 1001000 a 1 1 inc a jp jump 0100110 jp [,]
, 2 2 jp nie, label 0100110 2 2 jp label table 73 instruction op codes (continued) inst description op code synopsis operands words cycles examples
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 100 ld load destination with source 0000000 ld , a, 1 1 ld a, x 0000001 a, 1 1 ld a, d0:0 0001001 a, 1 1 ld a, p0:1 0000001 a, 1 1 ld a, @p1:1 0000101 a, 1 3 ld a, @d0:0 0000011 a, 1 1 ld a, 124 0000111 , a 1 1 ld 124, a 0000100 , 1 1 ld d0:0, ext7 0001100 , 1 1 ld p1:1, #%fa 0001010 , 1 1 ld p1:1, ext1 0000110 , 1 1 ld @p1:1, #%1234 0000010 , 1 1 ld @pm+, x 0001001 , 1 1 ld y, p0:0 0000001 , 1 1 ld sr, d0:0 0000100 , 2 2 ld pc, #%1234 0100101 , 1 3 ld x, @a 0000101 , 1 3 ld y, d0:0 0000001 , 1 1 ld a, @p0:0-loop 0000000 , 1 1 ld x, ext6 when is , cannot be p. when is and is , cannot be extn if is extn, cannot be x if is x, cannot be sr if is sr. when is cannot be a. table 73 instruction op codes (continued) inst description op code synopsis operands words cycles examples
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 101 neg negate 1001000 neg , a , a 1 1 neg nz,a 1001000 a 1 1 neg a nop no operation 0000000 nop none 1 1 nop or bitwise or 1101001 or , a, 1 1 or a, p0:1 1100001 a, 1 1 or a, d0:1 1100100 a, 2 2 or a,#%202 1100101 a, 1 3 or a, @@p2:1+ 1100011 a, 1 1 or a, %2c 1100001 a, 1 1 or a, @p1:0-loop 1100000 a, 1 1 or a, ext6 pop pop a value from the stack 0001010 pop 1 1 pop p0:0 0000100 1 1 pop d0:1 0000010 1 1 pop @p0:0 0000000 a 1 1 pop a push push a value onto the stack 0001001 push , 1 1 push p0:0 0000001 1 1 push d0:1 0000001 1 1 push @p0:0 0000000 1 1 push bu.s 0000100 2 2 push #%2345 0100101 1 3 push @a 0000101 1 3 push @@p0:0 ret return from subroutine 0000000 ret none 1 2 ret rl rotate left 1001000 rl , a , a 1 1 rl nz, a 1001000 a 1 1 rl a rr rotate right 1001000 rr , a , a 1 1 rr c, a 1001000 a 1 1 rr a scf set c flag 1001010 scf none 1 1 scf sief set ie flag 1001010 sief none 1 1 sief table 73 instruction op codes (continued) inst description op code synopsis operands words cycles examples
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 102 sll shift left logical 1001000 sll [,] a 1 1 sll nz, a 1001000 a 1 1 sll a sopf set op flag 1001010 sopf none 1 1 sopf sra shift right 1001000 sra , a , a 1 1 sra nz, a arithmetic 1001000 a 1 1 sra a sub subtract 0011001 sub , a, 1 1 sub a, p1:1 0010011 a, 1 1 sub a, d0:1 0010100 a, 2 2 sub a, #%2c2c 0010101 a, 1 3 sub a, @d0:1 0010011 a, 1 1 sub a, %15 0010001 a, 1 1 sub a, @p2:0-loop 0010000 a, 1 1 sub a, stack xor bitwise exclusive or xor , 1111001 a, 1 1 xor a, p2:0 1110001 a, 1 1 xor a, d0:1 1110100 a, 2 2 xor a, #%3933 1110001 a, 1 3 xor a, @p2:1+ 1110011 a, 1 1 xor a, %2f 1110001 a, 1 1 xor a, @p2:0 1110000 a, 1 1 xor a, bus table 73 instruction op codes (continued) inst description op code synopsis operands words cycles examples
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 103 instruction descriptions the dsp instruction set consists of 30 basic instructions, optimized for high-code density and reduced execution time. single-cycle instruction execution is possible because of the z90t366 pipeline and system architecture. table 74 contains a description for each instruction. each assembly instruction includes an example for each addressing mode available for the speci?c instruction. the mnemonics listed in table 75 are used in the instruction format. table 74 instruction descriptions mnemonic mnemonic expansion instruction operands lists the types of addressing methods for a speci?c instruction ( abs a or abs , a ). instruction format displays instruction format for register indirect addressing. operation displays operation sequence. affected flags lists ?ags affected by operation. description describes the instruction operation. examples a simple example displays the instruction operation and how registers are affected. the example includes initialization, instruction and result. it also includes the number of cycles and instruction length. table 75 instruction format mnemonics mnemonic description mnemonic description a address dest destination value am accumulator modi?cation fm flag modi?cation b ram bank op op code cc condition code rp register pointer const exp constant expression s source address d destination address src source value
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 104 abs absolute value abs instruction word syntax abs , a abs a operation if acc < 0 then -(acc) -> acc flags: n : set if the accumulator has 800000h (see below). description if the contents of the accumulator are determined to be less then 0 (a negative number), the absolute value of the accumulator is calculated (accumulator replaced by its two's complement value). using the condition code provides an additional method to evaluate a status ?ag before the absolute value of the accumulator is calculated. if the accumulator contains 800000h , the abs a instruction stores the value of the two's complement at address 800000h and sets the over?ow and negative status bits. there is no over?ow protection. example 1 abs a initialization: accumulator contains ffeb00h sr contains 0000h instruction: abs a result: accumulator contains 001500h sr contains 1000h 1514131211109876543210 1001000cccccccccc0111 op code condition code acc modi?cation note:
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 105 this example uses one word of memory and executes in one machine cycle. because the value in the accumulator is less than zero, the two's complement is performed and the result is placed in the accumulator abs(ffebh)=001500h . the carry bit is set. example 2 abs , a initialization: accumulator contains 456400h instruction: abs mi, a result: accumulator contains 456400h this example uses one word of memory and executes in one machine cycle. the condition code (negative bit) is not set because the accumulator value is positive; therefore, the instruction is not executed. = 456400h abs mi, a = 456400h example: = c56400h abs mi, a = 3ac900h
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 106 add addition add instruction word syntax add a, add a, add a, add a, add a, add a, add a, operation acc + -> acc flags: c set if carry from the most signi?cant bit is found. n : set if result in the accumulator is negative. z : set if result is 0. ov : set if addition exceeds upper ( fffffh ) or lower ( 800000h ) limit of the accumulator. description the addressed data memory operand is added to the accumulator. the result is loaded into the accumulator. the lower eight bits of the accumulator are unchanged while the add instruction is executed. 1514131211109 8 76543210 1000001 b 0000 ssss op code ram bank destination source note:
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 107 example 1 add a, initialization: accumulator contains 123456h p0:0 contains 4dh ram bank1: 4dh contains 8746h instruction: a dd a, @p0:0 result: a contains 997a56h @p0:0 contains 746h this example uses one word of memory and executes in one machine cycle. the pointer p0:0 contains the ram register location ( 4dh ). the contents of ram register 4dh are added to the accumulator to obtain the sum ( 874600h + 123456h = 997a56h ). the sum is contained in the accumulator and the pointer is left unchanged. the direct addressing equivalent is add a, %4d or add a, 77 ( 4dh = 77 decimal). example 2 add a, initialization: accumulator contains 123400h p0:0 contains 21h ram bank0: 21h contains 247ah rom address: 2 47ah contains 0c12h instruction: add a, @@p0:0 result: a contains le4600h p0:0 contains 21h ram bank0: 21h contains 247bh this example uses one word of memory and executes in three machine cycles. the pointer p0:0 contains the ram register location ( 21h ). the contents of this register have a rom address. this address refers to the rom data placed in the speci?ed accumulator by an and instruction 123400h + 0c1200h = 1e4600h . when memory indirect addressing is used, the rom address is automatically incremented. to provide a convenient method of accessing sequential data. using add a, @@p0:0+ performs the same operation and also increments the p0:0 content to 22h . example 3 add a,
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 108 initialization: accumulator contains 123400h instruction: add a, #%0c12 result: a contains le4600h this example uses two words of memory and executes in two machine cycles. the immediate operand 0c12h is added to the accumulator to obtain the sum 123400h + 0c1200h = 1e4600h . example 4 add a, initialization: accumulator contains 23400hh register x contains 0c12h instruction: add a, x result: a contains 1e4600h this example uses one word of memory and executes in one machine cycle. the contents of register x are added to the accumulator to obtain the sum. 123400h + 0c1200h = 1e4600h . all hardware registers can transfer from . example 5 add a, initialization: accumulator contains 123400h ram bank0: f3h contains 0c12h instruction: add a,%f3 result: a contains 1e4600h this example uses one word of memory and executes in one machine cycle. register f3h is added to the accumulator to obtain the sum. 123400h + 0c1200h = 1e4600h . an equivalent instruction is add a, 243 ( f3h = 243 decimal ). example 6 add a, initialization: accumulator contains 123400h p0:0 contains 56h instruction: add a, p0:0 result: accumulator contains 128a00h
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 109 this example uses one word of memory and executes in one machine cycle. the contents of the pointer register p0:0 is added to the accumulator. 123400h + 005600h = 128a00h . the pointer register is connected to the lower 8 bits of the d-bus. the d-bus is connected to the upper 16-bits of the p-bus. this causes the pointer register operand to become 005600h before being added to the accumulator. example 7 add a, initialization: accumulator contains 123400h d0: 1 contains 8746h instruction: add a,d0:1 result: a contains 997a00h d0: 1 contains 8746h this example uses one word of memory and executes in one machine cycle. the contents of the data pointer d0:1 are added to the accumulator. the sum is contained in the accumulator and the pointer is left unchanged. the data pointer contains 8746h .
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 110 and bitwise and and instruction word syntax and a, and a, and a, and a, and a, and a, and a, and a, operation . and. ? flags: n : set if accumulator result is less than 0. z : set if accumulator result is 0 . description data is stored in the speci?ed accumulator by an and instruction. the lower eight bits of the accumulator are cleared when this instruction is executed. example 1 and a, initialization: accumulator contains 123456h p0a contains 45h ram bank1: 45h contains 8746h instruction: and a, @p0:1 1514131211109 8 76543210 1011100 b 0000ssss op code ram bank destination source
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 111 result: accumulator contains 020400h this example uses one word of memory and executes in one machine cycle. the data in ram bank1, referenced by ram pointer 0, is stored in the speci?ed accumulator using an and instruction 123456h.and.874600h = 020400h. example 2 and a, initialization: accumulator contains 123400h p0:0 contains 45h ram bank0: 45h contains 047ah rom address: 04 7ah contains 8746h instruction: and a, @@p0:0 result: a contains 020400h p0:0 contains 45h ram bank0: 45h contains 247bh this example uses one word of memory and executes in three machine cycles. the pointer p0:0 contains the ram register location ( 45h ). the contents of this register has a rom address. this address refers to the rom data that is placed in the speci?ed accumulator by an and instruction 123400h.and.874600h = 020400h . with memory-indirect addressing, the rom address is automatically incremented. this provides a convenient method to access sequential data. using and a, @@p0:0+ performs the same operation and also increments the p0:0 content to 46h . example 3 and a, initialization: accumulator contains 362400h instruction: and a, #%1234 result: accumulator contains 122400h this example uses two words of memory and executes in two machine cycles. the immediate operand 1234h and an accumulator address are processed with an and instruction to produce the result, 362400h.and.123400h = 122400h . example 4 and a,
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 112 initialization: accumulator contains 123456h instruction: and a, #%1f result: accumulator contains 001400h this example uses one word of memory and executes in one machine cycle. the data in the immediate ?eld and the contents of the accumulator are processed with an and instruction. 123456h.and.001f00h = 001400h . example 5 and a, initialization: accumulator contains 123400h register x contains oc12h instruction: and a, x result: a contains 001000h this example uses one word of memory and executes in one machine cycle. use an and instruction to send the contents of register x to the accumulator to obtain the result 123400h.and.0c1200h = 001000h . all hardware registers can transfer from < hwregs >. example 6 and a, initialization: accumulator contains 123400h ram bank0: f3h contains 0c12h instruction: and a, %f3 result: a contains 001000h this example uses one word of memory and executes in one machine cycle. use an and instruction to send register f3h to the accumulator to obtain the result 123400h and oc1200h = 001000h . an equivalent instruction is and a, 243 ( f3h = 243 decimal). example 7 and a, initialization: accumulator contains 123400h p0:0 contains 56h instruction: and a, p0:0
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 113 result: accumulator contains 001400h this example uses one word of memory and executes in one machine cycle. use an and instruction to send the contents of the pointer register p0:0 to the accumulator 123400h.and.005600h = 001400h . the pointer register is connected to the lower 8 bits of the d-bus. the d-bus is connected to the upper 16 bits of the p-bus. this action changes the pointer register operand to 005600h before being added to the accumulator. example 8 and a, initialization: accumulator contains 123400h d0:1 contains 2645h instruction: and a, d0:1 result: accumulator contains 020400h this example uses one word of memory and executes in one machine cycle. the data register, d0:1 , references the operand 2645h . use an and instruction to send this data register to the accumulator to produce the result 123400h.and.2645h = 020400h.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 114 call subroutine call call instruction word syntax call , call operation pc + 2 ? stack 16-bit address ? pc flags: none description the current program counter ( pc ) register content is incremented by two and placed on the stack. the address of the speci?ed label in the call instruction is then placed in the pc register. the jump is made to the appropriate subroutine via the pc . the condition code option is used if call is executed. example 1 call initialization: pc contains 1ffbh fft2 subroutine address contains f234h stack level 0 contains 0025h instruction: call fft2 result: pc contains f234h stack level 0 contains 1ffdh stack level 1 contains 0025h 1514131211109876543210 0000000bcccccccc ssss op code condition code not used 1514131211109876543210 aaaaaaaaaaaaaaaa 16-bit address
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 115 this example uses two words of memory and executes in two machine cycles. the call to the subroutine fft2 places pc+2 ( 1 ffdh ) on the stack. all information currently on the stack is pushed up the stack. the subroutine address is then placed in the pc register. the processor executes the next instruction addressed by the pc , the fft2 subroutine. example 2 call , initialization: pc contains 1ffbh fft2 subroutine address contains f234h stack level 0 contains 0025h uo (user zero bit) contains 1 instruction: call uo, fft2 result: pc = f234h stack level 0 = 1ffdh stack level 1 = 0025h this example uses two words of memory and executes in two machine cycles. the condition code uo is tested by the processor before executing the call instruction. because the uo bit is enabled, the call routine is executed exactly like the example above. the condition code uo is input to the processor that determines if subroutine fft2 is used. another call instruction can determine if another subroutine, fft1 , is used. example 3 call initialization: pc contains 1ffbh fft2 subroutine address contains f234h stack level 0 contains 0025h instruction: call fft2 result: pc contains f234h stack level 0 contains 1ffdh stack level 1 contains 0025h this example uses two words of memory and executes in two machine cycles. the call to the subroutine fft2 places pc+2 ( 1 ffdh ) on the stack. all information currently on the stack is pushed up the stack. the subroutine address is then placed in the pc register. the processor executes the next instruction addressed by the pc , the fft2 subroutine.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 116 ccf clear carry flag ccf instruction word syntax ccf operation zero ? carry bit flags: c : set to 0 . description the clear carry flag instruction resets the carry ?ag with a 0 . example ccf initialization: sr contains 3000h instruction: ccf result: sr contains 2000h c contains 0 this example uses one word of memory and executes in one machine cycle. 1514131211109876543210 1001010000000010 op code condition code flag modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 117 cief clear interrupt enable flag cief instruction word syntax cief operation zero ? ie bit flags: ie : set to 0 . description the clear interrupt enable flag instruction sets the ie ?ag to 0 . example cief initialization: sr contains 3080h instruction: cief result: sr contains 3000h ie contains 0 this example uses one word of memory and executes in one machine cycle. 1514131211109876543210 1001010000000100 op code condition code flag modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 118 copf clear overflow protection flag copclear instruction word syntax copf operation zero ? op bit flags: p : set to 0 . the clear over?ow protection flag instruction resets the op ?ag to 0 . example copf initialization: sr contains 0100h instruction: copf result: sr contains 0000h op contains 0 this example uses one word of memory and executes in one machine cycle. 1514131211109876543210 1001010000001000 op code condition code flag modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 119 cp comparison cp instruction word syntax cp a, cp a, cp a, cp a, cp a, cp a, cp a, cp a, operation a - ? set appropriate status bits flags: c : set if carry is required for operation. z : set if operands are equal. ov : set if operation exceeds the low ( 800000h ) or high limit ( 7fffffh ) of accumulator. n : set if result is negative. description the contents of the register speci?ed in the instruction are compared to the contents of the accumulator in 16-bit mode. the register speci?ed is subtracted from the accumulator and the appropriate ?ags are set. because the registers are 16-bit, a comparison with the 24-bit accumulator requires that the lower eight bits of the accumulator be ?lled with zeros for accurate comparisons. the instruction does not affect the contents of the accumulator except when the over?ow 1514131211109 8 76543210 0110010 b 0000 ssss op code ram bank destination source
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 120 protection bit is set and an over?ow occurs after the compare is executed. the accumulator updates with the appropriate low ( 800000h ) or high ( 7fffffh ) limit. example 1 cp a, initialization: a contains 7a2500h p2:1 contains a4h ram bank1: a4h contains 5463h instruction: cp a, @p2:1 result: a contains 7a2500h sr contains 1000h this example uses one word of memory and executes in one machine cycle. the operand referenced by p2:1 is subtracted from the accumulator. 7a2500h - 546300h = 25c200h . because the comparison does not yield a 0 , bit 0 is not set. the content of the p2:1 register is appended with eight additional 0 bits. for consistent comparisons, the accumulator must contain zeros in the lower eight bits. the accumulator is unaffected by the operation. example 2 cp a, initialization: a contains 7a2500h p2:1 contains a4h ram bank1: a4h contains 5463h rom address: 5463h contains oc12h instruction: cp a, @@p2:1 result: a contains 7a2500h p2:1 contains a4h ram bank1: a4h contains 5464h sr contains 1000h this example uses one word of memory and executes in three machine cycles.the pointer p2:1 contains the ram register location ( a4h ). the contents of this register have a rom address. this address refers to the rom data compared to the accumulator 7a2500h - oc1200h = 6e1300h . because the comparison does not yield a 0 , bit 0 is not set. with memory indirect addressing,
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 121 the rom address is automatically incremented. using cp a,@@p2:1 + performs the same operation and also increments p2:1 content to a5h . example 3 cp a, initialization: a contains 7a2500h instruction: cp a, #%7a25 result: a contains 7a2500h sr contains 3000h this example uses two words of memory and executes in two machine cycles. the immediate operand is compared to the accumulator. because they are equal, the zero flag is set. example 4 cp a, initialization: a contains 7a2500h sr contains 0000h bus contains 7a25h instruction: cp a, bus result: a contains 7a2500h sr contains 3000h this example uses one word of memory and executes in one machine cycle. the < hwreg > operand is subtracted from the accumulator. because the two operands are equal, the zero-status bit is set high . < hwregs > can be compared from all hardware registers. example 5 cp a, initialization: accumulator contains 7a2500h ram bank0 f3h contains 5463h instruction: cp a, %f3 result: a contains 7a2500h sr contains 1000h
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 122 this example uses one word of memory and executes in one machine cycle. register f3h is compared to the accumulator. 7a2500h - 546300h = 25c200h. an equivalent instruction is cp a,243 ( 173h = 243 decimal). example 6 cp a, initialization: accumulator contains 123400h p0:0 contains 56h instruction: cp a, p0:0 result: accumulator contains 123400h sr contains 1000h this example uses one word of memory and executes in one machine cycle. the contents of the pointer register p0:0 are compared to the accumulator. 123400h - 005600h = 11de00h the pointer register is connected to the lower 8 bits of the d-bus. the d-bus is connected to the upper 16 bits of the p-bus. this action changes the pointer register operand to 005600h before being compared to the accumulator. example 7 cp a, initialization: a contains 7a2500h d2:1 contains 5463h instruction: cp a, d2:1 result a contains 7a2500h sr contains 1000h this example uses one word of memory and executes in one machine cycle. the contents of the data pointer d2:1 are compared to the accumulator. 7a2500h - 546300h = 25c200h.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 123 dec decrement dec instruction word syntax dec a dec , a operation acc - 1 ? acc flags: c : set if carry is required for operation z : set if result is 0 . n : set if decrement results in a value less then 0 . ov : set if upper (7fffffh) or lower (800000h) limits are exceeded. description the accumulator decrements by 1 . a condition code can be used to test for a speci?c condition before decrementing. example 1 dec a initialization: a contains 7a2500h instruction: dec a result: a contains 7a24ffh this example uses one word of memory and executes in one machine cycle. the value in the accumulator decrements by 1 . example 2 dec , a initialization: a contains 7a2500h 1514131211109876543210 1001000cccccccccc0101 op code condition code acc modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 124 instruction: dec mi, a result: a contains 7a2500h this example uses one word of memory and executes in one machine cycle. because the accumulator is not negative, the decrement instruction is not executed.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 125 inc increment inc instruction word syntax inc , a inc a operation acc + 1 ? acc flags: c : set if carry is required for operation. z : set if result is 0 . n : set if results in a value less then 0. ov : set if upper (7fffffh) or lower (800000h) limits are exceeded. description the increment instruction adds one to the accumulator. a condition code can be used to test for a speci?c condition for an increment to occur. example 1 inc , a initialization: a contains 7a2500h instruction: inc mi, a result: a contains 7a2500h this example uses one word of memory and executes in one machine cycle. because the accumulator is not negative, the increment instruction is not executed. example 2 inc a 1514131211109876543210 1001000cccccccccc0100 op code condition code acc modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 126 initialization: a contains 7a2500h instruction: inc a result: a contains 7a2501h this example uses one word of memory and executes in one machine cycle. the value in the accumulator is incremented by 1.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 127 jp jump jp instruction word syntax jp , jp operation 16-bit address ? pc flags: none description the instruction places the address of the referenced rom location in the program counter ( pc ). because the processor obtains its next instruction address from the pc , the processor jumps to the appropriate location. a condition code can be used to test for a speci?c condition for a jump to occur. example 1 jp , initialization: routine 1 address contains 1455h pc contains 1343h user 0 input contains 1 instruction: jp nuo, routine 1 result: pc contains 1343h this example uses two words of memory and executes in two machine cycles. because the user 0 input is set high , the condition code is not met. therefore, 1514131211109876543210 1 000110cccccccccc0000 op code condition code not used 1514131211109876543210 a aaaaaaaaaaaaaaa 16-bit address
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 128 the jump instruction does not execute. the user 0 input is used to control the ?ow of the software. example 2 jp initialization: routine 1 address contains 1455h pc contains 1343h instruction: jp routine 1 result: pc contains 1455h this example uses two words of memory and executes in two machine cycles. the value in the program counter is replaced by the routine 1 address ( 1455h ).
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 129 ld load ld instruction word syntax ld a, ld , a ld , ld a, ld , ld , ld a, ld , ld , ld a, ld , ld , ld a, ld , ld , ld a, ld , < pregs> ld , operation ? 1514131211109 8 7654 3210 0000001 b 0011 ssss op code ram bank destination source
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 130 flags: none description the load command provides the ability to transfer data to several different locations in the processor including hardware registers, accumulator, stack, pointers and memory. all transfers across the various internal buses are transparent to the user. notes: 1. a load using the x or y register provides an automatic multiply operation. this means the operand can be obtained from any register location. 2. the p register is a read-only register, therefore the destination of the load cannot be the p register. 3. ld extn , extn is not allowed. 4. a load instruction to the accumulator clears the lower 8 bits of the 24-bit accumulator. example 1 ld a, initialization: a contains 7a2500h p2:1 contains a4h ram bank1: a4h contains 5463h instruction: ld a, @p2:1 result: a contains 546300h this example uses one word of memory and executes in one machine cycle. indirect addressing through the pointer registers provides access to ram data. the data in ram bank 1 , register a4 is transferred to the accumulator. the contents of the p2:1 register are appended with eight additional 0 bits. this is added to verify a correct arithmetic comparison. example 2 ld a, initialization: accumulator contains 123400h p0:0 contains 21h ram bank0: 21h contains 247ah rom address: 247ah equals oc1 2h
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 131 instruction: ld a, @@p0:0 result: a contains oc1 200h p0:0 contains 21h ram bank0: 21h contains 247bh this example uses one word of memory and executes in three machine cycles. the pointer p0:0 contains the ram register location (21h) . the contents of this register have a rom address. this address refers to the rom data that loads to the accumulator. when memory indirect addressing is used, the rom address is automatically incremented. using ld a, @@p0:0+ has the same result, also incrementing the p0:0 content to 22h . example 3 ld a, initialization: accumulator contains 123400h instruction: ld a, #%2474 result: a contains 247400h this example uses two words of memory and executes in two machine cycles. the immediate operand 2474h loads to the accumulator. example 4 ld a, initialization: accumulator contains 123400h register x contains oc12h instruction: ld a, x result: a contains oc1200h this example uses one word of memory and executes in one machine cycle. the contents of register x are loaded to the accumulator. all hardware registers can transfer from . example 5 ld a, initialization: accumulator contains 123400h ram bank0 f3h contains oc12h instruction: ld a, %f3
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 132 result: a contains oc1200h this example uses one word of memory and executes in one machine cycle. register f3h is loaded to the accumulator. an equivalent instruction is ld a,243 ( f3h = 243 decimal). example 6 ld a, initialization: accumulator contains 123400h d0: 1 contains 8746h instruction: ld a, d0:1 result: a contains 874600h d0: 1 contains 8746h this example uses one word of memory and executes in one machine cycle. the contents of the data pointer d0:1 load to the accumulator. example 7 ld a, initialization: accumulator contains 123400h p0:0 contains 56h instruction: ld a, p0:0 result: accumulator contains 005600h this example uses one word of memory and executes in one machine cycle. the contents of the pointer register p0:0 are loaded to the accumulator. the pointer register is connected to the lower 8 bits of the d-bus. the d-bus is connected to the upper 16 bits of the p-bus. this operation causes the pointer register operand to become 005600h before being loaded into the accumulator. example 8 ld , a initialization: accumulator contains 123400h ram bank0: 3ch contains 5678h instruction: ld %3c, a result: accumulator contains 123400h ram bank0: 3ch contains 1234h
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 133 this example uses one word of memory and executes in one machine cycle. the current value in the accumulator is loaded to the register addressed by the instruction ( 3ch ). an equivalent instruction is ld 60, a . ( 3ch = 60 decimal). example 9 ld , initialization: p2:0 contains 2fh ram bank0: 3fh contains 254645h instruction: ld p2:0, #%3f result: p2:0 contains 3fh ram bank0: 3fh contains 254645h this example uses one word of memory and executes in one machine cycle. the immediate data ( 3fh ) is loaded into the pointer register p2:0 . this action provides a convenient method for initializing pointer registers. example 10 ld , initialization: p0: 1 contains 2fh y contains 2376h instruction: ld p0:1, y result: p0: 1 contains 76h y contains 2376h this example uses one word of memory and executes in one machine cycle. the lower 8-bits of the y register are transferred to the pointer register p0:1 . all hardware registers can transfer from . example 11 ld , initialization: p0:1 contains 2fh ram bank0: 2fh contains 2376h instruction: ld @p0:1, #%35b8 result: p0:1 contains 2fh ram bank1: 2fh contains 35b8h
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 134 this example uses two words of memory and executes in two machine cycles. the immediate operand 35b8h is transferred to the register 2fh of ram bank1. example 12 ld , initialization: p2:0 contains 2fh x register contains 8b87h instruction: ld x,p2:0 result: p2:0 contains 2fh x register contains 002fh this example uses one word of memory and executes in one machine cycle. the contents of the p2:0 pointer ( 2fh ) are loaded into the x register. transfer to < hwreg > is possible to all hardware registers except the read-only p register. example 13 ld , initialization: d2:0 contains 3c87h accumulator contains 8bb722h instruction: ld a,d2:0 result: d2:0 contains 3c87h accumulator contains 3c8700h this example uses one word of memory and executes in one machine cycle. the contents of the d2:0 pointer ( 3c87h ) are loaded into the accumulator. transfer to < hwregs > is possible to all hardware registers except the read-only p register. example 14 ld , initialization: stack0 contains 8b2fh stack1 contains 0000h instruction: ld stack, #%35b8 result: stack0 contains 35b8h stack1 contains 8b2fh this example uses two words of memory and executes in two machine cycles. the immediate data is pushed onto the stack as previous stack data is pushed up
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 135 the stack. transfer to < hwregs > is possible to all hardware registers except the read-only p register. example 15 ld , initialization: ext7 register contains 8b87h accumulator contains 77b6h rom 77b6h contains 387dh instruction: ld ext7, @a result: ext7 register contains 387dh accumulator contains 77b6h this example uses one word of memory and executes in one machine cycle. the contents of the rom register 77b6h ( 387dh ) are loaded into external register 7 . transfer to < hwregs > is possible to all hardware registers except the read-only p register and the accumulator register. example 16 ld , initialization: y register contains 1234h p0:0 contains 21h ram bank0: 21h contains 247ah rom address: 247ah contains 0c12h instruction: lid y, @@p0:0 result: y register contains 0c12h p0:0 contains 21h ram bank0: 21h contains 247bh this example uses one word of memory and executes in three machine cycles. the pointer p0:0 contains the ram register location ( 21h ). the contents of this register have a rom address that refers to the rom data that loads to the y register. transfer to < hwregs > is possible to all hardware registers except the read-only p register. when memory indirect addressing is used the rom address is automatically incremented. using ld a,@@p0:0+ performs the same operation and also increments the p0:0 content to 22h . example 17 ld ,
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 136 initialization: x register contains 7a25h p21 contains a4h ram bank1: a4h contains 5463h instruction: ld x, @p2:1 result: x register contains 5463h this example uses one word of memory and executes in one machine cycle. indirect addressing through the pointer registers provides access to ram data. the data in ram bank 1, register a4 is transferred to the x register. transfer to < hwreg > is possible to all hardware registers except the read-only p register. example 18 ld , initialization: x register contains 7a25h ext5 register contains 789ah instruction: ld x, ext5 result: x register contains 789ah ext5 register contains 789ah this example uses one word of memory and executes in one machine cycle. the ext5 register contents are transferred to the x register. transfer to < hwregs > is possible to all hardware registers except the read-only p register.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 137 neg negate neg instruction word syntax neg a neg , a operation -acc ? acc flags: n set if result is a negative number. two special cases are: 1. if acc contains 000000 after execution, then n and 0v are cleared, and z and c are set 2. if acc contains 800000 after execution, then n and 0v are set; and z and c are cleared. the accumulator is replaced with a negative of the current value. to achieve this state, the two's complement is performed. example 1 neg a initialization: a contains 003654h instruction: neg a result: a contains ffc9ach this example uses one word of memory and executes in one machine cycle. 1514131211109876543210 1001000cccccccccc0110 op code condition code acc modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 138 example 2 neg , a initialization: a contains 000111h carry bit contains 1 instruction: neg c, a result: a contains fffeefh this example uses one word of memory and executes in one machine cycle.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 139 nop no operation nop instruction word syntax nop operation pc+ 1? pc flags: none description the nop instruction causes the processor to continue operation for one cycle without affecting previous registers and i/0. 1514131211109876543210 0000000000000000
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 140 or bitwise or or instruction word syntax or a, or a, or a, or a, or a, or a, or a, or a, operation acc .or. source ? acc flags: n set if result in accumulator is negative. z set if result is 0 . description the accumulator performs an or instruction on the contents of the speci?ed register. the upper 16 bits of the accumulator are used. the result is placed in the accumulator. the or instruction is frequently used to compare speci?c bits to assist in program control. the lower eight bits of the accumulator are unchanged after execution of the or instruction. 1514131211109 8 76543210 1100001 b 0000 ssss op code ram bank destination source
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 141 example 1 or a, initialization: accumulator contains 3264a0h p0:0 contains e2h ram bank0: e2h contains 1126h instruction: or a, @p0:0 result: a contains 336600h this example uses one word of memory and executes in one machine cycle. use an or instruction to reference the operand p0:0 with the upper 16 bits of the accumulator. the result is stored in the accumulator. 3264a0h or. 1126a0h = 3366a0h. example 2 or a, initialization: a contains 3264a0h p2:1 contains a4h ram bank 1: a4h contains 5463h rom address: 5463h contains 1126h instruction: or a, @@p2:1 result a contains 3366a0h p2:1 contains a4h ram bank0: a4h contains 5464h sr contains 0000h this example uses one word of memory and executes in three machine cycles. the pointer p2:1 contains the ram register location ( a4h ). the contents of this register have a rom address. this address refers to the rom data that is compared to the accumulator. 3264a0h.or.112600h = 3366a0h . with memory indirect addressing, the rom address is automatically incremented. using ora,@@p0:0+ performs the same operation and also increments the p0:0 content to a5h . example 3 or a, initialization: a contains 3264a0h
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 142 instruction: or a, #%1126 result: a contains 3366a0h sr contains 0000h this example uses two words of memory and executes in two machine cycles. the accumulator performs an or instruction on the immediate data.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 143 pop pop value from stack pop instruction word syntax pop pop pop pop operation stack 0 ? stack n ? stack n-1 flags: none description the current value of the stack is copied to the speci?ed register. because the stack is a last-in, ?rst-out (lifo) hard-wired architecture, the copy and shift of data remaining in the stack are all performed in a single cycle. the pop instruction provides the ability to control information sent to the stack, making it possible to expand the stack using software. example 1 pop initialization: stack 1 contains 0426h stack 0 contains 0c06h p0:0 contains 24h instruction: pop p0:0 1514131211109 8 76543210 opopopopopopopb dddd ssss op code ram bank destination source
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 144 result stack 0 contains 0426h p0:0 contains 06h this example uses one word of memory and executes in one machine cycle. the destination of stack 0 (item on top of stack) is p0:0 . the 8-lsb s of the data in stack 0 are loaded into p0:0 . at transfer, stack 1 is automatically moved to stack 0 . example 2 pop initialization: stack 1 contains 0426h stack 0 contains 0c06h d0:0 contains 7676h instruction: pop d0:0 result: stack 0 contains 0426h d0:0 contains 0c06h this example uses one word of memory and executes in one machine cycle. the destination of the stack 0 (item on top of stack) is given by d0:0 . when transferred, stack 1 is automatically moved to stack 0 . example 3 pop initialization: stack 1 contains 0426h stack 0 contains 0c06h p0:0 contains 24h ram bank0: 24h contains 42a4h instruction: pop @p0:0 result stack 0 contains 0426h ram bank0: 24h contains 0c06h this example uses one word of memory and executes in one machine cycle. the destination of the stack 0 (item on top of stack) is given by p0:0 . 24h is the register location in ram bank0 to which the stack item is transferred. at transfer, stack 1 is automatically moved to stack 0.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 145 example 4 pop initialization: stack 1 contains 0426h stack 0 contains 0c06h x register contains 089ch instruction: pop x result: stack 0 contains 0426h x register contains 0c06h this example uses one word of memory and executes in one machine cycle. the destination of the stack 0 (item on top of stack) is given by the x register. at transfer, stack 1 is automatically moved to stack 0. transfer to < hwregs > is possible to all hardware registers except the read-only p register.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 146 push push value onto stack push instruction word syntax push push push push push push push push operation ? stack stack n ? stack n+ 1 flags: none description the contents of the speci?ed register are placed on the stack. because the stack is a last-in, ?rst-out (lifo) hard-wired architecture, the placement and shifting of current stack data is performed in a single cycle. the push instruction provides the ability to control information sent to the stack, making it possible to expand the stack through software. example 1 push 1514131211109 8 76543210 1100001 b 0000 ssss op code ram bank destination source
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 147 initialization: stack 0 contains 0c06h p1:1 contains a4h instruction: push p1:1 result stack 1 contains 0c06h stack 0 contains 00a4h this example uses one word of memory and executes in one machine cycle. the pointer p1:1 contains the 8-bit value a4h . the 16-bit value, 00a4h , is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1. example 2 push initialization: stack 1 contains 0426h stack 0 contains 0c06h d1:1 contains 42a4h instruction: push d1:1 result stack 1 contains 0c06h stack 0 contains 42a4h this example uses one word of memory and executes in one machine cycle. the pointer d1:1 is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1. example 3 push initialization: stack 1 contains 0426h stack 0 contains 0c06h ram bank0: 24h contains 42a4h p1:1 contains a4h ram bank1: a4h contains 5463h rom address 5463h contains 1126h instruction: push @@p1:1 result: stack 1 contains 0c06h stack 0 contains 1126h ram bank1: a4h contains 5464h
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 148 this example uses one word of memory and executes in three machine cycles. when memory indirect addressing is used, the rom address is automatically incremented. using or a,@@p0:0+ performs the same operation and also increments the p0:0 content to a5h . example 4 push initialization: stack 1 contains 0426h stack 0 contains 0c06h accumulator contains 42a4h rom addres s 42a4h contains 4c45h instruction: push @a result stack 1 contains 0c06h stack 0 contains 4c45h this example uses one word of memory and executes in one machine cycle. indirect addressing with the accumulator points to the rom memory ( 42a4h ) the data in this location is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1. example 5 push initialization: stack 1 contains 0426h stack 0 contains 0c06h p1:1 contains a4h ram bank1: a4h contains 42a4h instruction: push @p1:1 result: stack 1 contains 0c06h stack 0 contains 42a4h ram bank1: a4h contains 42a4h this example uses one word of memory and executes in one machine cycle. the pointer p1:1 contains the ram register location ( a4h ). the data at this location is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1. example 6 push
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 149 initialization: stack 1 contains 0426h stack 0 contains 0c06h x register contains 42a4h instruction: push x result: stack 1 contains 0c06h stack 0 contains 42a4h this example uses one word of memory and executes in one machine cycle. the data in the x register is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1 . transfer from < hwregs > is possible from all hardware registers. example 7 push initialization: stack 1 contains 0426h stack 0 contains 0c06h ram bank0: 24h contains 42a4h instruction: push %24 result: stack 1 contains 0c06h stack 0 contains 42a4h this example uses one word of memory and executes in one machine cycle. the instruction ( 24h ) provides the direct register address. the value contained in this register is pushed onto the stack ( 42a4h ). at transfer, stack 0 is automatically moved to stack 1. example 8 push initialization: stack 1 contains 0426h stack 0 contains 0c06h instruction: push #%5757 result: stack 1 contains 0c06h stack 0 contains 5757h this example uses two words of memory and executes in two machine cycles. the immediate operand 5757h is pushed onto the stack. at transfer, stack 0 is automatically moved to stack 1 .
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 150 ret return from subroutine ret instruction word syntax ret operation stack 0 ? pc stack n ? stack n-1 flags: none description the current stack information is popped from the stack and placed in the program counter (pc) register. the jump is made from the subroutine via the pc. example ret initialization: stack 1 contains 0624 stack 0 contains 0401 pc contains 06df instruction: ret result: stack 0 contains 0624 pc contains 0401h this example uses one word of memory and executes in one machine cycle. 1514131211109 8 76543210 0000000 0 01100101 op code ram bank destination source
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 151 rl rotate left rl instruction word syntax rl a rl ,a operation c <= 23 ------------ < ---------- 8 <= c flags: n set if result of accumulator is negative z set if result is zero. c set if msb is set before rotate. description the upper 16 bits of the accumulator are rotated left through the carry bit. the lower 8 bits remain unchanged while the resultant lsb, bit 0, is placed with the value 0 (see the accumulator section). example 1 rl a initialization: a contains 226a84h carry bit contains 1 instruction: rl a result: a contains 44d584h carry bit contains 0 this example uses one word of memory and executes in one machine cycle. the upper 16 bits ( 226ah ) are shifted left through the carry bit to produce 44d5h . the lower 8 bits ( 84h ) remain unchanged. 1514131211109876543210 1001000cccccccccc0111 op code condition code acc modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 152 example 2 rl , a initialization: a contains 226a84h carry bit contains 0, z=0 instruction: rl z, a result: a contains 226a84h this example uses one word of memory and executes in one machine cycle. the condition code 0 is not set; therefore, the instruction is not executed.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 153 rr rotate right rr instruction word syntax rr a rr , a operation c =>23 ---- > 8 = => 7 - -> -- 0 ? discarded flags: n set if result of accumulator is negative. z set if result is 0. c set if lsb is set before rotate. description the upper 16 bits of acc are rotated right through the carry bit. the msb of the lower 8 bits also obtains the data shifted from the lsb of upper 16 bits. the lower 8 bits are shifted right with the lsb being discarded. example 1 rr a initialization: a contains 226a84h carry bit contains 0 instruction: rr a result: a contains 113542h this example uses one word of memory and executes in one machine cycle. the upper 16 bits ( 226ah ) are shifted right through the carry bit to produce 1135h . the lower 8 bits ( 84h ) are shifted right to provide 42h . example 2 rr , a 1514131211109876543210 1001000cccccccccc0000 op code condition code acc modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 154 initialization: a contains 226a84h carry bit contains 0, z=0 instruction: rr z, a result: a contains 226a84h this example uses one word of memory and executes in one machine cycle. the condition code 0 is not set; therefore, the instruction is not executed.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 155 scf set carry flag scf instruction word syntax scf operation 1 ? carry bit flags: c set to 1. description the set carry flag instruction places a one in the carry bit (bit 12 of the status register). example scf initialization: sr contains 2000h instruction: scf result: sr contains 3000h c contains 1 this example uses one word of memory and executes in one machine cycle. 1514131211109876543210 op op op op op op op cc cc cc cc cc fm fm fm fm op code condition code flag modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 156 sief set interrupt enable flag sief instruction word syntax sief operation 1 ? ie bit flags: none description the instruction places a 1 in bit 7 of the status register and is used to enable interrupts. example sief initialization: sr contains 3000h instruction: sief result: sr contains 3080h ie contains 1 this example uses one word of memory and executes in one machine cycle. 1514131211109876543210 1001010cccccccccc0101 op code condition code flag modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 157 sll shift left logical sll instruction word syntax sll a sll , a operation discarded z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 158 example 2 sll , a initialization: a contains 226a84h carry bit contains 0 instruction: sll mi, a result: a contains 226a84h this example uses one word of memory and executes in one machine cycle. the condition code n is not set, and the instruction is not executed.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 159 sopf set overflow protection flag sopf instruction word syntax sopf operation 1 ? op bit flags: none description the set over?ow protection flag instruction places a one in bit 8 of the status register. if an alu operation exceeds the limits of the processor, the over?ow protection sets the over?ow ?ag ( ov) and holds the limit value in the accumulator. example sopf initialization: sr contains 0000h instruction: sopf result: sr contains 0100h op contains 1 this example uses one word of memory and executes in one machine cycle. 1514131211109876543210 1001010000001001 op code condition code flag modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 160 sra shift right arithmetic sra instruction word syntax sra a sra , a operation 23 => 23 --- > ---- 0 => discarded flags: n set if result of accumulator is negative. z set if result is 0. c set if lsb is set before the shift. description all 24 bits of the accumulator are shifted right with sign extension through the carry bit. the msb, bit 23 , is replicated in vacated bits. the lsb, bit 0 , is passed through the carry before it is discarded. example 1 sra a initialization: a contains 226a84h carry bit contains 0 instruction: sra a result: a contains 113542h carry bit contains 0 this example uses one word of memory and executes in one machine cycle. all 24 bits of the accumulator are shifted right. the msb, bit 23 , is copied into bit 22. the lsb, bit 0 , is discarded. 1514131211109876543210 1001000cccccccccc0000 op code condition code acc modi?cation
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 161 example 2 sra , a initialization: a contains 226a84h carry bit contains 0, n=0 instruction: sra a result: a contains 113542h carry bit contains 0 this example uses one word of memory and executes in one machine cycle. the condition code is set; therefore, the instruction is executed. the initialization of the accumulator sets the pl ( nn ) condition code.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 162 sub subtract sub instruction word syntax sub a, sub a, sub a, sub a, sub a, sub a, sub a, sub a, operation acc ?(source) ? acc flags: c set if a carry from the most signi?cant bit is performed. n set if the result in the accumulator is negative. z set if the result is 0 . ov set if the addition exceeds the upper ( 7fffffh ) or lower ( 800000h ) limit of the accumulator. description the addressed data memory operand is subtracted from the accumulator. the result is loaded into the accumulator. the lower eight bits of the accumulator are cleared by the execution of the subtract instruction. 1514131211109 8 76543210 0010001 b 0000 ssss op code ram bank destination source
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 163 example 1 sub a, initialization: accumulator contains 874600h p0: 1 contains 45h ram bank1: 45h contains 1234h instruction: sub a, @p0:1 result: a contains 751200h @p0:1 contains 1234h this example uses one word of memory and executes in one machine cycle. the contents of the register pointed by p0:1 are subtracted from the accumulator. the difference is contained in the accumulator and the pointer is left unchanged. the register pointer contains 45h . because the pointer references ram bank1, the absolute register is 145h ( 325 ). therefore, the contents of register 145h are subtracted from the accumulator. 874600h - 123400h = 751200h . the direct addressing equivalent is sub a,%145 or sub a,325. example 2 sub a, initialization: accumulator contains 874600h p0:0 contains 21h ram bank0: 21h contains 247ah rom address: 247ah contains 1234h instruction: sub a, @@p0:0 result: a contains 751200h p0:0 contains 22h ram bank0: 21 h contains 247bh this example uses one word of memory and executes in three machine cycles. the pointer is used for memory indirect addressing. the pointer contains the address of the ram (address 247ah ). the ram contains the address of the requested rom data ( data 247ah ). this operand is subtracted from the accumulator. 874600h - 123400h = 751200h . example 3 sub a, initialization: accumulator contains 874600h
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 164 instruction: sub a, #%1234 result: accumulator contains 751200h this example uses two words of memory and executes in two machine cycles. the immediate operand 8746h is subtracted from the accumulator. 874600h - 123400h = 751200h. example 4 sub a, initialization: accumulator contains 874600h register x contains 1234h instruction: sub a, x result: a contains 751200h this example uses one word of memory and executes in one machine cycle. the contents of register x are subtracted from the accumulator. 874600h - 123400h = 751200h . transfer from < hwregs > is possible from all hardware registers. example 5 sub a, initialization: accumulator contains 874600h ram bank0: f3h contains 1234h instruction: sub a, %f3 result: a contains 751200h this example uses one word of memory and executes in one machine cycle. the contents of register f3h are subtracted from the accumulator. 874600h - 123400h = 751200h . an equivalent instruction is sub a, 243 ( f3h = 243 decimal). example 6 sub a, initialization: accumulator contains 874600h d0: 1 contains 1234h instruction: sub a, d0:1
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 165 result: a contains 751200h d0:1 contains 1234h this example uses one word of memory and executes in one machine cycle. the contents of the data pointer d0:1 are subtracted from the accumulator. the difference is contained in the accumulator and the pointer is left unchanged. example 7 sub a, initialization: accumulator contains 874600h p0:0 contains 56h instruction: sub a, p0:0 result: accumulator contains 86f000h this example uses one word of memory and executes in one machine cycle. the contents of pointer register p0:0 are subtracted from the accumulator. 874600h - 005600h = 86f000h. the pointer register is connected to the lower 8 bits of the d-bus. the d-bus is connected to the upper 16 bits of the p-bus. this causes the pointer register operand to become 005600h before it is subtracted from the accumulator.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 166 xor bitwise exclusive or xor instruction word syntax xor a, xor a, xor a, xor a, xor a, xor a, xor a, xor a, operation a.xor. ? a flags: c set if carry from the most signi?cant bit is performed. n set if result in the accumulator is negative. z set if result is 0 . ov set if operation exceeds upper ( 7fffffh ) or lower ( 800000h ) limit of accumulator. description with the accumulator, perform an xor instruction on the addressed data memory operand. the result loads into the accumulator. the lower eight bits of the accumulator are cleared by the xor instruction. 1514131211109 8 76543210 1110001 b 0000 ssss op code ram bank destination source
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 167 example 1 xor a, initialization: accumulator contains 005600h p0:0 contains 00h ram bank0: 00h contains 1234h instruction: xor a, @p0:0 result: a contains 126200h this example uses one word of memory and executes in one machine cycle. the pointer is used for memory indirect addressing. the pointer contains the address of the ram (address 00h ). location 00h has operand 1234h . with the accumulator, 005600h , perform an xor instruction to obtain the result 126200h . example 2 xor a, initialization: a contains 3264a0h p2:1 contains a4h ram bank1: a4h contains 5463h rom address: 5463h contains 1126h instruction: xor a, @@p2:1 result a contains 2342a0h p2:1 contains a41h ram bank1: a4h contains 5464h sr contains 0000h this example uses one word of memory and executes in three machine cycles. the pointer p2:1 contains the ram register location( a4h ). the contents of this register have a rom address. this address refers to the rom data compared to the accumulator. 3264a0h.xor.112600h = 2342a0h . when indirect memory addressing is used, the rom address is automatically incremented. using xor a, @@p2:1+ performs the same operation and also increments the p21 content to a5h .
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 168 example 3 xor a, initialization: a contains 3264a0h instruction: xor a, #%1126 result: a contains 2342a0h sr contains 0000h this example uses two words of memory and executes in two machine cycles. perform an xor instruction on the immediate data. example 4 xor a, initialization: a contains 3264a0h sr contains 0000h bus contains 1126h instruction: xor a, bus result: a contains 2342a0h sr contains this example uses one word of memory and executes in one machine cycle. with the accumulator, perform an xor instruction on the < hwreg > operand. example 5 xor a, initialization: accumulator contains 3264a0h ram bank0: f3h contains 1126h instruction: xor a, %f3 result: a contains 2342a0h sr contains 0000h this example uses one word of memory and executes in one machine cycle. register f3h is compared to the accumulator. 3264a0h.xor.112600h = 2342a0h. an equivalent instruction is xor a, 243 ( f3h = 243 decimal).
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 169 5 system design considerations the z90t366 provides the ability to decode closed-caption transmissions display characters on the screen manipulate analog and digital control circuits monitor keypad button and infrared signals directly generate osd if the z90t366 receives vertical and horizontal synchronization signals in a typical system, normal transmission is received and demodulated. the signals received from the color decoder and de?ection unit control the crt display. to display characters generated by the z90t366 requires a video multiplexor which enables the crt displays rgb signals and synchronization to be controlled by the video outputs from the processor. when the controller has to display a character on the screen, the multiplexor is switched, and the processors video signals appear on the display. the band-limited, a/c-coupled composite video signal is clamped internally to the negative reference voltage (refC) during the back porch interval. it is then passed to the analog-to-digital converter through a 6:1 multiplexor. the digital signal is then decoded to extract the closed-caption text embedded in the video signal. the characters received are generated as video signals and are then passed to the display. when a detectable composite video signal is received, the sync separator extracts the horizontal and vertical synchronization signals and passes them to the de?ection module of the television. the flyback signals from the de?ection coils are fed back to the z90t366. the controller uses these signals to align its video signals with those of the normal display. if the composite video signal is not present, video synchronization is provided by the controller. in this case, the sync signal pins are set to be outputs. the pins then feed to the de?ection unit which controls the display. the sync generators can be con?gured to provide either hsync and vsync, or h-flyback and v-flyback. analog functions such as volume and color controls can be controlled by pulse width modulated outputs from the z90t366. additional digital controls like channel ?ne tuning are controlled via the serial i 2 c bus. an infrared remote control receiver can be directly decoded through the capture register, and keypad input can be scanned by directly controlling i/o pins as keyscan ports.
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 170 the processor clock is available by referencing an internal phase locked loop to an external 32.768 khz crystal oscillator. the oscillator minimizes emi emissions from the clock circuitry. the internal system clock frequency can be selected as 12.058 mhz in normal operation or 32.768 khz in low power consumption sleep mode (usually used if there is a general system power failure). the z90t366s stop mode suspends processor clocking for a power-down. program, display, and character graphics memory are on the chip, eliminating the requirement for external memory components. characters can be displayed as two or three times normal size. smoothing and fringing circuits enhance display appearance. figure 28 diagrams a typical application of the z90t366 television controller as an embedded controller in a television. figure 28 system block diagram color decoder deflection unit rgb osd mux rgb crt ezvision front panel detector television tuner, if i 2 c bus composite video tuning control fm audio sync/ flyback ovl h & v deflection sync/ flyback audio l r control rgb ampli- fiers z90t366 television controller ir keypad
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 171 6 electrical characteristics table 76 absolute maximum and minimum ratings sym parameter min max units conditions v cc power supply voltage 0 7 v v id input voltage C0.3 v cc +0.3 v digital inputs v ia input voltage C0.3 v cc +0.3 v analog inputs (a/d0Ca/d4) v o output voltage C0.3 v cc +0.3 v all push-pull digital outputs v o output voltage C0.3 v cc +0.3 v pwm outputs i oh output current high C10 ma one pin i oh output current high C100 ma all pins i ol output current low 20 ma one pin i ol output current low 200 ma all pins t a operating temperature 0 70 o c t s storage temperature C65 150 o c table 77 dc characteristics symbol parameter min typ max units conditions v cc power supply voltage 4.75 5.00 5.25 v v il input voltage low 0 0.4 0.2 v cc v v ih input voltage high 0.7v cc 3.6 v cc v v ihr input voltage high on reset pin 0.75 v cc 4.2 v cc v v pu maximum pull-up voltage v cc v for pwm v ol output voltage low 0.16 0.4 v @ i ol = 1 ma v oh output voltage high v cc C 0.4 4.75 v @ i oh = C0.75 ma i ol output current low 7.2 12 ma @ v ol = 0.4v i ol1 output current low 12 20 ma @ v ol = 0.8v
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 172 6.1 dc peripherals i oh output current high 4.0 7.0 ma @ v oh = v cc C0.4 i oh1 output current high 16 20 ma @ v oh = 2.4v v xl input voltage xtal1 low 0.3 v cc v external clock generator driven v xh input voltage xtal1 high 0.6 v cc v i ir reset input current 25 90 150 av rl = 0v i il input leakage C3.0 0.01 3.0 a @ 0v and v cc i cc supply current 60 100 ma all ports are inputs, rgb is in digital mode i cc supply current 30 50 ma all ports are inputs, rgb is in analog mode i cc1 supply current 5 10 ma sleep mode @ 32.768 khz i cc2 supply current 50 100 a stop mode all pwm outputs are @ v in = 0v table 78 r, g, and b analog output output voltage (30 k ? load) settling time @ v cc = 4.75v @ v cc = 5.00v @ v cc = 5.25v 70% of dc level, 10pf load data = 00 0.00vC0.65v 0.00vC0.70v 0.00vC0.75v <50ns data = 01 1.70vC0.20v 1.80vC0.20v 1.90vC0.20v data = 10 2.80vC0.25v 2.90vC0.25v 3.00vC0.25v data = 11 3.90vC0.30v 4.00vC0.30v 4.10vC0.30v table 77 dc characteristics (continued) symbol parameter min typ max units conditions
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 173 table 79 adc0/small range* sym parameter min typ max units u rC clamping voltage at adc0 1.0 1.5 2.0 v adc 0 input voltage for level 0 u rC C(u r+ +u rC )/15 u rC u rC +(u r+ Cu rC )/15 v adc 1 input voltage for level 1 u rC u rC +(u r+ Cu rC )/15 u rC +2(u r+ Cu rC )/15 v adc 2 input voltage for level 2 u rC +(u r+ Cu rC )/15 u rC +2(u r+ Cu rC )/15 u rC +3(u r+ Cu rC )/15 v adc 3 input voltage for level 3 u rC +2(u r+ Cu rC )/15 u rC +3(u r+ Cu rC )/15 u rC +4(u r+ Cu rC )/15 v adc 4 input voltage for level 4 u rC +3(u r+ Cu rC )/15 u rC +4(u r+ Cu rC )/15 u rC +5(u r+ Cu rC )/15 v adc 5 input voltage for level 5 u rC +4(u r+ Cu rC )/15 u rC +5(u r+ Cu rC )/15 u rC +6(u r+ Cu rC )/15 v adc 6 input voltage for level 6 u rC +5(u r+ Cu rC )/15 u rC +6(u r+ Cu rC )/15 u rC +7(u r+ Cu rC )/15 v adc 7 input voltage for level 7 u rC +6(u r+ Cu rC )/15 u rC +7(u r+ Cu rC )/15 u rC +8(u r+ Cu rC )/15 v adc 8 input voltage for level 8 u rC +7(u r+ Cu rC )/15 u rC +8(u r+ Cu rC )/15 u rC +9(u r+ Cu rC )/15 v adc 9 input voltage for level 9 u rC +8(u r+ Cu rC )/15 u rC +9(u r+ Cu rC )/15 u rC +10(u r+ Cu rC )/15 v adc a input voltage for level a u rC +9(u r+ Cu rC )/15 u rC +10(u r+ Cu rC )/15 u rC +11(u r+ Cu rC )/15 v adc b input voltage for level b u rC +10(u r+ Cu rC )/15 u rC +11(u r+ Cu rC )/15 u rC +12(u r+ Cu rC )/15 v adc c input voltage for level c u rC +11(u r+ Cu rC )/15 u rC +12(u r+ Cu rC )/15 u rC +13(u r+ Cu rC )/15 v adc d input voltage for level d u rC +12(u r+ Cu rC )/15 u rC +13(u r+ Cu rC )/15 u rC +14(u r+ Cu rC )/15 v adc e input voltage for level e u rC +13(u r+ Cu rC )/15 u rC +14(u r+ Cu rC )/15 u rC +15(u r+ Cu rC )/15 v adc f input voltage for level f u rC +14(u r+ Cu rC )/15 u r+ u rC +16(u r+ Cu rC )/15 v r in input impedance 1.0 m ? note: * the input voltage level indicated in the table is a switch point from one adc level to another. to be in the middle of the level half, lsb ((u r+ ? r )/(15*2)) must be added. the input voltage must be prorated accordingly if v cc is changed. 1.5?.0v; ta = 0? to 70?; vcc = 4.75v to 5.25v
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 174 6.2 ac characteristics table 81 lists the ac characteristics. table 80 adc1-adc4/full range data from adc input voltage (volts) data from adc input voltage (volts) data from adc input voltage (volts) data from adc input voltage (volts) 0000 0.000 0.15 0100 1.250 0.15 1000 2.500 0.15 1100 3.750 0.15 0001 0.312 0.15 0101 1.563 0.15 1001 2.813 0.15 1101 4.063 0.15 0010 0.625 0.15 0110 1.875 0.15 1010 3.125 0.15 1110 4.375 0.15 0011 0.934 0.15 0111 2.188 0.15 1011 3.438 0.15 1111 4.688 0.15 input impedance > 1.0 m ? note: 0-5.0v; vcc = 5.0v; temp=0-70c table 81 ac characteristics sym parameter min typ max units t pc input clock period 16 32 100 sec t rc , t fc clock input rise and fall 12 nsec td por power on reset delay 0.8 1.2 sec tw res power on reset minimum width 5 tpc sec td hs h sync incoming signal width 1 10 15 sec td vs v sync incoming signal width 1 200 10000 sec td es time delay between leading edge of v sync and h sync in even ?eld C12 0 +12 sec td os time delay between leading edge of v sync and h sync in odd ?eld 20 32 44 sec tw hvs h sync /v sync edge width 0.5 2.0 sec note: *all timing of the i 2 c bus interface are defined by related specifications of the i 2 c bus interface. note: t a = 0?c to 70?c; v cc =4.75v to 5.25v; f osc =32,768hz
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 175 6.3 analog rgb the rgb outputs in analog mode are controlled current sources with an internal load. these outputs display gamma-corrected, v cc prorated characteristics. see table 82, table 83, and figure 29. figure 29 recommended application schematics table 82 rgb voltage speci?cation parameter min typical max units supply voltage 4.5 5.0 5.5 v full scale voltage 1.8v 1.9v (0.40 * v cc ) 2.2v v 2/3 scale voltage 1.5v 1.6v (0.33 * v cc ) 1.815v v 1/3 scale voltage 1.125v 1.2v (0.25 * v cc ) 1.375v v zero scale voltage 0.0v (0.00 * v cc ) +0.1 v v note: *measured with 3.9 k ? load. table 83 rgb time speci?cation parameter min typical max units output rise time 50 65 ns output fall time 50 65 ns note: *measured with 4 k ? resistor in parallel with 30 pf capacitor load. r1 r2 r, g, b r1 + r2 = 3.9k v out = 2 * r2 4.0 z90t366
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 176 7 packaging figure 30 and table 84 indicate the controlling dimensions. figure 30 52-pin sdip package dimensions d 26 1 27 52 e1 c e ea controlling dimension in inches q1 a2 a1 l b1 b e s detail a optional end lead config detail a
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 177 table 84 controlling dimensions symbol millimeter min max inch min max a1 0.51 0.020 a2 3.25 3.94 0.128 0.155 b 0.38 0.53 0.015 0.021 b1 0.89 1.14 0.035 0.045 c 0.23 0.38 0.009 0.015 d 47.50 1.870 e 15.24 15.75 0.600 0.620 e1 13.72 14.10 0.540 0.555 1.778 typ 0.070 typ ea 15.49 16.76 0.610 0.660 l 3.05 3.68 0.120 0.145 q1 1.52 1.91 0.060 0.075 s 0.64 1.78 0.025 0.070 e
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 178 8 ordering information rom code submission rom code submission instructions rom code can be submitted on zilogs web site at http://www.zilog.com. top mark information mark permanency: 3x soak into alpha 2110 at 63 to 70 c, for 30 seconds duration each soak. mechanical brush after each soak. device order number description z90t361 64 kword otp z90t361pz016sc 16 mhz, 64 kword otp television controller with osd z90t366 64 kword rom z90t366pz016sc rxxxx* 16 mhz, 64 kword mask rom television controller with osd emulation kit z9036900zem emulator/ programmer otp adapter z903xx00100zdp otp programming adapter evaluation board z9034600zco osd evaluation board note: * xxxx is a unique rom number assigned to each customer code
z90t366 rom and z90t361 otp ezvision 64 kword television controller with osd ps005901-1100 179 customer feedback form ezvision z90t366 product speci?cation i f there are any problems while operating this product, or any inaccuracies in the speci?cation, please copy and complete this form, then mail or fax it to zilog. suggestions welcome! customer information product information return information zilog system test/customer support 910 e. hamilton avenue, suite 110, ms 4C3 campbell, ca 95008 fax: (408) 558-8536 email: tools@zilog.com problem description or suggestion provide a complete description of the problem or suggestion. for speci?c problems, include all steps leading up to the occurrence of the problem. attach additional pages as necessary. name country company phone address fax city/state/zip e-mail serial # or board fab #/rev. # software version document number host computer description/type

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