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data sheet august 2000 u13749eu2v0ds00 1 nec vrc chipsets are designed and verified for use with nec vr series? microprocessors. nec makes no claim as to the suitability of vrc chipsets for use with non-nec microprocessors and does not warrant their performance, suitability or use in such applications. v rc 4375 system controller description the v rc 4375 tm s y stem controller is a software-confi g urable chip that interfaces directl y with an nec v r 43xx tm 64-bit mips ? risc cpu and pci bus without external lo g ic or bufferin g . the s y stem controller also interfaces with memor y ( sdram, edo, fast-pa g e dram, and flash/boot rom ) with minimal to no bufferin g . the memor y bus can also interface with sram and g eneral-purpose i/o devices. as an interface with the v r 43xx cpu, the v rc 4375 acts as a memor y controller, dma controller, and pci brid g e. as an interface with pci a g ents, the v rc 4375 acts as either a pci bus master or a pci bus tar g et. alternativel y , the v rc 4375 ma y be located on a pci bus add-on board. features ? cpu interface direct connection to the 66 mhz v r 43xx cpu bus 3.3-volt i/o support for all v r 43xx bus cycles little-endian or bi g -endian byte orderin g modes ? memory interface support for boot rom/flash memory, base memory, and up to two simms simm capacity of up to 128 mb pro g rammable address ran g es for base and simm memory support for two-bank 4/16 mb devices and four-bank 64/128/256 mb devices cas latency of 2 or 3 in base memory or simm sdram, pro g rammable to support faster new devices or slower le g acy devices simm burst access time pro g rammable in one or two cycle(s) 66 mhz memory bus 64 mb base memory ran g e: sdram and edo dram 256 mb simm memory ran g e: sdram, edo and fast-pa g e dram several speed g rades supported within each memory ran g e open dram pa g e maintained within base memory ei g ht-word (32-byte) write fifo (cpu to memory) two-word (8-byte) prefetch fifo (memory to cpu or memory to pci) on-chip dram and sdram refresh g eneration up to 64 mb of write-protectable boot rom or up to 64 mb of flash rom flash/boot rom devices with 8-/16-/32-bit confi g uration support pro g rammable timin g to interface g eneral-purpose i/o device or boot rom in the boot rom address ran g e
2 v rc 4375 system controller ? pci interface master and tar g et capabilities host brid g e and add-on board modes pci bus arbiter with pro g rammable arbitration scheme pro g rammable arbitration scheme for pci/cpu accessed to memory bi g -endian or little-endian byte orderin g modes 4-word (16-byte) bidirectional pci master fifo (cpu is pci bus master) 8-word (32-byte) bidirectional pci tar g et fifo (memory is pci bus tar g et) 33 mhz pci bus clock rate 132 mb/s burst transfers interrupt support for add-on board mode 3.3 v inputs; 5 v-tolerant inputs/outputs ? dma controller four hi g hly robust dma channels cpu-initiated block transfers between memory and pci bus 8-word (32-byte) bidirectional dma fifo sophisticated, pro g rammable dma channel arbitration priority scheme four sets of dma control re g isters for chained transfers next address pointer in each channel to support scatter/ g ather operation pro g rammable dma arbitration priority bidirectional unali g ned transfers transfers at maximum pci bandwidth of 132 mb/s ? interrupt controller nonmaskable interrupt and interrupt si g nals (nmi# and int#) maskable interrupt-causin g events ? uart ny16550l universal asynchronous receiver/transmitter modem control functions separate receiver and transmitter fifos (16 bytes each) even-, odd- or no-parity bit g eneration fully prioritized interrupt control ? timers one 32-bit loadable watchdo g timer that g enerates a nonmaskable interrupt two 32-bit loadable g eneral-purpose timers that g enerate interrupts hi g hly sophisticated timers with pro g rammable clock, start/stop, auto reload/ restart, and enable/disable interrupt bits ordering information part number package v rc 4375 pd65948s1-068 256-pin tbga
3 v rc 4375 system controller system configuration fi g ure 1 shows the controller used as a host brid g e in a typical system. alternatively, the controller can be located on a pci bus add-on board. fi g ure 1. system connection note: f244- or f245-type buffers may be needed on the muxad bus and, for dimm, on certain chip-select signals. v r 43xx cpu v rc 4375 system controller memory pci bus uart 32 bits, 66 mhz 32 bits, 33 mhz 32 bits, 66 mhz
4 v rc 4375 system controller terminology in this document: ? signal names ending with # (such as nmi#) are active-low si g nals . ? word means 4 bytes. this definition of word differs from the definition in the pci local bus specification , where a word is 2 bytes. ? b means byte. ? b means bit. ? cas means column address strobe. ? memory means the local memory attached to the v rc 4375 controller. ? simm tm and dimm tm mean sin g le and dual in-line memory module unless explicitly stated otherwise. ? module means a set of chips, as in a simm or dimm. ? edo dram means extended data out dynamic random access memory. ? sdram means synchronous dram. ? rdram ? means rambus ? dram, which is desi g ned to conform to the interface that defines the rambus channel. reference documents the followin g documents were used in the creation of this data sheet. unless other- wise specified, the latest version of each document applies. ? mips ? r4300 preliminary risc processor specification revision 2.2 (available from mips technolo g ies, inc.) ? pci local bus specification revision 2.1 and pci system design guide revision 1.0 (available from the peripheral component interconnect special interest group) ? nec v r 4300 tm microprocessor user ? s manual (document number u10504ej6v0um00)
5 v rc 4375 system controller contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 orderin g information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 system confi g uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 terminolo g y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.0 pin confi g uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 block dia g ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.0 si g nal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.0 re g isters, resources, and implementation . . . . . . . . . . . . . . . . . . . 14 5.0 cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.0 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.0 pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.0 dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.0 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.0 clockin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.0 reset confi g uration si g nals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.0 endian mode software issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 13.0 timin g dia g rams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 14.0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.0 packa g e drawin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6 v rc 4375 system controller 1.0 pin configuration fi g ure 2. pin confi g uration (bottom view) nec japan sample 256n * b6 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 pin index gnd vdd i/o 16 16 224 yr t u v w pnmlk jhgfedcb a (top view) 256tbga 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 abcdefghjklmnprtuvwy
7 v rc 4375 system controller table 1. pin assi g nment pin number grid number pin name pin number grid number pin name pin number grid number pin name pin number grid number pin name 1 a1 gnd 45 p20 muxad[24] 89 p2 trdy# 133 b14 mda[26] 2 b1 clk [0] 46 n20 roe# 90 r2 ad[17] 134 b13 mras[0]# 3 c1 clk[1] 47 m20 muxad[20] 91 t2 frame# 135 b12 mcas[0]# 4 d1 gnt[3]# 48 l20 bras# 92 u2 ad[18] 136 b11 gnd 5 e1 inta# 49 k20 vdd 93 v2 gnd 137 b10 gnd 6 f1 lock# 50 j20 mda[15] 94 w2 cbe[3]# 138 b9 muxad[8] 7 g1 gnt[0]# 51 h20 mda[13] 95 w3 vdd 139 b8 gnd 8 h1 gnd 52 g20 vdd 96 w4 ad[26] 140 b7 muxad[6] 9 j1 ad[1] 53 f20 muxad[19] 97 w5 ad[29] 141 b6 muxad[2] 10 k1 ad[5] 54 e20 muxad[18] 98 w6 sysad[16] 142 b5 gnd 11 l1 gnd 55 d20 gnd 99 w7 sysad[13] 143 b4 mda[18] 12 m1 vdd 56 c20 muxad[14] 100 w8 iochrdy 144 b3 mda[2] 13 n1 ad[13] 57 b20 bbe[0]# 101 w9 sysad[8] 145 c3 nmi# 14 p1 gnd 58 a20 vdd 102 w10 gnd 146 d3 gnd 15 r1 devsel 59 a19 mda[23] 103 w11 sysad[2] 147 e3 serr# 16 t1 irdy# 60 a18 mda[22] 104 w12 rst# 148 f3 gnt[1]# 17 u1 gnd 61 a17 muxad[11] 105 w13 gnd 149 g3 req[2]# 18 v1 ad[20] 62 a16 gnd 106 w14 pvalid# 150 h3 ad[0] 19 w1 ad[22] 63 a15 boe# 107 w15 sysad[28] 151 j3 ad[3] 20 y1 ad[21] 64 a14 mda[27] 108 w16 sysad[30] 152 k3 ad[6] 21 y2 ad[23] 65 a13 mras[1]# 109 w17 sysad[23] 153 l3 ad[8] 22 y3 ad[24] 66 a12 mcas[3]# 110 w18 gnd 154 m3 ad[11] 23 y4 gnd 67 a11 mcas[2]# 111 w19 sysad[19] 155 n3 ad[15] 24 y5 ad[28] 68 a10 muxad[9] 112 v19 vdd 156 p3 cbe[1]# 25 y6 gnd 69 a9 vdd 113 u19 syscmd[4] 157 r3 stop# 26 y7 sysad[14] 70 a8 mda[7] 114 t19 syscmd[2] 158 t3 cbe[2]# 27 y8 int# 71 a7 mda[6] 115 r19 gnd 159 u3 ad[19] 28 y9 sysad[9] 72 a6 muxad[10] 116 p19 muxad[25] 160 v3 ad[25] 29 y10 sysad[5] 73 a5 muxad[3] 117 n19 sdcke[0] 161 v4 ad[27] 30 y11 sysad[3] 74 a4 vdd 118 m19 muxad[21] 162 v5 ad[30] 31 y12 vdd 75 a3 mda[19] 119 l19 gnd 163 v6 sysad[15] 32 y13 eok# 76 a2 mda[3] 120 k19 bromcs# 164 v7 sysad[12] 33 y14 gnd 77 b2 gnd 121 j19 gnd 165 v8 sysad[10] 34 y15 sysad[29] 78 c2 clk[2] 122 h19 mda[12] 166 v9 sysad[7] 35 y16 sysad[26] 79 d2 idsel 123 g19 mda[30] 167 v10 sysad[4] 36 y17 vdd 80 e2 req[3]# 124 f19 gnd 168 v11 gnd 37 y18 sysad[21] 81 f2 gnt[2]# 125 e19 muxad[17] 169 v12 refclk 38 y19 sysad[20] 82 g2 req[0]# 126 d19 muxad[15] 170 v13 masterclock (m c lk) 39 y20 vdd 83 h2 gnd 127 c19 bbe[1]# 171 v14 sysad[31] 40 w20 gnd 84 j2 ad[2] 128 b19 gnd 172 v15 sysad[27] 41 v20 sysad[18] 85 k2 ad[7] 129 b18 mda[21] 173 v16 sysad[25] 42 u20 gnd 86 l2 cbe[0]# 130 b17 muxad[12] 174 v17 sysad[22] 43 t20 syscmd[3] 87 m2 ad[12] 131 b16 mda[11] 175 v18 sysad[17]
8 v rc 4375 system controller 44 r20 uart_rxd 88 n2 ad[14] 132 b15 bwe# 176 u18 evalid# 177 t18 syscmd[1] 197 c11 mcas[1]# 217 t4 ad[16] 237 l17 vdd 178 r18 uart_txd 198 c10 muxad[7] 218 u4 gnd 238 k17 sdcas# 179 p18 uart_dsr 199 c9 mda[5] 219 u5 ad[31] 239 j17 sdras# 180 n18 sdcke[1] 200 c8 muxad[5] 220 u6 vdd 240 h17 gnd 181 m18 muxad[22] 201 c7 muxad[1] 221 u7 sysad[11] 241 g17 mda[28] 182 l18 gnd 202 c6 mda[16] 222 u8 gnd 242 f17 vdd 183 k18 sdclk[1] 203 c5 mda[17] 223 u9 sysad[6] 243 e17 bbe[3]# 184 j18 sdclk[0] 204 c4 mda[1] 224 u10 vdd 244 d17 gnd 185 h18 mda[14] 205 d4 gnd 225 u11 sysad[1] 245 d16 mda[9] 186 g18 mda[29] 206 e4 perr# 226 u12 sysad[0] 246 d15 vdd 187 f18 mda[31] 207 f4 vdd 227 u13 gnd 247 d14 mda[24] 188 e18 muxad[16] 208 g4 req[1]# 228 u14 testb 248 d13 gnd 189 d18 bbe[2]# 209 h4 gnd 229 u15 vdd 249 d12 mras[3]# 190 c18 mda[20] 210 j4 ad[4] 230 u16 sysad[24] 250 d11 vdd 191 c17 muxad[13] 211 k4 vdd 231 u17 gnd 251 d10 mda[4] 192 c16 mda[10] 212 l4 ad[9] 232 t17 syscmd[0] 252 d9 muxad[4] 193 c15 mda[8] 213 m4 ad[10] 233 r17 vdd 253 d8 gnd 194 c14 mda[25] 214 n4 gnd 234 p17 uart_dtr 254 d7 muxad[0] 195 c13 mwe# 215 p4 par 235 n17 gnd 255 d6 vdd 196 c12 mras[2]# 216 r4 vdd 236 m17 muxad[23] 256 d5 mda[0] table 1. pin assi g nment (continued) pin number grid number pin name pin number grid number pin name pin number grid number pin name pin number grid number pin name
9 v rc 4375 system controller 2.0 block diagram this section provides the block dia g ram for the system controller. for descriptions of each interface block, see: ? section 5.0 "cpu interface" on pa g e17 ? section 6.0 "memory interface" on pa g e18 ? section 7.0 "pci bus interface" on pa g e55
10 v rc 4375 system controller fi g ure 3. block dia g ram pci master interface pci target interface interrupt timer memory arbiter dma engine cpu/ memory/ dma controller cpu-mem 8 address/data interface cpu/memory/ dma data select address generation: simm, boot, edo memory mem-cpu 8 cpu address data interface cpu command decoder sysad syscmd/ctl memory timer controller muxad mda ras/cas/ctl cpu/dma memory data mux memory data/ address interface pci ad pci cmd/ctl internal resources/ registers cpu/ dma interface txd/rxd arbiter cpu interface controller command decoder dma control register 4 dma controllers arbiter cpu interface memory interface pci interface internal interface controller fifo fifo uart pci dma mailbox
11 v rc 4375 system controller 3.0 signal summary the v rc 4375 controller utilizes a 256-pin tape ball g rid array (tbga) packa g e. table 2 throu g h table 5 summarize the si g nal functions. the # symbol followin g a si g nal name indicates an active-low si g nal. table 2. cpu interface si g nals signal buffer type (nec library) i/o reset value pull-up/ pull-down resistance (ohms) max imum ac load (pf) maximum dc drive (ma) description eok# b001 o high 20 12 external ready. signifies that the controller is capable of accepting a processor request. evalid# b001 o high 20 12 external agent valid. indicates that the controller is driving valid information on the sysad and syscmd buses. int# b001 o high 30 12 interrupt request masterclock (mclk) b001 o toggle 20 12 66-mhz master clock to cpu nmi# b0uc o high 50 k pull-up 20 6 nonmaskable interrupt; asserted when a pci device asserts serr# or by the internal counter pvalid# fiu1 i processor valid. signifies that the v r 43xx cpu is driving valid information on the sysad and syscmd buses. sysad[31:0] b00c i/o hi-z 20 6 system address/data bus syscmd[4:0] b00c i/o hi-z 20 6 system command/data id bus
12 v rc 4375 system controller table 3. memory interface si g nals signal buffer type (nec library) i/o reset value pull-up/ pull-down resistance (ohms) maximum ac load (pf) maximum dc drive (ma) description boe# b001 o high 50 12 base memory output enable. see figure 4. bras# b001 o high 50 12 base memory row address strobe. see figure 4. bromcs# b001 o high 30 12 boot rom chip select bwe# b001 o high 50 12 base memory write enable. see figure 4. roe# b001 o high 30 12 boot rom/flash rom output enable. connect to rom oe pin. bbe[3:0]# b001 o high 30 12 byte enable for prom/flash rom mras[3:0]# b001 o high 70 12 memory row address strobes. see figure 5. mcas[3:0]# b001 o high 70 12 memory column address strobes. see figure 5. mda[31:0] b00c i/o high 50 12 memory data (even), boot rom address muxad[14:0] b0d1 i/o hi-z 50k pull- down (internal) 70 12 multiplexed row/column address; also lower boot rom address bits muxad[25:15] b0d1 i/o hi-z 50k pull- down (internal) 50 12 upper boot rom address bits mwe# b001 o high 30 12 boot rom and simm write enable iochrdy b001 i high 30 12 i/o channel ready signal. input during normal operation. see section 6.6 for more details. sdcas# b001 o high 50 12 sdram column address strobe sdras# b001 o high 50 12 sdram row address strobe sdcke[1:0] b001 o high 50 12 sdram clock enable sdclk[1:0] b001 o high 50 12 66-mhz sdram clock
13 v rc 4375 system controller table 4. pci interface si g nals signal buffer type (nec library) i/o reset value pull-up/ pull-down resistance (ohms) maximum ac load (pf) maximum dc drive (ma) description ad[31:0] bw01 i/o hi-z 70 pci, 12 note pci multiplexed address and data bus cbe[3:0]# bw01 i/o hi-z 50 12 pci bus command and byte-enable clk[2:0] bw01 o toggle 50 12 pci clock, 33 mhz devsel# bw01 i/o hi-z 50 12 pci device select frame# bw01 i/o hi-z 50 12 pci cycle frame gnt[0]# bw01 i/o high 10 12 pci bus grant gnt[3:1]# bw01 o high 10 12 pci bus grant idsel bw01 i pci initialization device select inta# bw01 i/o 10 12 pci interrupt a irdy# bw01 i/o hi-z 50 12 pci initiator ready lock# bw01 i/o hi-z 10 12 pci lock atomic operation par bw01 i/o hi-z 50 12 pci parity of a/d[31:0] and c/be[3:0]# perr# bw01 i/o hi-z 10 12 pci parity error req[0]# bw01 i/o 10 12 pci bus request req[3:1]# bw01 i pci bus request rst# bw01 i reset (chip) serr# bw01 i/o hi-z 10 12 pci system error stop# bw01 i/o hi-z 50 12 pci stop request from target trdy# bw01 i/o hi-z 50 12 pci target ready note: compatible with pci specification. table 5. utility si g nals signal buffer type (nec library) i/o reset value pull-up/ pull-down resistance (ohms) max imum ac load (pf) maximum dc drive (ma) description refclk f1v1 i toggle 66 mhz system reference clock uart_txd bwdc i/o hi-z 50 k (to gnd, inter- nal) 50 6 uart transmit data uart_rxd f1v1 i hi-z 50 6 uart receive data uart_dtr bwdc i/o hi-z 50 k (to gnd, inter- nal) 50 6 uart data terminal ready uart_dsr f1v1 i hi-z 50 6 uart data set ready uart test/ muxad 15 b0d1 i hi-z 50 6 used to test uart hardmacro at lsi chip tester testb b0d1 i hi-z 50 6 input used by uart. pulled high for normal oper- ation.
14 v rc 4375 system controller 4.0 registers, resources, and implementation 4.1 re g ister summar y table 6 summarizes the controller ? s re g ister set (base memory address 0x0f00_0000 in system memory). accesses above offset 0x1ff return 0 with the data error bit set on syscmd[0], update the controller ? s bus error status re g ister (section 9.1.1), and cause an interrupt (int#), if enabled. table 6. re g ister summary offset from base memory address 0x0f00_0000 register name size ( b y tes ) cpu bus r/w pci bus (r/w) reference 0x0 base memory control register 4 r/w not accessible section 6.7.1 on page 30 0x4 simm memory control register 1 4 r/w not accessible section 6.8.1 on page 38 0x8 reserved 4 not accessible 0xc simm memory control register 2 4 r/w not accessible section 6.8.1 on page 38 0x10 reserved 4 not accessible 0x14 pci master address window register 1 4 r/w not accessible section 7.3.1 on page 57 0x18 pci master address window register 2 4 r/w not accessible section 7.3.1 on page 57 0x1c pci target address window register 1 4 r/w not accessible section 7.4.1 on page 59 0x20 pci target address window register 2 4 r/w not accessible section 7.4.1 on page 59 0x24 pci master i/o window register 4 r/w not accessible section 7.3.1 on page 57 0x28 pci configuration data register 4 r/w not accessible section 7.5 on page 61 0x2c pci configuration address register 4 r/w not accessible section 7.5 on page 61 0x30 pci mailbox register 1 4 r/w r/w section 7.11 on page 72 0x34 pci mailbox register 2 4 r/w r/w section 7.11 on page 72 0x38 dma control register 1 4 r/w not accessible section 8.3.1 on page 77 0x3c dma memory address register 1 4 r/w not accessible section 8.3.3 on page 80 0x40 dma pci address register 1 4 r/w not accessible section 8.3.4 on page 81 0x44 dma control register 2 4 r/w not accessible section 8.3.1 on page 77 0x48 dma memory address register 2 4 r/w not accessible section 8.3.3 on page 80 0x4c dma pci address register 2 4 r/w not accessible section 8.3.4 on page 81 0x50 bus error status register 4 r not accessible section 9.1.1 on page 85 0x54 interrupt control and status register 1 4 r/w not accessible section 9.1.2 on page 85 0x58 dram refresh counter register 4 r/w not accessible section 6.9.1 on page 44 0x5c boot rom write-protect register 4 r/w not accessible section 6.5.3 on page 26 0x60 pci exclusive access register 4 r/w not accessible section 7.12.1 on page 73 0x64 dma words remaining register 4 r not accessible section 8.3.6 on page 82 0x68 dma current memory address register 4 r not accessible section 8.3.7 on page 82 0x6c dma current pci address register 4 r not accessible section 8.3.8 on page 82 0x70 pci retry counter 4 r not accessible section 7.8 on page 70 0x74 pci enable register 4 r/w not accessible section 7.10 on page 71 0x78 power-on memory initialization register 4 r/w not accessible section 6.11.1 on page 45 0x7c endian mode register (em) 4 r/w not accessible section 12.0 on page 94 0x80 dm a/cpu/pci m em ory arbiter priority selection register 4r/w not accessible section 8.3.2 on page 79 0x84 uart receiver data buffer register (uartrbr) 4r not accessible section 6.12.1 on page 47 0x84 uart transm itter data holding register (uartthr) 4w not accessible section 6.12.2 on page 47 0x88 uart interrupt enable register (uartier) 4 r/w not accessible section 6.12.3 on page 47 0x84 uart divisor latch lsb (uartdll) 4 r/w not accessible section 6.12.4 on page 48
15 v rc 4375 system controller 0x88 uart divisor latch msb register (uartdlm) 4 r/w not accessible section 6.12.5 on page 48 0x8c uart interrupt id register (uartiir) 4 r not accessible section 6.12.6 on page 48 0x8c uart fifo control register (uartfcr) 4 w not accessible section 6.12.7 on page 49 0x90 uart line control register (uartlcr) 4 r/w not accessible section 6.12.8 on page 50 0x94 uart modem control register (uartmcr) 4 r/w not accessible section 6.12.9 on page 51 0x98 uart line status register (uartlsr) 4 r/w not accessible section 6.12.10 on page 52 0x9c uart modem status register (uartmsr) 4 r/w not accessible section 6.12.11 on page 53 0xa0 uart scratch register (uartscr) 4 r/w not accessible section 6.12.12 on page 54 0xa4 dma control register 3 4 r/w not accessible section 8.3.1 on page 77 0xa8 dma memory address register 3 4 r/w not accessible section 8.3.3 on page 80 0xac dma pci address register 3 4 r/w not accessible section 8.3.4 on page 81 0xb0 dma control register 4 4 r/w not accessible section 8.3.1 on page 77 0xb4 dma memory address register 4 4 r/w not accessible section 8.3.3 on page 80 0xb8 dma pci address register 4 4 r/w not accessible section 8.3.4 on page 81 0xbc dma next record pointer register 1 4 r/w not accessible section 8.3.5 on page 81 0xc0 dma next record pointer register 2 4 r/w not accessible section 8.3.5 on page 81 0xc4 dma next record pointer register 3 4 r/w not accessible section 8.3.5 on page 81 0xc8 dma next record pointer register 4 4 r/w not accessible section 8.3.5 on page 81 0xcc set timer counter register 1 4 r/w not accessible section 9.1.3 on page 88 0xd0 set timer counter register 2 4 r/w not accessible section 9.1.3 on page 88 0xd4 set nmi timer register 4 r/w not accessible section 9.1.3 on page 88 0xd8 read timer counter register 1 4 r not accessible section 9.1.3 on page 88 0xdc read timer counter register 2 4 r not accessible section 9.1.3 on page 88 0xe0 read nmi timer register 4 r not accessible section 9.1.3 on page 88 0xe4 timers/pci inta # interrupt control and status register 2 4r/w not accessible section 9.1.3 on page 88 0xe8 general-purpose i/o timing control register 4 r/w not accessible section 6.6.1 on page 29 0xec reserved 0xf0:0xff reserved 0x100:0x1ff pci configuration space registers (host bridge mode) 1, 2, 4 r/w not accessible section 7.5 on page 61 0x100:0x1ff pci configuration space registers (add-on board mode, where the controller is located on a pci bus board rather than on the motherboard) 1, 2, 4 not ac- cessible r/w section 7.7 on page 67 table 6. re g ister summary (continued) offset from base memory address 0x0f00_0000 register name size ( b y tes ) cpu bus r/w pci bus (r/w) reference
16 v rc 4375 system controller 4.2 resource accessibilit y table 7 summarizes the accessibility of the controller ? s internal re g isters, memory ran g es, and pci bus resources from the cpu and from pci bus masters. 4.3 implementation summar y to create a system usin g the v rc 4375 system controller: 1. confi g ure the hardware usin g the information provided throu g hout this data sheet. 2. power-up and initialize the memory, followin g the steps in section 6.11 on pa g e 45. 3. initialize the pci bus interface, usin g the confi g uration information provided in sec- tion 7.0 on pa g e 55. table 7. resources accessible throu g h the v rc 4375 system controller resource accessible from cpu accessible from pci bus reference cpu ? no section 5.0 on page 17 controller ? s internal registers (except pci mailboxes) word no section 6.0, section 7.0, sec- tion 8.0, section 9.0 boot rom byte writes word, halfword, or byte reads no 1 section 6.5 on page 24 base memory any cpu burst 2 any pci burst 3 section 6.7 on page 30 simm memory any cpu burst 1 any pci burst 2 section 6.8 on page 38 pci mailboxes word word 4 section 7.11 on page 72 pci configuration space registers word, halfword, or byte 5 word, halfword, or byte in add- on board mode only section 7.5 on page 61, sec- tion 7.7 on page 67 pci memory space any cpu burst of 4 words or less 1 no pci local bus specification pci i/o space any cpu burst of 4 words or less 1 no pci local bus specification pci configuration space word, halfword, or byte 5 word, halfword, or byte pci local bus specification notes: 1. because the boot rom does not support burst transfers, it cannot be accessed from the pci bus. the pci interface issues cache-line reads to the target inside the controller. 2. alignment and burst length as defined by the v r 43xx cpu. 3. any size burst length, any alignment. burst may be disconnected by the controller. 4. the controller accepts bursts of words to the pci mailboxes. however, the controller performs a target disconnect without data after each data transfer. 5. any size access less than or equal to one word, aligned as defined by the v r 43xx cpu.
17 v rc 4375 system controller 5.0 cpu interface the controller interfaces directly with the v r 43xx series cpu, in full compliance with the mips r4300 preliminary risc processor specification, revision 2.2 . the connec- tion is via the cpu ? s 66-mhz sysad bus usin g a 3.3-volt i/o. all of the cpu ? s sysad bus operations are supported. 5.1 endian confi g uration the be bit in the v r 43xx cpu ? s confi g uration re g ister specifies the cpu ? s byte order- in g at reset. be = 0 confi g ures little-endian order; be = 1 confi g ures bi g -endian order. the bc bit in the v r 43xx cpu ? s confi g uration re g ister specifies the pci byte orderin g at reset. bc = 0 confi g ures little-endian order; bc = 1 confi g ures bi g -endian order. the v rc 4375 controller ? s cpu interface supports either bi g - or little-endian byte order- in g on the sysad bus. the endianness for the cpu depends on the state of the muxad[11] si g nal at reset; the endianness for the pci depends on the state of the muxad[12] si g nal at reset, as described in section 11.0. all of the controller ? s other interfaces operate only in little-endian mode. all of the internal confi g uration, com- mand, status and control re g isters are considered little endian. the software implica- tions of this, and some related pci device examples, are described in section 12.0. 5.2 data rate control the controller-to-cpu data rate is determined by the evalid# si g nal. the cpu to con- troller data rate is pro g rammable in the ep field (bits 27:24) of the cpu ? s confi g uration re g ister. althou g h the cpu supports both d and dxx data rates, the controller only sup- ports the d data rate. 5.3 address decodin g the controller latches the address on the sysad bus. it then decodes the address and syscmd si g nals to determine the transaction type. ten address ran g es can be decoded: ? two ran g es for boot rom ? boot rom address ran g es for i/o devices. (do not put i/o devices in the ? fault recovery address ? ran g e.) ? one ran g e for the controller ? s internal confi g uration re g isters ? one ran g e for base memory ? two ran g es for simm/dimm memory ? two ran g es for the pci master address windows ? one ran g e for the pci i/o address window boot rom is mapped accordin g to its size, as specified in table 14 on pa g e 24. the controller ? s internal re g isters are fixed at base memory address 0x0f00_0000, to allow the cpu to access them durin g boot, before they have been confi g ured. all other decode ran g es are pro g rammable. 5.4 trace requirements all traces between the cpu and the controller must be limited to 3 inches or less. tclk is not used. see section 10.0 on pa g e 92 for details on clockin g .
18 v rc 4375 system controller 6.0 memory interface the cpu accesses memory attached to the controller in the normal way, by address- in g the system memory space. for lar g e block transfers, the cpu can also initiate dma transfers between memory and the pci (bidirectionally), as described in section 8.0. external pci bus masters access the controller ? s memory throu g h the pci tar g et address windows, as described in section 7.4. the controller ? s memory interface has the followin g internal fifos that support trans- fers between memory and the various sources and destinations: ? 8-word (32-byte) write fifo (cpu to memory) ? 2-word (8-byte) prefetch fifo (memory to cpu or memory to pci) ? 8-word (32-byte) bidirectional dma fifo (pci to memory or memory to pci) 6.1 memor y re g ions and devices the controller connects directly to memory and mana g es the addresses, data, and control si g nals for the followin g address ran g es. ? two boot rom ran g es: standard and fault recovery ? one base memory ran g e (pro g rammable) ? two simm memory ran g es (pro g rammable). dimm modules can also be used. ? general-purpose i/o device within the boot rom ran g e the followin g memory modules are examples of what can be used. ? flash in boot rom and/or simm 2 memory ran g es ? edo dram for base or simm memory; maximum of 64 mb in simm ran g e usin g edo drams ? synchronous dram (sdram); maximum of 256 mb in simm ran g e 16 mb for base or simm memory (nec part numbers pd4516421, pd4564841, pd4564163, and pd4516821) 64-mb, 4-bank devices for base or simm memory (nec part numbers pd4564441 and pd4564841) 64-mb, 4 m x 16 devices 128-mb, 4-bank devices for base or simm memory (nec part number pd45128841) 2 m x 32-bit devices in base and simm memory boot rom can be confi g ured with 85-ns or slower flash chips. in addition to its stan- dard boot address ran g e, boot rom can also be mapped to a fault-recovery ran g e in simm memory slot 2, if that slot is confi g ured with 85-ns flash chips. prior to accessin g boot rom, software must confi g ure this address ran g e, as described in section 6.5. boot rom timin g is flexible; the timin g is controlled by two re g isters as described in section 6.6. base memory can include 4-mb edo or nec 8-/16-mb sdram chips. if sdram is used for base memory, it cannot be bank interleaved. prior to accessin g base memory, software must confi g ure this address ran g e, as described in section 6.7. the two simm memory ran g es can be sin g le sided (simm) or double sided (dimm), pa g e mode or non-pa g e mode, and may include any of the supported memory types.
19 v rc 4375 system controller the 100-pin dimm packa g e is the only dimm packa g e supported. prior to accessin g simm memory, software must confi g ure this address ran g e, as described in section 6.8. fi g ure 4 shows a block dia g ram of controller-to-memory connections for dram. fi g ure 6 on pa g e 36 and fi g ure 7 on pa g e 37 show examples of controller-to-memory con- nections for sdram. a typical system with sdram in the base memory address ran g e and simm memory address ran g e is shown in fi g ure 4 on pa g e 19. fi g ure 4. memory block dia g ram mda[31:0] muxad[25:0] mwe# bromcs# mras[3:0]# mcasa[3:0]# bras# bwe# boe# v rc 4375 controller edo (side a) flash/ boot rom address data edo simm #1 (side a) edo simm #2 (side a) 0 1 2 3 oe# we# cs# address address bbe[3:0]# roe# we# ras0# ras1# cas[3:0]# ras2# ras3# cas[3:0]# we# base memory
20 v rc 4375 system controller 6.2 address multiplexin g modes the controller supports four address multiplexin g modes (mux modes) in the base memory and simm memory ran g es. table 8 shows these modes and the row address x column address confi g urations they support. confi g uration of the address multiplexin g modes is done in the base memory control re g ister (section 6.7.1) and simm memory control re g isters (section 6.8.1). the selec- tion of mode determines which system address bits are output from the controller on the memory interface muxad bus durin g row and column addressin g . table 9 shows the muxad-to-sysad mappin g for dram. when edo dram is used for base memory, either the 12 x 8 or 10 x 10 confi g uration may be used. 16-/64-/128- mb edo devices are supported. table 8. address multiplexin g modes address multiplexing mode row address x column address configurations mux mode 0 9 x 9 mux mode 1 10 x 9, 10 x 10 mux mode 2 11 x 9, 11 x 10, 11 x 11 mux mode 3 12 x 9, 12 x 10, 12 x 11, 12 x 12 mux mode 4 14 x 14 (64-/128-mb sdrams only) any mux mode 12 x 8, 11 x 8, 10 x 8 table 9. muxad-to-sysad address mappin g for edo dram muxad signals sysad mapping row column mode 0 (x9) mode 1 (x10) mode 2 (x11) mode 3 (x12) 0 113333 1 124444 2 135555 3 146666 4 157777 5 168888 6 179999 7 102222 8 1819202122 9 1920212223 10 20 21 22 23 24 11 21 22 23 24 25
21 v rc 4375 system controller table 10 shows the muxad-to-sysad mappin g for sdram. when sdram is used in base memory, mux mode 3 must be used and 16-/64-/128-mb sdram devices can be used. table 10. muxad-to-sysad address mappin g for sdram muxad signals sysad mapping row column mode 3 (16-mb sdram) mode 4 1 (64-/128-mb sdram) mode 5 2 (128-mb sdram) mode 6 3 (256-mb sdram) 0112222 1123333 2134444 3146666 4157777 5168888 6179999 7105555 81822 24 24 24 91923 25 25 25 10 20 hardwired to 0 hardwired to 0 hardwired to 0 hardwired to 0 11 21 21 21 26 27 12 22 21 22 22 22 13 23 23 23 23 14 24 24 24 24 notes: 1. 16-mb sdram can be used in either the base memory or simm ranges. 64-mb, 4-bank sdrams are supported only in simm and base memory regions. it can also drive 1 m x 32-bit memory devices. 2. mux mode 5 is used to drive 4-bank, 128-mb memory devices. these devices can be organized in x4, x8, x16, and x32 configurations. 3. mux mode 6 is used to drive 4-bank, 256-mb devices. these devices can be organized in x4, x8, x16, and x32 configurations.
22 v rc 4375 system controller 6.3 memor y performance memory access speed is determined by memory type and speed. table 11 lists examples of 66-mhz memory bus clock cycles required for each 8-word (32-byte) cpu instruction cache line fill transfer. the first number in the ? sysad cpu clocks (66 mhz) ? column is for the first word; the remainin g numbers are for the subsequent words. only the most common combinations are shown. refer to more details in section 6.7.1 and section 6.8.1. read performance is calculated by countin g the risin g ed g e for mclk, where the read command is issued by the cpu. because the cpu issues write data with no wait states once the write command is issued, the numbers in the table represent the rate at which data is written to memory. the sum of the numbers represents the number of cycles between when the write operation was issued and when the next cpu memory operation can be g in. table 11 provides examples of memory performance. table 11. examples of memory performance memory type/ speed cas latency page mode page hit r/w sequential addresses base or simm memory sysad cpu clocks (66 mhz) sdram, 10 ns no, cas = 3 no no r no base 7-1-1-1-1-1-1-1 sdram, 10 ns no, cas = 3 no no w no base 5-1-1-1-1-1-1-1 sdram, 10 ns no, cas = 3 no no r no simm 10-2-2-2-2-2-2-2 or 10-1-1-1-1-1-1-1 sdram, 10 ns no, cas = 3 no no w no simm 6-2-2-2-2-2-2-2 or 6-1-1-1-1-1-1-1 sdram, 10 ns no, cas = 2 no no r no base 6-1-1-1-1-1-1-1 sdram, 10 ns no, cas = 2 no no w no base 5-1-1-1-1-1-1-1 sdram, 10 ns no, cas = 2 no no r no simm 8-1-1-1-1-1-1-1 sdram, 10 ns no, cas = 2 no no w no simm 6-1-1-1-1-1-1-1 edo, 60 ns no no no r base 9-2-2-2-2-2-2-2 edo, 60 ns no no no w not applicable base 7-2-2-2-2-2-2-2 edo, 60 ns no no no r simm 11-4-4-4-4-4-4-4 edo, 60 ns no no no w simm 9-4-4-4-4-4-4-4 fast-page, 70 ns no no no r simm 11-5-5-5-5-5-5-5 fast-page, 70 ns no no no w simm 10-5-5-5-5-5-5-5 flash/sram/i/o no no no r 13-7-7-7-7-7-7-7 flash/sram/i/o no no no w 11-6-6-6-6-6-6-6
23 v rc 4375 system controller 6.4 placement, loadin g , and example dela y s fi g ure 5 shows the physical placement recommendations for motherboard chips. table 12 shows minimum and maximum ac loadin g s for the memory interface si g nals. table 13 shows example trace delays between memory and the controller. fi g ure 5. memory placement table 12. memory si g nal ac loadin g signal min. (pf) max. (pf) description muxad[25:15] 10 50 rom address upper bits muxad[14:00] 10 70 multiplexed row/column address, rom address low bits bras# 5 50 base memory row address strobe mras[3:0]# 15 70 simm memory row address strobes mcasa[3:0]# 20 70 column address strobe, even addresses mwe# 10 30 boot rom and simm write enable boe# 10 50 base memory output enable roe# 10 30 rom/flash output enable bwe# 10 50 base memory write enable bromcs# 10 30 boot rom chip select mda[31:0] 20 70 memory data, boot rom data sdclk[1:0] 10 50 66-mhz sdram clock sdcke[1:0] 10 70 sdram clock enable sdcs[1:0]# 10 50 sdram command select sdcas# 20 50 sdram column address strobe sdras# 20 50 sdram row address strobe v rc 4375 flash boot rom dram (side a) dram (side a) ? f245 ? f245 ? f245 ? f245 simm #2 simm #1 v r 43xx controller cpu
24 v rc 4375 system controller 6.5 boot rom boot rom can be confi g ured with 85-ns flash chips; access time should be 200 ns or less. the controller supports 8-/16-/32-bit boot rom at locations 0x1c00_0000 throu g h 0x1fff_ffff in the system memory space. in addition to this standard boot- address ran g e, boot rom can also be mapped to a fault-recovery ran g e in simm memory slot 2, if that slot is confi g ured with 85-ns flash chips. the boot rom does not support cpu cache operations ? it can not operate in burst mode ? only durin g one address/data cycle at a time. it is not accessible from the pci bus. durin g boot rom accesses, muxad[25:0] provide a 26-bit address. this allows a user to place up to 64 mb of boot rom on the motherboard. a user can also place up to 16 mb of boot rom on the board and an additional 48 mb on the simm slot 2, for a total of 64 mb. simm slot 2 is used to boot from in fault-recovery mode (section 6.5.6 on pa g e 27). the boot rom size and boot base memory address are confi g ured at the ris- in g ed g e of rst# by the state of muxad[2:0], as shown in table 14. write and read cycles may be in word, halfword, or byte sizes. durin g a read operation, the controller assembles four consecutive byte read cycles into words. the boot rom data is connected to mda[31:0]. table 13. example simm dram delays signal source destination delay subtotal (120 ps/inch) rc delay (2 x r x c) total delay 1 mcas[3:0]# controller simm dram 1.0 ns (8 in) 2 x 33 x 100 pf = 6.6 ns 7.6 ns muxad[14:0] 2 controller buffer input buffer output buffer buffer output (100 pf) simm dram 0.5 ns 14.0 ns 2.0 ns 2 x 10 x 250 pf = 5.0 ns 21.5 ns mda[31:0] controller simm dram 2.0 ns 2.0 ns mda[31:0] simm dram controller 2.0 ns 2.0 ns mras# controller simm dram 2.2 ns 2 x 33 x 180 pf = 12 ns 14.2 ns mwe# 2 controller buffer input buffer output buffer buffer output (130 pf) simm dram 1.3 ns 11.0 ns 2.0 ns 2 x 10 x 130 pf = 2.6 ns 16.9 ns notes: 1. from controller to simm dram. 2. to accomodate simm loading, f244 or f245 buffers must be used on these signals. table 14. boot rom size confi g uration at reset muxad[2:0] boot rom size address range 000 0.5 mb 0x1fc0_0000 through 0x1fc7_ffff 001 1.0 mb 0x1fc0_0000 through 0x1fcf_ffff 010 2 mb 0x1fc0_0000 through 0x1fdf_ffff 011 4 mb 0x1fc0_0000 through 0x1fff_ffff 100 8 mb 0x1f80_0000 through 0x1fff_ffff 101 16 mb 0x1f00_0000 through 0x1fff_ffff 110 32 mb 0x1e00_0000 through 0x1fff_ffff 111 64 mb 0x1c00_0000 through 0x1fff_ffff
25 v rc 4375 system controller the controller asserts the boot rom chip select (bromcs#) in the address ran g e 0x1c00_0000 throu g h 0x1fff_ffff. when write cycles are performed to the boot rom/flash memory space, the controller asserts mwe# in conjunction with bro- mcs#. when read cycles are performed, the controller asserts bbe# and roe# in conjunction with bromcs#. if the cpu attempts to access boot rom addresses outside the defined size of the boot rom, the controller returns 0 with the data error bit set on syscmd[0]. in addition, the controller ? s bus error status re g ister (section 9.1.1) is updated and an interrupt is asserted on the int# si g nal, if the interrupt is enabled in the interrupt control and sta- tus re g ister (section 9.1.2). 6.5.1 boot rom write protection boot rom can be protected in hardware and/or software. hardware protection is implemented at boot time. software protection is implemented by pro g rammin g the boot rom write-protect re g ister (section 6.5.3). 6.5.2 hardware versus software protection hardware can implement write protection on up to 960 kb of the boot rom, in blocks of 64 kb at boot time. on the risin g ed g e of reset (rst#), four bits of the muxad bus, muxad[7:3], are sampled and used to determine the number of 64-kb blocks to be protected. up to 15 blocks can be protected; 0000 indicates one 64-kb block, 0001 indicates two blocks, and so on. a value of 1111 indicates that no blocks are to be pro- tected. for boot rom sizes less than or equal to 4 mb, the base memory address of the rom and the base memory address for hardware protection are both 0x1fc0_0000. for boot rom sizes of 8 mb, 16 mb, and 64 mb, the base memory addresses of rom are 0x1f80_0000, 0x1f00_0000, and 0x1c00_0000, respectively. the base memory address for hardware protection is 0x1fc0_0000 when boot rom size is less than or equal to 4 mb; 0x1f80_0000 when boot rom size is equal to 8 mb; 0x1f00_0000 when boot rom size is equal to 16 mb; 0x1e00_0000 when boot rom size is equal to 32 mb; and 0x1c00_0000 when boot rom size is equal to 64 mb, as shown in table 14. software can also implement write protection by writin g to the boot rom write-protect re g ister. the 7 least-si g nificant bits of this re g ister provide additional protection for up to 127 64-kb blocks, totalin g 1984 kb. the base memory address for software protec- tion is the same as for hardware protection (table 14); the protected ran g e consists of a combination of software-implemented protection and hardware-implemented protec- tion. software can override or re-enable hardware write protection as described in the boot rom write-protect re g ister ? s key field (section 6.5.3).
26 v rc 4375 system controller 6.5.3 boot rom write-protect register the boot rom write-protect re g ister stores a word at offset 0x5c. the re g ister is ini- tialized to 0xffff_ff7f at reset. software can override the hardware write protection confi g ured at reset by writin g 0xc0de_99xx to this re g ister, with the least-si g nificant 7 bits containin g the desired software write protection value. care must be taken not to chan g e the protection while data is bein g written to the boot rom. to prevent this, read a word from the boot rom immediately before chan g in g this re g ister. the re g ister has the followin g fields: bits 6:0 wprot write protection value the number of 64-kb blocks, minus 1, to be write protected (up to 127 blocks). 0 = protects 1 block all 1s = disables protection bit 7 reserved hardwired to 0 bits 31:8 key hardware protection override key 0xc0de_99 = override the hardware protection confi g ured at reset to re-enable hardware protection, software must write a value other than 0xc0de_99 to this field. after re-enablin g hardware protection, the key field chan g es to all 1s. 6.5.4 boot rom protection ranges the boot rom protection ran g es as defined by the protection bits are as follows. the boot rom may be confi g ured with two distinct address spaces: standard and fault recovery. the standard address space is used for normal operation. the fault-recovery space is used when the standard flash rom is corrupted or requires updatin g . table 15. boot rom protection ran g es muxad [2:0] boot rom size protection ranges 000 0.5 mb start at 0x1fc0_0000 + 6-bit protection value x 64 kb 001 1 mb start at 0x1fc0_0000 + 6-bit protection value x 64 kb 010 2 mb start at 0x1fc0_0000 + 6-bit protection value x 64 kb 011 4 mb start at 0x1fc0_0000 + 6-bit protection value x 64 kb 100 8 mb start at 0x1f 80_0000 + 7-bit protection value x 64 kb 101 16 mb start at 0x1f00_0000 + 7-bit protection value x 64 kb 110 32 mb start at 0x1e00_0000 + 7-bit protection value x 64 kb 111 64 mb start at 0x1c00_0000 + 7-bit protection value x 64 kb
27 v rc 4375 system controller 6.5.5 standard space the standard boot rom address space consists of a hardware-protected boot block and a software-protected address ran g e (section 6.5.1). table 14 shows the boot rom memory map durin g standard operation for a 1-mb rom. 6.5.6 simm slot 2 fault-recovery space the fault-recovery boot rom address space can be accessed when the standard flash/boot rom is corrupted or requires updatin g . the controller may be confi g ured to boot from simm slot 2 instead of from boot rom. this is done by drivin g muxad[8] hi g h durin g reset. when the controller detects that this si g nal is hi g h on the risin g ed g e of rst#, the boot rom address ran g e (0x1c00_0000 throu g h 0x1fff_ffff) is mapped into simm slot 2. the actual startin g address and ran g e depends on the boot rom size selected per table 15. when bootin g the system in this manner, the control- ler assumes that simm slot 2 is confi g ured with an 85-ns flash simm. when bootin g from simm slot 2, the boot rom will be forced into address 0x1e00_0000, 0x1e80_0000, or 0x1c00_0000, dependin g on its size. table 17 shows the boot rom memory map durin g fault-recovery mode 1 operation. table 18 shows the required values in simm memory control re g ister 2 for bootin g from simm 2. in this mode, simm memory control re g ister 2 returns the value 0x1f00_100e when read. the hardware protection for the boot rom remains in place even when the rom is remapped for bootin g from simm 2. table 16. standard mode example: 1-mb boot rom memory map a[31:28] address a[27:0] size description 1 e00_0000 to fbf_ffff 28 mb unused fc0_0000 to fc0_ffff 64 kb boot block, hardware protected against writes fc1 0000 to fcf_ffff 1986 kb regular flash rom, software protected only fd0_0000 to fff_ffff 3 mb unused table 17. fault recovery mode example: 1-mb boot rom memory map a[31:28] address a[27:0] size description 1 e00_0000 to ebf_ffff 12 mb unused ec0_0000 to ec0_ffff 64 kb boot block alternate address, h/w protected against writes ec1 0000 to ecf_ffff 960 kb regular flash rom alternate address, s/w protected only ed0_0000 to eff_ffff 3 mb unused f00_0000 to fff_ffff e00_0000 to fff-ffff c00_0000 to fff_ffff 16 mb 32 mb 64 mb simm slot 2, configured for 85-ns flash, double-sided simm slot 2, configured for 85-ns flash, double-sided simm slot 2 configured for 85-ns flash, double-sided
28 v rc 4375 system controller 6.6 pro g rammable rom/prom or general-purpose i/o timin g interface the boot rom interface timin g is pro g rammable. this can be used to connect a slow prom, flash memory, or i/o device. the cycle time is controlled by the general-pur- pose i/o timin g control re g ister at offset 0xe8. the i/o channel ready input si g nal (iochrdy) is optionally used to sense when an i/o device is ready with data so the con- troller can terminate the cycle. if a device has predictable timin g , this si g nal can be pulled hi g h. table 18. simm memory control re g ister 2 values for bootin g from simm slot 2 register field value memory type 2 = flash number of sides 1 = double-sided simm memory enable 1 = enabled address multiplexing mode b100 = 14 x 11 (mux mode 4; bit 12 = 1, bit 5 = 0; bit 4 = 0) edo identification mode 0 = normal mode mda bit 31 during edo id 0 = read only bank interleaving 0 = non-bank interleaved physical address mask 0x00 = size of 64 mb simm memory base memory address note 0x78 = base memory address 0x0f00_0000 note: when booting from simm mode, muxad[8] must be set to one to access simm2.
29 v rc 4375 system controller 6.6.1 general-purpose i/o timing control register the general purpose i/o timin g re g ister len g thens the write and read cycle times of rom, prom, or ram devices of various speed g rades that can be placed on the memory bus. it can be used to interface with an i/o device as well. the address is mapped in the 64-mb allowable boot rom address space; care must be taken in assi g nin g boot block protection ran g es to the i/o device. if a write operation is issued to an i/o device that is erroneously mapped in the boot rom write protection ran g e, the cycle will terminate. when interfacin g with an i/o device, memory addressin g and a data bus move data with prom control si g nals. when interfacin g to a sram device, the timin g can be selected per the device ? s cycle time. care must be taken in mappin g this device so that no writes occur in the boot rom protected area. (section 13.0 con- tains timin g dia g rams.) the iochrdy si g nal can be used to throttle the read or write cycle timin g in addition to pro g rammable timin g . the samplin g of the iochrdy si g nal or the duration of minimum cycle times per their respective bit field values are enabled only when bit 4 is set. the re g ister is at offset 0xe8 in the system memory space. the cpu has read and write access. bits 3:0 read timin g control cycle time control for read operations 0000 = 1 clock cycle 1111 = 16 clock cycles default = 0 bit 4 enable enables activation of the programmable read and write cycle times default = 0 bits 8:5 write timin g control cycle time control for write operations 0000 = 1 clock cycle 1111 = 16 clock cycles default = 0 bit 9 i/odeverr indicates that an i/o device did not respond with iochrdy within the maximum number of clocks pro- g rammed by bits 25:10 of this re g ister. this case assumes that the iochrdy si g nal was driven low by the device and the controller is waitin g for it to g o hi g h. this feature is intended for devices that can be unpredictably slow and the memory bus is allowed to be relinquished after a controlled number of cycles. read-only bits 25:10 i/ochmaxtm determines the maximum number of cycles the con- troller will wait for the device to respond with the iochrdy si g nal before issuin g an error and settin g bit 9. the value could be pro g rammed from 0000 = 1 to ffff = 64 k sysclk cycles. in the event that the counter counts down to zero from its loaded value,
30 v rc 4375 system controller the cycle will terminate with read data 0000,0000 h. the counter is enabled by bit 4 of the i/o timin g control re g ister. the default value of the counter will be 0000,000f. this indicates a cycle time of 15 clocks. bits 31:26 unused hardwired to zero 6.7 base memor y the controller supports up to 64 mb of base memory. this memory, if installed, must include one of the followin g memory devices. ? 4-mb edo (60 ns) ? 16-mb sdram (10 ns) ? 64-mb sdram (10 ns) ? 128-mb sdram (10 ns) to allow pa g es to remain open between accesses to base memory, the controller can perform pa g e comparisons on addresses in the base memory ran g e. see ? note ? in section 6.7.6 on pa g e 35 for an anomaly in the desi g n and its work- around. 6.7.1 base memory control register the base memory control re g ister confi g ures base memory. at reset, all bits in this re g ister are set to 0, and this settin g must not be chan g ed durin g any other type of access (by the cpu, dma, or pci bus) to base memory. if base memory is enabled, software should perform a read immediately before writin g to this re g ister, because write cycles are posted in the controller ? s write fifo, and a read cycle will force the controller to write back the fifo contents before servicin g the read. for reference, a value of 0x0000803b is pro g rammed for an sdram, mux mode 3, 8-mb memory. the base memory control re g ister stores a word at offset 0x0 in the system memory space. it has the followin g fields: bits 1:0 type memory type 0 = edo 1 = invalid, could cause controller to han g 2 = invalid, could cause controller to han g 3 = sdram (16-/64-/128-mb devices) bit 2 dlyevalid when set, in response to a cpu command, this bit delays the evalid si g nal by one clock cycle. the default value is 0. bit 3 en base memory enable 1 = enables base memory 0 = disables base memory bits 5:4 muxmode address multiplexing mode 00 = mux mode 0 01 = mux mode 1 10 = mux mode 2 11 = mux mode 3
31 v rc 4375 system controller see table 9 and table 10 for descriptions of these modes. only mode 3 is allowed for sdram devices. when 64-mb or lar g er devices are used, mux mode 4 is selected (bit 12 = 1); in this case, bits 5:4 are i g nored. bit 6 reserved hardwired to 0
32 v rc 4375 system controller bit 7 pm page mode 1 = enables pa g e mode when enabled, accesses to base memory leave a memory pa g e open (mras# asserted) at the end of the cycle. pa g e mode can only be used when base memory is confi g ured with edo dram; it cannot be used with sdram. 0 = disables pa g e mode accessin g the same memory with address bit 28 set to 0 will cause the controller to close the pa g e at the end of the cycle. when disabled, accesses to base memory close the memory pa g e (mras# ne g ated) at the end of the cycle. bit 8 caslat cas latency selection this bit sets the cas latency in the sdram mode re g ister, where cas latency is defined as either two or three clock cycles. cas latency is set durin g power-up initialization of the sdram mode re g ister settin g . the latency is pro g rammable to optimize the performance of faster memory devices. the default value of this bit is 0. 0 = 3 cycles 1 = 2 cycles bits 11:9 reserved hardwired to 0 bit 12 muxmd4 mux mode 4 bit 13 reserved hardwired to 0 bits 17:14 mask physical address mask determines the size of base memory by maskin g off address bits from the address comparison, be g in- nin g with bit 22. thus, bits 25:22 of the physical address may be masked, providin g an address space between 4 mb (no bits masked) and 64 mb (4 bits masked). masks must be a pattern of left-justi- fied 1s or 0s. a 1 in the mask field indicates that the correspondin g address bit is not masked. address bit 28 is not used in the address comparison; it is only used when pa g e mode is enabled. addresses with address bit 28 cleared to 0 or set to 1 alias to one another. mask bit = 0: bit masked. see the example below. mask bit settin g examples mask bits set address bits decoded bras# selected boe# selected total memory selected 17 16 15 14 27 26 25 24 23 22 1111 dddddd 2 mb 2 mb 4 mb 1110 dddddx 4 mb 4 mb 8 mb 1100 ddddxx 8 mb 8 mb 16 mb 1000dddxxx 16 mb 16 mb 32 mb 0000dd xxxx 32 mb 32 mb 64 mb note: d = decoded; x = not decoded
33 v rc 4375 system controller bits 21:18 reserved hardwired to 0 bits 27:22 baseadd base memory address compared with bits 27:22 of the physical address. a match indicates that the access is to base memory. base memory must not be overlapped with any other resource in the system. bits 31:28 reserved hardwired to 0 6.7.2 base memory page mode the controller can maintain an open memory pa g e (mras# ne g ated) within the base memory ran g e. pa g e mode is enabled by the pm bit (7) in the base memory control re g ister. pa g e mode can only be used when base memory is confi g ured with edo dram; it cannot be used with sdram. when enabled, pa g e mode becomes active durin g accesses to base memory in which address bit 28 is set to 1. if a pa g e is currently open from the previous access, the con- troller performs an address comparison to determine if the current access is within the same pa g e. if so, access is performed usin g the edo pa g e-hit timin g (mcas# only). if the access is not within the same pa g e (a pa g e miss), the mras# si g nal is prechar g ed and a normal memory access occurs. the controller then holds the pa g e open at the end of the cycle. when the base memory is accessed with address bit 28 cleared to 0, pa g e mode is not used. if a pa g e is currently bein g held open, and the current access is a hit, a normal edo pa g e-hit cycle is performed. at the end of the cycle, the pa g e is closed. if the access is a miss, mras# is prechar g ed and the pa g e is closed at the end of the cycle. because address bit 28 is not used to decode base memory addresses, base memory is aliased to two ran g es, 256 mb apart. no other system resources may be placed in this address ran g e, whether or not pa g e mode is enabled.
34 v rc 4375 system controller 6.7.3 base memory prefetching when pa g e mode is enabled for base memory (bit 7 set in the base memory control re g ister), the controller automatically prefetches two words from base memory into a 2- word prefetch fifo. that is, after each read, the controller prefetches two additional words into its internal prefetch fifo. if the processor subsequently attempts a read from an address immediately followin g (sequential to) the address of the last read cycle, the first two words will be supplied from the prefetch fifo. table 19 shows the words that will be placed in the prefetch fifo followin g various types of base memory read cycles. the controller compares the current sysad address with the previous address to determine if the access is sequential. if sequential, the data will be available to the cpu three sysad clocks prior to the nonsequential case. prefetched words are retained in the prefetch fifo if accesses to resources other than base memory are performed between base memory accesses. writes to base memory invalidate the prefetched words and force a sequential miss. 6.7.4 sdram in base memory the base memory space can be confi g ured with either 16- or 64-mb sdram or 4-mb edo modules. this section describes the sdram option. 6.7.5 sdram device configurations the controller supports the followin g (but is not limited to) 16- or 64-mb nec sdram parts and confi g urations in base memory. (fi g ure 6 and fi g ure 7 show examples of sdram connections.) ? 512k x 32 (16-mb) chips, 2 banks of 2k rows, 256 columns (nec no. pd4516161) ? 1m x 16 (16 mb) chips, 2 banks of 2k rows, 256 columns (nec no. pd4516821) ? 2m x 8 (16 mb) chips, 2 banks of 2k rows, 512 columns (nec no. pd4516421) ? 4m x 16 (64 mb) chips (nec # pd456163) ? 2m x 32 (64 mb) chips (nec # pd454323) ? 8m x 8 (64 mb) chips, 4 banks of 4k rows, 512 columns (nec no. pd4564841) ? 16m x 8 (128 mb) chips, 4 banks of 4k rows, 1k columns (nec no. pd45128841) table 19. prefetch fifo contents versus read sizes and ali g nment start address (word address) one-word access two-word access four-word access eight-word access word(s) to cpu prefetched word(s) word(s) to cpu prefetched word(s) word(s) to cpu prefetched word(s) words to cpu prefetched word(s) 0 0 1 0, 1 2, 3 0, 1, 2, 3 4, 5 0, 7 8, 9 1 1 2, 3 not used note not used note not used note not used note not used note not used note 2 2 3 2, 3 4, 5 2, 3, 0, 1 4, 5 not used note not used note 3 3 4, 5 not used note not used note not used note not used note not used note not used note 4 4 5 4, 5 6, 7 4, 5, 6, 7 8, 9 not used note not used note 5 5 6, 7 not used note not used note not used note not used note not used note not used note note: access is illegal because of the alignment.
35 v rc 4375 system controller table 20 shows some of the sdram confi g urations supported for base memory. table 21 shows sdram confi g urations that are not supported in base memory (but may be supported in simm memory). 6.7.6 sdram signal connection example fi g ure 7 shows how the nec 16-mb sdrams are connected for base memory. the bank uses bras# and boe# for chip selects, mcasa[3:0]# for the data i/o masks (dqms), and mda[31:0] for data. banks share the same sdras#, sdcas#, and bwe# si g nals. the bank must be pro g rammed as non-bank interleaved, non-page mode . to do this, clear bit 7 in the base memory control re g ister (otherwise bit 7 has unpredictable results). note: there is an anomaly in the revision 3 desi g n for sdram base memory confi g uration. the followin g two methods can be used as a workaround to access 16 mb of address space: confi g ure the control re g ister for 32 mb of address space. in this case, bras# will be valid for up to 16-mb addresses. confi g ure the control re g ister for 16 mb of address spaces; use si g nal bras# to access the lower 8 mb, and use si g nal boe# to access the upper 8 mb. example: control/word for 8 devices, 2 m x 8 or g anization = 0003_003b hx. table 20. base memory sdram confi g urations supported memory size sysad address bits required banks sides sysad[25:22] mask bits nec part number 4 mb 21:0 2, 1 m x 16 single 1111 pd4516821g5-a10 8 mb 22:0 4, 2 m x 8 single 1110 pd4516421g5-a10 16 mb 23:0 2, 4 m x 16 single 1100 pd4564163-a10 32 mb 25:0 4, 8 m x 8 single 0000 pd4564841 64 mb 25:0 8, 16 m x 4 single 0000 pd4564441 table 21. base-memory sdram confi g uration not supported memory size sysad address bits required banks sides sysad[25:21] mask bits nec part number 16 mb 23:0 8, 4 m x 4 single 1100 not supported in base mem- ory
36 v rc 4375 system controller fi g ure 6. sdram connections for base memory (example) 4m x 16 sdram v rc 4375 system controller we# cas# ras# cs# clk ldqm udqm a[11:0] dq[15:0] sdcas# sdras# bras# sdclk[0] mcasa[0]# mcasa[1]# bwe# muxad[11:0] mda[31:0] 4m x 16 sdram we# cas# ras# cs# clk ldqm udqm a[11:0] dq[15:0] sdclk[1] mcasa[2]# mcasa[3]# 4m x 16 sdram we# cas# ras# cs# clk ldqm udqm a[11:0] dq[15:0] 4m x 16 sdram we# cas# ras# cs# clk ldqm udqm a[11:0] dq[15:0] boe# lower 16 mb upper 16 mb cke cke# cke cke high high high high
37 v rc 4375 system controller fi g ure 7. sdram connections for simm 1 and simm 2 (example) 6.7.7 sdram banks and burst types the terms bank and burst type have multiple meanin g s in memory desi g n usin g sdram chips. banks referenced with respect to memory modules differ from banks inside an sdram. memory modules are external and two or more form a bank. for sdrams, muxad[11] serves as the bank select for all chips on a module. the burst type of a sin g le sdram chip is pro g rammed in the chip ? s mode re g ister to be either interleaved or sequential . this concept relates only to the word order in which data is read into and written out of the sdram chip. the concept does not relate to the number of words transferred in a g iven clock cycle. the burst type for all sdram chips attached to the controller is confi g ured durin g memory initialization (section 6.11). 4m x 16 sdram v rc 4375 system controller we# cas# ras# cs# clk ldqm udqm a[11:0] dq[15:0] sdcas# sdras# mras0# sdclk[0] mcas[0]# mcas[1]# mwe# muxad[11:0] mda[31:0] 4m x 16 sdram we# cas# ras# cs# clk ldqm udqm a[11:0] dq[15:0] sdclk[1] mcas[2]# mcas[3]# 4m x 16 sdram we# cas# ras# cs# clk ldqm udqm a[11:0] dq[15:0] 4m x 16 sdram we# cas# ras# cs# clk ldqm udqm a[11:0] dq[15:0] mras[2]# sdcke[1] sdcke[0] cke cke cke cke simm 1 simm 2
38 v rc 4375 system controller 6.7.8 sdram word ordering table 22 shows the word address order for an 8-word instruction cache line fill from sdram. this order is determined by the sdram chips ? burst type, which is pro- g rammed durin g memory initialization (section 6.11). the controller pro g rams the burst type and word order in the same way for all sdram chips connected to it (in both simm and base memory ran g es). the controller initializes any sdram chips in the 8-word burst len g th mode. because of this, the controller always reads 8 words from sdram, re g ardless of the data width requested. however, the controller only returns the requested number of words to the cpu or pci bus master; remainin g words are either stored in the controller ? s internal base memory prefetch fifo (section 6.7.3) or discarded. the cpu or pci bus master can write any number of bytes, and the controller automatically issues a burst stop or prechar g e termination command to the sdram in order to store only the correct num- ber of bytes in the sdram. 6.8 simm/dimm the controller supports four pro g rammable address ran g es for independently con- trolled 72-pin simm or dimm. simm slots 1 and 2 are connected to the mda bus. the two simm slots may be confi g ured with sdram, edo dram, fast-pa g e dram, or flash memory modules. to accommodate simm loadin g , f244 or f245 buffers must be used on the controller ? s muxad si g nals. 6.8.1 simm memory control registers the confi g uration of each simm is controlled by its own simm control re g ister. the control re g ister for simm slot 1 is called simm memory control re g ister 1, and so on for simm slot 2. the re g isters are initialized to 0 at reset. they must not be chan g ed durin g any other type of access (cpu, dma, or pci bus) to the simm memory space. if simm memory is enabled, software should perform a read immediately before writin g to this re g ister, because write cycles are posted in the controller ? s write fifo and a read cycle will force the controller to write back the fifo contents before servicin g the read cycle. the controller can be confi g ured to force the system to boot from simm slot 2 instead of from boot rom. (fi g ure 7 on pa g e 37 shows an example of sdram connections for simm. for details, and for the values in simm memory control re g ister 2, see section 6.5.4 throu g h section 6.5.6. table 22. sdram word order for instruction cache line fill word address a[4:2] sdram chip burst type sequential note interleaved 000 not supported 0-1-2-3-4-5-6-7 001 not supported 1-0-3-2-5-4-7-6 010 not supported 2-3-0-1-6-7-4-5 011 not supported 3-2-1-0-7-6-5-4 100 not supported 4-5-6-7-0-1-2-3 101 not supported 5-4-7-6-1-0-3-2 110 not supported 6-7-4-5-2-3- 0-1 111 not supported 7- 6- 5- 4-3- 1-0 note: the controller does not support sequential bursts for sdrams. it assumes that all sdrams are initialized to the interleaved bursts, using a burst length of 8 words.
39 v rc 4375 system controller the two simm memory control re g isters are each 4 bytes wide, at offsets 0x4 and 0x0c. each contains the followin g fields: bits 1:0 type memory type 0 = edo dram 1 = fast-pa g e dram 2 = flash 3 = sdram (16 mb or 64 mb) bit 2 sd number of sides 1 = two sided. see section 6.8.4 on pa g e 41. 0 = sin g le sided bit 3 en simm memory enable 1 = enables simm memory 0 = disables simm memory bits 5:4 muxmode address multiplexing modes 0, 1, 2, or 3 00 = mux mode 0 01 = mux mode 1 10 = mux mode 2 11 = mux mode 3 see table 9 and table 10 for descriptions of these modes. mux mode 4 is confi g ured by clearin g bits 5:4 to 0 (as in mux mode 0) and settin g bit 12. bit 6 id edo identification mode 1 = places the controller into the edo identification mode, which is a special boot sequence. this bit is used in conjunction with bit 7. bit 7 d31 value of mda bit 31 during edo identification mode read only. the state of bit 31 on the mda bus, at the time bit 6 of this re g ister (the id bit) is set to 1 (while the edo identification sequence is performed). at all other times, the value of this bit is 0. this bit is used only in conjunction with bit 6 (the id bit). bit 8 cas latency 1 = 2 cycles 0 = 3 cycles for cas latency of 2, initial latency is reduced by two more clock cycles in each case. upon power-up reset, muxad[20] sets cas latency for base and simm memory. this bit should be set to the same value as muxad[20].
40 v rc 4375 system controller bit 9 burst access cycle control for access time for subsequent words after the initial word access in sdram simm memory durin g burst access. for a read access of 8 words, the access time for cas latency of 3 would be as follows. 0 = 10-2-2-2-2-2-2-2 (the first 10 cycles include the first word.) 1 = 9-1-1-1-1-1-1-1 (the first 9 cycles include the first word.) a correspondin g performance improvement is achieved in write cycles as well (table 11). bits 11:10 reserved hardwired to 0 bit 12 mux mode 4 address multiplexing mode 4 1 = mux mode 4 (used for 64-mb sdram only) 0 = mux modes 0, 1, 2, or 3, as determined by bits 5:4, above. see table 10 for a description of mux mode 4. mux mode 5 and mux mode 6 are determined per bits 12, 5, and 4 as follows. mux mode bit 12 bit 5 bit 4 5 1 0 1 6 1 1 0 4 1 0 0 bits 18:13 mask physical address mask determines simm memory size by maskin g off address bits from the address comparison, be g in- nin g with bit 21. thus, bits 26:21 of the physical address may be masked, providin g an address space between 2 mb (no bits masked) and 128 mb (6 bits masked). masks must be a pattern of left-jus- tified 1s or 0s. a 1 in the mask field indicates that the correspondin g address bit is not masked. bits 20:19 reserved hardwired to 0 bits 27:21 simmadd simm memory base memory address this 7-bit field (when appended with bits 31:28, which are always 0) is compared with the most-si g - nificant 11 bits of the physical address. a match indi- cates that the access is to the correspondin g simm. bit 28 is not used in the address comparison. bits 31:28 reserved hardwired to 0 6.8.2 sdram in simm the simm address ran g es can be confi g ured with flash, sdram, edo, or fast-pa g e simm or dimm. the system can boot from flash memory in slot 2. muxad bits 19:18 define the size of the flash memory per table 30.
41 v rc 4375 system controller 6.8.3 sdram device configurations the controller supports the followin g (but is not limited to) 16-/64-/128-mb nec sdram parts and confi g urations in simm memory. ? 512 k x 32 (16-mb) chips, 2 banks of 2 k rows, 256 columns (nec # pd4516161) ? 1 m x 16 (16-mb) chips, 2 banks of 2 k rows, 256 columns (nec # pd4516161) ? 2 m x 8 (16-mb) chips, 2 banks of 2 k rows, 512 columns (nec # pd4516821) ? 8 m x 8 (64-mb) chips, 4 banks of 4 k rows, 512 columns (nec # pd4564841) ? 4 m x 16 (64-mb) chips (nec # pd456163) ? 2 m x 32 (64-mb) chips (nec # pd454323) ? 16 m x 8 (128-mb) chips, 4 banks of 4 k rows, 1 k columns (nec # pd45128841) ? 16 m x 4 (64-mb) chips, 4 banks of 4 k rows, 1 k columns (nec # pd4564441) table 23 shows some of the sdram confi g urations supported for base memory. 6.8.4 dimm the 100-pin dimm packa g e is the only dimm packa g e supported. each dimm has four chip-select si g nals: s0, s1, s2, and s3. in noninterleaved (sin g le-bank) confi g urations, each module uses only its two front-side chip-select inputs (s0 and s2). in one bank confi g uration, each of the controller si g nals used as a chip select can be connected to a maximum of four chip-select inputs on a sin g le sdram chip (a dimm module typically carries between 1 and 16 such chips). table 23. simm memory sdram confi g uration examples memory size sysad address bits required bank a sides sysad[25:21] mask bits nec part number 4 mb 21:0 2, 1 m x 16 single 11110 pd4516821g5-a10 8 mb 22:0 2, 1 m x 16 double 11100 pd4516821g5-a10 8 mb 22:0 4, 2 m x 8 single 11100 pd4516421g5-a10 16 mb 23:0 4, 2 m x 8 double 11000 pd4516421g5-a10 16 mb 23:0 8, 4 m x 4 single 11000 not available
42 v rc 4375 system controller 6.8.5 sdram signal connections fi g ure 8 shows how sdram and simm or dimm packa g es are connected in the simm memory ran g e. this example shows six controller si g nals used as chip selects: mras[3:0]# and sdcs[1:0]. normally, ei g ht controller si g nals would be used as chip selects, as shown in table 24 (two si g nals for each side of each module), but two of the si g nals in fi g ure 8 (mras[1#] and mras[3]#) serve two modules each, due to the lim- ited number of si g nals available on the controller. mras[1]# and mras[3]# may need bufferin g . the available chip selects from the controller can be connected in any way to the modules; software need not be involved in these connections. if simm memory control re g isters 1 and 2 are pro g rammed to implement non-bank- interleaved memory, simm 1 and simm 2 contain both even and odd words. fi g ure 8. sdram connections for simm memory (example) sdram 1 (low) v rc 4375 system controller we# cas# ras# cs# cke clk dqm a[11:0] or [13:0] dq[31:0] sdcas# sdras# mras[1:0]# sdcke[0] sdclk[0] mcasa[3:0]# mwe# muxad[11:0] or [13:0] mda[31:0] sdram 2 (high) we# cas# ras# cs# cke clk dqm a[11:0] or [13:0] dq[31:0] mras[3:2]# sdcke[1] sdclk[1] mcasa[3:0]# f245
43 v rc 4375 system controller 6.8.6 sdram loads and signals table 24 shows the number of device loads and si g nals used by various sin g le-sided (simm) and double-sided (dimm) confi g urations. in this table, one sdram device load equals about 8 pf. the followin g dimm/simm modules are also supported. ? mc-454ad644, 32 mb, 2 m x 64 x 2, 3.3 v, pd4516821 (device) ? mc-454cb645, 32 mb, 4 m x 64 x 1, 3.3 v, pd4564163 (rev. e) (device) ? mc-452ab644, 16 mb, 2 m x 64 x 1, 3.3 v, pd4516821 (device) ? mc-452ad644, 16 mb, 1 m x 64 x 2, 3.3 v, pd4516161 (device) 6.8.7 sdram word ordering the word-address orderin g for cache line fills from sdram in the simm memory ran g e is the same as the word orderin g in the base memory ran g e (section 6.7.8 on pa g e 38). table 24. loads and si g nals for simm or dimm signal to simm or dimm number of loads 1 number of signals x4 x8 x16 x32 1 side 2 sides 1 side 2 sides 1 side 2 sides 1 side 2 sides 1 side 2 sides ras# 8 n/s 2 482412 1 1 cas# 8n/s482412 1 1 we# 8n/s482442 1 1 dqm 2 n/s 1 2 1 2 1 2 4 4 cs# 4 n/s 2 2 1 1 1 1 2 3 4 3 data 1n/s121212 16 16 address 8 n/s 4 8 2 4 1 2 12 or 14 4 12 or 14 4 clk 4 n/s 4 4 2 2 1 1 2 5 2 5 cke 4 n/s 4 4 2 2 1 1 2 6 2 6 notes: 1. one device load equals 8 pf. 2. n/s = not supported. 3. dimm have four chip-select signals (s0, s1, s2, and s3). in single-bank configurations, (noninterleaved) only two are used: s0 and s2 on the front side. each controller signal used for chip selection can connect to a maximum of four dimms. 4. twelve address bits for 16-mb sdram chips; 14 address bits for 64-mb sdram chips. 5. each simm or dimm has two clock signals (clk[1:0]). there can be a maximum of eight sdram devices per dimm, in either single- or double-bank configurations. each clock signal connects to four sdrams through two resistors. 6. each simm or dimm has two clock enable signals (cke[1:0]). there can be a maximum of eight sdram devices per simm, in either single- or double-bank configurations. each clock enable signal connects to four sdrams.
44 v rc 4375 system controller 6.9 dram refresh the controller supports cas-before-ras (cbr) dram refreshin g to all dram address ran g es. the refresh clock is derived from the system clock; its rate is deter- mined by a pro g rammable 12-bit counter in the dram refresh counter re g ister, described below. 6.9.1 dram refresh counter register the dram refresh counter re g ister stores a word at offset 0x58. at reset, all bits in this re g ister are set to 0. the re g ister contains the followin g fields: bits 11:0 cntr refresh counter value the refresh counter counts down from this value at the system clock rate. the refresh pulse is g enerated upon reachin g 0. the reset value is 0. a value of 0x400 is equivalent to approximately 15 ms at a 66- mhz clock rate. dram refreshin g is enabled and dis- abled in the power-on memory initialization re g ister (section 6.11.1). bits 31:12 reserved hardwired to 0 6.9.2 refresh mechanism the refresh lo g ic requests access to dram from the internal bus-arbitration lo g ic each time the counter reaches 0. the refresh lo g ic can accumulate up to a maximum of 8 refresh requests while it is waitin g for the bus. once the refresh lo g ic owns the bus, all accumulated refreshes are performed to base memory and any installed simms, and no other accesses (cpu, dma, or pci) are allowed. refreshes are sta gg ered by one clock (there is at least one bus clock between transitions on any pair of mras# si g - nals). refresh automatically closes all open dram pa g es and clears the base memory prefetch fifo. refresh is disabled whenever the id bit is set in any of the simm memory control re g isters, althou g h refreshes will accumulate normally even when refresh is disabled. accumulated refreshes are performed as soon as refreshin g is re- enabled. 6.10 cpu to memor y write fifo the controller has an 8-word cpu-to-memory write fifo. (pci writes to memory are buffered in the pci tar g et fifo, described in section 7.4.2.) this fifo accepts writes at the maximum cpu speed. a sin g le address is held for the buffered write cycle, allowin g the bufferin g of a sin g le write transaction. that transaction may be a word, double-word, or 4-word data cache write-back. when a word is placed in the fifo by the cpu, the controller attempts to write the fifo ? s contents to memory as quickly as possible. if the next cpu read or write cycle is addressed to memory, the controller ne g ates eok#, thus causin g the next cpu transaction (read or write) to stall until the controller empties its fifo. if the next cpu transaction (read or write) is addressed to a pci bus tar g et, the controller asserts eok#, thus allowin g the cpu transaction to complete. if, upon completion of such a cpu transaction to a pci bus tar g et, the con- troller ? s fifo is still not empty, the controller will a g ain ne g ate eok# to stall the next cpu write until the fifo contents are written back to memory.
45 v rc 4375 system controller 6.11 memor y initialization to be accessed, memory must first be initialized by software at power-on. the follow- in g sections describe the power-on memory initialization re g ister and the initialization sequence. 6.11.1 power-on memory initialization register the power-on memory initialization re g ister confi g ures sdram in both the base and simm memory address ran g es. at reset, the re g ister is set to 0 and it must be confi g - ured before memory is accessed after power-on. the re g ister stores a word at offset 0x78 and has the followin g fields: bit 0 mode sdram mode set 1 = enables writin g to the mode re g isters on all sdram chips. when this bit is set, the controller automatically provides the data that confi g ures all sdram chips on all simms or dimms for a burst len g th of 8 words and cas# latency of 3 cycles. 0 = disables writin g to mode re g isters on sdrams bit 1 prechar g e sdram precharge 1 = prechar g e settin g this bit causes the controller to issue two sequential prechar g e commands to any sdrams in the base and simm memory ran g es. do not set this bit durin g normal system operation. it should be set only durin g the power-on process. 0 = no prechar g e this bit is cleared automatically by the controller at the end of the two prechar g e commands. bit 2 refresh refresh enable (sdram and dram) 1 = refresh settin g this bit causes the controller to issue ei g ht sequential automatic refresh (cas#-before-ras#) commands to any sdrams in the base and simm memory ran g es. this is required durin g sdram ini- tialization. the refresh commands are issued only if the sdram memory type has been pro g rammed in the base or simm memory ran g es. this bit also enables refresh of drams. 0 = no refresh (default value at power-on or reset.) this bit is cleared automatically by the controller at the end of the ei g ht automatic refresh commands. bits 31:3 reserved hardwired to 0
46 v rc 4375 system controller 6.11.2 power-on initialization sequence follow this sequence to confi g ure memory at power-on. 1. initialize the 0f00_007c and 0f00_0080 re g isters to zero. 2. pro g ram the base memory control re g ister (see section 6.7.1). 3. pro g ram the two simm memory control re g isters if these address ran g es are used (see section 6.8.1). 4. if sdram is installed in any address ran g e, set the prechar g e bit (bit 1) in the power-on memory initialization re g ister. 5. if sdram devices are used, wait for ei g ht cpu clocks. (this is required to finish the sdram prechar g e sequence initiated in step 4.) 6. set the refresh bit (bit 2) in the power-on memory initialization re g ister. this enables refresh for all sdram and dram, and (if sdram is installed) it initiates 8 sequential sdram refresh cycles. 7. wait for step 6 to complete. if sdram is installed, this is approximately 60 cpu clocks (8 sdram refresh cycles). 8. if sdram is installed in any address ran g e, set the mode bit (bit 0) in the power-on memory initialization re g ister. this confi g ures all sdram chips for a burst len g th of ei g ht words and cas# latency of 3 cycles. 9. wait for nine cpu clock cycles and step 8 to complete. 10. pro g ram the dram refresh counter re g ister (section 6.9.1). at this point, memory is ready to use. all other confi g uration re g isters in the controller should then be pro g rammed before commencin g normal operation. 6.12 uart re g isters the v rc 4375 controller uses the nec ny16550l me g afunction macro as its internal universal asynchronous receiver/transmitter (uart). this uart is functionally iden- tical to the national semiconductor pc16550d ? me g afunction macro. refer to the nec megafunction: ny16550l user ? s manual for more information and pro g rammin g details. this section describes the available uart re g isters. the modem control function is not supported in this version of the uart, so the re g isters relatin g to those si g nals are not relevant. refer to the si g nal summary (section 3.0) for uart si g nals that are sup- ported. note: after writin g a value or a series of values in any re g ister or set of re g isters, a write to the scratch pad re g ister must be made.
47 v rc 4375 system controller 6.12.1 uart receiver data buffer register (uartrbr) bits 7:0 udata uart data (read only) when the divisor latch access bit (dlab) = 0 bits 31:8 reserved hardwired to 0 reset value: 0x0000 00xx this re g ister holds receive data. it is only accessed when the divisor latch access bit (dlab) is cleared in the uartlcr. 6.12.2 uart transmitter data holding register (uartthr) bits 7:0 udata uart data (read only) when dlab = 0 bits 31:8 reserved hardwired to 0 reset value: 0x0000 00xx this re g ister holds transmit data. it is only accessed when the divisor latch access bit (dlab) is cleared in the uartlcr. 6.12.3 uart interrupt enable register (uartier) this re g ister is used to enable uart interrupts. it is only accessed when dlab is set in the uartlcr. interrupt control and status re g ister (section 9.1.2) uartinten bit 22 is a g lobal enable for interrupt sources enabled by this re g ister. bit 0 erbfi uart receive data buffer full interrupt 1 = enables receive data available interrupts 0 = disables receive data available interrupts receive data buffer full state is reported to uartlsr. bit 1 erbei uart transmitter buffer empty interrupt 1 = enables transmitter buffer empty interrupt 0 = disables transmitter buffer empty interrupt transmitter buffer empty state is reported to uartlsr. bit 2 erbfi uart line status interrupt 1 = enables line status error interrupt 0 = disables line status error interrupt line status error interrupt state is reported to uartlsr. bit 3 erbfi uart modem status change interrupt 1 = enables modem status chan g e interrupt 0 = disables modem status chan g e interrupt modem status chan g es are reported to uartmsr[3:0]. bits 7:4 reserved hardwired to 0 bits 31:8 reserved hardwired to 0
48 v rc 4375 system controller reset value: 0x0000 00xx 6.12.4 uart divisor latch lsb register (uartdll) bits 7:0 divlsb uart divisor latch (least-significant byte) only accessed when dlab = 1 in uartlcr bits 31:8 reserved hardwired to 0 reset value: 0x0000 00xx 6.12.5 uart divisor latch msb register (uartdlm) bits 7:0 divmsb uart divisor latch (most-significant byte) only accessed when dlab = 1 in uartlcr bits 31:8 reserved hardwired to 0 reset value: 0x0000 00xx 6.12.6 uart interrupt id register (uartiir) bit 0 intpendl 0 = uart interrupt pendin g (read only) 1 = no uart interrupt pendin g bits 3:1 uiid # only valid when intpendl = 0. uiid[3:1]#: priority: source of interrupt: 0x3 hi g hest receiver line status: overrun error, parity, framin g error, or break interrupt 0x2 second hi g hest received data available: receiver data available or tri gg er level reached 0x6 third hi g hest character time-out indication: no chan g e in receiver fifo durin g the last four character times and fifo is not empty 0x1 fourth hi g hest transmitter holdin g re g ister is empty 0x0 fifth hi g hest modem status: cts_l, dsr_l or dcd_l bits 5:4 reserved hardwired to 0 bits 7:6 ufifoen uart fifo is enabled (read only) both bits are set to 1 when the transmit/receive fifo is enabled and the ufifoen0 bit is set in the uartscr. bits 31:8 reserved hardwired to 0
49 v rc 4375 system controller reset value: 0x0000 00xx 6.12.7 uart fifo control register (uartfcr) bit 0 ufifoen0 uart fifo enable (write only) 1 = enables receive and transmit fifos 0 = disables and clears receive and transmit fifos bit 1 urfrst uart receiver fifo reset (write only) 1 = clears receive fifo and reset counter 0 = does not clear receive fifo and reset counter bit 2 utfrst uart transmitter fifo reset (write only) 1 = clears transmit fifo and reset counter 0 = does not clear transmit fifo and reset counter bits 5:3 reserved hardwired to 0x0 bits 7:6 urtr uart receive fifo trigger level rcvr trig lvl bits[7:6] number of bytes in receiver fifo 0x0 01 0x1 04 0x2 08 0x3 14 when the tri gg er level is reached, a receive buffer full interrupt is g enerated, if enabled by the erbfi bit in the uartier. bits 31:8 reserved hardwired to 0x0000 00 reset value: 0x0000 00xx
50 v rc 4375 system controller 6.12.8 uart line control register (uartlcr) bits 1:0 wls word length select 11 = 8 bits 10 = 7 bits 01 = 6 bits 00 = 5 bits bit 2 stb number of stop bits enabled 1 = enables 2 bits, except 1.5 stop bits for 5 words 0 = enables 1 bit bit 3 pen parity enable 1 = generates parity on writes, checks it on reads 0 = does not g enerate or check parity for the uart, even or odd parity can be g enerated or checked, as specified in bit 4 (eps). this is differ- ent from the parity on the cpu, memory, or pci bus, which is considered even parity. bit 4 eps parity select 1 = selects even parity 0 = selects odd parity bit 5 usp stick parity 1 = forces uart_txdrdy# si g nal output low 0 = generates and checks parity normally this bit is only valid when the parity enable (pen) bit is set. bit 6 usb set break 1= forces uart_txdrdy# si g nal output low 0 = generates normal operation of uart_txdrdy si g nal output bit 7 dlab divisor latch access 1 = accesses baud-rate divisor at offset 0x88 0 = accesses txd/rxd and ie at offset 0x88 when this bit is set, uart accesses the uart divi- sor latch lsb re g ister (uartdlm) at offset 0x88. when cleared, the uart accesses the receiver data buffer re g ister (uartrbr) on reads at offset 0x84, the uartthr on writes at offset 0x84, and uartier on any accesses at offset 0x88. bits 31:8 reserved hardwired to 0x0000 00 reset value: 0x0000 00xx
51 v rc 4375 system controller 6.12.9 uart modem control register (uartmcr) this re g ister controls the state of external uart_dtr# and uart_rts# modem- control si g nals and of the loopback test. bit 0 dtr data terminal ready 1 = ne g ates uart_dtr# si g nal 0 = asserts uart_dtr# si g nal bit 1 rts request to send 1 = ne g ates uart_rts# si g nal 0 = asserts uart_rts# si g nal bit 2 out1 out 1 1 = out1# state active 0 = out1# state inactive (reset value) this is a user-defined bit that has no associated external si g nal. software can write to the bit, but this has no effect. bit 3 out2 out 2 1 = out2# state active 0 = out2# state inactive (reset value) this is a user-defined bit that has no associated external si g nal. software can write to the bit, but this has no effect. bit 4 loop loopback test 1 = enables loopback 0 = enables normal operation this is an nec internal test function. bits 7:5 mbz must be zero. hardwired to 0x0. bits 31:8 mbz must be zero. hardwired to 0x0000 00.
52 v rc 4375 system controller 6.12.10 uart line status register (uartlsr) this re g ister reports the current state of the transmitter and receiver lo g ic. bit 0 dr receive data ready 1 = receive data buffer full 0 = receive data buffer not full receive data is stored in the uart receiver data buffer re g ister (uartrbr). bit 1 oe receive data overrun error 1 = overrun error on receive data 0 = no overrun error bit 2 pe receive data parity error 1 = parity error on receive data 0 = no parity error bit 3 fe receive data framing error 1 = framin g error on receive data 0 = no framin g error bit 4 bi break interrupt 1 = break received on uart_rxdrdy# si g nal 0 = no break bit 5 thre transmitter holding register empty 1 = transmitter holdin g re g ister empty 0 = transmitter holdin g re g ister not empty transmit data is stored in the uart transmitter data holdin g re g ister (uartthr). bit 6 temt transmitter empty 1 = transmitter holdin g and shift re g isters empty 0 = transmitter holdin g or shift re g ister not empty bit 7 rferr receiver fifo error 1 = parity, framin g , or break error in receiver buffer 0 = no parity, framin g , or break error bits 31:8 mbz must be zero. hardwired to 0x0000 00.
53 v rc 4375 system controller 6.12.11 uart modem status register (uartmsr) this re g ister reports the current state of and chan g es in various control si g nals. bit 0 dcts delta clear to send 1 = uart_cts# state chan g ed since this re g ister was last read 0 = uart_cts# state did not chan g e bit 1 ddsr delta data set ready 1 = uart_dsr# input si g nal chan g ed since this re g ister was last read 0 = uart_dsr# input si g nal did not chan g e bit 2 teri trailing-edge ring indicator 1 = ri# state chan g ed since this re g ister was last read 0 = ri# state did not chan g e ri# is not implemented as an external si g nal, so this bit is never set by the controller bit 3 ddcd delta data carrier detect 1 = uart_dcd# state chan g ed since this re g ister was last read 0 = uart_dcd# state did not chan g e bit 4 cts clear to send 1 = uart_cts# state active 0 = uart_cts# state inactive this bit is the complement of the uart_cts# input si g nal. if the loop bit in the uart modem control re g ister (uartmcr) is set to 1, the cts bit is equivalent to the rts bit in the uartmcr. bit 5 dsr data set ready 1 = uart_dsr# state active 0 = uart_dsr# state inactive this bit is the complement of the uart_dsr# input si g nal. if the loop bit in the uart modem control re g ister (uartmcr) is set to 1, the dsr bit is equivalent to the dtr bit in the uartmcr. bit 6 ri ring indicator 1 = not valid 0 = always reads 0 this bit has no associated external si g nal. bit 7 dcd data carrier detect 1 =uart_dcd# state active 0 = uart_dcd# state inactive this bit is the complement of the uart_dcd# input si g nal. if the loop bit in the uart modem control re g ister (uartmcr) is set to 1, the dcd bit is equivalent to the out2 bit in the uartmcr. reset value: 0x0000 00xx
54 v rc 4375 system controller 6.12.12 uart scratch register (uartscr) this re g ister contains a uart reset bit plus ei g ht bits of space for any software use. bits 7:0 uscr uart scratch register available to software for any purpose. bit 8 ureset uart reset 1 = resets uart 0 = no reset reset value: 0x0000 0xxx to achieve a desired baud rate, the uart divisor latch must be properly pro g rammed. the relationship between uart clock frequency, baud rate, and divisor value is: baud_rate = sys_clock_freq / (divisor_value x 16 x 8) example: to calculate a divisor value for a desired baud rate of 9600 and sysclk = 66 mhz: divisor = 66000000 hz/(9600 x 16 x 8) = 53.7 decimal = 36 hex table 25 g ives divisor values for several input clock frequencies. note: the actual baud rate may vary si g nificantly from the desired baud rate. table 25. input clock frequency divisor values baud rate divisor % error divisor % error divisor % error divisor % error 50 2304 10368 9216 7680 75 1536 6912 6144 5120 110 1047 0.026 4713 0.006 4189 0.002 3491 0.003 134.5 857 0.058 3854 0.007 3426 0.001 2855 0.001 150 768 3456 3072 2560 300 384 1728 1536 1280 600 192 864 768 640 1200 96 432 384 320 1800 64 288 256 213 0.156 2000 58 0.690 259 0.077 230 0.174 192 2400 48 216 192 160 3600 32 144 128 107 0.312 4800 24 108 96 80 7200 16 72 64 53 0.629 9600 12 54 48 40 19,200 6 27 24 20 38,400 3 14 3.571 12 10 57,600 2 9 8 7 4.762
55 v rc 4375 system controller 7.0 pci bus interface the controller ? s pci bus interface complies with the pci local bus specification, revi- sion 2.1 . complete master and tar g et capabilities are supported. no external lo g ic or bufferin g is necessary. the interface implements 3.3-v, pci-compliant pads (5-v toler- ant) usin g the nec cmos-9 process technolo g y. all pci interface electrical character- istics (loadin g , drive, impedance, capacitance, and so forth) comply fully with the pci specification. the pci bus interface contains two separate data paths ? one for cpu access and one for dma. each path has its own data pipeline and fifo, and each one operates inde- pendently of the other. the fifos in this interface include: ? 4-word (16-byte) bidirectional pci master fifo (cpu is a pci bus master) ? 8-word (32-byte) bidirectional pci tar g et fifo (memory is a pci bus tar g et) ? 8-word (32-byte) bidirectional dma fifo (pci to memory or memory to pci) 7.1 pci bus timin g the pci bus operates at 33 mhz and supports full burst transfers; no wait states are required with adequately fast memory. peak pci bus bandwidth is 133 mb/s. the pci bus is synchronized to the sysad bus, with the sysad bus clock runnin g at two times the pci clock.
56 v rc 4375 system controller 7.2 pci commands supported table 26 summarizes the pci command codes and whether they are supported or not supported by the controller when it is functionin g as a master and as a tar g et. 7.3 pci master transactions (cpu to pci bus) the controller supports bidirectional data transfers between the cpu and pci bus tar- g ets by becomin g a pci bus master. the cpu obtains access to pci bus resources (summarized in table 7 on pa g e 16) by accessin g a local physical address that corre- sponds to one of three pci address windows: pci master address window 1 pci master address window 2 pci master i/o window these re g isters are at offsets 14, 18, and 24, respectively (see table 6). they are con- fi g ured throu g h the pci master address window re g isters, described below. table 26. pci commands cbe#[3:0] command command supported when controller is master command supported when controller is target 0000 interrupt acknowledge no ignored 0001 special cycle no ignored 0010 i/o read yes, via pci master i/o win- dow (see section 7.3) yes; must be in add-on board mode and hit pci i/o base memory address range 0011 i/o write yes, via pci master i/o win- dow (see section 7.3) yes; must be in add-on board mode and hit pci i/o base memory address range 010x reserved ? ignored 0110 memory read yes, via pci master address windows (see section 7.3) yes; must hit a pci target ad- dress window (see section 7.4) 0111 memory write yes, via pci master address windows (see section 7.3) yes; must hit a pci target ad- dress window (see section 7.4) 100x reserved ? ignored 1010 configuration read yes, via pci configuration reg- isters (see section 7.5) yes, via pci configuration reg- isters (see section 7.5) 1011 configuration write yes, via pci configuration reg- isters (see section 7.5) yes, via pci configuration reg- isters (see section 7.5) 1100 memory read multiple no aliased to memory read 1101 dual address cycle no ignored 1110 memory read line no aliased to memory read 1111 memory write and invalidate no aliased to memory write
57 v rc 4375 system controller 7.3.1 pci master address window registers the three pci master address window re g isters described above have the same structure. at reset, they are set to 0. a re g ister must not be chan g ed while a write is posted to the pci bus. there must be at least two cpu clocks between writin g to this type of re g ister and performin g a pci access throu g h the window mapped by the re g - ister. each of the three pci master address window re g isters contains the followin g fields. bits 7:0 pciadd pci address this 8-bit field replaces the most-si g nificant 8 bits of the address defined in the ladd field when the address is transmitted to the pci bus. bits masked by the mask field (bits 19:13) are directly transferred from the cpu ? s sysad bus (rather than from the pciadd field). bits 11:8 reserved hardwired to 0 bit 12 e enable 1 = enables access to the pci bus throu g h the address window specified in this re g ister 0 = disables access bits 19:13 mask physical address mask this mask is used to determine the size of the pci window. it masks 7 address bits from the address comparison, be g innin g with bit 24. thus, bits 30 to 24 may be masked, providin g an address block size between 16 mb (no bits masked) and 2 gb (7 bits masked). a 0 in a mask bit indicates that the corre- spondin g address bit is masked. bits 23:20 reserved hardwired to 0 bits 31:24 ladd local base memory address this 8-bit field is compared with the most-si g nificant 8 bits of the physical cpu address, conditioned on the mask field. a match indicates that the access is to the pci bus. ladd should not be pro g rammed to overlap pci space with local resources (memory, re g isters or boot rom) or pci tar g et windows; this would result in improper operation.
58 v rc 4375 system controller 7.3.2 pci master transaction details transfers between the cpu and pci bus are buffered throu g h a 4-word bidirectional pci master fifo. this fifo stores data and latches the address and byte enables for one cpu-to-pci read or write transaction. when the cpu accesses an address in the window defined by the ladd fields (bits 31:24) of either of the two pci master address window re g isters or the pci master i/o window, the data is transferred to and from the pci bus throu g h the fifo. the fifo improves performance and provides a mecha- nism for resolvin g deadlocks between the pci and sysad buses. the fifo size of 4 words allows the cpu to perform all possible write transactions. all cpu read transactions are supported, except instruction cache line fills (8-word burst transfers). for data cache line fills from the pci bus, the controller reads 4 words from the pci bus, be g innin g with the first word in the line (word address = 0), and returns them to the cpu in the correct subblock order. for example, a data cache line fill from address 2 is read from the pci bus as 4 words, be g innin g at address 0 (0, 1, 2, 3) and returned to the cpu be g innin g at address 2 (2, 3, 0, 1). the controller does not support the pci cache line wrap mode. durin g cpu-to-pci bus transactions, the fifo accepts write data at the cpu rate. if the cpu is performin g a data cache write-back, a burst of 4 words occurs. the address and byte-enables for the cycle are first latched in the fifo. then the data words are placed in the fifo, and the pci bus is requested. if the cpu attempts another pci write before the fifo is empty, the controller stalls the cpu write. if the pci bus has not been acquired before the fifo is filled, the controller indicates to the cpu that fur- ther write (and read) cycles will be stalled by ne g atin g the eok# si g nal to the proces- sor. write cycles to resources other than the pci bus are allowed to complete after the controller decodes the address. the controller uses the pci block transfer protocol if the cpu read is also more than one word. durin g block reads, the cpu is stalled by the controller until a word has been placed in the fifo from the pci bus. for cpu accesses to the pci bus of less than one word, the controller reads or writes the correct number of bytes. until the controller is g ranted the pci bus, another pci master may have ownership of the pci bus and may request access to the controller as a pci tar g et. a pci tar g et fifo in the controller allows such an access to occur without causin g deadlock, as described in the next section.
59 v rc 4375 system controller 7.4 pci tar g et transactions (pci to memor y ) the controller supports bidirectional data transfers between a pci bus master and the controller ? s memory as the tar g et. the pci bus master obtains access to the control- ler ? s memory by accessin g a local physical address that corresponds to one of two pci address windows: pci tar g et address window 1 pci tar g et address window 2 these re g isters are at offsets 1c and 20, respectively (see table 6). they are confi g - ured throu g h the pci tar g et address window re g isters, as described below. 7.4.1 pci target address window registers the two pci tar g et address window re g isters described above are set to 0 at reset. there must be at least two cpu clocks between writin g to such a re g ister and perform- in g a pci access throu g h the window mapped by the re g ister. each of the two pci tar g et address window re g isters contains the followin g fields. bits 10:0 ladd local address this 11-bit field replaces the most-si g nificant 11 bits of the pci address defined in the pciadd field (bits 31:24) when the address is transmitted to the mem- ory. bits masked by the mask field are directly trans- ferred from the pci bus, rather than from the ladd field. bit 11 reserved hardwired to 0 bit 12 e enable 1 = enables the pci bus to access local resources throu g h the address window specified in this re g ister 0 = disables access bits 19:13 mask pci address mask this mask is used to determine the size of the local window. it will mask 7 address bits from the address comparison, be g innin g with bit 21. thus, bits 27:21 may be masked, providin g an address block size between 2 mb (no bits masked) and 256 mb (7 bits masked). a 0 in a mask bit indicates that the corre- spondin g address bit is masked. bit 20 reserved hardwired to 0 bits 31:21 pciadd pci address this 11-bit field is compared with the most-si g nificant 11 bits of the pci address, conditioned on the mask field. a match indicates that the access is to the con- troller. care must be taken not to overlap the two pci tar g et windows.
60 v rc 4375 system controller 7.4.2 pci to cpu transaction details when the controller sees an address on the pci bus that falls within one of its two pci ta r g et address window ran g es, it responds by requestin g access to its attached mem- ory. this prevents the cpu from obtainin g access to the memory. the controller sup- ports full-speed burst read and write cycles from a pci master. accesses are performed throu g h an 8-word bidirectional pci tar g et fifo. this fifo stores data and latches the address and byte-enables for one pci to cpu read or write transaction. pci tar g et transfers have hi g her priority than pci master transfers. thus, if both cpu requests and pci tar g et requests for memory are present simultaneously, the pci tar- g et transfer occurs first. durin g pci tar g et read cycles, the controller always accesses memory in 4-word reads, usin g the data cache miss protocol. these words are placed in the tar g et fifo and sent to the pci bus at maximum speed. if the pci read address is not ali g ned to a cache line boundary, the controller stores only the required words in the tar g et fifo. when the pci word address is 2 or 3, the controller transfers the word(s) and then dis- connects from the tar g et; the controller always disconnects if there are fewer than 2 words left in the fifo for a pci read cycle. the controller uses the cpu ? s subblock orderin g for pci tar g et read cycles. table 27 shows the read order for various access quantities. if the controller detects bad parity on a pci tar g et address cycle, the controller reports the error in the pci header, g enerates an interrupt on inta# (if enabled), and performs the access (i g norin g the parity error). if the controller detects bad parity on a pci tar g et data cycle, the controller reports the error in the pci header, g enerates an interrupt on inta# (if enabled), and performs the write. table 27. pci tar g et read order and bufferin g pci word address words placed in pci target fifo 0 0, 1, 2, 3 11, 2, 3 22, 3 33
61 v rc 4375 system controller 7.5 pci confi g uration space the controller provides a pci confi g uration space, as described in the pci local bus specification , section 6. this space supports bus master confi g uration cycles of pci devices usin g a mechanism similar to confi g uration mechanism #1 ( pci local bus specification, section 3.7.4.1). two 1-word re g isters are provided for software to perform confi g uration cycles: pci confi g uration data re g ister pci confi g uration address re g ister these re g isters are at offsets 28 and 2c, respectively (see table 6), and are cleared to 0 at reset. to perform a confi g uration cycle, the cpu first writes an address to the pci confi g uration address re g ister, then writes the transaction data to the pci confi g ura- tion data re g ister. the access to the data re g ister causes the cycle to be g in. byte enables, read/write states, and the full 32-bit address pass throu g h to the pci bus with- out mappin g . the cpu is stalled durin g read cycles until the pci confi g uration cycle completes. this mechanism precludes the cpu from performin g burst transfers to con- fi g uration space. the pci confi g uration address re g ister format contains a re g ister number field that is used to address specific pci bus tar g ets. fi g ure 3-20 of the pci local bus specifica- tion shows the format. each confi g urable tar g et on the pci bus maintains a set of pci confi g uration space re g isters that consist of header re g isters and device-dependent re g isters, as defined in section 6.1 of the pci local bus specification. the controller implements two sets of the pci confi g uration space re g isters, depend- in g on its mode of operation: host bridge mode: in this mode, the controller is located on the motherboard and acts as the pci host brid g e for the system. the pci confi g uration space re g isters for this mode are described in section 7.6. add-on board mode: in this mode, the controller is located on a pci board rather than on the motherboard. the pci confi g uration space re g isters for this mode are described in section 7.7. 7.6 pci confi g uration re g isters (host brid g e mode) the cpu uses this confi g uration space durin g system boot to confi g ure the controller. in host brid g e mode, the cpu accesses the controller directly throu g h the controller ? s re g isters in the cpu ? s memory space (table 6); the pci confi g uration address re g ister and pci confi g uration data re g ister are not used. table 28 shows the controller ? s pci confi g uration space re g isters for this mode. the sections that follow define the fields in each re g ister. after chan g in g any of these re g isters, at least two cpu clock cycles must elapse before a pci access by the cpu, dma, or an external master.
62 v rc 4375 system controller 7.6.1 vendor and device id registers the vendor and device id re g isters are read only. to g ether, they constitute a word at offset 0x100. 7.6.1.1 vendor id re g ister the 2-byte vendor id re g ister is read only and can be accessed at offset 0x100 . bits 15:0 vid vendor id hardwired to 0x1033 for nec table 28. pci confi g uration space re g isters (host brid g e mode) 1 offset from base memory address 0f00_0000 size (bytes) register name symbol cpu read/ write reset value description reference 0x100 2 vendor id vid r 0x1033 vendor id for nec section 7.6.1 on page 62 0x102 2 device id did r 0x005b v rc 4375 controller ? s de- vice id, assigned by nec section 7.6.1 on page 62 0x104 2 command pcicmd r/w 0x0 provides general control of pci interface section 7.6.2 on page 63 0x106 2 status pcists r/wc 2 0x0280 status for pci events section 7.6.2 on page 63 0x108 1 revision id rid r 0x0 device revision section 7.6.3 on page 64 0x109 3 class code class r 0x06_0000 device type section 7.6.3 on page 64 0x10c 1 cache line size clsiz r 0x04 system cache line size (words) section 7.6.4 on page 65 0x10d 1 latency timer mltim r/w 0x0 value of latency timer for this master, in pci clock cycles section 7.6.4 on page 65 0x10e 2 reserved r 0x0 0x110 4 mailbox base address mbadd r/w 0x0 base memory address for both mailboxes section 7.6.5 on page 65 0x13b ? 0x114 reserved r 0x0 0x13c 1 interrupt line intlin r 0x0 pci interrupt signal section 7.6.6 on page 66 0x13d 1 interrupt pin intpin r 0x0 pci interrupt pin section 7.6.6 on page 66 0x13f ? 0x13e 2 reserved r0x0 0x140 1 reserved r 0x0 0x141 1 retry value rtyval r/w 0x0 number of pci bus retries the controller performs section 7.6.7 on page 66 0x142 2 pci arbiter pri- ority control and take away grant papc r/w 0x0 priority scheme used in granting access to pci bus section 7.6.7 on page 66 0x1ff ? 0x144 reserved r0x0 notes: 1. the row shading/no shading pattern defines 4-byte word boundaries. some registers can be accessed along byte or 2-byte boundaries. 2. the bits can only be set by the controller hardware, and they are cleared by writing to them. writing a 0 leaves them unaffected. for example, writing 0x8000 clears the most-significant bit.
63 v rc 4375 system controller 7.6.1.2 device id re g ister the 2-byte device id re g ister is read only and can be accessed at offset 0x102. bits 31:16 did device id hardwired to 0x005b for the v rc 4375 controller 7.6.2 command and status registers the command and status re g isters, plus reserved fields, constitute a word at offset 0x104. 7.6.2.1 command re g ister the 2-byte command re g ister is read/write and can be accessed at offset 0x104. bit 0 ioen i/o space enable cleared to 0 at reset. software must set it to 1 to enable access to the pci interrupt re g ister status in the add-on board mode. bit 1 memen memory space enable cleared to 0 at reset. software must set it to 1 to allow the controller to respond to memory space accesses. bit 2 bmas bus master enable cleared to 0 at reset. software must set it to 1 to allow the controller to g enerate pci accesses. bit 3 spc special cycle enable hardwired to 0. the controller i g nores special cycles. bit 4 mwi memory write and invalidate enable hardwired to 0. the controller does not g enerate mwi commands. bit 5 vga hardwired to 0 the v rc 4375 controller is not a vga device. bit 6 per parity error (perr#) enable 1 = enable 0 = disable default = 0 bit 7 wait_ctl wait cycle control hardwired to 0. the controller never does address steppin g . bit 8 serr_en system error (serr#) enable 1 = enable 0 = disable default = 0 bit 9 fbbe fast back-to-back enable hardwired to 0. the controller never g enerates back- to-back transactions. the 1-byte location 0x105 is reserved.
64 v rc 4375 system controller bits 15:10 reserved hardwired to 0 7.6.2.2 status re g ister the 2-byte status re g ister can be accessed at offset 0x106. it uses a special read/ write protocol: the bits can be set only by the controller hardware, but they can be cleared by writin g 1 to them; writin g 0 leaves them unaffected. for example, writin g 0x8000 clears the most-si g nificant bit. bits 20:16 reserved hardwired to 0 bit 21 66 mhz 66-mhz capability hardwired to 0. the controller is a 33-mhz device. bit 22 udf user-definable configuration (udf) support hardwired to 0. the controller doesn ? t support udf. bit 23 fbbc fast back-to-back capability hardwired to 1. the controller will accept fast back- to-back accesses. bit 24 dpr data parity reported 1 = enable 0 = disable bits 26:25 devsel device select (devsel) timing hardwired to 01 (medium response) bit 27 sta signaled target abort set to 1 if the controller si g nals a tar g et abort. other- wise, cleared to 0. bit 28 rta received target abort set to 1 whenever the master receives a tar g et abort. otherwise, cleared to 0. bit 29 rma received master abort set whenever the master receives a master abort. otherwise, cleared to 0. bit 30 sse signaled system error 1 = generates a bus error interrupt 0 = does not g enerate a bus error interrupt bit 31 dpe detected parity error set when the controller detects a parity error. other- wise, cleared to 0. 7.6.3 revision id and class code registers the revision id and class code re g isters are read only. to g ether, they constitute a word at offset 0x108. they contain the followin g fields. 7.6.3.1 revision id re g ister the 1-byte revision id re g ister is read only and can be accessed at offset 0x108.
65 v rc 4375 system controller bits 7:0 rid revision id hardwired to 0, indicatin g a g ate array 7.6.3.2 class code re g ister the 3-byte class code re g ister is read only and can be accessed at offset 0x109. bits 15:8 pro g programming interface hardwired to 0 bits 23:16 subcl subclass hardwired to 0 bits 31:24 basecl base class hardwired to 0x06 to indicate a brid g e device 7.6.4 cache line size and latency timer the cache line size and latency timer re g isters are both 1 byte wide, followed by two reserved bytes. to g ether, these locations constitute a word at offset 0x10c. 7.6.4.1 cache line size the 1-byte cache line size re g ister is read only and can be accessed at offset 0x10c. bits 7:0 clsiz cache line size hardwired to 0x04, indicatin g four 32-bit words in a cache line 7.6.4.2 latency timer the 1-byte latency timer re g ister is read/write and can be accessed at offset 0x10d. bits 10:8 mltim master latency timer (low 3 bits) hardwired to 0 bits 15:11 mltim master latency timer see the pci local bus specification , sections 3.4.4.1 and 6.2.4. the hi g h 2 bytes in the word startin g at offset 0x10e are reserved. bits 23:16 reserved hardwired to 0 bits 31:24 reserved hardwired to 0 7.6.5 mailbox base memory addresses the 1-word, read/write mailbox base address re g ister is accessed at offset 0x110 in the pci confi g uration space header. this re g ister must not be chan g ed while an exter- nal a g ent is accessin g one of the pci mailboxes. bits 10:0 reserved hardwired to 0 indicates that the controller ? s pci mailbox re g isters are located in a 32-bit memory space on a 4-kb boundary and are not prefetchable. bit 11 mbnum 0 = pci mailbox register 1
66 v rc 4375 system controller bits 31:12 mbadd mailbox base memory address used to map the controller ? s two mailboxes into the pci memory space on a 4-kb boundary. 7.6.6 interrupt line and interrupt pin registers the interrupt line and interrupt pin re g isters to g ether constitute a word at offset 0x13c. 7.6.6.1 interrupt line re g ister the 1-byte interrupt line re g ister is read only and can be accessed at offset 0x13c. bits 7:0 intlin pci interrupt line register this field should be written by power-on self-test software to indicate which system interrupt controller input is connected to the inta# si g nal. 7.6.6.2 interrupt pin re g ister the 1-byte interrupt pin re g ister is read only and can be accessed at offset 0x13d. bits 15:8 intpin pci interrupt pin register reset to 1, indicatin g that inta# is the controller ? s pci interrupt si g nal. the two hi g h bytes in the word startin g at offset 0x13d are reserved. bits 31:16 reserved hardwired to 0 7.6.7 retry value and pci arbiter priority control registers the retry value and pci arbiter priority control re g isters are read/write. to g ether, these locations constitute the word at offset 0x140. they have the followin g fields. bits 7:0 reserved hardwired to 0 7.6.7.1 retry value re g ister the 1-byte retry value re g ister can be accessed at offset 0x141. bits 15:8 rtyval retry value the number of retries the controller should attempt before g ivin g up on a pci transaction. the actual retry count is readable in the pci retry counter (section 7.8). bits 23:16 reserved hardwired to 0
67 v rc 4375 system controller 7.6.7.2 pci arbiter priority control re g ister the 2-bit pci arbiter priority control re g ister can be accessed at offset 0x142. bits 25:24 papc pci arbiter priority control 00 = rotatin g fair. (this is the reset value.) in this scheme, the priority of each requester chan g es, in round-robin fashion, after each request to g ive each request a fair chance to acquire the bus. the rotation sequence be g ins with the controller ? s internal request, followed by requesters 0, 1, and 2 and back to an internal request. if any of the requesters is not active, the next requester in the sequence becomes the hi g hest priority. after a requester has been g ranted the bus, it retains the bus, dependent on the tkygnt bit. 01 = rotatin g alternate 0. in this scheme, req0# is g ranted the bus every other transaction, if asserted. the rotation sequence is 0, i, 0, 1, 0, 2, 0, 3, 0, i..., where i is the controller ? s internal request. after a requester is g ranted the bus, it retains the bus, dependent on the tkygnt bit. 10 = rotatin g alternate 1. this scheme is identical to the rotatin g alternate 0 scheme, except that the controller ? s internal request, rather than req0#, has the advanta g e. the rotation sequence is i, 0, i, 1, i, 2, 0... after a requester is g ranted the bus, it retains the bus, dependent on the tkygnt bit. bit 26 tkygnt take away grant 0 = when reqn# is g ranted, it remains g ranted until the reqn# is ne g ated. this is the reset value. 1 = when reqn# is g ranted, the bus loses gntx# if it receives a hi g her priority request. a rotatin g priority scheme is used, so all requests are at a hi g her prior- ity. the hi g h byte in the word startin g at offset 0x140 is reserved. bits 31:27 reserved hardwired to 0 7.7 pci confi g uration re g isters (add-on board mode) table 29 shows the controller ? s pci confi g uration space re g isters when the controller is is in add-on board mode (when the controller is located on a pci bus add-on board, rather than on the system motherboard). as shown in table 29, there are four more re g isters defined in the add-on board mode than in host brid g e mode (see table 28 on pa g e 62).
68 v rc 4375 system controller table 29. pci confi g uration space re g isters (add-on board mode) 1 offset from base memory address 0f00_0000 size (bytes) register name symbol cpu bus r/w 2 pci bus r/w reset value description reference 0x100 2 vendor id vid r r 0x1033 vendor id for nec section 7.6.1 on page 62 0x102 2 device id did r r 0x0095 v rc 4375 controller ? s de- vice id, assigned by nec section 7.6.1 on page 62 0x104 2 command pcicmd r/w 3 r/w 3 0x0 provides general control of pci interface section 7.6.2 on page 63 0x106 2 status pcists r/wc 4 r/wc 4 0x0280 status for pci events section 7.6.2 on page 63 0x108 1 revision id rid r r 0x0 device revision section 7.6.3 on page 64 0x109 3 class code class r r 0x06_0000 device type section 7.6.3 on page 64 0x10c 1 cache line size clsiz ? r 0x04 system cache line size (words) section 7.6.4 on page 65 0x10d 1 latency timer mltim r/w 3 r/w 3 0x0 value of latency timer for this master, in pci clock cycles section 7.6.4 on page 65 0x10e 2 reserved ? r 0x0 0x110 4 mailbox base address mbadd r/w r/w 0x0 base memory address for both mailboxes section 7.6.5 on page 65 0x114 4 base address register 1 bar1 ? r/w 0x8 base address register 1, for target memory section 7.7.1 on page 69 0x118 4 base address register 2 bar2 ? r/w 0x8 base address register 2, for target memory section 7.7.1 on page 69 0x11c 4 base address register 3 bar3 ? r/w 0x1 base address register 3, for add-on board interrupt register section 7.7.2 on page 69 0x120 4 base address register 4 bar4 ? r/w 0x0 base address register 4, for add-on board interrupt register section 7.7.3 on page 69 0x138 ? 0x124 reserved ? ? 0x0 0x13c 1 interrupt line intlin ? r 0x0 pci interrupt signal section 7.6.6 on page 66 0x13d 1 interrupt pin intpin ? r 0x0 pci interrupt pin section 7.6.6 on page 66 0x13 ? 0x13e 2 reserved ? r0x0 0x140 1 reserved ? r 0x0 0x141 1 retry value rtyval ? r 0x0 number of pci bus retries the controller performs be- fore giving up section 7.6.7 on page 66 0x142 2 pci arbiter pri- ority control and take away grant papc ? r 0x0 priority scheme used in granting access to pci bus section 7.6.7 on page 66 0x1ff ? 0x144 reserved ? r0x0 notes: 1. the shading/no shading row pattern defines 4-byte word boundaries. 2. ? means not used. 3. writable by the cpu if the pci enable register bit 1 is set to 1. writable by the pci host if this bit is set to 0. see section 7.10 on page 71. 4. the bits can only be set by the controller hardware, and they are cleared by writing 1 to them. writing 0 leaves them unaffected. for example, writing 0x8000 clears the most-significant bit.
69 v rc 4375 system controller 7.7.1 bar1 and bar2 registers in the add-on board mode, after the controller's config_done bit in the pci enable re g ister is set to 1, a pci master can pro g ram the bar1 and bar2 re g isters and the controller will use them for the pci tar g et address window ran g es. at reset, both re g isters are set to 0. bits 20:0 pref prefetchable hardwired to 0x8, indicatin g prefetchable, relocat- able memory (see pci specification , section 6.2.5.1). this field is not used in the tar g et address window address comparison. bits 31:21 base pci base memory address this field is compared with the most-si g nificant 11 bits of the pci address, after maskin g bits 27:21 of this field with the correspondin g pci tar g et address window re g ister mask (bits 19:13 of pci tar g et address window re g ister 1 for bar1, or pci tar g et address window re g ister 2 for bar2). the memory ran g e can vary between 2 mb (no bits masked) and 256 mb (all bits masked). a match indicates that the access is to the controller. if the address is all 0s, this re g ister is treated as disabled and memory is not allocated. 7.7.2 bar3 register the bar3 re g ister contains the i/o address of the add-on board interrupt re g ister. bits 1:0 space space indicator hardwired to 01, indicatin g that the address is to i/o space. bits 31:2 ioaddr i/o address the i/o address of the add-on board interrupt re g is- ter (see section 7.7.4). 7.7.3 bar4 register the bar4 re g ister is shown in table 29. it contains the memory-mapped address of the add-on board interrupt re g ister. bits 3:0 space space indicator hardwired to 0, indicatin g that the address is to memory space. bits 31:4 maddr memory-mapped address the memory-mapped address for the bar3 i/o address.
70 v rc 4375 system controller 7.7.4 add-on board interrupt register the add-on board interrupt re g ister is located at the address specified in the bar3 re g ister (see section 7.7.2). the re g ister specifies the state of the inta# si g nal. bit 0 pci_int pci interrupt pending 1 = pci interrupt on inta# pendin g 0 = pci interrupt on inta# not pendin g bits 31:1 reserved hardwired to 0 when the cpu reads the set_pci_int bit (bit 3) of the pci enable re g ister (section 7.10), the controller returns the value of bit 0 in the add-on board interrupt re g ister, which is the state of the inta# si g nal. a pci master causes the controller to ne g ate inta# by writin g any value (1 or 0) to the pci_int bit (bit 0) of the add-on board inter- rupt re g ister. 7.8 pci retr y counter the pci retry counter is a read-only word at offset 0x70. it has only one status field. bits 4:0 rtrycnt retry count the number of pci bus transactions that the control- ler has retried. the maximum value for retries is set in the retry value re g ister (section 7.6.7.1 on pa g e 66). bits 31:5 reserved hardwired to 0 7.9 pci arbiter the pci bus arbiter determines access to the pci bus for the controller and four other pci bus masters. four request/ g rant si g nal pairs are provided for the other masters; the controller has a fifth, internal request/ g rant function for its own requests. the arbi- ter implements three priority schemes, which are pro g rammable in the pci arbiter pri- ority control re g ister (papc), described in section 7.6.7.2 on pa g e 67.
71 v rc 4375 system controller 7.10 pci enable re g ister the pci enable re g ister is accessed at base memory address offset 0x74, as shown in table 6. this re g ister enables the pci arbiter and the add-on board mode, specifies the completion of controller confi g uration, and sets and clears interrupts. at reset, all bits are set to 0. bit 0 arb_enable enable arbiter enables the built-in pci arbiter. bit 1 add_on_board enable add-on board mode in this mode, the v rc 4375 controller is located on a pci add-on board rather than on the motherboard. bit 2 config_done pci configuration done software should set this to 1 after confi g urin g the controller ? s other pci re g isters. when set to 1, the controller responds normally to pci operations. when cleared to 0, the controller responds to pci tar g et cycles with a retry. bit 3 set_pci_int assert pci interrupt used only in add-on board mode. when set to 1 by the cpu, the controller sets bit 0 of the add-on board interrupt re g ister (section 7.7.4) to 1 and asserts the pci interrupt si g nal (inta#). when the cpu reads set_pci_int, the controller returns the value of bit 0 in the add-on board interrupt re g ister, which is the state of inta#. the controller automati- cally clears set_pci_int to 0 one clock after soft- ware sets it to 1, so there is no need for software to clear it. a pci master causes the controller to ne g ate inta# by writin g any value (1 or 0) to bit 0 of the add- on board interrupt re g ister. bit 4 rst_nmi negate nmi# used only in add-on board mode. when set to 1, the controller ne g ates its nmi# si g nal. the controller asserts nmi# whenever it detects that serr# (pci system error) is asserted. the nmi# service routine can read this bit to determine its state or set it to 1, which clears the interrupt. the controller automati- cally clears the bit to 0 one clock after software sets it to 1. bits 31:5 reserved hardwired to 0
72 v rc 4375 system controller 7.11 pci mailbox re g isters the controller has two pci mailbox re g isters for passin g messa g es between the cpu and pci bus masters: pci mailbox re g ister 1 pci mailbox re g ister 2 both re g isters are 1 word wide and may be read and written by either the cpu or a pci bus master. from the cpu side, the addresses of the pci mailbox re g isters are at off- sets 30 and 34, respectively (see table 6). from the pci bus side, the addresses are software confi g urable, as described in section 7.5 and section 7.6. the pci mailbox re g isters are mapped into pci memory space and respond only to pci memory cycles. both pci mailbox re g isters are cleared to 0 at reset. the re g isters respond as soon as the memory space enable (memen) bit is set in the pci command re g ister (section 7.6.2); there is no enable function specific to these re g isters. if the mailbox base address re g ister (offset 0x110 in table 28) is not initialized before the memen bit (bit 1) is set in the command re g ister (offset 0x104 in table 28), the base memory addresses for the two pci mailbox re g isters will be mapped to offsets 0x0 and 0x800, respectively, and may collide with other pci devices. when a pci mailbox re g ister is accessed from the pci bus (either read or write), it causes a mailbox interrupt bit (mb1 or mb2) to be set in the controller ? s interrupt con- trol and status re g ister (section 9.1.2 on pa g e 85). the interrupt is automatically cleared when the cpu reads or writes the correspondin g pci mailbox re g ister. 7.12 exclusive access to pci bus resources as shown in table 28 and table 29, the controller provides a mechanism for obtainin g exclusive (locked) access to pci tar g ets, as defined in the pci local bus specification , section 3.6. as a master on the pci bus, the controller can lock a specific tar g et on the pci bus, usin g the lock# si g nal. to request exclusive access to a tar g et, software sets bit 0 of the pci exclusive access re g ister (described immediately below) to 1. when this bit is set, the next pci access uses the exclusive protocol, if possible, allowin g the addressed resource to become locked to the requester throu g h the controller. to release the tar g et, software clears bit 0 prior to the last exclusive access; the current access remains exclusive until com- pleted, at which time the tar g et resource is released. when the pci bus tar g et is locked, transactions are allowed only between the control- ler and the locked tar g et. transactions that do not complete are retried until they suc- cessfully complete. if the retry limit set in the retry value re g ister (section 7.6.7.1 on pa g e 66) is reached, the controller sets bit 2 of the pci exclusive access re g ister to 1. if the controller receives an abort durin g a locked transaction, it sets bit 3 of the pci exclusive access re g ister to 1. the controller can also perform exclusive accesses as a tar g et. to confi g ure this, soft- ware sets bit 1 of the pci exclusive access re g ister. when the controller senses that it is the tar g et of a locked pci bus cycle, it enters locked mode. while in locked mode, no other accesses to the controller, either from the pci bus or from the cpu bus, are allowed until the master ne g ates both frame# and lock#. however, refresh cycles are permitted to the dram system even while the memory is locked.
73 v rc 4375 system controller 7.12.1 pci exclusive access register the exclusive access re g ister stores a read/write word at offset 0x60. it contains the followin g fields. bit 0 eareq exclusive access request 1 = exclusive access request. in response, the con- troller asserts lock#, if conditions on the pci bus permit (see section 3.6 of the pci local bus specifi- cation for details). 0 = releases the tar g et; the controller ne g ates lock# after completin g the current access. bit 1 unlock controller is not a locked target 1 = disables controller as tar g et of exclusive access 0 = enables controller as tar g et of exclusive access bit 2 rtryreached retry limit reached 1 = retry limit has been reached. the limit is set in the retry value re g ister (section 7.6.7.1 on pa g e 66), and the retry count can be read in the pci retry counter re g ister (section 7.8 on pa g e 70). 0 = retry limit has not been reached. bit 3 abort abort received 1 = either a master abort or tar g et abort has been received while the controller was assertin g lock#. these aborts are described in fi g ures 3-4 and 3-10 of the pci local bus specification . 0 = no abort has been received. bits 31:4 reserved hardwired to 0
74 v rc 4375 system controller 8.0 dma transfers the controller supports cpu-initiated dma transfers between memory and the pci bus. these transfers can be unali g ned reads or writes at the full pci rate of 133 mb/s. four sets of cpu-pro g rammed re g isters confi g ure dma transfers; durin g transfers, other sets of re g isters can be read or written to. the dma fifo, an 8-word (32-byte) bidirectional fifo, temporarily stores pci-to-memory or memory-to-pci transfers inside the controller. to initiate a dma transfer, the cpu confi g ures the controller ? s dma re g isters (section 8.3) with the memory address, pci bus address, read/write transfer direction, bound- ary crossin g points, end-of-transfer interrupt enable, and transfer enable. once confi g - ured, the controller arbitrates for the memory and pci bus, then performs the transfer independently of the cpu. pci bus masters cannot initiate dma transfers. instead, such masters g ain access to the controller ? s memory throu g h pci tar g et address window re g isters, described in section 7.4. 8.1 dma operations dma transfers can be from the pci bus to memory (called a pci read), or from memory to the pci bus (called a pci write). the direction is set in the r/w bit (bit 29) of the dma control re g isters. 8.1.1 pci to memory transfers (pci read) for a pci bus read (from the pci bus to memory), the controller be g ins by requestin g access to the pci bus. when g ranted, the controller reads words from the pci bus and stores them in its 8-word dma fifo. when the fifo contains 4 words (the fifo is half full), the controller requests access to memory, which is g ranted as soon as any current cpu memory operation completes. then the controller empties data from the fifo to memory at the fastest rate supported by memory. if the controller ? s dma fifo becomes full durin g a transfer, the controller releases the resource responsible for fillin g the fifo until the fifo is emptied to 4 words (the fifo is half full). then the controller reacquires the resource and continues fillin g the fifo. 8.1.2 memory to pci transfers (pci write) for a pci bus write (from memory to the pci bus), the controller be g ins by requestin g access to memory. when g ranted, the controller reads the first 8 words into its dma fifo at the fastest rate supported by memory. the controller accumulates 4 words in its fifo before requestin g the pci bus. the controller attempts to empty the fifo as quickly as the pci tar g et can accept the data. meanwhile, the controller attempts to keep its fifo full. if the fifo becomes full, the controller releases memory until the fifo reaches 4 words (the fifo is half full), at which time it a g ain accesses memory and be g ins fillin g the fifo. if the fifo becomes empty, the controller issues a disconnect command to the pci bus. if there is more data to transfer in the same dma operation, the controller contin- ues fillin g its fifo from memory and accesses the pci bus when either one word or four words have been accumulated in the fifo, dependin g on the memory type described above. when the correct number of words has been read from memory, the
75 v rc 4375 system controller controller stops fillin g its fifo but continues emptyin g the fifo until the last transfer completes. 8.1.3 transfer completion when a dma transfer completes, the controller interrupts the cpu (if int# interrupts are enabled), with bit 1, 2, 16, or 17 set in the controller ? s interrupt control and status re g ister (section 9.1.2). the controller then checks the other set of dma control re g is- ters to determine if another dma transfer is pendin g . if another is pendin g , the control- ler allows one pendin g cpu-to-memory and one pendin g cpu-to-pci transaction to complete before be g innin g the next dma transfer. if there is a next record address already in place in the re g ister and a chainin g -enable bit is set (dma/pci/cpu-mem- ory arbitration priority re g ister at offset 0x80, bits 11:8), then the dma controller will automatically fetch the next record from the memory, load it in the controller, and start a new dma transaction. it will continue the transaction until the next record address re g ister is zero or the chainin g -enable bit is reset before startin g a new transaction. when chainin g and interrupt are both enabled, the dma transfer complete interrupt will occur only after completion of the last dma structure in the chain. if the controller receives a pci master-abort or tar g et-abort termination, the controller resets the dma channel, indicates the error type by settin g bits 1:0 of the bus error status re g ister (section 9.1.1), and interrupts the cpu (if int# interrupts are enabled). if a dma bus error occurs, the controller interrupts the cpu (if int# interrupts are enabled), with bit 5 set in the interrupt control and status re g ister (section 9.1.2). if the other dma channels are enabled to be g in a transfer (bit 28 is set in the other dma control re g isters), the controller be g ins the pendin g transfer. 8.2 cpu access durin g dma transfers after a dma transfer starts, the cpu cannot access memory until the dma reaches a boundary crossin g point in the memory address space. the boundary crossin g point is pro g rammed by the cpu, as defined in the dma control re g isters. the controller allows the cpu to perform one memory transaction at each boundary crossin g point. thus, a cpu memory read stalls between boundary crossin g points, but a cpu mem- ory write will be buffered in the cpu-to-memory write fifo. when the write fifo con- tains a posted write, all other cpu-to-memory transactions stall (eok# ne g ated) until a boundary crossin g point is reached or the dma transaction completes. if the cpu attempts to read an address mapped to the pci bus durin g a dma transfer, the cpu read stalls until the dma transfer completes. if the cpu attempts to write to an address mapped to the pci bus address durin g a dma transfer, the cpu write is posted in the pci master fifo until the dma transfer completes. when the pci master fifo contains a posted write, all other cpu transactions stall (eok# is deasserted) until the fifo is empty.
76 v rc 4375 system controller 8.3 dma re g isters the controller has four sets of dma confi g uration re g isters, each of which controls a dma transfer. one set of re g isters may be read from or written to while the other set is controllin g a dma transfer. the confi g uration re g isters are: dma control re g isters 1, 2, 3, and 4 dma memory address re g isters 1, 2, 3, and 4 dma pci address re g isters 1, 2, 3, and 4 dma next record address re g ister in addition to these confi g uration re g isters, the controller also has the followin g dma status re g isters: dma words remainin g re g ister dma current memory address re g ister dma current pci address re g ister the re g isters are located at offsets 0x38 throu g h 0x4c, offsets 0xa4 throu g h 0xb8, and offsets ox64 throu g h 0x6c, as shown in table 6 on pa g e 14. the followin g sec- tions describe the contents of these re g isters.
77 v rc 4375 system controller 8.3.1 dma control registers 1, 2, 3, and 4 the cpu uses these re g isters to confi g ure dma transfers. one re g ister can be read from or written to while the other is controllin g a dma transfer. when a dma transfer has started, remainin g bits in the dma control re g isters, except the drst and su bits (bits 24 and 27), have no effect. the cpu should not try to write to other bits unless a dma operation is in pro g ress. the re g isters are 4 bytes wide, at offsets 0x38, 0x44, 0xa4, and 0xb0. they are set to 0 at reset and contain the followin g fields. bits 19:0 blksize block size the number of bytes (up to 1 mb) to be transferred. 0 = 1 mb bits 23:20 boundpnt boundary crossing point the address boundary at which cpu memory trans- actions may be performed durin g a dma transaction. when the current dma memory address matches this boundary, as defined in this field, the controller allows the cpu to perform one memory transaction. boundaries are defined in the table below. bit 24 drst dma reset 1 = terminates an in-pro g ress dma transfer and resets the dma lo g ic, after completion of the current bus cycle. this bit takes precedence over all other bits in the dma command re g ister. the value writ- ten to the other bits of this re g ister when drst is 1 is irrelevant: this bit takes precedence. 0 = the controller clears this bit automatically after the dma channel has been reset. boundpnt field byte address boundary 0000 none 0001 32 0010 64 0011 128 0100 256 0101 512 0110 1 k 0111 2 k 1000 4 k 1001 8 k 1010 16 k 1011 32 k 1100 64 k 1101 128 k 1110 256 k 1111 512 k
78 v rc 4375 system controller bit 25 mio pci memory or i/o 1 = transfers data to or from pci memory space 0 = transfers data to or from pci i/o space bit 26 inc increment pci address 1 = increments the pci address as the dma transfer is performed. 0 = restarts from the ori g inal startin g address for any condition that causes the dma to restart a pci burst. the startin g address is pro g rammed in the dma memory address re g ister or the dma pci address re g ister. bit 27 su suspend dma 1 = suspends the current dma transfer after comple- tion of the current pci cycle. all re g ister values are preserved. 0 = restarts the suspended dma transfer. this bit may be set and cleared without consideration of the other bits in the dma control re g isters, except drst (bit 24). that is, when the dma transfer has started, chan g in g bits other than su and drst has no effect. bit 28 go begin transfer 1 = starts the dma transfer as soon as the pci and memory buses are available. 0 = the controller automatically clears this bit after the transfer completes. software-clearin g this bit has no effect; the dma transfer will continue. this bit must not be set if the bus master enable bit (bit 2) in the pci command re g ister (section 7.6.2.1) has not been previously set. bit 29 r/w pci read/write direction 1 = reads data from the pci bus and writes it to local memory. 0 = reads data from local memory and writes it to the pci bus. bit 30 ie interrupt enable 1 = when a dma transfer completes and if int# interrupts are enabled, interrupts the cpu with bit 1 or 2 set in the controller ? s interrupt control and sta- tus re g ister (see section 9.1.2). 0 = the controller does not interrupt the cpu on completion of the dma transfer. bit 31 bz busy (read only) 1 = the dma transfer controlled by this re g ister is currently in process. this bit may be polled. 0 = no dma transfer controlled by this re g ister is in process.
79 v rc 4375 system controller 8.3.2 dma/cpu/pci to memory arbitration priority selection register this re g ister is pro g rammed by the cpu at offset 0x80. it selects priority schemes from amon g four dma channels for memory accesses. bits 13:8 select priority and link list chainin g enable/disable, as described below. the default value is 0x0009 at reset, which selects the arbiter mode g ivin g priority to the pci slave for two consecutive accesses to the cpu. bits 7:0 reserved hardwired to 0 bits 11:8 dma chainin g en link list chaining chainin g of the link list stored in local memory asso- ciated with each dma channel can be enabled or disabled. the dma transfer takes place per one con- trol structure stored in their respective re g isters in the device. if the chainin g -enable bit is reset, transfer is considered complete and no dma control struc- ture is fetched from the memory; thus, no additional dma transfers take place. these enable bits can be used to control dma operations in conjunction with the next record address re g ister (section 8.3.5). the value of the next record address re g ister stored in memory needs to be 4-word ali g ned only durin g chainin g operations. for fastest dma opera- tions, set the values in the dma/pci address re g is- ter, dma/memory address re g ister, and next record pointer re g ister to be word ali g ned. link list chainin g is automatically stopped when the contents of this re g ister are zero. bit 8 = 1, dma channel 1 chainin g enabled bit 8 = 0, dma channel 1 chainin g disabled bit 9= 1, dma channel 2 chainin g enabled bit 9 = 0, dma channel 2 chainin g disabled bit 10 = 1, dma channel 3 chainin g enabled bit 10 = 0, dma channel 3 chainin g disabled bit 11 = 1, dma channel 4 chainin g enabled bit 11 = 0, dma channel 4 chainin g disabled
80 v rc 4375 system controller bits 13:12 dma arbit priority dma arbitration priority four dma channels comprise g roups a and b: group a includes channels 1 and 2; group b includes channels 3 and 4. the dma arbiter workin g between these two g roups issuin g dma requests for memory accesses (dma memory requests to be arbitrated by the dma/pci/cpu memory arbitration re g ister) can be pro g rammed with different priority schemes. 00 = arbitration priority sequence: 1, 2, 3, 4, 1, 2, 3, 4, .... 01 = arbitration priority sequence: 1, 2, 1, 2, 3, 4, 1, 2, 1, 2, 3, 4, .... 10 = arbitration priority sequence: 3, 4, 3, 4, 1, 2, 3, 4, 3, 4, 1, 2, .... example: assumin g dma channel requests are pri- oritized as the arbitration sequence: 1, 2, 3, 4, 1, 2, 3, 4, .... and bits 13:12 = 01, arbitration is performed as follows. channel 1 is allowed to complete one dma transac- tion, then channel 2, then channel 1 a g ain, and then channel 2, then 3 and 4 and so on. after each dma transaction per a control structure (either written to the re g isters by the cpu or fetched by the dma con- troller from memory when chainin g is enabled) is complete, dma requests from other channels are arbitrated and g ranted per the arbitration scheme. bits 31:14 reserved hardwired to 0 8.3.3 dma memory address registers 1, 2, 3, and 4 these re g isters are pro g rammed by the cpu with the startin g memory address for the transfer. the re g isters are at offsets 0x3c, 0x48, 0xa8, and 0xb4. at reset, they are set to 0x0. bits 31:0 local address memory starting address the startin g address to be used when accessin g the controller ? s memory. this field remains static throu g hout the dma transfer. the current memory address bein g accessed can be read from the dma current memory address re g ister (section 8.3.7).
81 v rc 4375 system controller 8.3.4 dma pci address registers 1, 2, 3, and 4 these re g isters are pro g rammed by the cpu with the startin g pci bus address for the transfer. the re g isters are at offsets 0x40, 0x4c, 0xac, and 0xb8. at reset, these re g - isters are set to 0. bits 31:0 localaddr pci bus starting address the startin g address to be used when accessin g the pci bus. this field remains static throu g hout the dma transfer. the current pci bus address bein g accessed can be read from the dma current pci address re g ister (section 8.3.8). 8.3.5 dma next record address registers 1, 2, 3, and 4 these re g isters are pro g rammed by the cpu. the re g isters are at offsets 0xbc, 0xc0, 0xc4 and 0xc8, and are set to 0x0 at reset. bits 31:0 nextaddr next record pointer address where the subsequent list of control struc- tures or descriptors (list is 4 conti g uous words each) reside. a value of 0 indicates the end of the structure chain. this field remains static throu g hout the dma transfer. the list g ets fetched directly by the dma controller from the local memory. the cpu can write new structure data in the local memory prior to the new structure data bein g fetched by the dma con- troller. the cpu can also write to all structures in the local memory prior to startin g a dma operation. the control structures may or may not be conti g uously located in the memory. the start address should be on a word boundary only when the next record pointer bits are used for link list operations (fi g ure 9). fi g ure 9. dma scatter/gather usin g link list descriptor 3 dma control register n dma pci address register n dma next record address register n dma memory address register n local memory control structure descriptor 5 descriptor 2 descriptor 4 descriptor 1
82 v rc 4375 system controller 8.3.6 dma words remaining register the cpu reads this re g ister to determine the number of words remainin g in the current dma transfer. the re g ister is at offset 0x64; at reset it is set to 0x0. bits 31:0 wordcnt words remaining (read only) the number of words remainin g to be transferred durin g dma operation 8.3.7 dma current memory address register the cpu reads this re g ister to determine the memory address accessed durin g a dma transfer. the re g ister is at offset 0x68; at reset it is set to 0x0. bits 31:0 crntaddr current memory address (read only) the current memory address durin g dma operation 8.3.8 dma current pci address register the cpu reads this re g ister to determine the pci address accessed durin g a dma transfer. the re g ister is at offset 0x6c; at reset it is set to 0x0. bits 31:0 crntaddr current pci address (read only) the current pci address durin g dma operation 8.4 data ali g ner the controller automatically handles unali g ned bidirectional transfers between the pci bus and memory. the ali g ner shifts byte data into the dma fifo or memory, in the ali g nment required or supplied by the pci bus (fi g ure 10). the ali g ner permits the con- troller to use hi g h-speed burst protocols for transfers, even when both the source and destination addresses are not ali g ned on word/address boundaries or with each other. fi g ure 10 shows the operation of the ali g ner for a dma transfer from byte address 0002 in memory to byte address 0003 on the pci bus (or in the opposite direction).
83 v rc 4375 system controller fi g ure 10. dma transfer ali g nment example byte 3 byte 2 byte 1 byte 0 21 6543 10 9 8 7 11 byte 3 byte 2 byte 1 byte 0 1 5432 9876 11 10 byte 3 byte 2 byte 1 byte 0 1 5432 9876 11 10 memory dma fifo pci bus data aligner
84 v rc 4375 system controller 9.0 interrupts the controller supports maskable interrupts usin g the int# input si g nal to the cpu, and nonmaskable interrupts usin g the nmi# input si g nal to the cpu. 9.1 maskable interrupts (int#) the controller can be enabled to interrupt the cpu when the followin g types of memory or pci bus errors occur. illegal address errors: memory accesses by the cpu to physical addresses outside of one of the five memory ran g es, one of the three pci windows, or one of the controller ? s internal re g isters target abort, master abort, and retry limit errors: pci bus accesses by the cpu that result in a tar g et abort, master abort, or more retries than specified by the retry value re g ister the controller reports errors to the cpu by assertin g the int# si g nal, if enabled by bit 0 in the interrupt control and status re g ister (section 9.1.2). the cpu ? s interrupt ser- vice routine can then read the bus error status re g ister (section 9.1.1) to determine the type of error. the int# si g nal is a level-sensitive output to the cpu and may not be shared with other interrupt g enerators. the controller does not prioritize the various interrupt sources. durin g cpu reads, any detected errors cause the controller to return the correct num- ber of data words. however, the bus error bit is set in syscmd[0] for those words that are returned after the word that caused the bus error. for dma accesses to controller memory that miss the confi g ured memory ran g es, the bus error status re g ister contains the error information, just as for errors durin g cpu accesses. dma accesses to the pci bus that result in a tar g et abort, master abort, or more retries than specified set the error type field in the bus error status re g ister but not the error address field. bus errors g enerated by the dma cause the dbe interrupt to be g enerated, if enabled. external pci accesses that hit either tar g et window, but miss all internal controller resources, will set the et code to 0 and the error address. the error address will be the translated address. external pci accesses can never set an et code other than 00. this bus error sets the pbe interrupt, if enabled.
85 v rc 4375 system controller 9.1.1 bus error status register the cpu reads this re g ister when the cpu detects a bus error interrupt from the con- troller to determine the cause of the error. the contents remain constant after the error, until read by the cpu. the re g ister is at offset 0x50; at reset, it is set to 0x50. this re g - ister contains the followin g fields. bits 1:0 et error type (read only) 00 = ille g al address 01 = tar g et abort received 10 = master abort si g naled 11 = retry limit reached. the value specified in the retry value re g ister (section 7.6.7.1) has been reached. bits 31:2 ea error address (read only) the most-si g nificant 30 bits of the local (controller side) physical address that caused the error. this field is valid for cpu and dma unit accesses to the controller ? s memory. it is not valid for dma unit accesses to the pci bus memory space. 9.1.2 interrupt control and status register the interrupt control and status re g ister is read only in its lower byte, read/write in its middle two bytes, and write only in the hi g h byte. the low byte should be read by the cpu, alon g with the bus error status re g ister, when the cpu detects an int# interrupt from the controller. the contents of the interrupt control and status re g ister remain constant after the error, until read by the cpu. the re g ister is at offset 0x50; it is set to 0 at reset. bit 0 cbe cpu bus error (read only) 1 = cpu bus error 0 = no such error bit 1 dma1 dma channel 1 complete (read only) 1 = transfer specified in dma control re g ister 1 is complete 0 = transfer 1 is not complete bit 2 dma2 dma channel 2 complete (read only) 1 = transfer specified in dma control re g ister 2 is complete 0 = transfer 2 is not complete bit 3 mb1 pci mailbox 1 accessed (read only) 1 = mailbox 1 accessed from the pci bus 0 = mailbox 1 not accessed bit 4 mb2 pci mailbox 2 accessed (read only) 1 = mailbox 2 accessed from the pci bus 0 = mailbox 2 not accessed bit 5 dbe dma bus error (read only) 1 = a bus error occurred durin g a dma transfer 0 = no bus error
86 v rc 4375 system controller bit 6 pbe pci bus error (read only) 1 = a bus error occurred durin g a pci tar g et access 0 = no bus error bit 7 par pci parity error (read only) 1 = parity error. the error can be on an address par- ity durin g a tar g et cycle, a data parity durin g a tar g et write cycle, or a data parity durin g a master read cycle. 0 = no parity error bit 8 cbemsk cpu bus error enable (read/write) 1 = enables cpu bus error interrupts 0 = disables cpu bus error interrupts bit 9 dma1msk dma channel 1 complete enable (read/write) 1 = enables dma channel 1 complete interrupts 0 = disables dma channel 1 complete interrupts bit 10 dma2msk dma channel 2 complete enable (read/write) 1 = enables dma channel 2 complete interrupts 0 = disables dma channel 2 complete interrupts bit 11 mb1msk pci mailbox 1 access enable (read/write) 1 = enables pci mailbox 1 accessed interrupts 0 = disables pci mailbox 1 accessed interrupts bit 12 mb2msk pci mailbox 2 access enable (read/write) 1 = enables pci mailbox 2 accessed interrupts 0 = disables pci mailbox 2 accessed interrupts bit 13 dbemsk dma bus error enable (read/write) 1 = enables dma bus error interrupts 0 = disables dma bus error interrupts bit 14 pbemsk pci bus error enable (read/write) 1 = enables pci bus error interrupts 0 = disables pci bus error interrupts bit 15 parmsk pci parity error enable (read/write) 1 = enables pci parity error interrupts 0 = disables pci parity error interrupts bit 16 dma3 dma channel 3 complete (read only) 1 = transfer specified in dma control re g ister 3 is complete 0 = transfer 3 is not complete bit 17 dma4 dma channel 4 complete (read only) 1 = transfer specified in dma control re g ister 4 is complete 0 = transfer 4 is not complete bit 18 dma3msk dma channel 3 complete enable (read/write) 1 = enables dma channel 3 complete interrupts 0 = disables dma channel 3 complete interrupts
87 v rc 4375 system controller bit 19 dma4msk dma channel 4 complete enable (read/write) 1 = enables dma channel 4 complete interrupts 0 = disables dma channel 4 complete interrupts bit 20 dma3clr dma channel 3 complete clear (write only) 1 = clears the dma channel 3 complete interrupt. always returns 0 when read. bit 21 dma4clr dma channel 4 complete clear (write only) 1 = clears the dma channel 4 complete interrupt. always returns 0 when read. bit 22 uartint uart interrupt to the cpu (read only) 1 = a uart interrupt to the cpu is active (always returns 0 when read). 0 = no uart interrupt the source of this interrupt is any of the four interrupt sources described in section 6.12. bit 23 uartinten uart interrupt to the cpu (read/write) 1 = enables all uart interrupt sources (always returns 0 when read) 0 = disables all uart interrupt sources this bit is a g lobal enable for all uart interrupt sources that are individually enabled in the uart interrupt enable re g ister (uartier), section 6.12. clearin g all bits in uartier would clear the uart interrupts, thus clearin g uartint (bit 22). bit 24 cbeclr cpu bus error clear (write only) 1 = clears the cpu bus error interrupt. always returns 0 when read. bit 25 dma1clr dma channel 1 complete clear (write only) 1 = clears the dma channel 1 complete interrupt. always returns 0 when read. bit 26 dma2clr dma channel 2 complete clear (write only) 1 = clears the dma channel 2 complete interrupt. always returns 0 when read. bit 27 mb1clr pci mailbox 1 access clear (write only) 1 = clears the pci mailbox 1 accessed interrupt. always returns 0 when read. bit 28 mb2clr pci mailbox 2 access clear (write only) 1 = clears the pci mailbox 2 accessed interrupt. always returns 0 when read. bit 29 dbeclr dma bus error clear (write only) 1 = clears the dma bus error interrupt. always returns 0 when read. bit 30 pbeclr pci bus error clear (write only) 1 = clears the pci bus error interrupt. always returns 0 when read. bit 31 parclr pci parity error clear (write only) 1 = clears the pci parity error interrupt. always returns 0 when read.
88 v rc 4375 system controller 9.1.3 timers/pci inta # interrupt control and status register 2 the timers/pci inta# interrupt control/status re g ister 2 has three timers: the set nmi timer, set timer counter, and read timer counter. these timers are clocked at the cpu bus clock rate. the frequency of the timer clock is pro g rammable; it can be slowed down to 1/8 of the cpu clock so that slower events can be timed. all three tim- ers are readable and writable by the cpu. timers can be read by the cpu while they are countin g . they can be automatically reloaded with the previously loaded value and restarted or can be stopped while in pro g ress. all three timers issue interrupts (which can be enabled/disabled) to the cpu upon reachin g their maximum value. the timers/pci inta # interrupt control/status re g ister 2 resides at offset 0xe4. bits 10:8 indicate the end of the timer count; when set, the bits indicate there is a timer event that completed, causin g an interrupt pendin g bit to set. this re g ister also con- tains pci inta# control bits. this input into the pci interface allows external pci devices to interrupt the cpu. upon receivin g an interrupt from the controller, they are read by the cpu to ascertain the interruptin g device. the contents of the interrupt con- trol and status re g ister remain constant after the interrupt, until read and cleared by the cpu. the timers are clocked at the cpu bus clock rate or selectable clock frequen- cies (bits 29:24), so timin g calculation must be made accordin g ly. all timers count up. the write re g isters (set timer re g isters) have a different offset from the read re g isters (read timer counter re g isters), so write re g isters are not affected while a value is read from the read re g isters, which indicate a runnin g count of the timer/counter. once a value is loaded in the set timer re g isters, it stays there until the timer ? s interrupts are cleared. in the timer interrupt control and status re g ister, the ori g inal value can be reloaded in the counter to restart it from that count, if the tn reload enable bit is set . interrupts are automatically cleared when the cpu reads this re g ister followin g asser- tion of an interrupt pendin g bit. 9.1.3.1 set nmi timer re g ister this re g ister is read/writable by the cpu. the cpu loads a value in it and the counter starts countin g up. when it reaches 0xffff ffff, it g enerates an interrupt to the cpu, provided appropriate control bits are set. see the bit description below for the timer interrupt control and status re g ister. 9.1.3.2 set timer counter re g ister 1 this re g ister is read/writable by the cpu. the cpu loads a value in it and the counter starts countin g up. when it reaches 0xffff ffff, it g enerates an interrupt to the cpu, provided appropriate control bits are set. see the bit description below for the timer interrupt control and status re g ister. 9.1.3.3 set timer counter re g ister 2 this re g ister is read/writable by the cpu. the cpu loads a value in it and the counter starts countin g up. when it reaches 0xffff ffff, it g enerates an interrupt to the cpu, provided appropriate control bits are set. see the bit description below for the timer interrupt control and status re g ister. 9.1.3.4 read nmi timer counter re g ister this re g ister is read only by the cpu. the cpu can read its value to g et the timer count.
89 v rc 4375 system controller 9.1.3.5 read timer counter re g ister 1 this re g ister is read only by the cpu. the cpu can read its value to g et the timer count. 9.1.3.6 read timer counter re g ister 2 this re g ister is read only by the cpu. the cpu can read its value to g et the timer count. the timer interrupt control and status re g ister is set to 0 at reset and contains the fol- lowin g fields. bit 0 nmiten nmi timer enable (read/write) 1 = enables, starts the timer 0 = disables, stops the timer bit 1 t1en timer 1 enable (read/write) 1 = enables, starts the timer 0 = disables, stops the timer bit 2 t2en timer 2 enable (read/write) 1 = enables, starts the timer 0 = disables, stops the timer bit 3 pciintaen pci interrupt (pci inta #) enable (read/write) 1 = enables pci inta# input for interruptin g the cpu 0 = disables pci inta# input from interruptin g the cpu; the interrupt will be pendin g . in the event the interrupt enable bit is not set, the inta# si g nal is latched internally and will not be released until cleared by the cpu. the cpu is inter- rupted only after this bit is set. bit 4 pciintclr pci interrupt a # clear (write only) 1 = clears the pendin g interrupt 0 = do not care; no action bit 5 pciint pci interrupt a # (read only) 1 = pci interrupt a# pendin g 0 = no pci interrupt a# pendin g bits 7:6 reserved hardwired to 0x00 bit 8 nmiint nonmaskable interrupt (read only) 1 = nonmaskable interrupt pendin g 0 = no nonmaskable interrupt pendin g if this bit is set while the cpu reads this re g ister, a clear pulse clears it. if the clock ed g e where this pulse is g enerated coincides with the clock ed g e where a new interrupt is to be recorded, then settin g of this bit takes priority (this bit is not cleared). it is cleared in a subsequent read by the cpu. this also applies to bits 9 and 10.
90 v rc 4375 system controller bit 9 t1int t1 interrupt (read only) 1 = t1 interrupt pendin g 0 = no t1 interrupt pendin g bit 10 t2int t2 interrupt (read only) 1 = t2 interrupt pendin g 0 = no t2 interrupt pendin g bit 11 reserved hardwired to 0 bit 12 nmiinten nmi interrupt enable (read/write) 1 = enables nmi interrupt 0 = disables nmi interrupt bit 13 t1inten t1 interrupt enable (read/write) 1 = enables t1 interrupt 0 = disables t1 interrupt bit 14 t2inten t2 interrupt enable (read/write) 1 = enables t2 interrupt 0 = disables t2 interrupt bit 15 reserved hardwired to 0 bit 16 nmitreload nmi timer reload (read/write) 1 = automatically reloads the ori g inal timer value and starts if nmiten is set 0 = does not reload bit 17 t1reload t1 reload (read/write) 1 = automatically reloads the ori g inal timer value and starts if t1en is set 0 = does not reload bit 18 t2reload t2 reload (read/write) 1 = automatically reloads the ori g inal timer value and starts if t2en is set 0 = does not reload bits 23:19 reserved hardwired to 0 bits 25:24 nmitfr nmi timer clock frequency selection 00 = cpu bus clock rate 01 = cpu bus clock rate divided by 2 10 = cpu bus clock rate divided by 4 11 = cpu bus clock rate divided by 8 bits 27:26 t1fr timer 1 clock frequency selection 00 = cpu bus clock rate 01 = cpu bus clock rate divided by 2 10 = cpu bus clock rate divided by 4 11 = cpu bus clock rate divided by 8 bits 29:28 t2fr timer 2 clock frequency selection 00 = cpu bus clock rate 01 = cpu bus clock rate divided by 2 10 = cpu bus clock rate divided by 4 11 = cpu bus clock rate divided by 8
91 v rc 4375 system controller bits 31:30 reserved hardwired to 0 9.2 nonmaskable interrupts (nmi#) the controller asserts nmi# when a pci device asserts serr#. it also asserts nmi# when the nmi interrupt timer times out.
92 v rc 4375 system controller 10.0 clocking the controller receives a 66-mhz oscillator reference clock (refclk) si g nal and dis- tributes the 66-mhz masterclock si g nal to the cpu. the controller also g enerates and distributes four copies of the 33-mhz pci clock (clk[3:0]). fi g ure 11 shows the con- troller ? s clock connections with the system. fi g ure 11. clock connections input pad refclk controller cpu masterclock syncout syncin tclk 0.1 inch nc 3 x 10 ohm clk[0] clk[1] clk[2] 1 inch sysad, syscmd, etc. ( 3 inches long) maximum clock-to-clock jitter: 200 ps board propagation delay: 1.6 2.2 ns (all clocks will track due to equal 11-inch traces routed on the inner layer) 33-mhz pci clock 3 output pads (~35 pf 10 pf) 66-mhz cpu masterclock 1 output pad (8 pf 4 pf) pci timing summary using the pci clock signal clk[0] at the controller pin as the reference edge: design budget: tov = (3.4 ns, 14.4 ns) tis = 6.6 ns available tih = 3.4 ns available cpu timing summary using masterclock at the controller pin as the reference edge: design budget: tov = (2.2 ns,10.5 ns) tis = 5.8 ns available tih = 1.5 ns available cpu timing summary using masterclock at the cpu pin as the reference edge: design budget: tov = (1.5 ns, 8.5 ns) tis = 4.0 ns tih = 2.0 ns
93 v rc 4375 system controller 11.0 reset configuration signals the risin g ed g e of the pci bus reset si g nal (rst#) serves as the controller ? s reset. table 30 lists the confi g uration si g nals that the controller samples for one refclk ed g e while rst# is active. table 30. reset confi g uration si g nals muxad signals function description muxad[2:0] boot rom size table 14 on page 24 muxad[7:3] boot rom write protect section 6.5.3 on page 26 muxad[8] flash memory boot enable 1 = enable 0 = disable section 6.5.4 on page 26 muxad[9] not used muxad[10] (legacy) processor interface (legacy) endian byte order 1 = big endian 0 = little endian muxad[11] pci interface endian byte order 1 = big endian 0 = little endian muxad[12] processor interface (new) endian byte order 1 = big endian 0 = little endian legal combinations allowed: bits 12:10 = 001, 100, 110, 000 muxad[14:13] boot rom width 00 = 8 bits, bbe0# asserted 01 = 16 bits, bbe0#,1# asserted 10 = 32 bits, bbe[3:0]# asserted 11 = not used writes to flash memory should be done in word format. reads from flash memory can be on any of the above boundaries. muxad[15] reserved muxad[19:18] flash/boot rom size in simm slot 2 00 = 8 mb 01 = 16 mb 10 = 32 mb 11 = 64 mb muxad[20] base and simm memory device ac- cess time for subsequent words after initial word (this is in addition to cas latency selection as defined in the control registers in section 6.0). 1 = two cycles 0 = three cycles
94 v rc 4375 system controller 12.0 endian mode software issues 12.1 overview endian mode refers to a device ? s word-addressin g method and byte order. big-endian devices address data items at the big end (most-si g nificant bit number). the most-si g - nificant byte (msb) in an addressed data item is at the lowest address. little-endian devices address data items at the little end (least-si g nificant bit number). for a little- endian device, the most-si g nificant byte (msb) in an addressed data item is at the highest address. the native endian mode for mips processors, such as motorola ? and ibm ? 370 ? pro- cessors, is bi g -endian mode. however, the native mode for intel ? (which developed the pci standard) and vax ? processors is little-endian mode. for pci-compatibility reasons, most pci-peripheral chips, includin g the v rc 4375 controller, operate natively in little-endian mode. while the v rc 4375 controller is natively little endian, it supports either bi g - or little- endian mode in the cpu interface. the state of the muxad[12:11] si g nal at reset deter- mines this endian mode. however, there are important considerations when usin g the controller in a mixed-endian desi g n. the most important aspect of the endian issue is which byte lanes of the sysad bus are activated for a particular address. if bi g -endian mode is implemented for the cpu interface, the controller swaps bytes within words and halfwords that are comin g in and g oin g out on the sysad bus. all of the controller ? s other interfaces operate in little-endian mode. the followin g implica- tions are associated with this: ? muxad[11] is sampled upon power-on reset and the correspondin g bit 0 (pbe) in the endian mode (em) re g ister is set/reset. if tied hi g h, bit 0 is set to 1. the cpu has read/write privile g es. ? muxad[12] is sampled upon power-on reset and the correspondin g bit 1 (cbe) in the em re g ister is set/reset. if tied hi g h, bit 1 is set to 1. the cpu has read/write privile g es. ? muxad[10] is sampled upon power-on reset and the pbe and cbe bits in the emulation mode (em) re g ister are set to 1. muxad[12:11] must be 00. fi g ure 12. endian mode (em) re g ister msb lsb 31 24 23 16 15 8 replicate byte 0 pbe word address 0 7 cbe 5 rev3 pcimw1en pcimw2en pcimi/oen 1 2 3 4
95 v rc 4375 system controller the endian mode re g ister contains the followin g bits. bit 0 pci bi g endian pci bus is big endian 0 = do not swap bytes 1 = swap bytes bit 1 cpu bi g endian cpu bus is big endian 0 = do not swap bytes 1 = swap bytes bit 2 rev3 v rc 4375 revision 0 = revision 2 or earlier 1 = revision 3 bit 3 pcimw1en pci access through master window 1 byte steerin g will be enabled if this bit is set with the be bit. see the truth table in table 31. bit 4 pcimw2en pci access through master window 2 byte steerin g will be enabled if this bit is set with the be bit. see the truth table in table 31. bit 5 pcii/oen pci access through i/o window byte steerin g will be enabled if this bit is set with the be bit. see the truth table in table 31. note: at power-on reset, do not pull muxad[10] and muxad[11] hi g h at the same time, as this may cause a malfunction. the sections below view the endian issue from a pro g rammer ? s perspective. they describe how to implement mixed-endian desi g ns and how to make code endian inde- pendent. ? data in memory is always ordered in little-endian mode, even with a bi g -endian cpu or pci interface. ? data in all internal re g isters and fifos is considered little endian, re g ardless of cpu or pci endianness.
96 v rc 4375 system controller 12.2 endian mode operation the controller provides steer-byte and swap-byte mechanisms from/to a bi g -endian cpu to/from internal re g isters and pci re g isters/devices. byte steerin g occurs durin g re g ister access only if steerin g is enabled. data swappin g is always enabled for the cpu and system controller in different endian modes. data steerin g has hi g her priority than data swappin g . table 31 displays the truth table. byte steerin g occurs as shown in fi g ure 13. after power-on reset, byte swappin g is controlled by the pbe and cbe si g nals, which are set if there is a pull-up resistor at the si g nal pins muxad[11] and muxad[12]. (see fi g ure 14.) fi g ure 15 shows the bit and byte order of the two endian modes, as it applies to bytes within word-sized data items. the bit order within bytes is the same for both modes. the bi g (most-si g nificant) bit is on the left side, and the little (least-si g nificant) bit is on the ri g ht side. only the bit order of subitems is reversed within a lar g er addressable data item (halfword, word, doubleword, or quadword) when crossin g between the two endian modes. the subitem order of si g nificance within the lar g er data item remains the same. for example, the least-si g nificant halfword (lshw) in a word is always to the ri g ht and the most-si g nificant halfword (mshw) is to the left. when endian mode re g ister bit 1 is set, the data bytes are steered as shown in fi g ure 13. fi g ure 13. byte steerin g mechanism aa lsb bb cc dd msb cpu is big endian. data as it appears on the sysad bus: 31 0 23 15 7 0 1 2 3 cpu adr lsbs access type 00 word aabbccdd lower halfword 10 ---- ----aabb ccdd---- ---- upper halfword 00 ---- ---- ---- aa ---- ---- bb ---- ---- cc ---- ---- dd ---- ---- ---- byte 0 (lsb) 11 10 01 00 byte 1 byte 2 byte 3 (msb) word start address v rc 4375 cpu 0 31 lsb msb sysad data aabbccdd aabb---- ---- ---- ----ccdd aa---- ---- ---- ---- bb ---- ---- ---- ---- cc ---- ---- ---- ---- dd 0 31 lsb msb ----> ----> ----> ----> ----> ----> ----> steered data as it appears in the internal registers, pci configuration registers, and pci data bus (external pci register):
97 v rc 4375 system controller table 31. byte steer/swap truth table when endian mode re g ister bit 1 is set, the data bytes are swapped as shown in fi g ure 14. fi g ure 14. byte swap mechanism em re g : rev3 re g . access note be swa p b y te or steer b y te 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ----> ----> ----> ----> ----> ----> ----> ----> 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 note: register access occurs when pcimw1en, pcimw2en, or pcii/oen = 1. aa lsb bb cc dd msb cpu is big endian. data as it appears on the sysad bus: 31 0 23 15 7 0 1 2 3 cpu adr lsbs access type 00 word ddccbbaa lower halfword 10 ---- ----bbaa ddcc---- ---- upper halfword 00 ---- ---- ---- aa ---- ---- bb ---- ---- cc ---- ---- dd ---- ---- ---- byte 0 (lsb) 11 10 01 00 byte 1 byte 2 byte 3 (msb) word start address v rc 4375 cpu 0 31 lsb msb sysad data aabbccdd aabb---- ---- ---- ----ccdd aa---- ---- ---- ---- bb ---- ---- ---- ---- cc ---- ---- ---- ---- dd 0 31 lsb msb ----> ----> ----> ----> ----> ----> ----> swap data as it appears in the internal registers, pci configuration registers, and pci data bus (external pci register):
98 v rc 4375 system controller fi g ure 15. bit and byte order of endian modes (word accesses) if the access type matches the data item type, subitem data swappin g is unnecessary. thus, when makin g halfword accesses into a data array consistin g of halfword data, no byte swappin g takes place. in this case, data item bit order is retained between the two endian modes. the code that sequentially accesses the halfword data array would be identical, re g ardless of the endianness of its cpu. the code would be endian indepen- dent. however, when makin g halfword accesses into a data array consistin g of word data, access to the more significant halfword requires the address correspondin g to the less significant halfword (and vice versa). such code is not endian independent. a super- g roup access (for example, accessin g two halfwords simultaneously as a word from a halfword data array) causes the same problem. such problems also arise when a half- word access is made into a 32-bit i/o re g ister, whereas a word access into a 32-bit re g - ister creates no problem. 12.3 lan controller example the amd ? am79c971 ? lan controller is one example of a pci bus device that is natively little endian but adapts to mixed-endian environments. this lan controller supports bi g -endian system interfaces with two data types: a 32-bit word correspond- in g to the width of i/o re g isters, and an 8-bit byte correspondin g to the width of the ethernet dma fifo. 12.3.1 dma accesses from ethernet fifo ethernet data packets consist of bytes. to maximize bus bandwidth, these bytes are transferred usin g 32-bit word dma accesses into memory. the mismatch in the mixed- endian environment means that a byte swap must be performed to allow the little- endian lan controller to access the bi g -endian memory. the lan controller provides its own internal hardware for this byte swap. aa msb bb cc dd lsb cpu big-endian sysad data 31 0 24 23 16 15 8 7 word start address dd msb cc bb aa lsb cpu little-endian sysad data 31 0 24 23 16 15 8 7 0 msb = most-significant byte lsb = least-significant byte 0 1 2 3 0 1 2 3
99 v rc 4375 system controller 12.3.2 word accesses into i/o registers the 32-bit internal i/o re g isters of the lan controller are assumed to be accessed by 32-bit word transfers. in that case, the access type and data type match, and no swap- pin g of bytes or halfwords is needed because the order of si g nificance is the same for both endian modes. for such word transfers, the i/o re g ister model is endian indepen- dent; internal swappin g hardware for nonword accesses into the i/o re g isters is not provided. word accesses offer the advanta g e that the re g ister address values documented in the am79c971 technical manual can be used without chan g e (althou g h offsets for individ- ual re g ister fields such as the pci latency timer must be i g nored). the position of indi- vidual re g ister fields, as well as byte position within these fields, would also remain as documented in the am79c971 technical manual . 12.3.3 byte or halfword accesses into i/o registers word accesses can cause some inconvenience (for example, shadow re g isters) when modifyin g only one or two fields within a 32-bit pci re g ister. in this case, byte or half- word access to the 32-bit re g ister may be simpler. this type of transfer is analo g ous to the halfword access into a data array consistin g of word data types shown in fi g ure 13 and fi g ure 14. such accesses are mismatched to the defined data type and must be cross-addressed to g et the byte or halfword of interest. the am79c971 lan controller does not provide bi g -endian hardware support to deal with byte or halfword transfers into the i/o re g isters. code written to perform byte or halfword accesses into the 32-bit i/o re g isters will not be endian independent. the i/o re g ister field addresses documented in the am79c971 technical manual are based on a re g ister model derived from a little-endian perspective. the number order of these addresses pro g resses from ri g ht (least si g nificant) to left. however, a bi g - endian system will respond to all addresses as if the number order pro g resses from left (most si g nificant) to ri g ht. to access the desired byte or halfword, the address order documented in the am79c971 technical manual must be reversed. the pci status re g ister and pci command re g ister fields are examples of frequently used i/o re g ister fields. the address offsets documented in the technical manual are 0x06 and 0x04, respectively. the pci command re g ister field is located in the less si g - nificant halfword of the 32-bit i/o re g ister that is also located at offset 0x04. the pci command re g ister field shares the same offset with its 32-bit re g ister because of the little-endian number order. in a bi g -endian system, the more si g nificant halfword (pci status re g ister field) would share the same offset value with its 32-bit re g ister. so, if the offset 0x04 is used to access the pci command re g ister field, a bi g -endian system would actually access the pci status re g ister field. to access the proper halfword, the offsets must be exchan g ed between the two 16-bit re g ister fields. in other words, there must be a reversal (or swappin g ) of number order, relative to the information docu- mented in the am79c971 technical manual . these special addressin g considerations are completely independent of the operand pointers associated with the cpu re g ister used as the source or destination. the source or destination within the cpu ? s re g ister file can be at any location, size, or ali g n- ment without alterin g the transfer results. a common error is to byte-swap cpu re g ister data when transferrin g a halfword to or from a 32-bit re g ister. the order of si g nificance is the same for both endian modes, so no byte swappin g is needed. this is purely an addressin g problem.
100 v rc 4375 system controller table 32 and table 33 show how the offsets in the am79c971 technical manual are swapped with other offsets to produce the proper cross-addressed offset required by bi g -endian systems. the determinin g factors for the swap are the values of the two least-si g nificant bits of the offsets. accordin g to the am79c971 technical manual , the pci command re g ister field has the offset 0x04. table 33 shows that the offset 0x06 is needed to access the pci command re g ister field. the two least-si g nificant bits of 0x04 are b00, which convert to b10 to g ive the result of 0x06h. 12.4 gui controller example the cirrus lo g ic ? cl-gd5465 ? gui controller is another example of a pci bus device that offers some mixed-endian support. the desi g ners of this gui controller assumed three data types: 32-bit word, 16-bit halfword, and 8-bit byte. unlike the lan controller, which could make certain assumptions as to data type (for i/o re g ister or dma fifo accesses), the gui hardware cannot determine what data type will be used durin g any particular data transfer; any data type mi g ht be involved in any i/o re g ister or rambus ? dram (rdram ? ) access. the data type must be known for a g iven bus transfer so that the appropriate byte or halfword swap can be performed. the data types may chan g e from one bus cycle to the next; one software task may be operatin g in parallel with and independently of another software task. one of the easiest methods by which to accommodate such an environment, without semaphores and such, is to provide address apertures into the memory space. the aperture scheme calls for gui hardware resources to be mirrored into three address ran g es. dependin g on which address ran g e is selected, a specific data type and data swap is used. chapter 13 of the cl-gd5465 technical reference manual g ives details of these three apertures. table 32. cross addressin g for byte accesses into a 32-bit i/o re g ister least-significant bits of offset from am79c971 technical manual least-significant bits of offset required by big-endian system b0 0 b1 1 b0 1 b1 0 b1 0 b0 1 b1 1 b0 0 table 33. cross addressin g for halfword accesses into a 32-bit i/o re g ister least-significant bits of offset from am79c971 technical manual least-significant bits of offset required by big-endian system b0 0 b1 0 b1 0 b0 0
101 v rc 4375 system controller 12.4.1 word accesses into i/o registers the gui controller ? s internal 32-bit i/o re g isters can be accessed with 32-bit word transfers. in this case, the access and data types match; no swappin g of bytes or half- words is required because the order of si g nificance is the same for both endian modes. with such word transfers, the i/o re g ister model is endian independent, so the first address aperture described in the cl-gd5465 technical reference manual is used. word accesses have the advanta g e that the re g ister address values documented in the technical manual can be used without chan g e (althou g h offsets for individual re g - ister fields such as the pc latency timer must be i g nored). individual re g ister field posi- tions and byte positions within these fields also remain the same, as shown in the cl-gd5465 technical reference manual . 12.4.2 accessing byte or halfword i/o registers as in the lan controller example, byte or halfword access may be simpler than word accesses when modifyin g only one or two fields within a 32-bit i/o re g ister. this type of transfer is analo g ous to the halfword access into a data array consistin g of word data types, as shown in fi g ure 13 and fi g ure 14. such accesses are mismatched to the defined data type and must be swapped to g et the byte or halfword of interest. code written to perform byte or halfword accesses into the 32-bit word i/o re g isters will not be endian independent. there are two methods for performin g byte or halfword accesses into the gui control- ler. the first method uses the apertures for halfword-swap (second aperture) and byte- swap (third aperture) operations. this method has the advanta g e that the little-endian addresses documented in the cl-gd5465 technical reference manual are the same as those used by bi g -endian code, except for the addition of the offset required to select the appropriate aperture. (as of this printin g , the second aperture remains unverified.) the second method of performin g byte or halfword accesses is to cross-address the transfer. care must be taken, however, when referencin g the cl-gd5465 technical reference manual . the i/o re g ister field addresses documented in the technical man- ual are based on a little-endian re g ister model. the address number order pro g resses from ri g ht (least si g nificant) to left. however, bi g -endian systems respond to addresses as if the number order pro g resses from left (most-si g nificant) to ri g ht. to access the desired byte or halfword, the address order documented in the cl-gd5465 technical reference manual must be reversed.
102 v rc 4375 system controller 12.4.3 accessing rdram the cl-gd5465 gui controller ? s internal pixel and video en g ines constrain rdram to little-endian state. here a g ain, bi g -endian systems have a few problems accessin g data sub g roups, such as a sin g le-byte access into a 32-bit data type. subitem accesses are also a factor for rdram. cross-addressin g and address aperture solu- tions are the same as those described in section 12.4.2. super g roup accesses are also encountered with rdram. this situation is mentioned in section 12.2. a specific gui-oriented example of this would be an 8-bit data type, such as a pixel, which is transferred four at a time to maximize pci bus bandwidth. there are two methods for dealin g with super g roup transfers. one is the address aper- ture method, used in the subitem scenario of section 12.4.2. the third aperture, byte swap, is used to provide the proper data swap for the four 8-bit pixel case. the second aperture, halfword swap, is used to transfer such thin g s as two 16-bit pixels simulta- neously. the second aperture method requires that the data order in the cpu re g ister be swapped prior to an rdram write access, or immediately after an rdram read access. to continue with the previous four-pixel transfer example, the byte number order of the four pixels in the cpu re g ister would be reversed. now the pixel number order increases, startin g from the ri g ht side of the re g ister (the first pixel ori g inally on the left is now on the ri g ht). then the four pixels are written into the rdram with a standard 32-bit word transfer (first aperture). the case of two 16-bit pixels requires the two halfwords to be swapped, but not the order of the two bytes inside the halfwords. this second method is probably more time-consumin g and is not recommended.
103 v rc 4375 system controller 13.0 timing diagrams this section provides the timin g dia g rams for v rc 4375 system controller operations, as follows. section 13.1 memory timing fi g ure 16, flash rom write, on pa g e 104 fi g ure 17, cpu word read from sdram base memory, on pa g e 105 fi g ure 18, cpu word write to sdram base memory, on pa g e 106 fi g ure 19, cpu quad read from sdram base memory, on pa g e 107 fi g ure 20, cpu quad write to sdram base memory, on pa g e 108 fi g ure 21, cpu octet read from sdram base memory, on pa g e 109 fi g ure 22, cpu octet write to sdram base memory, on pa g e 110 fi g ure 23, cpu quad read from sdram simm, on pa g e 111 fi g ure 24, cpu quad write to sdram simm, on pa g e 112 fi g ure 25, cpu octet read from sdram simm, on pa g e 113 fi g ure 26, cpu octet write to sdram simm, on pa g e 114 fi g ure 27, cpu word write to sdram simm, on pa g e 115 fi g ure 28, cpu word read from sdram simm, on pa g e 116 fi g ure 29, iochrdy si g nal timin g , on pa g e 117 fi g ure 30, cpu word read from edo base memory, on pa g e 118 fi g ure 31, cpu word write to edo base memory, on pa g e 119 fi g ure 32, cpu quad read from edo base memory, on pa g e 120 fi g ure 33, cpu quad write to edo base memory, on pa g e 121 fi g ure 34, cpu octet write to edo base memory, on pa g e 122 fi g ure 35, cpu octet read from edo base memory (1 of 3), on pa g e 123 fi g ure 36, cpu octet read from edo base memory (2 of 3), on pa g e 124 fi g ure 37, cpu octet read from edo base memory (3 of 3), on pa g e 125 section 13.2 dma timing fi g ure 38, dma transfer, on pa g e 126 fi g ure 39, dma interrupt (1 of 2), on pa g e 127 fi g ure 40, dma interrupt (2 of 2), on pa g e 128 fi g ure 41, dma transaction start (1 of 3), on pa g e 129 fi g ure 42, dma transaction end and next pointer fetch (2 of 3), on pa g e 130 fi g ure 43, dma start of next transaction (3 of 3), on pa g e 131 section 13.3 pci timing fi g ure 44, pci burst write: 16 words, on pa g e 132 fi g ure 45, pci burst read: 16 words, on pa g e 133 fi g ure 46, pci burst write: 32 words, on pa g e 134 fi g ure 47, pci burst read: 32 words, on pa g e 135 fi g ure 48, pci write: 20 words back to back, on pa g e 136 fi g ure 49, cpu 3-byte read/write from pci memory, on pa g e 137 fi g ure 50, cpu 2-byte read/write from pci memory, on pa g e 138 fi g ure 51, cpu 1-byte read/write from pci memory, on pa g e 139 fi g ure 52, pci to controller sin g le 8-byte write, on pa g e 140 fi g ure 53, pci to controller sin g le 8-byte read, on pa g e 141 fi g ure 54, pci to controller burst write: 16 words, on pa g e 142 fi g ure 55, pci to controller burst read: 16 words, on pa g e 143 fi g ure 56, pci to controller 1-byte write, on pa g e 144 fi g ure 57, pci to controller 1-byte read, on pa g e 145 fi g ure 58, pci and cpu simultaneous write: 8 words, on pa g e 146 fi g ure 59, pci and cpu simultaneous read: 8 words, on pa g e 147 fi g ure 60, pci to controller read: 2 words, on pa g e 148 fi g ure 61, pci to controller write: 2 words, on pa g e 149
104 v rc 4375 system controller 13.1 memor y timin g fi g ure 16. flash rom write 290000 300000 310000 320000 330000 340000 refclk sysad[31:0] 1fc00000 syscmd[4:0] 03 eok# evalid# pvalid# muxad[25:0] 0000000 3c00000 mras#[3:0] 1 3 7 f e c 8 0 1 3 7 f mcasa#[3:0] 0 f mda[31:0] zzzzzzzz dead1234 bras# bwe# boe# bbe#[3:0] f 0 roe# bromcs# mwe# memory write data cpu write data cpu write address a d
105 v rc 4375 system controller fi g ure 17. cpu word read from sdram base memory 720000 722000 724000 726000 728000 730000 732000 refclk sysad[31:0] 00000400 00000000 a5a5a5a5 2d2d2d28 syscmd[4:0] 03 zz 0e 11 zz sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000000 0000080 0000000 0000080 0000480 mras#[3:0] f mcasa#[3:0] 0 mda[31:0] zzzzzzzz 2d2d2d28 xxxxxxxx bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 cpu read data memory read data cpu read address/command
106 v rc 4375 system controller fi g ure 18. cpu word write to sdram base memory 622000 624000 626000 628000 refclk sysad[31:0] 00000000 a5a5a5a5 00000100 syscmd[4:0] 10 0b 10 0b sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0004000 0000000 0000400 mras#[3:0] f mcasa#[3:0] f 0 f mda[31:0] zzzzzzzz 00000001 a5a5a5a5 xxxxxxxx bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 3 0 3 0 3 0 3 0 3 0 3 0 3 memory write data write data write address/command
107 v rc 4375 system controller fi g ure 19. cpu quad read from sdram base memory 1195000 1200000 1205000 1210000 1215000 1220000 refclk sysad[31:0] 00010000 xxxxxxxx syscmd[4:0] 05 0e 19 11 sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000420 0000020 0000000 xxxxxxx xxxxxxx mras#[3:0] f mcasa#[3:0] 0 f 0 mda[31:0] zzzzzzzz cs/bras# bwe# sdcke[1:0] 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 cpu read address/command d1 d2 d3 d4 d1 d2 d3 d4 pre- charge row address column address active read
108 v rc 4375 system controller fi g ure 20. cpu quad write to sdram base memory 1186000 1188000 1190000 1192000 1194000 1196000 1198000 refclk sysad[31:0] 00010000 aaaaaaaa 55555555 2aaaaaaa 15555555 00010000 syscmd[4:0] zz 0d 18 10 05 sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000020 0000000 active write 0000420 mras#[3:0] f mcasa#[3:0] 0 f 0 f mda[31:0] zzzzzzzz xxaaaa precharge 55555555 2aaaaaaa 15555555 xxxxxxxx zzzzzzzz bras# bwe# boe# bbe#[3:0] 0 roe# iochrdy sdcke[1:0] 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 memory write data cpu write address/command
109 v rc 4375 system controller fi g ure 21. cpu octet read from sdram base memory 1150000 1155000 1160000 1165000 1170000 1175000 1180000 refclk sysad[31:0] 00010000 xxxxxxxx syscmd[4:0] 06 0e 19 11 zz sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000420 0000020 0000000 0000020 0000420 mras#[3:0] f mcasa#[3:0] 0 f 0 mda[31:0] zzzzzzzz bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 memory read data cpu read data cpu read address/command d2 d3 d4 d5 d6 d7 d8 d1 d2 d3 d4 d5 d6 d7 d8 d1
110 v rc 4375 system controller fi g ure 22. cpu octet write to sdram base memory 1135000 1140000 1145000 1150000 refclk sysad[31:0] 00010000 syscmd[4:0] 0e 18 10 06 sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000020 0000000 0000420 mras#[3:0] f mcasa#[3:0] 0 f 0 f mda[31:0] zzzzzzzz 5a5a5a50 zzzzzzzz bras# bwe# boe# bbe#[3:0] c 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 write address/command d1 d2 d3 d4 d5 d6 d7 d8 d1 d2 d3 d4 d5 d6 d7 d8
111 v rc 4375 system controller fi g ure 23. cpu quad read from sdram simm 650000 660000 670000 680000 refclk sysad[31:0] 02000004 a5a5a5ac syscmd[4:0] 05 0e 19 0e 19 0e 19 0e 11 zz sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000000 0002400 0000000 0000201 0000000 0002400 mras#[3:0] a f a f a f a f a f mcasa#[3:0] 0 f 0 mda[31:0] zzzzzzzz bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 sdclk[1:0] memory read data cpu read data cpu read address d1 d2 d3 d4 zz d1 d3 d4 d2
112 v rc 4375 system controller fi g ure 24. cpu quad write to sdram simm 635000 640000 645000 650000 655000 refclk sysad[31:0] 02000004 syscmd[4:0] 0d 18 10 05 sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000000 0000201 0000000 0002400 mras#[3:0] f a f a f a f mcasa#[3:0] 0 f mda[31:0] zzzzzzzz a5a5a5a5 a5a5a5a6 a5a5a5a7 a5a5a5a8 a5a5a5a9 bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 0 3 0 3 0 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 cpu write data cpu write address d1 d2 d3 d4 d1 d2 d3 d4
113 v rc 4375 system controller fi g ure 25. cpu octet read from sdram simm 500000 510000 520000 530000 540000 550000 refclk sysad[31:0] 02000000 00000000 syscmd[4:0] 06 0e sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000000 0000000 0000000 mras#[3:0] f a f a f a f a f mcasa#[3:0] 0 f 0 mda[31:0] zzzzzzzz bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 sdclk[1:0] cpu read address/command d1 d2 d3 d4 d5 d6 d7 d8 d1 d2 d3 d4 d5 d6 d7 d8 19 0e 19 0e 19 0e 09 0e 19 0e 19 0e 19 0e 11
114 v rc 4375 system controller fi g ure 26. cpu octet write to sdram simm 485000 490000 495000 500000 505000 510000 refclk sysad[31:0] 18 syscmd[4:0] 0e 10 06 sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000000 0000080 0000001 0000083 0002400 mras#[3:0] f mcasa#[3:0] f 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f mda[31:0] zzzzzzzz bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 f a5a5a5ac d8 d1 d2 d3 d4 d5 d7 d8 d6 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 f aa a5a5a5a5 a5a5a5ab d7 a5a5a5aa d6 a5a5a5a9 d5 a5a5a5a8 d4 a5a5a5a7 d3 a5a5a5a6 d2 a5a5a5a5 d1 f a 10 02000000 515000 cpu write data cpu write address/command 02000000 memory write data
115 v rc 4375 system controller fi g ure 27. cpu word write to sdram simm 444000 446000 448000 450000 452000 454000 refclk sysad[31:0] 04000000 ffffffff 04000000 syscmd[4:0] 0b 10 03 sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000000 0000800 0000000 0002400 mras#[3:0] f e f e f e f mcasa#[3:0] f 0 f mda[31:0] zzzzzzzz 00000001 ffffffff xxxxxxxx bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 memory write data write data cpu read address/command
116 v rc 4375 system controller fi g ure 28. cpu word read from sdram simm 450000 455000 460000 465000 470000 475000 refclk sysad[31:0] 04000000 00000000 syscmd[4:0] 03 0e 11 zz sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000000 0000800 0002400 0000000 0000800 0000000 0002400 mras#[3:0] f e f e f e f e f e f e f mcasa#[3:0] f 0 f 0 mda[31:0] ffffffff xxxxxxxx zzzzzzzz ffffffff bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 2 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 cpu read data memory read data cpu read address/command
117 v rc 4375 system controller fi g ure 29. iochrdy si g nal timin g 270000 280000 290000 300000 310000 refclk sysad[31:0] 0f0000e8 0f0000e8 syscmd[4:0] zz 10 0b 10 03 0e 11 zz 03 0e 11 zz 03 0e sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000000 mras#[3:0] 0 1 3 7 f e c 8 0 1 3 7 f e c 8 0 1 3 7 f mcasa#[3:0] 0 f mda[31:0] zzzzzzzz bras# bwe# boe# bbe#[3:0] f roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] general-purpose i/o timing control register 00000c00 (hex)
118 v rc 4375 system controller fi g ure 30. cpu word read from edo base memory 414000 416000 418000 420000 422000 424000 426000 428000 430000 refclk sysad[31:0] 00000000 syscmd[4:0] 03 0x 0e 11 zz sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0001000 0000000 0000080 0000000 mras#[3:0] f mcasa#[3:0] f 0 f mda[31:0] zzzzzzzz xxxxxxxx a5a5a5a5 bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 memory read data cpu read data cpu read addresss
119 v rc 4375 system controller fi g ure 31. cpu word write to edo base memory 310000 315000 320000 325000 refclk sysad[31:0] 00000100 syscmd[4:0] 0b 10 0b sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000000 mras#[3:0] 0 1 3 7 f mcasa#[3:0] 0 f 0 f mda[31:0] zzzzzzzz a5a5a5a5 bras# bwe# boe# bbe#[3:0] f 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 memory write data cpu write data cpu write address d
120 v rc 4375 system controller fi g ure 32. cpu quad read from edo base memory 680000 685000 690000 695000 700000 refclk sysad[31:0] 00010000 syscmd[4:0] 05 zz 0e sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000000 0000080 0000001 0000081 0000020 mras#[3:0] f mcasa#[3:0] f 0 f 0 f 0 f 0 f mda[31:0] aaaaaaaa 55555555 2aaaaaaa 15555555 zzzzzzzz bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 read address/command
121 v rc 4375 system controller fi g ure 33. cpu quad write to edo base memory 675000 680000 685000 refclk sysad[31:0] 00010000 55555555 15555555 00010000 syscmd[4:0] zz 0d 18 10 05 sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000020 0000000 0000080 0000001 0000081 mras#[3:0] f mcasa#[3:0] f 0 f 0 f 0 f 0 mda[31:0] zzzzzzzz aaaaaaaa 55555555 2aaaaaaa 15555555 bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3
122 v rc 4375 system controller fi g ure 34. cpu octet write to edo base memory 595000 600000 605000 610000 615000 620000 625000 refclk sysad[31:0] 00010000 syscmd[4:0] zz 0e 18 10 06 sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000020 0000000 0000080 0000001 0000081 0000002 0000082 0000003 0000083 mras#[3:0] f mcasa#[3:0] f 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f mda[31:0] zzzzzzzz aaaaaaaa aaaaaaab aaaaaaac aaaaaaad aaaaaaae aaaaaaaf aaaaaab0 aaaaaab1 bras# bwe# boe# bbe#[3:0] c 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 memory write data cpu write address d1 d2 d3 d4 d5 d6 d7 d8
123 v rc 4375 system controller fi g ure 35. cpu octet read from edo base memory (1 of 3) 635000 640000 645000 650000 655000 660000 665000 refclk sysad[31:0] 00000000 syscmd[4:0] 0e 19 0e 19 0e 19 0e 19 0e 19 0e 19 0e 19 0e 11 sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000020 0000000 0000080 0000001 0000081 0000002 0000082 0000003 0000083 0000004 mras#[3:0] f mcasa#[3:0] f 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f mda[31:0] zzzzzzzz bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 d1 d2 d3 d4 d5 d6 d7 d8 xx xx xx xx xx xx xx xx xx zz d1 00 d2 00 d3 00 d4 00 d5 00 d6 00 d7 00 d8
124 v rc 4375 system controller fi g ure 36. cpu octet read from edo base memory (2 of 3) 635000 640000 645000 650000 655000 660000 665000 refclk sysad[31:0] 00000000 syscmd[4:0] 0e 19 0e 19 0e 19 0e 19 0e 19 0e 19 0e 19 0e 11 sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000020 0000000 0000080 0000001 0000081 0000002 0000082 0000003 0000083 0000004 mras#[3:0] f mcasa#[3:0] f 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f mda[31:0] zzzzzzzz bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 d1 d2 d3 d4 d5 d6 d7 d8 xx xx xx xx xx xx xx xx xx zz d1 00 d2 00 d3 00 d4 00 d5 00 d6 00 d7 00 d8
125 v rc 4375 system controller fi g ure 37. cpu octet read from edo base memory (3 of 3) 645000 650000 655000 660000 665000 refclk sysad[31:0] 00000000 syscmd[4:0] 0e 19 0e 19 0e 19 0e 19 0e 19 0e 19 0e 19 0e 11 sdras# sdcas# eok# evalid# pvalid# muxad[25:0] 0000080 0000001 0000081 0000002 0000082 0000003 0000083 0000004 mras#[3:0] f mcasa#[3:0] 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f mda[31:0] aaaaaab1 bras# bwe# boe# bbe#[3:0] 0 roe# bromcs# mwe# iochrdy sdcke[1:0] 3 sdclk[1:0] 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 d1 d2 d3 d4 d5 d6 d7 d8 xx xx xx xx xx xx xx xx xx d1 00 d2 00 d3 00 d4 00 d5 00 d6 00 d7 00 d8
126 v rc 4375 system controller 13.2 dma timin g fi g ure 38. dma transfer 1270000 1280000 1290000 1300000 1310000 1320000 sysclk sysad[31:0] 0f000038 16000020 syscmd[4:0] 0b 10 pvalid# evalid# eok# mda[31:0] zzzzzzzz zzzzzzzz muxad[25:0] 0000002 0000004 0000002 0000006 bras# bwe# boe# mcasa#[3:0] f 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f pciclk frame# irdy# devsel# trdy# ad[31:0] f0000520 fffffff7 zzzzzzzz cbe#[3:0] 0 z 7 0 z stop#
127 v rc 4375 system controller fi g ure 39. dma interrupt (1 of 2) 520000 540000 560000 580000 600000 620000 sysclk sysad[31:0] 0f000038 56000040 syscmd[4:0] 0b 10 pvalid# evalid# eok# mda[31:0] zzzzzzzz zzzzzzzz muxad[25:0] 0004000 0000000 bras# bwe# boe# mcasa#[3:0] f f f f pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 zzzzzzzz cbe#[3:0] 0 z 7 0 z 7 0 z 0 z stop# int#
128 v rc 4375 system controller fi g ure 40. dma interrupt (2 of 2) 640000 660000 680000 700000 720000 740000 sysclk sysad[31:0] 56000040 0f000054 0f000054 syscmd[4:0] 10 0e 03 0b 03 pvalid# evalid# eok# mda[31:0] zzzzzzzz muxad[25:0] 0000000 0004000 bras# bwe# boe# mcasa#[3:0] f f pciclk frame# irdy# devsel# trdy# ad[31:0] zzzzzzzz f0000040 cbe#[3:0] 0 z 7 0 z 7 0 z 0 stop# int# end_dma transfer
129 v rc 4375 system controller fi g ure 41. dma transaction start (1 of 3) 2840000 2850000 2860000 2870000 2880000 sysclk sysad[31:0] 16000020 syscmd[4:0] 10 pvalid# evalid# eok# mda[31:0] zzzzzzzz zzzzzzzz muxad[25:0] 0000000 0000000 0000002 bras# bwe# boe# mcasa#[3:0] f 0 f 0 f 0 f 0 f 0 f 0 f 0 f 0 f pciclk frame# irdy# devsel# trdy# ad[31:0] f0000020 ffffffff zzzzzzzz cbe#[3:0] 0 z 7 0 z stop# int# start of a normal transaction 1
130 v rc 4375 system controller fi g ure 42. dma transaction end and next pointer fetch (2 of 3) 2930000 2935000 2940000 2945000 2950000 2955000 2960000 sysclk sysad[31:0] 16000020 syscmd[4:0] 10 pvalid# evalid# eok# mda[31:0] zzzzzzzz 00000000 muxad[25:0] 0000000 0000080 0000020 00000a0 0000021 00000a1 0000022 bras# bwe# boe# mcasa#[3:0] f 0 f 0 f 0 f 0 f pciclk frame# irdy# devsel# trdy# ad[31:0] fffffff9 fffffff8 zzzzzzzz f0000020 cbe#[3:0] 0 z 0 stop# int# fetch of next descriptor dma end of transaction 1
131 v rc 4375 system controller fi g ure 43. dma start of next transaction (3 of 3) 2960000 2970000 2980000 2990000 3000000 sysclk sysad[31:0] 16000020 syscmd[4:0] 10 pvalid# evalid# eok# mda[31:0] zzzzzzzz zzzzzzzz muxad[25:0] 0000022 0000080 0000002 0000004 0000084 0000005 0000085 0000006 0000002 bras# bwe# boe# mcasa#[3:0] f 0 f 0 f 0 f 0 f pciclk frame# irdy# devsel# trdy# ad[31:0] f0000020 cbe#[3:0] 0 z 7 0 stop# int# start of next transaction memory fetch (from source address of next pointer) fetched data goes to pci
132 v rc 4375 system controller 13.3 pci timin g fi g ure 44. pci burst write: 16 words 790000 800000 810000 820000 830000 840000 850000 860000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] zzzzzzzz muxad[25:0] 0004400 0004000 0001e07 0001e07 0001e07 bwe# boe# bras# casa#[3:0] 0 f 0 f 0 f 0 pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 aa000000 cbe#[3:0] 0 z 0 z 7 0 z stop# pci write data data on memory bus pci write address cpu write address data on pci bus 01 02 03 04 05 aa000000 01 02 03 04 05
133 v rc 4375 system controller fi g ure 45. pci burst read: 16 words 730000 740000 750000 760000 770000 780000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] aa000001 aa000001 zzzzzzzz zzzzzzzz muxad[25:0] 0000000 0000400 0000000 0000001 0000400 0000000 0000400 0000000 bras# bwe# boe# mcasa#[3:0] f 0 f 0 f 0 sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 00000000 aa000001 cbe#[3:0] z 0 z 6 0 z stop# gnt# req# pci master read data pci master write address
134 v rc 4375 system controller fi g ure 46. pci burst write: 32 words 980000 1000000 1020000 1040000 1060000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] zzzzzzzz muxad[25:0] 0001e07 0001e07 0001e07 0001e07 0001e07 0001e07 0001e07 bwe# boe# bras# casa#[3:0] f 0 f 0 f 0 f 0 f 0 f 0 f pciclk frame# irdy# devsel# trdy# ad[31:0] cbe#[3:0] 0 z 7 0 z stop# pci write data pci write address
135 v rc 4375 system controller fi g ure 47. pci burst read: 32 words 1120000 1140000 1160000 1180000 1200000 1220000 1240000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] zzzzzzzz zzzzzzzz zzzzzzzz zzzzzzzz muxad[25:0] 0001e07 0001e07 0001e07 0001e07 0001e07 0001e07 bwe# boe# bras# casa#[3:0] f 0 pciclk frame# irdy# devsel# trdy# ad[31:0] aa000010 cbe#[3:0] z 6 0 stop#
136 v rc 4375 system controller fi g ure 48. pci write: 20 words back to back 660000 680000 700000 720000 740000 760000 sysclk sysad[31:0] 00000008 0000000c 00000010 00000014 00000018 syscmd[4:0] 0b 0b 0b 0b 0b 0b pvalid# evalid# eok# mda[31:0] zzzzzzzz zzzzzzzz muxad[25:0] 0000000 0000000 0001e07 0000000 0001e07 0000000 bras# bwe# boe# mcasa#[3:0] f f f f 0 f f 0 f f sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk ad[31:0] 00000000 aa000010 00000000 cbe#[3:0] 7 0 z 0 z 7 0 z 0 z 7 0 z 0 irdy# devsel# stop#
137 v rc 4375 system controller fi g ure 49. cpu 3-byte read/write from pci memory 450000 460000 470000 480000 490000 sysclk sysad[31:0] f0000001 a1522e00 syscmd[4:0] 02 0e zz pvalid# evalid# eok# mda[31:0] zzzzzzzz muxad[25:0] 0000000 bras# bwe# boe# mcasa#[3:0] f sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] f0000004 a1522e00 zzzzzzzz f0000004 zzzzzzzz cbe#[3:0] 0 z 7 1 z 0 z 6 1 z 0 stop# cpu read address pci read address pci write address cpu write address
138 v rc 4375 system controller fi g ure 50. cpu 2-byte read/write from pci memory 490000 500000 510000 520000 530000 540000 550000 sysclk sysad[31:0] f0000002 522e0000 syscmd[4:0] 0e zz 01 0e zz pvalid# evalid# eok# mda[31:0] zzzzzzzz muxad[25:0] 0000000 bras# bwe# boe# mcasan[3:0] f sdrasn sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] f0000004 522e0000 zzzzzzzz f0000004 cbe#[3:0] z 0 z 7 3 z 0 z 6 3 z 0 stop#
139 v rc 4375 system controller fi g ure 51. cpu 1-byte read/write from pci memory 550000 560000 570000 580000 590000 600000 sysclk sysad[31:0] f0000003 2e000000 syscmd[4:0] 00 0e zz pvalid# evalid# eok# mda[31:0] zzzzzzzz muxad[25:0] 0000000 bras# bwe# boe# mcasa#[3:0] f sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] f0000004 2e000000 zzzzzzzz f0000004 cbe#[3:0] 0 z 7 z 0 z 6 7 z stop# zzzzzzzz pci read data pci read address pci write data pci write address cpu write address cpu read address
140 v rc 4375 system controller fi g ure 52. pci to controller sin g le 8-byte write 700000 705000 710000 715000 720000 725000 730000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] zzzzzzzz muxad[25:0] 0000000 bras# bwe# boe# mcasa#[3:0] 0 f sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 zzzzzzzz 00000000 aa000001 cbe#[3:0] z 0 z 7 0 z stop# gnt# req# pci master write address pci master write data pci bus grant request for bus
141 v rc 4375 system controller fi g ure 53. pci to controller sin g le 8-byte read 730000 740000 750000 760000 770000 780000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] aa000001 aa000001 zzzzzzzz zzzzzzzz muxad[25:0] 0000000 0000400 0000000 0000001 0000400 0000000 0000400 0000000 bras# bwe# boe# mcasa#[3:0] f 0 f 0 f 0 sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 00000000 aa000001 cbe#[3:0] z 0 z 6 0 z stop# gnt# req# pci master read data pci master write address
142 v rc 4375 system controller fi g ure 54. pci to controller burst write: 16 words 790000 800000 810000 820000 830000 840000 850000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] zzzzzzzz zzzzzzzz muxad[25:0] 0000400 0000000 0001e07 0001e07 0001e07 bras# bwe# boe# mcasa#[3:0] 0 f 0 f 0 f 0 sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 aa000000 cbe#[3:0] z 0 z 7 0 z stop# gnt# req# pci master write data (burst-write) pci master write address
143 v rc 4375 system controller fi g ure 55. pci to controller burst read: 16 words 860000 880000 900000 920000 940000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] zzzzzzzz zzzzzzzz zzzzzzzz muxad[25:0] 0001e07 0001e07 0001e07 0001e07 0001e07 bras# bwe# boe# mcasa#[3:0] 0 f 0 f 0 sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 00000000 aa000000 cbe#[3:0] 0 z 6 0 z stop# gnt# req# pci master read data pci master write address
144 v rc 4375 system controller fi g ure 56. pci to controller 1-byte write 950000 955000 960000 965000 970000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] zzzzzzzz muxad[25:0] 0001e07 0000000 bras# bwe# boe# mcasan[3:0] 0 f sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 zzzzzzzz 00000003 aa000001 zzzzzzzz cbe#[3:0] z 0 z 7 0 z stop# gnt# req# pci master write address pci master write data pci master bus grant pci master bus request
145 v rc 4375 system controller fi g ure 57. pci to controller 1-byte read 980000 990000 1000000 1010000 1020000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] aa000001 zzzzzzzz muxad[25:0] 0000000 0000400 0000000 0000400 bras# bwe# boe# mcasa#[3:0] f 0 f 0 sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 00000003 00000000 aa000001 cbe#[3:0] z 0 z 6 0 z stop# gnt# req# pci master write address pci master read data pci master bus grant pci master bus request
146 v rc 4375 system controller fi g ure 58. pci and cpu simultaneous write: 8 words 620000 640000 660000 680000 700000 sysclk sysad[31:0] 0f00007c 00000004 00000008 0000000c 00000010 syscmd[4:0] 03 0e 03 0b 0b 0b 0b pvalid# evalid# eok# mda[31:0] zzzzzzzz zzzzzzzz zzzzzzzz zzzzzzzz muxad[25:0] 0004000 0000000 0000000 0000000 0000000 0001e07 bras# bwe# boe# mcasa#[3:0] f f f f f 0 sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 00000000 cbe#[3:0] 0 z 7 0 z 0 stop# gnt# req#
147 v rc 4375 system controller fi g ure 59. pci and cpu simultaneous read: 8 words 800000 850000 900000 950000 1000000 sysclk sysad[31:0] syscmd[4:0] pvalid# evalid# eok# mda[31:0] zzzzzzzz muxad[25:0] 0000000 bras# bwe# boe# mcasa#[3:0] f 0 sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] aa000000 aa000002 cbe#[3:0] 0 0 0 0 0 0 stop# gnt# req# aa000000 aa000004 0 0001e07 0000000 0000001c 0 0 0 0 0 0 00 03 0e 0e 0e 0e 0e 0e 0e 0e 03 0001e07
148 v rc 4375 system controller fi g ure 60. pci to controller read: 2 words 1060000 1070000 1080000 1090000 1100000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] aa000000 aa000001 zzzzzzzz zzzzzzzz muxad[25:0] 0001e07 0001800 0001e07 0001801 0001e07 0001800 0001e07 bras# bwe# boe# mcasa#[3:0] f 0 f 0 f 0 sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 00000000 aa000000 cbe#[3:0] 0 z 6 0 stop# gnt# req# perr# serr# data on memory bus data on pci bus pci master bus grant pci master bus request aa000001 latency aa000000 aa000001
149 v rc 4375 system controller fi g ure 61. pci to controller write: 2 words 1030000 sysclk sysad[31:0] 0f00007c syscmd[4:0] 03 pvalid# evalid# eok# mda[31:0] muxad[25:0] 0001e07 0001e07 0001800 0001e07 bras# bwe# boe# mcasa#[3:0] 0 f 0 f sdras# sdcas# sdcke[1] sdcke[0] sdclk[1] sdclk[0] pciclk frame# irdy# devsel# trdy# ad[31:0] 00000000 aa000000 cbe#[3:0] 0 z 7 0 stop# gnt# req# perr# serr# data on pci data bus data on memory data bus pci master bus grant pci master bus request aa000001 1035000 1040000 1045000 1050000 1055000 1060000 1065000 aa000000 zzzzzzzz aa000001 00000000 0 z zzzzzzzz 00783800
150 v rc 4375 system controller 14.0 electrical characteristics caution: if any of the parameters exceed the specified value, the device may be physically dama g ed. 14.1 absolute maximum ratin g s 14.2 operatin g conditions 14.3 dc specifications table 34. maximum ratin g s parameter maximum rating storage temperature ? 55 c to 125 c operating ambient temperature 0 c to 70 c dc supply voltage with respect to gnd ? 0.5 v to 4.6 v dc voltage on input pins with respect to gnd ? 0.5 v to 5.5 v voltage discharged between any two pins through a 1-k ? resistor from 100 pf 2000 v maximum power dissipation 1 w table 35. operatin g conditions symbol parameter minimum typical maximum units v dd all power pins 3.0 3.3 3.6 v i dss static current consumption 2.0 300 a t c case temperature ? 40 +85 c t i junction temperature ? 40 +125 c t r input rise time 0 200 ns t f input fall time 0 200 ns table 36. dc specifications for input, output, and bidirectional pins symbol parameter minimum typical maximum units notes v il input low voltage 0 0.8 v v in input high voltage 2.0 v dd v v ol output low voltage 0.4 v v oh output high voltage 2.4 v i i input leakage current with no pull-down resistor 10 av i = v dd or gnd (maximum) i i input leakage current with 50-k ? internal pull-down resistance 28 83 190 av i = v dd i oz off-state output current 10 a i os output short-circuit current ? 250 ma v in = v il to v in c in input capacitance 7 10 pf c out output capacitance 7 10 pf c i/o i/o capacitance 7 10 pf
151 v rc 4375 system controller 14.4 ac specifications 14.4.1 pci clk[3:0] outputs the pci clk[3:0] outputs must meet ttl input levels at the destinations. fi g ure 62, fi g ure 63, and table 37 summarize the clock destination requirements per the pci local bus specification . see section 10.0 for details about clock distribution and rout- in g . fi g ure 62. pci clk input waveform at destinations fi g ure 63. clk[3:0] versus masterclock output skew at controller pins t ph0 t per0 4373-001.eps t pl0 t mid0 2.0 v 1.5 v 0.8 v 0.4 v 2.4 v t pf0 t pr0 t skw1 1.5 v 1.5 v masterclock clk[3:0] 4373-002.e p
152 v rc 4375 system controller 14.4.2 pci inputs, outputs, and input/outputs the controller can be used in both 3.3- and 5-volt pci systems. to accommodate both volta g es, consideration must be g iven to switchin g and si g nalin g levels, per the pci local bus specification .table 38 reproduces table 4-7 of the pci local bus specifica- tion, with substitutions made for v cc minimum and maximum values for the controller. timin g measurements on the controller pci pads are taken with respect to a v test volta g e of 1.5 volts. setup and hold input times are measured from the 1.5-volt level on the risin g ed g e of clk[3:0] to the 1.5-volt level on the si g nal. likewise, minimum and maximum output valid times are measured from the 1.5-volt level on the risin g ed g e of clk[0] at the controller to the 1.5-volt level on the si g nal at the controller. . table 37. clk[3:0] and masterclock destination timin g requirements symbol parameter minimum maximum units notes tper0 clk[3:0] period 30 ns tmid0 clk[3:0] mid time 0.4 tper0 0.6 tper0 ns tph0 clk[3:0] high time 11 ns tpl0 clk[3:0] low time 11 ns tpr0 clk[3:0] rise time 1 8 ns tpf0 clk[3:0] fall time 1 8 ns tjit0 jitter clk[n] to clk[m] at controller output signals 0 0 ps loading on all clocks is exactly identical. tskw0 skew clk[n] to clk[m] at destina- tions 0 1 ns this includes 200 ps of system jitter and 800 ps of system skew. tskw1 skew clk[3:0] at controller to mas- terclock at controller 0 1 clk[3:0] outputs must always be even or ahead of the masterclock output when both are measured at controller signals. table 38. timin g reference volta g es symbol 5 v pci signaling requirement 3.3-v pci signaling requirement controller universal pci timing reference values pci specification vcc = 3.0 vcc = 3.6 vth 2.4 v 0.6 vcc 1.8 v 2.16 v 2.4 v vtl 0.4 v 0.2 vcc 0.6 v 0.72 v 0.4 v vtest 1.5 v 0.4 vcc 1.2 v 1.44 v 1.5 v vstep1 n/a 0.285 vcc .86 v 1.03 v 0.285 vcc vstep2 n/a 0.615 vcc 1.85 v 2.15 v 0.615 vcc vmax 2.0 v 0.4 vcc 1.2 v 1.4 v 2.0 v
153 v rc 4375 system controller table 39. pci si g nal timin g desi g n bud g et 1 symbol parameter minimum maximum units tval clk[0] to signal valid delay: all but req[3:0]# and gnt[3:0]# 3.4 2 14.4 ns tval(ptp) clk[0] to signal valid delay: req[3:0]# and gnt[3:0]# 3.4 2 14.4 ns ton float to active delay 3.4 2 ns toff active to float delay 31.4 ns tsu input setup to clk[0]: all but req[3:0]# and gnt[3:0]# 6.6 ns tsu(ptp1) input setup to clk[0]: gnt[3:0]# 6.6 ns th input hold time from clk[0] 3.4 ns trst-off reset active to output float delay (all output drivers) 43.4 ns trst reset active time after power stable 1 s trst-clk reset active time after clk stable 100 s ttst test active to test output state (all output drivers) 43.4 ns notes: 1. the pci timing here is slightly different from the pci specification because the controller is the source of the pci clock. a controller asic meeting this timing budget will be pci compliant in a system that uses the pci clocking scheme described in section 10.0 on page 92. all timing is measured with respect to the clk[0] output signal at the controller. 2. this minimum rating is set at an extra 1 ns to provide 1-ns hold time to all pci devices.
154 v rc 4375 system controller 14.4.3 cpu interface all cpu interface si g nals are measured at the controller with respect to the 1.5-volt level of the risin g ed g e of the masterclock output si g nal at the controller. table 42 shows the cpu timin g bud g et for the controller ? s cpu interface. the controller drives the masterclock output to valid cpu masterclock input levels, as shown in fi g ure 64. for other cpu interface si g nals, the controller meets standard ttl input and output level requirements. fi g ure 64. masterclock input waveform at cpu fi g ure 65. delay from refclk t ph1 t per1 t pl1 0.8 x 3.3 v 1.5 v 0.2 x 3.3 v t pf1 t pr1 4373-003.eps table 40. clock timin g name i/o minimum typical maximum loading master clock o 1.60 3.26 5.05 50 pf sdclk o 1.57 2.86 4.37 50 pf clk[2:0] o 2.69 4.45 6.52 50 pf refclk clocks delay
155 v rc 4375 system controller fi g ure 66. timin g relationship; cpu interface, memory interface, pci interface table 41. cpu interface timin g name output delay input i/o minimum maximum minimum setup( t su ) minimum hold( t h ) loading sysad[31:0] i/o 2.80 6.63 3.20 0.00 20 pf syscmd[4:0] i/o 2.57 6.46 2.00 0.00 ? pvalid i/o ?? 2.00 0.00 ? eok i 2.71 7.74 ?? 20 pf evalid o 2.70 6.30 ?? 20 pf int# o 2.00 4.30 ?? 20 pf nmi# o 1.80 4.30 ?? 20 pf master clock output from bn input of bn delay t su t h
156 v rc 4375 system controller table 42. cpu interface si g nal timin g symbol parameter minimum maximum units tper1 masterclock period 15 50 ns tph1 masterclock high time 4 ns tpl1 masterclock low time 4 ns tpr1 masterclock rise time 1 3 ns tpf1 masterclock fall time 1 3 ns tov0 masterclock at the controller to output valid at the controller 2.2 10.5 ns trst-off reset active to output float delay (all output drivers) 43.4 ns table 43. memory interface timin g name output delay input i/o minimum maximum minimum setup minimum hold loading sdras# o 2.40 6.20 ?? 50 pf sdcas# o 2.40 6.20 ?? 50 pf boe# o 2.30 6.00 ?? 50 pf bras# o 2.30 6.50 ?? 50 pf bwe# o 2.30 6.00 ?? 50 pf bromcs# o 2.30 6.00 ?? 50 pf roe# o 2.20 5.90 ?? 50 pf bbe#[3:0] o 2.40 6.00 ?? 50 pf mras#[3:0] o 2.40 6.00 ?? 70 pf mcas#[3:0] o 2.40 6.00 ?? 70 pf mwe# o 2.30 5.90 ?? 50 pf mda[31:0] i/o 5.40 9.60 0.00 2.00 50 pf muxad[25:15] o 3.30 9.00 ?? 70 pf muxad[14:00] o 3.30 9.00 ?? 70 pf iochrdy i ?? 0.00 0.70 ? table 44. pci interface timin g name output delay input i/o minimum maximum minimum setup minimum hold loading ad[31:0] i/o 5.60 8.20 0.00 0.80 50 pf cbe#[3:0] i/o 5.60 8.20 0.00 0.80 50 pf devsel# i/o 5.50 6.40 0.00 0.60 50 pf frame# i/o 5.40 6.30 0.00 0.60 50 pf gnt#[3.0] i/o 5.50 6.50 0.00 0.60 50 pf irdy# i/o 5.50 6.30 0.00 0.60 50 pf trdy# i/o 5.40 6.10 0.00 0.60 50 pf idsel i/o 5.50 6.40 0.00 0.60 50 pf inta# i/o 5.50 6.40 0.00 0.60 50 pf lock# i/o 5.50 6.50 0.00 0.60 50 pf par i/o 4.70 5.60 0.00 2.00 50 pf perr# i/o 5.50 6.50 0.00 0.60 50 pf req[3.0] i/o 4.70 5.40 0.00 0.60 50 pf
157 v rc 4375 system controller serr# i/o 5.50 6.50 0.00 0.60 50 pf stop# i/o 5.50 6.30 0.00 0.60 50 pf rst# i ?? 0.00 2.00 ? table 44. pci interface timin g name output delay input i/o minimum maximum minimum setup minimum hold loading
158 v rc 4375 system controller 15.0 package drawing the v rc 4375 system controller uses a 256-pin tape ball g rid array (tbga) packa g e, as shown in fi g ure 67. fi g ure 67. packa g e drawin g a 1.063 0.008 item millimeters inches 27.00 0.20 a 1 0.611 max. 15.50 max. a 2 0.611 max. 15.50 max. d 1.063 0.008 27.00 0.20 e 0.056 1.435 k 0.006 0.15 m 0.012 0.30 n 0.009 min. 0.25 min. p 0.004 0.10 u 0.552 max. 14.00 max. v 0.552 max. 14.00 max. w 0.595 0.006 15.11 0.15 x 0.595 0.006 15.11 0.15 p256n2 y c 0.016 c 0.40 z 0.008 0.20 f 0.050 (t.p.) 1.27 (t.p.) g 0.024 + 0.004 ? 0.005 0.60 0.10 b 1.047 + 0.007 ? 0.006 26.60 0.15 c 1.047 + 0.007 ? 0.006 26.60 0.15 l 0.030 + 0.006 ? 0.007 0.75 0.15 h 0.020 + 0.008 ? 0.005 0.50 + 0.20 ? 0.10 j 0.043 + 0.013 ? 0.008 1.10 + 0.30 ? 0.20 notes: 1 each ball centerline is located within 0.30 mm ( 0.012 inch) of its true position (t.p.) at maximum material condition. 2 each ball centerline is located within 0.10 mm ( 0.004 inch) of its true position (t.p.) at maximum material condition. u c index mark b w x y n (z) detail of a part s k detail of b part g h j a s m m s a b*1 p l m s*2 b e v a 1 a 2 f a b a d
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