product selection guide parameter WS57LV291C-70 WS57LV291C-90 address access time (max) 70 ns 90 ns cs to output valid time (max) 20 ns 30 ns high speed 3.3 volt 2k x 8 cmos prom/rprom key features 3.3 volt 0.3 volt v cc available in 300 mil "skinny" dip fast access time immune to latch-up ? t acc = 70 ns ? up to 200 ma ? cs = 20 ns esd protection exceeds 2000v low power consumption 25 ma i cc general description the WS57LV291C is a high performance 2k x 8 uv erasable r e-p rogrammable r ead o nly m emory (rprom). this rprom is manufactured using an advanced cmos eprom manufacturing process resulting in a very low power die that affords exceptional speed capabilities with a 3.3 volt v cc supply. the WS57LV291C is configured in the standard bipolar prom pinouts, the preferred and most common pinout for high speed proms of 16k density. operating at 3.3 volts, the WS57LV291C dissipates a maximum of 25 ma under worst case conditions at maximum speed (70 ns t aa ). typical i cc at 25? is less than 20 milliamps. the WS57LV291C is packaged in a space saving 300 mil windowed, hermetic dip package. WS57LV291C v cc a 8 a 9 a 10 cs1/v pp cs2 cs3 o 7 o 6 o 5 o 4 o 3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 top view cerdip preliminary pin configuration 2-15 row decoder eprom array 16,384 bits column decoder sense amplifiers 8 cs2 cs3 outputs cs1/ v pp a0 - a4 column addresses a5 - a10 row addresses 6 5 block diagram return to main menu
a c read chara cteristics over operating range. (see above) parameter symbol WS57LV291C-70 WS57LV291C-90 units min max min max address to output delay t acc 70 90 cs to output delay t cs 20 30 ns output disable to output float * t df 20 30 address to output hold t oh 0 0 WS57LV291C 2-16 dc read chara cteristics over operating range. (see above) symbol parameter test conditions min max units v il input low voltage (note 3) ?.1 0.6 v v ih input high voltage (note 3) 2.0 v cc + 0.3 v v ol output low voltage i ol = 16 ma 0.4 v v oh output high voltage i oh = 4 ma 2.4 v (notes 1 and 2) i cc v cc active current (cmos) i cc at maximum frequency 25 ma outputs not loaded i li input leakage current v in = 3.6v or gnd ?0 10 a i lo output leakage current v out = 3.6 v or gnd ?0 10 a opera ting range range temperature v cc commercial 0 c to +70 c + 3.3v 0.3v absolute maximum ra tings* storage temperature ............................ 65 to + 150 c voltage on any pin with respect to ground .................................... 0.6v to +7v v pp with respect to ground ................... 0.6v to + 14v esd protection .................................................. > 2000v notes: 1. cmos inputs: gnd 0.3v or v cc 0.3v. 2. for ttl inputs add 5 ma i cc . 3. these are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. do not attempt to test these values without suitable equipment. * notice: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. *sampled, not 100% tested. mode pins cs1/ cs2 cs3 v cc outputs v pp read v i l v i h v i h v c c d out output disable v i h x x v c c high z output x v i l x v cc high z disable output disable x x v i l v cc high z program v pp x x v cc d in program verify v i l v i h v i h v cc d out mode selection
symbol parameter conditions ty p (5) max units c i n input capacitance v i n = 0v 4 6 pf c out output capacitance v out = 0v 8 12 pf c vpp v pp capacitance v pp = 0 v 18 25 pf 2-17 WS57LV291C a c read timing dia gram valid addresses outputs t acc t oh t cs t df valid cs cap a cit anc e (4) t a = 2 5 c, f = 1 mhz 30 pf (including scope and jig capacitance) 98 w 1.80 v d.u.t. a.c. testing input/output w a veform test lo ad (high impedance test systems) 3.0 0.0 1.5 1.5 test points note: 6. provide adequate decoupling capacitance as close as possible to this device to achieve the published a.c. and d.c. parameters. a 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between v cc and ground is recommended. inadequate decoupling may result in access time degradation or other transient performance failures. notes: 4. this parameter is only sampled and is not 100% tested. 5. typical values are for t a = 25 c and nominal supply voltages. a.c. testing inputs are driven at 3.0 v for a logic "1" and 0.0 v for a logic "0." timing measurements are made at 1.5 v for input and output transitions in both directions.
WS57LV291C 2-18 1.2 1.1 1.0 0.9 0.8 -55 -35 -15 5 25 45 65 85 105 125 ambient temperature (?) normalized i cc 1.60 1.40 1.20 1.00 0.80 0.60 4.0 4.5 5.0 5.5 6.0 supply voltage ( v ) normalized i cc 1.6 1.4 1.2 1.0 0.8 0.6 -55 -35 -15 5 25 45 65 85 105 125 ambient temperature ( ? ) normalized t aa 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 0.0 200 400 600 800 1000 capacitance ( pf ) delta t aa ( ns ) normalized supply current vs. supply voltage typical access time change vs. output loading normalized t a a vs. ambient temperature normalized supply current vs. ambient temperature
pr ogramming informa tion dc chara cteristics (t a = 25 5 c, v cc = 6.25 v 0.25 v, v pp = 12.75 0.25 v) symbols parameter min max units i li input leakage current ?0 10 a (v in = v cc or gnd) i pp v pp supply current during 60 ma programming pulse i cc v cc supply current 25 ma v ol output low voltage during verify 0.45 v (i ol = 16 ma) v oh output high voltage during verify 2.4 v (i oh = 4 ma) 2-19 WS57LV291C symbols parameter min typ max units t as address setup time 2 s t df chip disable setup time 30 ns t ds data setup time 2 s t pw program pulse width 100 200 s t dh data hold time 2 s t cs chip select delay 30 ns t rf v pp rise and fall time 1 s notes: 7. v pp must not be greater than 13 volts including overshoot. a c chara cteristics (t a = 25 5 c, v cc = 6.25 v 0.25 v, v pp = 12.75 0.25 v) pr ogramming w a veform address stable addresses v i h v i l v pp v i h v i h v i l v i l cs1/v pp data t as t df t ds t pw t dh t cs t rf t rf data out data in don't care cs2/cs3 v i h v i l
WS57LV291C 2-20 ordering information speed package package operating wsi part number (ns) type drawing temperature manufacturing range procedure WS57LV291C-70t 70 24 pin cerdip, 0.3" t1 comm? standard WS57LV291C-90t 90 24 pin cerdip, 0.3" t1 comm? standard note: 8. the actual part marking will not include the initials "ws." programming/algorithms/erasure/programmers refer to page 5-1 the WS57LV291C is programmed using algorithm d shown on page 5-9. return to main menu
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