View TMS320C6713-225_2231792.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 1 post office box 1443 ? houston, texas 77251 ? 1443 highest-performance floating-point digital signal processor (dsp): tms320c6713 ? eight 32-bit instructions/cycle ? 32/64-bit data word ? 225-, 200-mhz (gdp), and 200-, 167-mhz (pyp) clock rates ? 4.4-, 5-, 6-instruction cycle times ? 1800 /1350 , 1600 /1200 , and 1336 /1000 mips /mflops ? rich peripheral set, optimized for audio ? highly optimized c/c++ compiler velociti ? advanced very long instruction word (vliw) tms320c67x ? dsp core ? eight independent functional units: ? two alus (fixed-point) ? four alus (floating- and fixed-point) ? two multipliers (floating- and fixed-point) ? load-store architecture with 32 32-bit general-purpose registers ? instruction packing reduces code size ? all instructions conditional instruction set features ? native instructions for ieee 754 ? single- and double-precision ? byte-addressable (8-, 16-, 32-bit data) ? 8-bit overflow protection ? saturation; bit-field extract, set, clear; bit-counting; normalization l1/l2 memory architecture ? 4k-byte l1p program cache (direct-mapped) ? 4k-byte l1d data cache (2-way) ? 256k-byte l2 memory total: 64k-byte l2 unified cache/mapped ram, and 192k-byte additional l2 mapped ram device configuration ? boot mode: hpi, 8-, 16-, 32-bit rom boot ? endianness: little endian, big endian 32-bit external memory interface (emif) ? glueless interface to sram, eprom, flash, sbsram, and sdram ? 512m-byte total addressable external memory space enhanced direct-memory-access (edma) controller (16 independent channels) 16-bit host-port interface (hpi) two multichannel audio serial ports (mcasps) ? two independent clock zones each (1 tx and 1 rx) ? eight serial data pins per port: individually assignable to any of the clock zones ? each clock zone includes: ? programmable clock generator ? programmable frame sync generator ? tdm streams from 2-32 time slots ? support for slot size: 8, 12, 16, 20, 24, 28, 32 bits ? data formatter for bit manipulation ? wide variety of i2s and similar bit stream formats ? integrated digital audio interface transmitter (dit) supports: ? s/pdif, iec60958-1, aes-3, cp-430 formats ? up to 16 transmit pins ? enhanced channel status/user data ? extensive error checking and recovery two inter-integrated circuit bus (i 2 c bus ? ) multi-master and slave interfaces two multichannel buffered serial ports: ? serial-peripheral-interface (spi) ? high-speed tdm interface ? ac97 interface two 32-bit general-purpose timers dedicated gpio module with 16 pins (external interrupt capable) flexible phase-locked-loop (pll) based clock generator module ieee-1149.1 (jtag ? ) boundary-scan-compatible package options: ? 208-pin powerpad ? plastic (low-profile) quad flatpack (pyp) ? 272-ball, ball grid array package (gdp) 0.13- m/6-level copper metal process ? cmos technology 3.3-v i/os, 1.2-v internal (pyp) 3.3-v i/os, 1.26-v internal (gdp) please be aware that an important notice concerning availability, standard warrant y, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 2003, texas instruments incorporated tms320c67x, velociti, and powerpad are trademarks of texas instruments. i 2 c bus is a trademark of philips electronics n.v. corporation all trademarks are the property of their respective owners. ? ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 2 post office box 1443 ? houston, texas 77251 ? 1443 table of contents emif device speed 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bootmode 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range 91 . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 91 . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 92 . . parameter measurement information 93 . . . . . . . . . . . . . . . signal transition levels 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . timing parameters and board routing analysis 94 . . . . . . . . input and output clocks 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 99 . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing 102 . . . . . . . . . . . . . . . . synchronous dram timing 104 . . . . . . . . . . . . . . . . . . . . . . . hold /holda timing 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . busreq timing 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 114 . . . . . . . . . . . . . . . . . . . . . . . . . multichannel audio serial port (mcasp) timing 115 . . . . . . inter-integrated circuits (i2c) timing 118 . . . . . . . . . . . . . . . host-port interface timing 120 . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing 123 . . . . . . . . . . . . timer timing 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (gpio) port timing 135 . . . . jtag test-port timing 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision history 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gdp 272-ball bga package (bottom view) 3 . . . . . . . . . . . . . pyp powerpad ? qfp package (top view) 8 . . . . . . . . . . . . . description 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block and cpu (dsp core) diagram 11 . . . . . . . . . cpu (dsp core) description 12 . . . . . . . . . . . . . . . . . . . . . . . . memory map summary 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral register descriptions 16 . . . . . . . . . . . . . . . . . . . . . . signal groups description 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . device configurations 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . configuration examples 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . debugging considerations 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . terminal functions 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . documentation support 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . cpu csr register description 65 . . . . . . . . . . . . . . . . . . . . . . . interrupts and interrupt selector 67 . . . . . . . . . . . . . . . . . . . . . . external interrupt sources 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . edma module and edma selector 70 . . . . . . . . . . . . . . . . . . . pll and pll controller 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . multichannel audio serial port (mcasp) peripherals 80 . . . . . i2c 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (gpio) 86 . . . . . . . . . . . . . . . . . power-supply sequencing 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply decoupling 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . ieee 1149.1 jtag compatibility statement 88 . . . . . . . . . . . .
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 3 post office box 1443 ? houston, texas 77251 ? 1443 gdp 272-ball bga package (bottom view) v ss v ss clkin cv dd v ss v ss v ss cv dd dv dd ce2 ea4 dv dd ed17 ea6 dv dd ea13 v ss ea15 ea19 ce1 cv dd v ss gp[5] (ext_int5)/ amutein0 gp[4]/ (ext_int4)/ amutein1 cv dd ed16 be3 ce3 ea3 ea5 ea8 ea10 emu4 rsv nmi ea12 dv dd hd9/ gp[9] hd6/ ahclkr1 cv dd hd4/ gp[0] hd3/ amute1 ed20 ed19 cv dd clk mode0 pllhv are / sdcas / ssads dv dd hd14/ gp[14] hd12/ gp[12] cv dd dv dd v ss cv dd dv dd rsv v ss trst tms emu1 dv dd aoe / sdras / ssoe v ss dv dd ea11 hd15/ gp[15] hd10/ gp[10] v ss hd8/ gp[8] hd5/ ahclkx1 cv dd v ss v ss v ss ed18 be2 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss 1 2 3 4 5 6 7 8 9 1011121314 1516 1718 1920 y w v u t r p n m l k j h g f e d c b a v ss awe / sdwe / sswe rsv tck tdi tdo cv dd cv dd v ss reset v ss hd13/ gp[13] hd11/ gp[11] dv dd hd7/ gp[3] rsv dv dd ea7 ea9 v ss ea14 ea16 ea18 dv dd ea20 ea2 ardy eclkout eclkin clkout2/ gp[2] emu3 rsv emu5 be0 dv dd ce0 cv dd ea17 v ss v ss v ss dv dd emu2 v ss dv dd cv dd dv dd v ss v ss cv dd cv dd dv dd v ss cv dd cv dd dv dd v ss ea21 be1 v ss v ss cv dd cv dd rsv v ss emu0 clkout3 cv dd rsv v ss cv dd cv dd dv dd v ss hd2/ afsx1 dv dd hd1/ axr1[7] ed22 ed21 ed23 gp[6] (ext_int6) clks1/ scl1 v ss gp[7] (ext_int7) v ss v ss ed13 ed15 ed14 v ss v ss hds1 / axr1[6] has / aclkx1 hd0/ axr1[4] ed24 ed25 dv dd cv dd dv dd ed27 ed26 cv dd hds2 / axr1[5] v ss hcs / axr1[2] tout1/ axr0[4] tinp1/ ahclkx0 dv dd cv dd cv dd dv dd ed11 ed12 tout0/ axr0[2] tinp0/ axr0[3] clkx0/ aclkx0 v ss v ss ed9 v ss ed10 v ss ed28 ed29 ed30 v ss hcntl0/ axr1[3] hcntl1/ axr1[1] hr/w / axr1[0] fsx0/ afsx0 sda0 v ss v ss ed6 ed7 ed8 clkr0/ aclkr0 v ss dx0/ axr0[1] scl0 ed31 v ss dv dd hrdy / aclkr1 hhwil/ afsr1 fsr0/ afsr0 clkr1/ axr0[6] dr1/ sda1 v ss v ss dv dd ed4 ed5 dr0/ axr0[0] dv dd v ss fsr1/ axr0[7] hold holda bus req hint / gp[1] fsx1 dx1/ axr0[5] clkx1/ amute0 cv dd cv dd ed2 ed3 cv dd cv dd v ss clks0/ ahclkr0 cv dd cv dd ed0 ed1 v ss shading denotes the gdp package pin functions that drop out on the pyp package.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 4 post office box 1443 ? houston, texas 77251 ? 1443 gdp 272-ball bga package (bottom view) (continued) table 1. terminal assignments for the 272-ball gdp package (in order of ball no.) ball no. signal name ball no. signal name a1 v ss c1 gp[5](ext_int5)/amutein0 a2 v ss c2 gp[4](ext_int4)/amutein1 a3 clkin c3 cv dd a4 cv dd c4 clkmode0 a5 rsv c5 pllhv a6 tck c6 v ss a7 tdi c7 cv dd a8 tdo c8 v ss a9 cv dd c9 v ss a10 cv dd c10 dv dd a11 v ss c11 emu4 a12 rsv c12 rsv a13 reset c13 nmi a14 v ss c14 hd14/gp[14] a15 hd13/gp[13] c15 hd12/gp[12] a16 hd11/gp[11] c16 hd9/gp[9] a17 dv dd c17 hd6/ahclkr1 a18 hd7/gp[3] c18 cv dd a19 v ss c19 hd4/gp[0] a20 v ss c20 hd3/amute1 b1 v ss d1 dv dd b2 cv dd d2 gp[6](ext_int6) b3 dv dd d3 emu2 b4 v ss d4 v ss b5 rsv d5 cv dd b6 trst d6 cv dd b7 tms d7 rsv b8 dv dd d8 v ss b9 emu1 d9 emu0 b10 emu3 d10 clkout3 b11 rsv d11 cv dd b12 emu5 d12 rsv b13 dv dd d13 v ss b14 hd15/gp[15] d14 cv dd b15 v ss d15 cv dd b16 hd10/gp[10] d16 dv dd b17 hd8/gp[8] d17 v ss b18 hd5/ahclkx1 d18 hd2/afsx1 b19 cv dd d19 dv dd b20 v ss d20 hd1/axr1[7] shading denotes the gdp package pin functions that drop out on the pyp package.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 5 post office box 1443 ? houston, texas 77251 ? 1443 table 1. terminal assignments for the 272-ball gdp package (in order of ball no.) (continued) ball no. signal name ball no. signal name e1 clks1/scl1 j17 hold e2 v ss j18 holda e3 gp[7](ext_int7) j19 busreq e4 v ss j20 hint /gp[1] e17 v ss k1 cv dd e18 has /aclkx1 k2 v ss e19 hds1 /axr1[6] k3 clks0/ahclkr0 e20 hd0/axr1[4] k4 cv dd f1 tout1/axr0[4] k9 v ss f2 tinp1/ahclkx0 k10 v ss f3 dv dd k11 v ss f4 cv dd k12 v ss f17 cv dd k17 cv dd f18 hds2 /axr1[5] k18 ed0 f19 v ss k19 ed1 f20 hcs /axr1[2] k20 v ss g1 tout0/axr0[2] l1 fsx1 g2 tinp0/axr0[3] l2 dx1/axr0[5] g3 clkx0/aclkx0 l3 clkx1/amute0 g4 v ss l4 cv dd g17 v ss l9 v ss g18 hcntl0/axr1[3] l10 v ss g19 hcntl1/axr1[1] l11 v ss g20 hr/w /axr1[0] l12 v ss h1 fsx0/afsx0 l17 cv dd h2 dx0/axr0[1] l18 ed2 h3 clkr0/aclkr0 l19 ed3 h4 v ss l20 cv dd h17 v ss m1 clkr1/axr0[6] h18 dv dd m2 dr1/sda1 h19 hrdy /aclkr1 m3 fsr1/axr0[7] h20 hhwil/afsr1 m4 v ss j1 dr0/axr0[0] m9 v ss j2 dv dd m10 v ss j3 fsr0/afsr0 m11 v ss j4 v ss m12 v ss j9 v ss m17 v ss j10 v ss m18 dv dd j11 v ss m19 ed4 j12 v ss m20 ed5 shading denotes the gdp package pin functions that drop out on the pyp package.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 6 post office box 1443 ? houston, texas 77251 ? 1443 table 1. terminal assignments for the 272-ball gdp package (in order of ball no.) (continued) ball no. signal name ball no. signal name n1 scl0 u9 v ss n2 sda0 u10 cv dd n3 ed31 u11 cv dd n4 v ss u12 dv dd n17 v ss u13 v ss n18 ed6 u14 cv dd n19 ed7 u15 cv dd n20 ed8 u16 dv dd p1 ed28 u17 v ss p2 ed29 u18 ea21 p3 ed30 u19 be1 p4 v ss u20 v ss p17 v ss v1 ed20 p18 ed9 v2 ed19 p19 v ss v3 cv dd p20 ed10 v4 ed16 r1 dv dd v5 be3 r2 ed27 v6 ce3 r3 ed26 v7 ea3 r4 cv dd v8 ea5 r17 cv dd v9 ea8 r18 dv dd v10 ea10 r19 ed11 v11 are /sdcas /ssads r20 ed12 v12 awe /sdwe /sswe t1 ed24 v13 dv dd t2 ed25 v14 ea12 t3 dv dd v15 dv dd t4 v ss v16 ea17 t17 v ss v17 ce0 t18 ed13 v18 cv dd t19 ed15 v19 dv dd t20 ed14 v20 be0 u1 ed22 w1 v ss u2 ed21 w2 cv dd u3 ed23 w3 dv dd u4 v ss w4 ed17 u5 dv dd w5 v ss u6 cv dd w6 ce2 u7 dv dd w7 ea4 u8 v ss w8 ea6 shading denotes the gdp package pin functions that drop out on the pyp package.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 7 post office box 1443 ? houston, texas 77251 ? 1443 table 1. terminal assignments for the 272-ball gdp package (in order of ball no.) (continued) ball no. signal name ball no. signal name w9 dv dd y5 ardy w10 aoe /sdras /ssoe y6 ea2 w11 v ss y7 dv dd w12 dv dd y8 ea7 w13 ea11 y9 ea9 w14 ea13 y10 eclkout w15 ea15 y11 eclkin w16 v ss y12 clkout2/gp[2] w17 ea19 y13 v ss w18 ce1 y14 ea14 w19 cv dd y15 ea16 w20 v ss y16 ea18 y1 v ss y17 dv dd y2 v ss y18 ea20 y3 ed18 y19 v ss y4 be2 y20 v ss shading denotes the gdp package pin functions that drop out on the pyp package.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 8 post office box 1443 ? houston, texas 77251 ? 1443 pyp powerpad ? qfp package (top view) trst hd5/ahclkx1 hd8/gp[8] hd6/ahclkr1 hd7/gp[3] hd9/gp[9] hd10/gp[10] hd11/gp[11] hd12/gp[12] hd13/gp[13] hd14/gp[14] hd15/gp[15] nmi rsv rsv emu1 emu0 tdo tdi tms tck rsv rsv clkin clkmode0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 hd4/gp[0] hd2/afsx1 hd3/amute1 hd1/axr1[7] hd0/axr1[4] hcntl0/axr1[3] hcntl1/axr1[1] hr/ hhwil/afsr1 busreq hint ed0 ed1 ed2 ed3 ed5 ed4 ed8 ed7 ed6 ed10 ed9 ed12 ed11 ed14 ed15 ed13 ea21 ea20 ea19 ea17 ea18 ea15 ea12 ea16 ea13 ea14 ea11 clkout2/gp[2] eclkin eclkout ea10 ea9 ea7 ea8 ea6 ea5 ea4 ea3 ea2 ardy 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 gp[4](ext_int4)/amutein1 gp[6](ext_int6) gp[5](ext_int5)/amutein0 dd gp[7](ext_int7) clks1/scl1 tinp1/ahclkx0 tout1/axr0[4] clkx0/aclkx0 tinp0/axr0[3] tout0/axr0[2] clkr0/aclkr0 dx0/axr0[1] fsx0/afsx0 fsr0/afsr0 dr0/axr0[0] clks0/ahclkr0 fsx1 dx1/axr0[5] clkx1/amute0 clkr1/axr0[6] dr1/sda1 fsr1/axr0[7] scl0 sda0 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 reset /gp[1] w/axr1[0] has /aclkx1 hcs/axr1[2] hds1/axr1[6] hds2/axr1[5] hrdy/aclkr1 ce3 ce2 ce1 ce0 be1 be0 holda hold are /sdcas /ssads aoe /sdras /ssoe awe /sdwe /sswe dv dd dv dd rsv pllhv clkout3 dv dv dd dd dv dd dv dd dv dd dv dd dv dv dd dv dd dv dd dv dd dd cv cv dd dv dd dv dd cv dd cv dd cv dd cv dd dd cv dd cv dd cv cv dd cv dd dd cv cv dd dd cv dd cv dd cv dd cv cv dd cv dd dd cv dd cv cv dd cv dd v ss v ss v ss ss v v ss ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v v ss ss v v ss v ss ss v v ss ss v ss v v ss v ss v ss ss v v ss rsv v ss ss v dd cv dv dd dd dv dd cv dd cv dd dv ss v dd cv dv dd v ss cv dd dd dv dd cv v ss cv dd cv dd pyp 208-pin powerpad ? plastic quad flatpack (pqfp) ( top view ) v ss cv dd v ss
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 9 post office box 1443 ? houston, texas 77251 ? 1443 description the tms320c67x dsps (including the tms320c6713 device) compose the floating ? point dsp generation in the tms320c6000 dsp platform. the tms320c6713 (c6713) device is based on the high-performance, advanced velociti very-long-instruction-word (vliw) architecture developed by texas instruments (ti), making this dsp an excellent choice for multichannel and multifunction applications. operating at 225 mhz, the c6713 delivers up to 1350 million floating-point operations per second (mflops), 1800 million instructions per second (mips), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (mmacs). the c6713 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. the level 1 program cache (l1p) is a 4k-byte direct-mapped cache and the level 1 data cache (l1d) is a 4k-byte 2-way set-associative cache. the level 2 memory/cache (l2) consists of a 256k-byte memory space that is shared between program and data space. 64k bytes of the 256k bytes in l2 memory can be configured as mapped memory, cache, or combinations of the two. the remaining 192k bytes in l2 serves as mapped sram. the c6713 has a rich peripheral set that includes two multichannel audio serial ports (mcasps), two multichannel buffered serial ports (mcbsps), two inter-integrated circuit (i2c) buses, one dedicated general-purpose input/output (gpio) module, two general-purpose timers, a host-port interface (hpi), and a glueless external memory interface (emif) capable of interfacing to sdram, sbsram, and asynchronous peripherals. the two mcasp interface modules each support one transmit and one receive clock zone. each of the mcasp has eight serial data pins which can be individually allocated to any of the two zones. the serial port supports time-division multiplexing on each pin from 2 to 32 time slots. the c6713 has sufficient bandwidth to support all 16 serial data pins transmitting a 192 khz stereo signal. serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the philips inter-ic sound (i2s) format. in addition, the mcasp transmitter may be programmed to output multiple s/pdif, iec60958, aes-3, cp-430 encoded data channels simultaneously, with a single ram containing the full implementation of user data and channel status fields. the mcasp also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. the two i2c ports on the tms320c6713 allow the dsp to easily control peripheral devices and communicate with a host processor. in addition, the standard multichannel buffered serial port (mcbsp) may be used to communicate with serial peripheral interface (spi) mode peripheral devices. the tms320c6713 device has two bootmodes: from the hpi or from external asynchronous rom. for more detailed information, see the bootmode section of this data sheet. the tms320c67x dsp generation is supported by the ti expressdsp set of industry benchmark development tools, including a highly optimizing c/c++ compiler, the code composer studio integrated development environment (ide), jtag-based emulation and real-time debugging, and the dsp/bios kernel. tms320c6000, expressdsp, code composer studio, and dsp/bios are trademarks of texas instruments.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 10 post office box 1443 ? houston, texas 77251 ? 1443 device characteristics table 2 provides an overview of the c6713 dsp. the table shows significant features of the c6713 device, including the capacity of on-chip ram, the peripherals, the execution time, and the package type with pin count. for more details on the c67x ? dsp device part numbers and part numbering, see table 24 and figure 12. table 2. characteristics of the c6713 processor hardware features internal clock source c6713 (floating-point dsp) hardware features source gdp pyp peripherals emif sysclk3 or eclkin 1 (32 bit) 1 (16 bit) peripherals not all peripheral pins are edma (16 channels) cpu clock frequency 1 n ot a ll per i p h era l p i ns are available at the same time. hpi (16 bit) sysclk2 1 available at the same time . (for more details, see the device configuration mcasps auxclk, sysclk2 ? 2 device configuration section. ) i2cs sysclk2 2 section . ) pih l f i mcbsps sysclk2 2 peripheral performance is depe n de n t o n c hi p -l e v e l 32-bit timers 1/2 of sysclk2 2 dependent on chip - level configuration. gpio module sysclk2 1 size (bytes) 264k on-chip memory organization 4k-byte (4kb) l1 program (l1p) cache 4kb l1 data (l1d) cache 64kb unified l2 cache/mapped ram 192kb l2 mapped ram cpu id+cpu rev id control status register (csr.[31:16]) 0x0203 bsdl file for the c6713 bsdl file, contact your field sales representative. frequency mhz 225, 200 200, 167 cycle time ns 4.4 ns (c6713gdp-225) 5 ns (c6713gdpa-200) 5 ns (c6713pyp-200) 6 ns (c6713pypa-167) voltage core (v) 1.26 v [gdp package] 1.2 v [pyp package] voltage i/o (v) 3.3 v clock generator options prescaler multiplier postscaler /1, /2, /3, ..., /32 x4, x5, x6, ..., x25 /1, /2, /3, ..., /32 27 x 27 mm 272-ball bga (gdp) ? packages 28 x 28 mm ? 208-pin powerpad ? pqfp (pyp) process technology m 0.13 product status ? product preview (pp) advance information (ai) production data (pd) pd pd ? product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice. advance informa tion concerns new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice. production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. ? auxclk is the mcasp internal high-frequency clock source for serial transfers. sysclk2 is the mcasp system clock used for the clock check (high-frequency) circuit. c67x is a trademark of texas instruments.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 11 post office box 1443 ? houston, texas 77251 ? 1443 functional block and cpu (dsp core) diagram test c67x ? cpu data path b b register file instruction fetch instruction dispatch instruction decode data path a a register file power-down logic .l1 ? .s1 ? .m1 ? .d1 .d2 .m2 ? .s2 ? .l2 ? l1p cache direct mapped 4k bytes total control registers control logic l1d cache 2-way set associative 4k bytes in-circuit emulation interrupt control c6713 digital signal processor ? in addition to fixed-point instructions, these functional units execute floating-point instructions. enhanced dma controller (16 channel) l2 cache/ memory 4 banks 64k bytes total (up to 4-way) clock generator and pll x4 through x25 multiplier /1 through /32 dividers l2 memory 192k bytes emif mcasp1 mcasp0 mcbsp1 mcbsp0 i2c1 i2c0 timer 1 timer 0 gpio hpi pin multiplexing mcbsps interface to: ? spi control port ? high-speed tdm codecs ? ac97 codecs ? serial eeprom emif interfaces to: ? sdram ? sbsram ? sram, ? rom/flash, and ? i/o devices mcasps interface to: ? i2s multichannel adc, dac, codec, dir ? dit: multiple outputs 32 16
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 12 post office box 1443 ? houston, texas 77251 ? 1443 cpu (dsp core) description the tms320c6713 floating-point digital signal processor is based on the c67x cpu. the cpu fetches velociti ? advanced very-long instruction words (vliw) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. the velociti ? vliw architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. the first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. fetch packets are always 256 bits wide; however, the execute packets can vary in size. the variable-length execute packets are a key memory-saving feature, distinguishing the c67x cpu from other vliw architectures. the cpu features two sets of functional units. each set contains four units and a register file. one set contains functional units .l1, .s1, .m1, and .d1; the other set contains units .d2, .m2, .s2, and .l2. the two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. the two sets of functional units, along with two register files, compose sides a and b of the cpu (see the functional block and cpu diagram and figure 1). the four functional units on each side of the cpu can freely share the 16 registers belonging to that side. additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. while register access by functional units on the same side of the cpu as the register file can service all the units in a single clock cycle, register access using the register file across the cpu supports one read and one write per cycle. the c67x cpu executes all c62x instructions. in addition to c62x fixed-point instructions, the six out of eight functional units (.l1, .s1, .m1, .m2, .s2, and .l2) also execute floating-point instructions. the remaining two functional units (.d1 and .d2) also execute the new lddw instruction which loads 64 bits per cpu side for a total of 128 bits per cycle. another key feature of the c67x cpu is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). two sets of data-addressing units (.d1 and .d2) are responsible for all data transfers between the register files and the memory. the data address driven by the .d units allows data addresses generated from one register file to be used to load or store data to or from the other register file. the c67x cpu supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit of fsets. all instructions are conditional, and most can access any one of the 32 registers. some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically ?true?). the two .m functional units are dedicated for multiplies. the two .s and .l functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. the processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. the 32-bit instructions destined for the individual functional units are ?linked? together by ?1? bits in the least significant bit (lsb) position of the instructions. the instructions that are ?chained? together for simultaneous execution (up to eight in total) compose an execute packet. a ?0? in the lsb of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with nop instructions. the number of execute packets within a fetch packet can vary from one to eight. execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. after decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. while most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. all load and store instructions are byte-, half-word, or word-addressable.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 13 post office box 1443 ? houston, texas 77251 ? 1443 cpu (dsp core) description (continued) 8 long src dst src2 src1 src1 src1 src1 src1 src1 src1 src1 long dst long dst dst dst dst dst dst dst dst src2 src2 src2 src2 src2 src2 src2 long src long src long dst long dst long src 8 8 8 ? a15) register file b (b0 ? b15) ld1 32 msb 32 st2 32 8 8 8 ? in addition to fixed-point instructions, these functional units execute floating-point instructions. figure 1. tms320c67x ? cpu (dsp core) data paths
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 14 post office box 1443 ? houston, texas 77251 ? 1443 memory map summary table 3 shows the memory map address ranges of the c6713 device. table 3. tms320c6713 memory map summary memory block description block size (bytes) hex address range internal ram (l2) 192k 0000 0000 ? 0002 ffff internal ram/cache 64k 0003 0000 ? 0003 ffff reserved 24m ? 256k 0004 0000 ? 017f ffff external memory interface (emif) registers 256k 0180 0000 ? 0183 ffff l2 registers 128k 0184 0000 ? 0185 ffff reserved 128k 0186 0000 ? 0187 ffff hpi registers 256k 0188 0000 ? 018b ffff mcbsp 0 registers 256k 018c 0000 ? 018f ffff mcbsp 1 registers 256k 0190 0000 ? 0193 ffff timer 0 registers 256k 0194 0000 ? 0197 ffff timer 1 registers 256k 0198 0000 ? 019b ffff interrupt selector registers 512 019c 0000 ? 019c 01ff device configuration registers 4 019c 0200 ? 019c 0203 reserved 256k ? 516 019c 0204 ? 019f ffff edma ram and edma registers 256k 01a0 0000 ? 01a3 ffff reserved 768k 01a4 0000 ? 01af ffff gpio registers 16k 01b0 0000 ? 01b0 3fff reserved 240k 01b0 4000 ? 01b3 ffff i2c0 registers 16k 01b4 0000 ? 01b4 3fff i2c1 registers 16k 01b4 4000 ? 01b4 7fff reserved 16k 01b4 8000 ? 01b4 bfff mcasp0 registers 16k 01b4 c000 ? 01b4 ffff mcasp1 registers 16k 01b5 0000 ? 01b5 3fff reserved 160k 01b5 4000 ? 01b7 bfff pll registers 8k 01b7 c000 ? 01b7 dfff reserved 264k 01b7 e000 ? 01bb ffff emulation registers 256k 01bc 0000 ? 01bf ffff reserved 4m 01c0 0000 ? 01ff ffff qdma registers 52 0200 0000 ? 0200 0033 reserved 16m ? 52 0200 0034 ? 02ff ffff reserved 720m 0300 0000 ? 2fff ffff mcbsp0 data port 64m 3000 0000 ? 33ff ffff mcbsp1 data port 64m 3400 0000 ? 37ff ffff reserved 64m 3800 0000 ? 3bff ffff mcasp0 data port 1m 3c00 0000 ? 3c0f ffff mcasp1 data port 1m 3c10 0000 ? 3c1f ffff reserved 1g + 62m 3c20 0000 ? 7fff ffff emif ce0 ? 256m 8000 0000 ? 8fff ffff emif ce1 ? 256m 9000 0000 ? 9fff ffff emif ce2 ? 256m a000 0000 ? afff ffff emif ce3 ? 256m b000 0000 ? bfff ffff reserved 1g c000 0000 ? ffff ffff ? the number of emif address pins (ea[21:2]) limits the maximum addressable memory (sdram) to 128mb per ce space.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 15 post office box 1443 ? houston, texas 77251 ? 1443 l2 memory structure expanded figure 2 shows the detail of the l2 memory structure. 0x0000 0000 011 010 001 111 0x0003 0000 000 l2 mode l2 memory block base address ?????????? ??????????
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 16 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions table 4 through table 17 identify the peripheral registers for the c6713 device by their register names, acronyms, and hex address or hex address range. for more detailed information on the register contents, bit names, and their descriptions for the emif, edma, hpi, and mcbsp modules, see the tms320c6000 peripherals reference guide (literature number spru190). table 4. emif registers hex address range acronym register name 0180 0000 gblctl emif global control 0180 0004 cectl1 emif ce1 space control 0180 0008 cectl0 emif ce0 space control 0180 000c ? reserved 0180 0010 cectl2 emif ce2 space control 0180 0014 cectl3 emif ce3 space control 0180 0018 sdctl emif sdram control 0180 001c sdtim emif sdram refresh control 0180 0020 sdext emif sdram extension 0180 0024 ? 0183 ffff ? reserved table 5. l2 cache registers hex address range acronym register name 0184 0000 ccfg cache configuration register 0184 4000 l2wbar l2 writeback base address register 0184 4004 l2wwc l2 writeback word count register 0184 4010 l2wibar l2 writeback-invalidate base address register 0184 4014 l2wiwc l2 writeback-invalidate word count register 0184 4020 l1pibar l1p invalidate base address register 0184 4024 l1piwc l1p invalidate word count register 0184 4030 l1dwibar l1d writeback-invalidate base address register 0184 4034 l1dwiwc l1d writeback-invalidate word count register 0184 5000 l2wb l2 writeback all register 0184 5004 l2wbinv l2 writeback-invalidate all register 0184 8200 mar0 controls ce0 range 8000 0000 ? 80ff ffff 0184 8204 mar1 controls ce0 range 8100 0000 ? 81ff ffff 0184 8208 mar2 controls ce0 range 8200 0000 ? 82ff ffff 0184 820c mar3 controls ce0 range 8300 0000 ? 83ff ffff 0184 8240 mar4 controls ce1 range 9000 0000 ? 90ff ffff 0184 8244 mar5 controls ce1 range 9100 0000 ? 91ff ffff 0184 8248 mar6 controls ce1 range 9200 0000 ? 92ff ffff 0184 824c mar7 controls ce1 range 9300 0000 ? 93ff ffff 0184 8280 mar8 controls ce2 range a000 0000 ? a0ff ffff 0184 8284 mar9 controls ce2 range a100 0000 ? a1ff ffff 0184 8288 mar10 controls ce2 range a200 0000 ? a2ff ffff 0184 828c mar11 controls ce2 range a300 0000 ? a3ff ffff 0184 82c0 mar12 controls ce3 range b000 0000 ? b0ff ffff 0184 82c4 mar13 controls ce3 range b100 0000 ? b1ff ffff 0184 82c8 mar14 controls ce3 range b200 0000 ? b2ff ffff 0184 82cc mar15 controls ce3 range b300 0000 ? b3ff ffff 0184 82d0 ? 0185 ffff ? reserved
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 17 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions (continued) table 6. interrupt selector registers hex address range acronym register name comments 019c 0000 muxh interrupt multiplexer high selects which interrupts drive cpu interrupts 10 ? 15 (int10 ? int15) 019c 0004 muxl interrupt multiplexer low selects which interrupts drive cpu interrupts 4 ? 9 (int04 ? int09) 019c 0008 extpol external interrupt polarity sets the polarity of the external interrupts (ext_int4 ? ext_int7) 019c 000c ? 019f ffff ? reserved table 7. device registers hex address range acronym register description 019c 0200 devcfg device configuration allows the user to control peripheral selection. this register also offers the user control of the emif input clock source. for more detailed information on the device configuration register, see the device configurations section of this data sheet. 019c 0204 ? 019f ffff ? reserved n/a csr cpu control status register identifies which cpu and defines the silicon revision of the cpu. this register also offers the user control of device operation. for more detailed information on the cpu control status register, see the cpu csr register description section of this data sheet. table 8. edma parameter ram ? hex address range acronym register name 01a0 0000 ? 01a0 0017 ? parameters for event 0 (6 words) or reload/link parameters for other event 01a0 0018 ? 01a0 002f ? parameters for event 1 (6 words) or reload/link parameters for other event 01a0 0030 ? 01a0 0047 ? parameters for event 2 (6 words) or reload/link parameters for other event 01a0 0048 ? 01a0 005f ? parameters for event 3 (6 words) or reload/link parameters for other event 01a0 0060 ? 01a0 0077 ? parameters for event 4 (6 words) or reload/link parameters for other event 01a0 0078 ? 01a0 008f ? parameters for event 5 (6 words) or reload/link parameters for other event 01a0 0090 ? 01a0 00a7 ? parameters for event 6 (6 words) or reload/link parameters for other event 01a0 00a8 ? 01a0 00bf ? parameters for event 7 (6 words) or reload/link parameters for other event 01a0 00c0 ? 01a0 00d7 ? parameters for event 8 (6 words) or reload/link parameters for other event 01a0 00d8 ? 01a0 00ef ? parameters for event 9 (6 words) or reload/link parameters for other event 01a0 00f0 ? 01a0 00107 ? parameters for event 10 (6 words) or reload/link parameters for other event 01a0 0108 ? 01a0 011f ? parameters for event 11 (6 words) or reload/link parameters for other event 01a0 0120 ? 01a0 0137 ? parameters for event 12 (6 words) or reload/link parameters for other event 01a0 0138 ? 01a0 014f ? parameters for event 13 (6 words) or reload/link parameters for other event 01a0 0150 ? 01a0 0167 ? parameters for event 14 (6 words) or reload/link parameters for other event 01a0 0168 ? 01a0 017f ? parameters for event 15 (6 words) or reload/link parameters for other event 01a0 0180 ? 01a0 0197 ? reload/link parameters for event 0 ? 15 01a0 0198 ? 01a0 01af ? reload/link parameters for event 0 ? 15 ... ... 01a0 07e0 ? 01a0 07f7 ? reload/link parameters for event 0 ? 15 01a0 07f8 ? 01a0 07ff ? scratch pad area (2 words) ? the c6713 device has 85 edma parameters total: 16 event/reload parameters and 69 reload-only parameters.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 18 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions (continued) for more details on the edma parameter ram 6-word parameter entry structure, see figure 3. 31 0 edma parameter word 0 edma channel options parameter (opt) opt word 1 edma channel source address (src) src word 2 array/frame count (frmcnt) element count (elecnt) cnt word 3 edma channel destination address (dst) dst word 4 array/frame index (frmidx) element index (eleidx) idx word 5 element count reload (elerld) link address (link) rld figure 3. edma channel parameter entries (6 words) for each edma event table 9. edma registers hex address range acronym register name 01a0 0800 ? 01a0 fefc ? reserved 01a0 ff00 esel0 edma event selector 0 01a0 ff04 esel1 edma event selector 1 01a0 ff08 ? 01a0 ff0b ? reserved 01a0 ff0c esel3 edma event selector 3 01a0 ff1f ? 01a0 ffdc ? reserved 01a0 ffe0 pqsr priority queue status register 01a0 ffe4 cipr channel interrupt pending register 01a0 ffe8 cier channel interrupt enable register 01a0 ffec ccer channel chain enable register 01a0 fff0 er event register 01a0 fff4 eer event enable register 01a0 fff8 ecr event clear register 01a0 fffc esr event set register 01a1 0000 ? 01a3 ffff ? reserved
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 19 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions (continued) table 10. quick dma (qdma) and pseudo registers ? hex address range acronym register name 0200 0000 qopt qdma options parameter register 0200 0004 qsrc qdma source address register 0200 0008 qcnt qdma frame count register 0200 000c qdst qdma destination address register 0200 0010 qidx qdma index register 0200 0014 ? 0200 001c ? reserved 0200 0020 qsopt qdma pseudo options register 0200 0024 qssrc qdma pseudo source address register 0200 0028 qscnt qdma pseudo frame count register 0200 002c qsdst qdma pseudo destination address register 0200 0030 qsidx qdma pseudo index register ? all the qdma and pseudo registers are write-accessible only table 11. pll controller registers hex address range acronym register name 01b7 c000 pllpid peripheral identification register (pid) [c6713 value: 0x00010801 for pll controller] 01b7 c004 ? 01b7 c0ff ? reserved 01b7 c100 pllcsr pll control/status register 01b7 c104 ? 01b7 c10f ? reserved 01b7 c110 pllm pll multiplier control register 01b7 c114 plldiv0 pll controller divider 0 register 01b7 c118 plldiv1 pll controller divider 1 register 01b7 c11c plldiv2 pll controller divider 2 register 01b7 c120 plldiv3 pll controller divider 3 register 01b7 c124 oscdiv1 oscillator divider 1 register 01b7 c128 ? 01b7 dfff ? reserved
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 20 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions (continued) table 12. mcasp0 and mcasp1 registers hex address range acronym register name mcasp0 mcasp1 acronym register name 3c00 0000 ? 3c00 ffff 3c10 0000 ? 3c10 ffff rbuf/xbufx mcaspx receive buffer or mcaspx transmit buffer via the peripheral data bus. (used when rsel or xsel bits = 0 [these bits are located in the rfmt or xfmt registers, respectively].) 01b4 c000 01b5 0000 mcasppidx peripheral identification register [c6713 value: 0x00100101 for mcasp0 and for mcasp1] 01b4 c004 01b5 0004 pwrdemux power down and emulation management register 01b4 c008 01b5 0008 ? reserved 01b4 c00c 01b5 000c ? reserved 01b4 c010 01b5 0010 pfuncx pin function register 01b4 c014 01b5 0014 pdirx pin direction register 01b4 c018 01b5 0018 pdoutx pin data out register 01b4 c01c 01b5 001c pdin/pdsetx pin data in / data set register read returns: pdin writes affect: pdset 01b4 c020 01b5 0020 pdclrx pin data clear register 01b4 c024 ? 01b4 c040 01b5 0024 ? 01b5 0040 ? reserved 01b4 c044 01b5 0044 gblctlx global control register 01b4 c048 01b5 0048 amutex mute control register 01b4 c04c 01b5 004c dlbctlx digital loop-back control register 01b4 c050 01b5 0050 ditctlx dit mode control register 01b4 c054 ? 01b4 c05c 01b5 0054 ? 01b5 005c ? reserved 01b4 c060 01b5 0060 rgblctlx alias of gblctl containing only receiver reset bits, allows transmit to be reset independently from receive. 01b4 c064 01b5 0064 rmaskx receiver format unit bit mask register 01b4 c068 01b5 0068 rfmtx receive bit stream format register 01b4 c06c 01b5 006c afsrctlx receive frame sync control register 01b4 c070 01b5 0070 aclkrctlx receive clock control register 01b4 c074 01b5 0074 ahclkrctlx high-frequency receive clock control register 01b4 c078 01b5 0078 rtdmx receive tdm slot 0 ? 31 register 01b4 c07c 01b5 007c rintctlx receiver interrupt control register 01b4 c080 01b5 0080 rstatx status register ? receiver 01b4 c084 01b5 0084 rslotx current receive tdm slot register 01b4 c088 01b5 0088 rclkchkx receiver clock check control register 01b4 c08c ? 01b4 c09c 01b5 008c ? 01b5 009c ? reserved 01b4 c0a0 01b5 00a0 xgblctlx alias of gblctl containing only transmitter reset bits, allows transmit to be reset independently from receive. 01b4 c0a4 01b5 00a4 xmaskx transmit format unit bit mask register 01b4 c0a8 01b5 00a8 xfmtx transmit bit stream format register 01b4 c0ac 01b5 00ac afsxctlx transmit frame sync control register 01b4 c0b0 01b5 00b0 aclkxctlx transmit clock control register 01b4 c0b4 01b5 00b4 ahclkxctlx high-frequency transmit clock control register
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 21 post office box 1443 ? houston, texas 77251 ? 1443 table 12. mcasp0 and mcasp1 registers (continued) hex address range register name acronym mcasp0 register name acronym mcasp1 01b4 c0b8 01b5 00b8 xtdmx transmit tdm slot 0 ? 31 register 01b4 c0bc 01b5 00bc xintctlx transmit interrupt control register 01b4 c0c0 01b5 00c0 xstatx status register ? transmitter 01b4 c0c4 01b5 00c4 xslotx current transmit tdm slot 01b4 c0c8 01b5 00c8 xclkchkx transmit clock check control register 01b4 c0d0 ? 01b4 c0fc 01b5 00cc ? 01b5 00fc ? reserved 01b4 c100 01b5 0100 ditcsra0x left (even tdm slot) channel status register file 01b4 c104 01b5 0104 ditcsra1x left (even tdm slot) channel status register file 01b4 c108 01b5 0108 ditcsra2x left (even tdm slot) channel status register file 01b4 c10c 01b5 010c ditcsra3x left (even tdm slot) channel status register file 01b4 c110 01b5 0110 ditcsra4x left (even tdm slot) channel status register file 01b4 c114 01b5 0114 ditcsra5x left (even tdm slot) channel status register file 01b4 c118 01b5 0118 ditcsrb0x right (odd tdm slot) channel status register file 01b4 c11c 01b5 011c ditcsrb1x right (odd tdm slot) channel status register file 01b4 c120 01b5 0120 ditcsrb2x right (odd tdm slot) channel status register file 01b4 c124 01b5 0124 ditcsrb3x right (odd tdm slot) channel status register file 01b4 c128 01b5 0128 ditcsrb4x right (odd tdm slot) channel status register file 01b4 c12c 01b5 012c ditcsrb5x right (odd tdm slot) channel status register file 01b4 c130 01b5 0130 ditudra0x left (even tdm slot) user data register file 01b4 c134 01b5 0134 ditudra1x left (even tdm slot) user data register file 01b4 c138 01b5 0138 ditudra2x left (even tdm slot) user data register file 01b4 c13c 01b5 013c ditudra3x left (even tdm slot) user data register file 01b4 c140 01b5 0140 ditudra4x left (even tdm slot) user data register file 01b4 c144 01b5 0144 ditudra5x left (even tdm slot) user data register file 01b4 c148 01b5 0148 ditudrb0x right (odd tdm slot) user data register file 01b4 c14c 01b5 014c ditudrb1x right (odd tdm slot) user data register file 01b4 c150 01b5 0150 ditudrb2x right (odd tdm slot) user data register file 01b4 c154 01b5 0154 ditudrb3x right (odd tdm slot) user data register file 01b4 c158 01b5 0158 ditudrb4x right (odd tdm slot) user data register file 01b4 c15c 01b5 015c ditudrb5x right (odd tdm slot) user data register file 01b4 c160 ? 01b4 c17c 01b5 0160 ? 01b5 017c ? reserved 01b4 c180 01b5 0180 srctl0x serializer 0 control register 01b4 c184 01b5 0184 srctl1x serializer 1 control register 01b4 c188 01b5 0188 srctl2x serializer 2 control register 01b4 c18c 01b5 018c srctl3x serializer 3 control register 01b4 c190 01b5 0190 srctl4x serializer 4 control register 01b4 c194 01b5 0194 srctl5x serializer 5 control register 01b4 c198 01b5 0198 srctl6x serializer 6 control register 01b4 c19c 01b5 019c srctl7x serializer 7 control register 01b4 c1a0 ? 01b4 c1fc 01b5 01a0 ? 01b5 01fc ? reserved peripheral register descriptions (continued)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 22 post office box 1443 ? houston, texas 77251 ? 1443 table 12. mcasp0 and mcasp1 registers (continued) hex address range register name acronym mcasp0 register name acronym mcasp1 01b4 c200 01b5 0200 xbuf0x transmit buffer for serializer 0 through configuration bus ? 01b4 c204 01b5 0204 xbuf1x transmit buffer for serializer 1 through configuration bus ? 01b4 c208 01b5 0208 xbuf2x transmit buffer for serializer 2 through configuration bus ? 01b4 c20c 01b5 020c xbuf3x transmit buffer for serializer 3 through configuration bus ? 01b4 c210 01b5 0210 xbuf4x transmit buffer for serializer 4 through configuration bus ? 01b4 c214 01b5 0214 xbuf5x transmit buffer for serializer 5 through configuration bus ? 01b4 c218 01b5 0218 xbuf6x transmit buffer for serializer 6 through configuration bus ? 01b4 c21c 01b5 021c xbuf7x transmit buffer for serializer 7 through configuration bus ? 01b4 c220 ? 01b4 c27c 01b5 c220 ? 01b5 027c ? reserved 01b4 c280 01b5 0280 rbuf0x receive buffer for serializer 0 through configuration bus ? 01b4 c284 01b5 0284 rbuf1x receive buffer for serializer 1 through configuration bus ? 01b4 c288 01b5 0288 rbuf2x receive buffer for serializer 2 through configuration bus ? 01b4 c28c 01b5 028c rbuf3x receive buffer for serializer 3 through configuration bus ? 01b4 c290 01b5 0290 rbuf4x receive buffer for serializer 4 through configuration bus ? 01b4 c294 01b5 0294 rbuf5x receive buffer for serializer 5 through configuration bus ? 01b4 c298 01b5 0298 rbuf6x receive buffer for serializer 6 through configuration bus ? 01b4 c29c 01b5 029c rbuf7x receive buffer for serializer 7 through configuration bus ? 01b4 c2a0 ? 01b4 ffff 01b5 02a0 ? 01b5 3fff ? reserved ? the transmit buffers for serializers 0 ? 7 are accessible to the cpu via the peripheral bus if the xsel bit = 1 (xfmt register). ? the receive buffers for serializers 0 ? 7 are accessible to the cpu via the peripheral bus if the rsel bit = 1 (rfmt register). table 13. i2c0 and i2c1 registers hex address range acronym register description i2c0 i2c1 acronym register description 01b4 0000 01b4 4000 i2coarx i2cx own address register 01b4 0004 01b4 4004 i2cierx i2cx interrupt enable register 01b4 0008 01b4 4008 i2cstrx i2cx interrupt status register 01b4 000c 01b4 400c i2cclklx i2cx clock low-time divider register 01b4 0010 01b4 4010 i2cclkhx i2cx clock high-time divider register 01b4 0014 01b4 4014 i2ccntx i2cx data count register 01b4 0018 01b4 4018 i2cdrrx i2cx data receive register 01b4 001c 01b4 401c i2csarx i2cx slave address register 01b4 0020 01b4 4020 i2cdxrx i2cx data transmit register 01b4 0024 01b4 4024 i2cmdrx i2cx mode register 01b4 0028 01b4 4028 i2cisrcx i2cx interrupt source register 01b4 002c 01b4 402c ? reserved 01b4 0030 01b4 4030 i2cpscx i2cx prescaler register 01b4 0034 01b4 4034 i2cpid10 i2cpid11 i2cx peripheral identification register 1 [c6713 value: 0x0000 0101 ] 01b4 0038 01b4 4038 i2cpid20 i2cpid21 i2cx peripheral identification register 2 [c6713 value: 0x0000 0005 ] 01b4 003c ? 01b4 3fff 01b4 403c ? 01b4 7fff ? reserved peripheral register descriptions (continued)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 23 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions (continued) table 14. hpi registers hex address range acronym register name comments ? hpid hpi data register host read/write access only ? hpia hpi address register host read/write access only 0188 0000 hpic hpi control register both host/cpu read/write access 0188 0004 ? 018b ffff ? reserved table 15. timer 0 and timer 1 registers hex address range acronym register name comments timer 0 timer 1 acronym register name comments 0194 0000 0198 0000 ctlx timer x control register determines the operating mode of the timer, monitors the timer status, and controls the function of the tout pin. 0194 0004 0198 0004 prdx timer x period register contains the number of timer input clock cycles to count. this number controls the tstat signal frequency. 0194 0008 0198 0008 cntx timer x counter register contains the current value of the incrementing counter. 0194 000c ? 0197 ffff 0198 000c ? 019b ffff ? reserved ? table 16. mcbsp0 and mcbsp1 registers hex address range acronym register description mcbsp0 mcbsp1 acronym register description 018c 0000 0190 0000 drrx mcbspx data receive register via configuration bus the cpu and edma controller can only read this register; they cannot write to it. 3000 0000 ? 33ff ffff 3400 0000 ? 37ff ffff drrx mcbspx data receive register via peripheral data bus 018c 0004 0190 0004 dxrx mcbspx data transmit register via configuration bus 3000 0000 ? 33ff ffff 3400 0000 ? 37ff ffff dxrx mcbspx data transmit register via peripheral data bus 018c 0008 0190 0008 spcrx mcbspx serial port control register 018c 000c 0190 000c rcrx mcbspx receive control register 018c 0010 0190 0010 xcrx mcbspx transmit control register 018c 0014 0190 0014 srgrx mcbspx sample rate generator register 018c 0018 0190 0018 mcrx mcbspx multichannel control register 018c 001c 0190 001c rcerx mcbspx receive channel enable register 018c 0020 0190 0020 xcerx mcbspx transmit channel enable register 018c 0024 0190 0024 pcrx mcbspx pin control register 018c 0028 ? 018f ffff 0190 0028 ? 0193 ffff ? reserved
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 24 post office box 1443 ? houston, texas 77251 ? 1443 peripheral register descriptions (continued) table 17. gpio registers hex address range acronym register name 01b0 0000 gpen gpio enable register 01b0 0004 gpdir gpio direction register 01b0 0008 gpval gpio value register 01b0 000c ? reserved 01b0 0010 gpdh gpio delta high register 01b0 0014 gphm gpio high mask register 01b0 0018 gpdl gpio delta low register 01b0 001c gplm gpio low mask register 01b0 0020 gpgc gpio global control register 01b0 0024 gppol gpio interrupt polarity register 01b0 0028 ? 01b0 3fff ? reserved
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 25 post office box 1443 ? houston, texas 77251 ? 1443 signal groups description trst gp[7](ext_int7) ? ieee standard 1149.1 (jtag) emulation reset and interrupts control/status tdi tdo tms tck emu0 emu1 nmi gp[6](ext_int6) ? gp[5](ext_int5) /amutein0 ? gp[4](ext_int4) /amutein1 ? reset clock/pll oscillator clkin clkmode0 pllhv clkout2 /gp[2] emu2 ? emu3 ? emu4 ? emu5 ? hhwil /afsr1 hcntl0 /axr1[3] hcntl1 /axr1[1] data register select half-word select control hpi (host-port interface) has /aclkx1 hr/w /axr1[0] hcs /axr1[2] hds1 /axr1[6] hds2 /axr1[5] hrdy /aclkr1 hint /gp[1] hd15 /gp[15] hd14 /gp[14] hd13 /gp[13] hd12 /gp[12] hd11 /gp[11] hd10 /gp[10] hd9 /gp[9] hd8 /gp[8] hd7 /gp[3] hd6 /ahclkr1 hd5 /ahclkx1 hd4 /gp[0] hd3 /amute1 hd2 /afsx1 hd1 /axr1[7] hd0 /axr1[4] clkout3 ? these external pins are applicable to the gdp package only. ? the gp[15:0] pins, through interrupt sharing, are external interrupt capable via gpint0. for more details, see the external interrupt sources section of this data sheet. for more details on interrupt sharing, see the tms320c6000 peripherals reference guide (literature number spru190). all of these pins are external interrupt sources. for more details, see the external interrupt sources section of this data she et. hd4/ gp[0] ? note a: on multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. figure 4. cpu (dsp core) and peripheral signals
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 26 post office box 1443 ? houston, texas 77251 ? 1443 signal groups description (continued) general-purpose input/output (gpio) port gp[7](ext_int7) gp[6](ext_int6) gp[5](ext_int5) /amutein0 gp[4](ext_int4) /amutein1 hd7/ gp[3] clkout2/ gp[2] hint / gp[1] hd4/ gp[0] gpio ? hd15/ gp[15] hd14/ gp[14] hd13/ gp[13] hd12/ gp[12] hd11/ gp[11] hd10/ gp[10] hd9/ gp[9] hd8/ gp[8] tout1 /axr0[4] tout0 /axr0[2] timer 1 timer 0 timers tinp1 /ahclkx0 tinp0 /axr0[3] clks1/ scl1 scl0 i2c1 i2c0 i2cs dr1/ sda1 sda0 note a: on multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. ? the gp[15:0] pins, through interrupt sharing, are external interrupt capable via gpint0. gp[15:0] are also external edma event source capable. for more details, see the external interrupt sources and external edma event sources sections of this data sheet. figure 5. peripheral signals
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 27 post office box 1443 ? houston, texas 77251 ? 1443 signal groups description (continued) ce3 eclkout ed[31:16] ? ce2 ce1 ce0 ea[21:2] be3 ? be2 ? be1 be0 clkx1 /amute0 fsx1 dx1 /axr0[5] clkr1 /axr0[6] fsr1 /axr0[7] dr1 /sda1 clks1 /scl1 aoe /sdras /ssoe awe /sdwe /sswe ardy clkx0 /aclkx0 fsx0 /afsx0 dx0 /axr0[1] clkr0 /aclkr0 fsr0/ afsr0 dr0 /axr0[0] clks0 /ahclkr0 data memory map space select address byte enables 16 20 memory control emif (external memory interface) receive receive mcbsp1 mcbsp0 transmit transmit clock clock mcbsps (multichannel buffered serial ports) eclkin hold holda busreq bus arbitration are /sdcas /ssads ? these external pins are applicable to the gdp package only. ed[15:0] 16 note a: on multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. figure 5. peripheral signals (continued)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 28 post office box 1443 ? houston, texas 77251 ? 1443 signal groups description (continued) mcasp0 (multichannel audio serial port 0) clkx0/ aclkx0 clks0/ ahclkr0 transmit clock generator gp[5](ext_int5)/ amutein0 auto mute logic clkx1/ amute0 fsx0/ afsx0 transmit frame sync fsr0/ afsr0 receive frame sync clkr0/ aclkr0 tinp1/ ahclkx0 receive clock generator tout1/ axr0[4] tout0/ axr0[2] dx0/ axr0[1] dr0/ axr0[0] dx1/ axr0[5] tinp0/ axr0[3] clkr1/ axr0[6] fsr1/ axr0[7] 8-serial ports flexible partitioning tx, rx, off transmit clock check circuit receive clock check circuit error detect (see note a) (transmit/receive data pins) (receive bit clock) (transmit bit clock) (receive master clock) (transmit master clock) (receive frame sync or left/right clock) (transmit frame sync or left/right clock) notes: a. the mcasps? error detect function detects underruns, overruns, early/late frame syncs, dma errors, and external mute in put. b. on multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. c. bolded and italicized text within parentheses denotes the function of the pins in an audio system. figure 5. peripheral signals (continued)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 29 post office box 1443 ? houston, texas 77251 ? 1443 signal groups description (continued) hd0/ axr1[4] hcs / axr1[2] hcntl1/ axr1[1] hr/w / axr1[0] mcasp1 (multichannel audio serial port 1) hds2 / axr1[5] has / aclkx1 hd5/ ahclkx1 transmit clock generator hcntl0/ axr1[3] gp[4](ext_int4)/ amutein1 auto mute logic hd3/ amute1 hd2/ afsx1 transmit frame sync hhwil/ afsr1 receive frame sync hds1 / axr1[6] hd1/ axr1[7] hrdy / aclkr1 hd6/ ahclkr1 receive clock generator 8-serial ports flexible partitioning tx, rx, off transmit clock check circuit receive clock check circuit error detect (see note a) (transmit/receive data pins) (receive bit clock) (transmit bit clock) (receive master clock) (transmit master clock) (receive frame sync or left/right clock) (transmit frame sync or left/right clock) notes: a. the mcasps? error detect function detects underruns, overruns, early/late frame syncs, dma errors, and external mute in put. b. on multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. c. bolded and italicized text within parentheses denotes the function of the pins in an audio system. figure 5. peripheral signals (continued)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 30 post office box 1443 ? houston, texas 77251 ? 1443 device configurations on the c6713 device, bootmode and certain device configurations/peripheral selections are determined at device reset, while other device configurations/peripheral selections are software-configurable via the device configurations register (devcfg) [address location 0x019c0200] after device reset. device configurations at device reset table 18 describes the c6713 device configuration pins, which are set up via internal or external pullup/pulldown resistors through the hpi data pins (hd[4:3] and hd8) and clkmode0 pin. these configuration pins must be in the desired state until reset is released. for more details on these device configuration pins, see the terminal functions table and the debugging considerations section of this data sheet. table 18. device configurations pins at device reset (hd[4:3], hd8, and clkmode0) ? configuration pin pyp gdp functional description hd8 160 b17 device endian mode (lend) 0 ? system operates in big endian mode 1 ? system operates in little endian mode (default) hd[4:3] (bootmode) 156, 154 c19, c20 bootmode configuration pins (bootmode) 00 ? ce1 width 32-bit, hpi boot/emulation boot 01 ? ce1 width 8-bit, asynchronous external rom boot with default timings (default mode) 10 ? ce1 width 16-bit, asynchronous external rom boot with default timings 11 ? ce1 width 32-bit, asynchronous external rom boot with default timings for more detailed information on these bootmode configurations, see the bootmode section of this data sheet. clkmode0 205 c4 clock generator input clock source select 0 ? reserved. do not use. 1 ? clkin square wave [default] this pin must be pulled to the correct level even after reset. ? all other hd pins (hd [15, 13:9, 7:5, 2:0]) have pullups/pulldowns (ipus or ipds). for proper device operation of the hd [15, 1 3:9, 7, 1, 0], do not oppose these pins with external pullups/pulldowns at reset; however, the hd[6, 5, 2] pins can be opposed and driven during reset.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 31 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) peripheral pin selection at device reset some c6713 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., hpi, general-purpose input/output pins gp[15:8, 3, 1, 0] and mcasp1). hpi, mcasp1, and gpio peripherals the hpi_en (hd14 pin) is latched at reset. this pin selects whether the hpi peripheral pins or mcasp1 peripheral pins and gp[15:8, 3, 1, 0] pins are functionally enabled (see table 19). table 19. hpi_en (hd14 pin) peripheral selection (hpi or mcasp1, and select gpio pins) ? peripheral pin selection peripheral pins selected description hpi_en (hd14 pin) [173, c14] hpi mcasp1 and gp[15:8,3,1,0] description 0 hpi_en = 0 hpi pins are disabled; mcasp1 peripheral pins and gp[15:8, 3, 1,0] pins are enabled. all multiplexed hpi/mcasp1 and hpi/gpio pins function as mcasp1 and gpio pins, respectively. to use the gpio pins, the appropriate bits in the gpen and gpdir registers need to be configured. 1 hpi_en = 1 hpi pins are enabled; mcasp1 peripheral pins and gp[15:8, 3, 1,0] pins are disabled [default]. all multiplexed hpi/mcasp1 and hpi/gpio pins function as hpi pins. ? the hpi_en (hd[14]) pin cannot be controlled via software.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 32 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) peripheral selection/device configurations via the devcfg control register the device configuration register (devcfg) allows the user to control the pin availability of the mcbsp0, mcbsp1, mcasp0, i2c1, and t imer peripherals. the devcfg register also offers the user control of the emif input clock source and the timer output pins. for more detailed information on the devcfg register control bits, see table 20 and table 21. table 20. device configuration register (devcfg) [address location: 0x019c0200 ? 0x019c02ff] 31 16 reserved ? rw-0 15 54 3 210 reserved ? eksrc tout1sel tout0sel mcbsp0dis mcbsp1dis rw-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 legend: r/w = read/write; -n = value after reset ? do not write non-zero values to these bit locations. table 21. device configuration (devcfg) register selection bit descriptions bit # name description 31:5 reserved reserved. do not write non-zero values to these bit locations. 4 eksrc emif input clock source bit. determines which clock signal is used as the emif input clock. 0 = sysclk3 (from the clock generator) is the emif input clock source (default) 1 = eclkin external pin is the emif input clock source 3 tout1sel timer 1 output (tout1) pin function select bit. selects the pin function of the tout1/axr0[4] external pin independent of the rest of the peripheral selection bits in the devcfg register. 0 = the pin functions as a timer 1 output (tout1) pin (default) 1 = the pin functions as the mcasp0 transmit/receive data pin 4 (axr0[4]). the timer 1 module is still active. 2 tout0sel timer 0 output (tout0) pin function select bit. selects the pin function of the tout0/axr0[2] external pin independent of the rest of the peripheral selection bits in the devcfg register. 0 = the pin functions as a timer 0 output (tout0) pin (default) 1 = the pin functions as the mcasp0 transmit/receive data pin 2 (axr0[2]). the timer 0 module is still active. 1 mcbsp0dis multichannel buffered serial port 0 (mcbsp0) disable bit. selects whether mcbsp0 or the mcasp0 multiplexed peripheral pins are enabled or disabled. 0 = mcbsp0 peripheral pins are enabled, mcasp0 peripheral pins (ahclkr0, aclkr0, aclkx0, axr0[0], axr0[1], afsr0, and afsx0) are disabled (default). [if the mcasp0 data pins are available, the mcasp0 peripheral is functional for dit mode only.] 1 = mcbsp0 peripheral pins are disabled, mcasp0 peripheral pins (ahclkr0, aclkr0, aclkx0, axr0[0], axr0[1], afsr0, and afsx0) are enabled. 0 mcbsp1dis multichannel buffered serial port 1 (mcbsp1) disable bit. selects whether mcbsp1 or i2c1 and mcasp0 multiplexed peripheral pins are enabled or disabled. 0 = mcbsp1 peripheral pins are enabled, i2c1 peripheral pins (scl1 and sda1) and mcasp0 peripheral pins (axr0[7:5] and amute0) are disabled (default) 1 = mcbsp1 peripheral pins are disabled, i2c1 peripheral pins (scl1 and sda1) and mcasp0 peripheral pins (axr0[7:5] and amute0) are enabled.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 33 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) multiplexed pins multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. most of these pins are configured by software via the device configuration register (devcfg), and the others (specifically, the hpi pins) are configured by external pullup/pulldown resistors only at reset. the muxed pins that are configured by software can be programmed to switch functionalities at any time. the muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. table 22 summarizes the peripheral pins affected by the hpi_en (hd14 pin) and devcfg register. table 23 identifies the multiplexed pins on the c6713 device; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure the specific multiplexed functions.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 34 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) table 22. peripheral pin selection matrix ? selection bits peripheral pins availability b i t n a m e b i t v a l u e m c a s p 0 ? m c a s p 1 i 2 c 0 i 2 c 1 m c b s p 0 m c b s p 1 t i m e r 0 t i m e r 1 h p i g p i o p i n s e m i f hpi_en (boot config pin) 0 ahclkx1 ahclkr1 aclkx1 aclkr1 afsx1 afsr1 amute1 axr1[0] to axr1[7] none gp[0:1], gp[3], gp[8:15] plus: gp[2] ctrl?d by gp2en bit 1 none all no gp[0:1], gp[3], gp[8:15] 0 none all mcbsp0dis (devcfg bit) 1 aclkk0 aclkr0 afsx0 afsr0 ahclkr0 axr0[0] axr0[1] none mcbsp1dis (devcfg bit) 0 no amute0 axr0[5] axr0[6] axr0[7] none all (devcfg bit) 1 amute0 axr0[5] axr0[6] axr0[7] all none tout0sel 0 no axr0[2] tout0 tout0sel (devcfg bit) 1 axr0[2] no tout0 tout1sel 0 no axr0[4] tout1 tout1sel (devcfg bit) 1 axr0[4] no tout1 ? gray blocks indicate that the peripheral is not affected by the selection bit. ? the mcasp0 pins axr0[3] and ahclkx0 are shared with the timer input pins tinp0 and tinp1, respectively. see table 23 for more d etailed information.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 35 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) table 23. c6713 device multiplexed/shared pins multiplexed pins default default setting description name pyp gdp default function default setting description clkout2/gp[2] 82 y12 clkout2 gp2en = 0 (gpen register bit) gp[2] function disabled, clkout2 enabled when the clkout2 pin is enabled , the clk2en bit in the emif global control register (gblctl) controls the clkout2 pin. clk2en = 0: clkout2 held high clk2en = 1: clkout2 enabled to clock [default] to use these software-configurable gpio pins, the gpxen bits in the gp enable register and the gpxdir bits gp[5](ext_int5)/amutein0 gp[4](ext_int4)/amutein1 6 1 c1 c2 gp[5](ext_int5) gp[4](ext_int4) no function gpxdir = 0 (input) gp5en = 0 (disabled) gp4en = 0 (disabled) [(gpen register bits) gp[x] function disabled] enable register and the gpxdir bits in the gp direction register must be properly configured. gpxen = 1: gp[x] pin enabled gpxdir = 0: gp[x] pin is an input gpxdir = 1: gp[x] pin is an output to use amutein0/1 pin function, the gp[5]/gp[4] pins must be configured as an input, the inen bit set to 1, and the polarity through the inpol bit selected in the associated mcasp amute register. clks0/ahclkr0 28 k3 by default mcbsp0 peripheral pins are dr0/axr0[0] 27 j1 b y d e f au l t, m c bsp0 per i p h era l p i ns are enabled u p on reset ( mcasp0 p ins are dx0/axr0[1] 20 h2 mcbsp0dis = 0 (devcfg i t bit) enabled upon reset (mcasp0 pins are disabled). fsr0/afsr0 24 j3 mcbsp0 pin function (devcfg register bit) mcasp0 pins disabled ) to enable the mcasp0 peripheral pins fsx0/afsx0 21 h1 mcbsp0 pin function m c asp0 p i ns di sa bl e d , mcbsp0 pins enabled t o ena bl e th e m c asp0 per i p h era l p i ns, the mcbsp0dis bit in the devcfg clkr0/aclkr0 19 h3 mcbsp0 pins enabled the mcbsp0dis bit in the devcfg register must be set to 1 (disabling the m bsp0 i h l i ) clkx0/aclkx0 16 g3 mcbsp0 peripheral pins). clks1/scl1 8 e1 by default, mcbsp1 peripheral pins are dr1/sda1 37 m2 mcbsp1dis = 0 by default, mcbsp1 peripheral pins are enabled upon reset (i2c1 and mcasp0 pins are disabled) dx1/axr0[5] 32 l2 mcbsp1 pin function mcbsp1dis = 0 (devcfg register bit) i2c1 and mcasp0 pins pins are disabled). fsr1/axr0[7] 38 m3 mcbsp1 pin function i2c1 and mcasp0 pins disabled , mcbsp1 p ins to enable the i2c1 and mcasp0 peripheral pins the mcbsp1dis bit in clkr1/axr0[6] 36 m1 disabled , mcbsp1 pins enabled peripheral pins, the mcbsp1dis bit in the devcfg re g ister must be set to 1 clkx1/amute0 33 l3 the devcfg register must be set to 1 (disabling the mcbsp1 peripheral pins).
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 36 post office box 1443 ? houston, texas 77251 ? 1443 table 23. c6713 device multiplexed/shared pins (continued) description default setting default function multiplexed pins description default setting default function gdp pyp name hint /gp[1] 135 j20 hd15/gp[15] 174 b14 hd14/gp[14] 173 c14 hd13/gp[13] 172 a15 b d f lt th hpi i h l i hd12/gp[12] 168 c15 by default, the hpi peripheral pins are enabled at reset mcasp1 peripheral hd11/gp[11] 167 a16 ena bl e d a t rese t . m c asp1 per i p h era l pins and eleven gpio pins are hd10/gp[10] 166 b16 pins and eleven gpio pins are disabled. hd9/gp[9] 165 c16 to enable the mcasp1 peripheral pins hd8/gp[8] 160 b17 t o ena bl e th e m c asp1 per i p h era l p i ns and the eleven gpio pins, an external hd7/gp[3] 164 a18 and the eleven gpio pins , an external pulldown resistor must be provided on the hd14 pin setting hpi en 0 at hd4/gp[0] 156 c19 the hd14 pin setting hpi_en = 0 at reset. hd1/axr1[7] 152 d20 hpi_en (hd14 pin) = 1 reset . hd0/axr1[4] 147 e20 hpi pin function hpi _ en (hd14 pin) 1 (hpi enabled) to use these software configurable hcntl1/axr1[1] 144 g19 hpi pin function mcasp1 pins and eleven to use these software-configurable gpio pins, the gpxen bits in the gp hcntl0/axr1[3] 146 g18 mcasp1 pins and eleven gpio pins are disabled. gpio pins , the gpxen bits in the gp enable register and the gpxdir bits in hr/w /axr1[0] 143 g20 gpio pins are disabled. enable register and the gpxdir bits in the gp direction register must be properly configured hds1 /axr1[6] 151 e19 properly configured. gpxen = 1: gp [ x ] p in enabled hds2 /axr1[5] 150 f18 gpxen = 1: gp[x] pin enabled gpxdir = 0: gp[x] pin is an input hcs /axr1[2] 145 f20 []p p gpxdir = 1: gp[x] pin is an output hd6/ahclkr1 161 c17 output hd5/ahclkx1 159 b18 mcasp1 pin direction is controlled by h pdir[ ] bi i h m asp pdir hd3/amute1 154 c20 py the pdir[x] bits in the mcasp1pdir register hd2/afsx1 155 d18 reg i ster. hhwil/afsr1 139 h20 hrdy /aclkr1 140 h19 has /aclkx1 153 e18 tinp0/axr0[3] 17 g2 timer 0 input function mcasp0pdir = 0 (input) [specifically axr0[3] bit] by default, the timer 0 input pin is enabled (and a shared input until the mcasp0 peripheral forces an output). mcasp0pdir = 0 input, = 1 output tout0/axr0[2] 18 g1 timer 0 output function tout0sel = 0 (devcfg register bit) [tout0 pin enabled and mcasp0 axr0[2] pin disabled] by default, the timer 0 output pin is enabled. to enable the mcasp0 axr0[2] pin, the tout0sel bit in the devcfg register must be set to 1 (disabling the timer 0 peripheral output pin function). the axr2 bit in the mcasp0pdir register controls the direction (input/output) of the axr0[2] pin mcasp0pdir = 0 input, = 1 output device configurations (continued)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 37 post office box 1443 ? houston, texas 77251 ? 1443 table 23. c6713 device multiplexed/shared pins (continued) description default setting default function multiplexed pins description default setting default function gdp pyp name tinp1/ahclkx0 12 f2 timer 1 input function mcasp0pdir = 0 (input) [specifically ahclkx bit] by default, the timer 1 input and mcasp0 clock function are enabled as inputs. for the mcasp0 clock to function as an output: mcasp0pdir = 1 (specifically the ahclkx bit] tout1/axr0[4] 13 f1 timer 1 output function tout1sel = 0 (devcfg register bit) [tout1 pin enabled and mcasp0 axr0[4] pin disabled] by default, the timer 1 output pin is enabled. to enable the mcasp0 axr0[4] pin, the tout1sel bit in the devcfg register must be set to 1 (disabling the timer 1 peripheral output pin function). the axr4 bit in the mcasp0pdir register controls the direction (input/output) of the axr0[4] pin mcasp0pdir = 0 input, = 1 output configuration examples figure 6 through figure 11 illustrate examples of peripheral selections that are configurable on this device. device configurations (continued)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 38 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) configuration examples (continued) emif ed [31:16], ed[15:0] ce[3:0] , be[3:0] , holda , hold , busreq, eclkin, eclkout, are /sdcas /ssads , awe /sdwe /sswe , aoe /sdras /ssoe , ardy hpi i2c1 mcbsp1 mcbsp0 timer1 timer0 clock, system, emu, and reset i2c0 gpio and ext_int mcasp1 clkin, clkout3, clkmode0, pllhv, tms, tdo, tdi, tck, trst , emu[5:3,1,0], reset , nmi gp[0], gp[4](ext_int4)/amutein1, gp[5](ext_int5)/amutein0, gp[6](ext_int6), gp[7](ext_int7) gp[15:8, 3:1] mcasp0 scl0, sda0 32 20 8 devcfg register value: 0x0000 000f mcbsp0dis = 1 mcbsp1dis = 1 tout0sel = 1 tout1sel = 1 eksrc = 0 hpi_en(hd14) = 0 gp2en bit = 1 (enabling gpen.[2]) ea[21:2] shading denotes a peripheral module not available for this configuration. scl1, sda1 8 axr0[7:0] {tinp0/axr0[3]} axr1[7:0] afsx1, afsr1, aclkx1, aclkr1, ahclkr1, ahclkx1, amute1 amute0, tinp1/ahclkx0, ahclkr0, aclkr0, aclkx0, afsr0, afsx0 figure 6. configuration example a (2 i2c + 2 mcasp + gpio)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 39 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) configuration examples (continued) emif ed [31:16], ed[15:0] ce[3:0] , be[3:0] , holda , hold , busreq, eclkin, eclkout, are /sdcas /ssads , awe /sdwe /sswe , aoe /sdras /ssoe , ardy hpi i2c1 mcbsp1 mcbsp0 timer1 timer0 clock, system, emu, and reset i2c0 gpio and ext_int mcasp1 clkin, clkout3, clkmode0, pllhv, tms, tdo, tdi, tck, trst , emu[5:3,1,0], reset , nmi gp[0], gp[4](ext_int4)/amutein1, gp[5](ext_int5)/amutein0, gp[6](ext_int6), gp[7](ext_int7) gp[15:8, 3:1] mcasp0 scl0, sda0 afsx1, afsr1, aclkx1, aclkr1, ahclkr1, ahclkx1, amute1 32 20 8 devcfg register value: 0x0000 000e mcbsp0dis = 1 mcbsp1dis = 0 tout0sel = 1 tout1sel = 1 eksrc = 0 hpi_en(hd14) = 0 gp2en bit = 1 (enabling gpen.[2]) ea[21:2] shading denotes a peripheral module not available for this configuration. dr1, clks1, clkr1, clkx1, fsr1, dx1, fsx1 5 axr1[7:0] axr0[4:0] {tinp0/axr0[3]} tinp1/ahclkx0, ahclkr0, aclkr0, aclkx0, afsr0, afsx0 figure 7. configuration example b (1 i2c + 1 mcbsp + 2 mcasp + gpio)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 40 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) configuration examples (continued) emif ed [31:16], ed[15:0] ce[3:0] , be[3:0] , holda , hold , busreq, eclkin, eclkout, are /sdcas /ssads , awe /sdwe /sswe , aoe /sdras /ssoe , ardy hpi i2c1 mcbsp1 scl1, sda1 mcbsp0 timer1 timer0 clock, system, emu, and reset i2c0 gpio and ext_int mcasp1 clkin, clkout3, clkmode0, pllhv, tms, tdo, tdi, tck, trst , emu[5:3,1,0], reset , nmi gp[0], gp[4](ext_int4)/amutein1, gp[5](ext_int5)/amutein0, gp[6](ext_int6), gp[7](ext_int7) gp[15:8, 3:1] mcasp0 (dit mode) scl0, sda0 afsx1, afsr1, aclkx1, aclkr1, ahclkr1, ahclkx1, amute1 32 20 8 devcfg register value: 0x0000 000d mcbsp0dis = 0 mcbsp1dis = 1 tout0sel = 1 tout1sel = 1 eksrc = 0 hpi_en(hd14) = 0 gp2en bit = 1 (enabling gpen.[2]) ea[21:2] shading denotes a peripheral module not available for this configuration. dr0, clks0, clkr0, clkx0, fsr0, dx0, fsx0 6 axr1[7:0] axr0[7:2] {tinp0/axr0[3]} amute0, tinp1/ahclkx0 figure 8. configuration example c [2 i2c + 1 mcbsp + 1 mcasp + 1 mcasp (dit) + gpio]
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 41 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) configuration examples (continued) emif ed [31:16], ed[15:0] ce[3:0] , be[3:0] , holda , hold , busreq, eclkin, eclkout, are /sdcas /ssads , awe /sdwe /sswe , aoe /sdras /ssoe , ardy hpi i2c1 mcbsp1 dr1, clks1, clkr1, clkx1, fsr1, dx1, fsx1 mcbsp0 timer1 timer0 clock, system, emu, and reset i2c0 gpio and ext_int mcasp1 clkin, clkout3, clkmode0, pllhv, tms, tdo, tdi, tck, trst , emu[5:3,1,0], reset , nmi gp[0], gp[4](ext_int4)/amutein1, gp[5](ext_int5)/amutein0, gp[6](ext_int6), gp[7](ext_int7) gp[15:8, 3:1] mcasp0 (dit mode) scl0, sda0 afsx1, afsr1, aclkx1, aclkr1, ahclkr1, ahclkx1, amute1 32 20 8 devcfg register value: 0x0000 000c mcbsp0dis = 0 mcbsp1dis = 0 tout0sel = 1 tout1sel = 1 eksrc = 0 hpi_en(hd14) = 0 gp2en bit = 1 (enabling gpen.[2]) ea[21:2] shading denotes a peripheral module not available for this configuration. dr0, clks0, clkr0, clkx0, fsr0, dx0, fsx0 3 axr1[7:0] axr0[4:2] {tinp0/axr0[3]} tinp1/ahclkx0 tout0/axr0[2] tout1/axr0[4] figure 9. configuration example d [1 i2c + 2 mcbsp + 1 mcasp + 1 mcasp (dit) + gpio + timers]
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 42 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) configuration examples (continued) emif ed [31:16], ed[15:0] ce[3:0] , be[3:0] , holda , hold , busreq, eclkin, eclkout, are /sdcas /ssads , awe /sdwe /sswe , aoe /sdras /ssoe , ardy hpi i2c1 mcbsp1 scl1, sda1 mcbsp0 timer1 timer0 clock, system, emu, and reset gpio and ext_int mcasp1 clkin, clkout3, clkmode0, pllhv, tms, tdo, tdi, tck, trst , emu[5:3,1,0], reset , nmi gp[4](ext_int4)/amutein1, gp[5](ext_int5)/amutein0, gp[6](ext_int6), gp[7](ext_int7) mcasp0 axr0[7:0], {tinp0/axr0[3]} 32 20 8 devcfg register value: 0x0000 000f mcbsp0dis = 1 mcbsp1dis = 1 tout0sel = 1 tout1sel = 1 eksrc = 0 hpi_en(hd14) = 1 gp2en bit = 0 (enabling gpen.[2]) ea[21:2] shading denotes a peripheral module not available for this configuration. clkout2 hd[15:0] 16 hint , hhwil, hrdy , hr/w , hcntrl1, hcntrl0, hcs , hds2 , hds1 , has i2c0 amute0, tinp1/ahclkx0, ahclkr0, aclkr0, aclkx0, afsr0, afsx0 scl0, sda0 figure 10. configuration example e (1 i2c + hpi + 1 mcasp)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 43 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) configuration examples (continued) emif ed [31:16], ed[15:0] ce[3:0] , be[3:0] , holda , hold , busreq, eclkin, eclkout, are /sdcas /ssads , awe /sdwe /sswe , aoe /sdras /ssoe , ardy hpi i2c1 mcbsp1 mcbsp0 timer1 timer0 clock, system, emu, and reset gpio and ext_int mcasp1 clkin, clkout3, clkmode0, pllhv, tms, tdo, tdi, tck, trst , emu[5:3,1,0], reset , nmi gp[4](ext_int4)/amutein1, gp[5](ext_int5)/amutein0, gp[6](ext_int6), gp[7](ext_int7) mcasp0 32 20 5 devcfg register value: 0x0000 000e mcbsp0dis = 1 mcbsp1dis = 1 tout0sel = 1 tout1sel = 1 eksrc = 0 hpi_en(hd14) = 1 gp2en bit = 0 (enabling gpen.[2]) ea[21:2] shading denotes a peripheral module not available for this configuration. dr1, clks1, clkr1, clkx1, fsr1, dx1, fsx1 clkout2 hd[15:0] 16 hint , hhwil, hrdy , hr/w , hcntrl1, hcntrl0, hcs , hds2 , hds1 , has axr0[4:0] {tinp0/axr0[3]} i2c0 tinp1/ahclkx0, ahclkr0, aclkr0, aclkx0, afsr0, afsx0 scl0, sda0 figure 11. configuration example f (1 mcbsp + hpi + 1 mcasp)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 44 post office box 1443 ? houston, texas 77251 ? 1443 device configurations (continued) debugging considerations it is recommended that external connections be provided to peripheral selection/device configuration pins, including hd[14, 8, 4, 3], and clkmode0. although internal pullup resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. internal pullup/pulldown resistors also exist on the non-configuration pins on the hpi data bus (hd[15, 13:9, 7:5, 2:0]). for proper device operation of the hd[15, 13:9, 7, 1, 0], do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. if an external controller provides signals to these hd[15, 13:9, 7, 1, 0] non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. however, the hd[6, 5, 2] non-configuration pins can be opposed and driven during reset. for the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 45 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions the terminal functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (i, o/z, or i/o/z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. for more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the device configurations section of this data sheet.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 46 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions signal pin no. type ? ipd/ description name pyp gdp type ? ipd/ ipu? description clock/pll configuration clkin 204 a3 i ipd clock input clkout2/gp[2] 82 y12 o/z ipd clock output at half of device speed ( o/z ) [default] (sysclk2 internal signal from the clock generator) or this pin can be programmed as gp[2] pin (i/o/z) clkout3 184 d10 o ipd clock output programmable by oscdiv1 register in the pll controller. clkmode0 205 c4 i ipu clock generator input clock source select 0 ? reserved, do not use. 1 ? clkin square wave [default] for proper device operation, this pin must be either left unconnected or externally pulled up with a 1-k ? resistor. pllhv 202 c5 a analog power (3.3 v) for pll (pll filter) jtag emulation tms 192 b7 i ipu jtag test-port mode select tdo 187 a8 o/z ipu jtag test-port data out tdi 191 a7 i ipu jtag test-port data in tck 193 a6 i ipu jtag test-port clock trst 197 b6 i ipd jtag test-port reset. for ieee 1149.1 jtag compatibility, see the ieee 1149.1 jtag compatibility statement section of this data sheet. emu5 ? b12 i/o/z ipu emulation pin 5. reserved for future use, leave unconnected. emu4 ? c11 i/o/z ipu emulation pin 4. reserved for future use, leave unconnected. emu3 ? b10 i/o/z ipu emulation pin 3. reserved for future use, leave unconnected. emu2 ? d3 i/o/z ipu emulation pin 2. reserved for future use, leave unconnected. emu1 185 b9 i/o/z ipu emulation [1:0] pins ? select the device functional mode of operation emu[1:0] operation 00 boundary scan/functional mode (see note) 01 reserved 10 reserved 11 emulation/functional mode [default] (see the ieee 1 149.1 jtag compatibility statement section of this data sheet) emu1 emu0 185 186 b9 d9 i/o/z ipu the dsp can be placed in functional mode when the emu[1:0] pins are configured for either boundary scan or emulation. note: when the emu[1:0] pins are configured for boundary scan mode, the internal pulldown (ipd) on the trst signal must not be opposed in order to operate in functional mode. for the boundary scan mode drive emu[1:0] and reset pins low. resets and interrupts reset 176 a13 i ipu device reset. when using boundary scan mode, drive the emu[1:0] and reset pins low. nmi 175 c13 i ipd nonmaskable interrupt ? edge-driven (rising edge) ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. [these ipd/ipu signal pins feature a 13-k ? resistor (approximate) for the ipd or 18-k ? resistor (approximate) for the ipu. an external pullup or pulldown resistor no greater than 4.4 k ? and 2.0 k ? , respectively, should be used to pull a signal to the opposite supply rail.] a = analog signal
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 47 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? ipd/ description name pyp gdp type ? ipd/ ipu? description resets and interrupts (continued) gp[7](ext_int7) 7 e3 general-purpose input/output pins ( i/o/z ) which also function as external interrupts gp[6](ext_int6) 2 d2 interrupts ? edge-driven polarity independently selected via the external interrupt polarity register gp[5](ext_int5)/ amutein0 6 c1 i/o/z ipu ? polarity independently selected via the external interrupt polarity register bits (extpol.[3:0]), in addition to the gpio registers. gp[4] d gp[5] i l f ti amutein1 m asp1 t i t d gp[4](ext_int4)/ amutein1 1 c2 gp[4] and gp[5] pins also function as amutein1 mcasp1 mute input and amutein0 mcasp0 mute input, respectively , if enabled by the inen bit in the associated mcasp amute register. host-port interface (hpi) hint /gp[1] 135 j20 o/z ipu host interrupt (from dsp to host) ( o ) [default] or this pin can be programmed as a gp[1] pin (i/o/z). hcntl1/axr1[1] 144 g19 i ipu host control ? selects between control, address, or data registers ( i ) [default] or mcasp1 data pin 1 (i/o/z). hcntl0/axr1[3] 146 g18 i ipu host control ? selects between control, address, or data registers ( i ) [default] or mcasp1 data pin 3 (i/o/z). hhwil/afsr1 139 h20 i ipu host half-word select ? first or second half-word (not necessarily high or low order) ( i ) [default] or mcasp1 receive frame sync or left/right clock (lrclk) (i/o/z). hr/w /axr1[0] 143 g20 i ipu host read or write select ( i ) [default] or mcasp1 data pin 0 (i/o/z). hd15/gp[15] 174 b14 ipu host-port data pins ( i/o/z ) [default] or general-purpose input/output pins (i/o/z) ? used f o r t r a n s f e r o f data, add r ess, a n d co n t r o l hd14/gp[14] 173 c14 ipu ? used for transfer of data , address , and control ? also controls initialization of dsp modes at reset via pullup/pulldown resistors ? device endian mode (hd8) hd13/gp[13] 172 a15 ipu ? d ev i ce e n di an mo d e (hd8) 0 ? big endian 1 ? little endian hd12/gp[12] 168 c15 ipu ? boot mode (hd[4:3]) 00 ? ce1 width 32-bit, hpi boot/emulation boot 01 ce1 width 8 bit asynchronous external rom boot with default hd11/gp[11] 167 a16 i/o/z ipu 01 ? ce1 width 8-bit, asynchronous external rom boot with default timings (default mode) 10 ? ce1 width 16-bit, asynchronous external rom boot with default ti i hd10/gp[10] 166 b16 ipu timings 11 ? ce1 width 32-bit, asynchronous external rom boot with default timings hd9/gp[9] 165 c16 ipu g ? hpi_en (hd14) 0 ? hpi disabled, mcasp1 enabled hd8/gp[8] 160 b17 ipu 0 d sab ed, c s e ab ed 1 ? hpi enabled, mcasp1 disabled (default) other hd pins (hd [15, 13:9, 7:5, 2:0] have pullups/pulldowns (ipus/ipds). for proper device operation of the hd[15, 13:9, 7, 1, 0], do not oppose these pins hd7/gp[3] 164 a18 ipu proper device operation of the hd[15 , 13:9 , 7 , 1 , 0] , do not oppose these pins with external ipus/ipds at reset; however, the hd[6, 5, 2] pins can be opposed and driven at reset. for more details, see the device configurations section of this data sheet. hd6/ahclkr1 161 c17 i/o/z ipu host-port data pin 6 ( i/o/z ) [ default] or mcasp1 receive high-frequency master clock (i/o/z). hd5/ahclkx1 159 b18 i/o/z ipu host-port data pin 5 ( i/o/z ) [ default] or mcasp1 transmit high-frequency master clock (i/o/z). ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. [these ipd/ipu signal pins feature a 13-k ? resistor (approximate) for the ipd or 18-k ? resistor (approximate) for the ipu. an external pullup or pulldown resistor no greater than 4.4 k ? and 2.0 k ? , respectively, should be used to pull a signal to the opposite supply rail.]
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 48 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? ipd/ description name pyp gdp type ? ipd/ ipu? description host-port interface (hpi) (continued) hd4/gp[0] 156 c19 i/o/z ipd host-port data pin 4 ( i/o/z ) [ default] or this pin can be programmed as a gp[0] pin (i/o/z). hd3/amute1 154 c20 ipu host-port data pin 3 ( i/o/z ) [ default] or mcasp1 mute output (o/z). hd2/afsx1 155 d18 i/o/z ipu host-port data pin 2 ( i/o/z ) [ default] or mcasp1 transmit frame sync or left/right clock (lrclk) (i/o/z). hd1/axr1[7] 152 d20 ipu host-port data pin 1 ( i/o/z ) [ default] or mcasp1 data pin 7 (i/o/z). hd0/axr1[4] 147 e20 i/o/z ipu host-port data pin 0 ( i/o/z ) [ default] or mcasp1 data pin 4 (i/o/z). has /aclkx1 153 e18 i ipu host address strobe ( i ) [default] or mcasp1 transmit bit clock (i/o/z). hcs /axr1[2] 145 f20 i ipu host chip select ( i ) [default] or mcasp1 data pin 2 (i/o/z). hds1 /axr1[6] 151 e19 i ipu host data strobe 1 ( i ) [default] or mcasp1 data pin 6 (i/o/z). hds2 /axr1[5] 150 f18 i ipu host data strobe 2 ( i ) [default] or mcasp1 data pin 5 (i/o/z) . hrdy /aclkr1 140 h19 o/z ipd host ready (from dsp to host) ( o ) [default] or mcasp1 receive bit clock (i/o/z). emif ? common signals to all types of memory ? ce3 57 v6 o/z ipu ce2 61 w6 o/z ipu memory space enables ? enabled by bits 28 through 31 of the word address ce1 103 w18 o/z ipu ? enabled by bits 28 through 31 of the word address ? o nl y o n e asse r ted du rin g a n y e x te rn a l data access ce0 102 v17 o/z ipu ? only one asserted during any external data access be3 ? v5 o/z ipu byte-enable control be2 ? y4 o/z ipu b yte-ena bl e contro l ? decoded from the two lowest bits of the internal address be1 108 u19 o/z ipu ? decoded from the two lowest bits of the internal address ? byte-write enables for most types of memory c b di tl t d t sdram d d it k i l (sdqm) be0 110 v20 o/z ipu yypy ? can be directly connected to sdram read and write mask signal (sdqm) emif ? bus arbitration ? holda 137 j18 o/z ipu hold-request-acknowledge to the host hold 138 j17 i ipu hold request from the host busreq 136 j19 o/z ipu bus request output emif ? asynchronous/synchronous memory control ? eclkin 78 y11 i ipd external emif input clock source eclkout 77 y10 o/z ipd emif output clock depends on the eksrc bit (devcfg.[4]) and on eken bit (gblctl.[5]). eksrc = 0 ? eclkout is based on the internal sysclk3 signal from the clock generator (default). eksrc = 1 ? eclkout is based on the the external emif input clock source pin (eclkin) eken = 0 ? eclkout held low eken = 1 ? eclkout enabled to clock (default) are /sdcas / ssads 79 v11 o/z ipu asynchronous memory read enable/sdram column-address strobe/sbsram address strobe aoe /sdras / ssoe 75 w10 o/z ipu asynchronous memory output enable/sdram row-address strobe/sbsram output enable ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. [these ipd/ipu signal pins feature a 13-k ? resistor (approximate) for the ipd or 18-k ? resistor (approximate) for the ipu. an external pullup or pulldown resistor no greater than 4.4 k ? and 2.0 k ? , respectively, should be used to pull a signal to the opposite supply rail.] ? to maintain signal integrity for the emif signals, serial termination resistors should be inserted into all emif output signal lines.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 49 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? ipd / description name pyp gdp type ? ipd/ ipu ? description emif ? asynchronous/synchronous memory control ? (continued) awe /sdwe / sswe 83 v12 o/z ipu asynchronous memory write enable/sdram write enable/sbsram write enable ardy 56 y5 i ipu asynchronous memory ready input emif ? address ? ea21 109 u18 ea20 101 y18 ea19 100 w17 ea18 95 y16 ea17 99 v16 ea16 92 y15 ea15 94 w15 external address (word half word and byte address) ea14 90 y14 external address (word, half-word, and byte address) the emif ad j usts the address based on memor y width: ea13 91 w14 the emif adjusts the address based on memory width: width pins address ea12 93 v14 o/z ipu 32 21:2 21 through 2 16 21:2 20 through 1 ea11 86 w13 o/z ipu 16 21:2 20 through 1 8 21:2 19 throu g h 0 ea10 76 v10 8 21:2 19 through 0 for more details on address width adjustments, see the external memory i f (emif) h f h tms c p ih l rf gid ea9 74 y9 j, y interface (emif) chapter of the tms320c6000 peripherals reference guide (literature number spru190) ea8 71 v9 (li terature num b er spru190) . ea7 70 y8 ea6 69 w8 ea5 68 v8 ea4 64 w7 ea3 63 v7 ea2 62 y6 emif ? data ? ed31 ? n3 ed30 ? p3 ed29 ? p2 ed28 ? p1 ed27 ? r2 ed26 ? r3 ed25 ? t2 i/o/z ipu external data pins (ed[31:16] pins applicable to gdp package only) ed24 ? t1 i/o/z ipu external data pins (ed[31:16] pins applicable to gdp package only) ed23 ? u3 ed22 ? u1 ed21 ? u2 ed20 ? v1 ed19 ? v2 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. [these ipd/ipu signal pins feature a 13-k ? resistor (approximate) for the ipd or 18-k ? resistor (approximate) for the ipu. an external pullup or pulldown resistor no greater than 4.4 k ? and 2.0 k ? , respectively, should be used to pull a signal to the opposite supply rail.] ? to maintain signal integrity for the emif signals, serial termination resistors should be inserted into all emif output signal lines.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 50 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? ipd/ description name pyp gdp type ? ipd/ ipu? description emif ? data ? (continued) ed18 ? y3 ed17 ? w4 ed16 ? v4 ed15 112 t19 ed14 113 t20 ed13 111 t18 ed12 118 r20 ed11 117 r19 ed10 120 p20 ed9 119 p18 i/o/z ipu external data pins (ed[31:16] pins applicable to gdp package only) ed8 123 n20 i/o/z ipu external data pins (ed[31:16] pins applicable to gdp package only) ed7 122 n19 ed6 121 n18 ed5 128 m20 ed4 127 m19 ed3 129 l19 ed2 130 l18 ed1 131 k19 ed0 132 k18 multichannel audio serial port 1 (mcasp1) gp[4](ext_int4)/ amutein1 1 c2 i/o/z ipu general-purpose input/output pin 4 and external interrupt 4 ( i/o/z ) [default] or mcasp1 mute input (i/o/z). hd3/amute1 154 c20 i/o/z ipu host-port data pin 3 ( i/o/z ) [ default] or mcasp1 mute output (o/z). hrdy /aclkr1 140 h19 i/o/z ipd host ready (from dsp to host) ( o ) [default] or mcasp1 receive bit clock (i/o/z). hd6/ahclkr1 161 c17 i/o/z ipu host-port data pin 6 ( i/o/z ) [ default] or mcasp1 receive high-frequency master clock (i/o/z). has /aclkx1 153 e18 i/o/z ipu host address strobe ( i ) [default] or mcasp 1 transmit bit clock (i/o/z). hd5/ahclkx1 159 b18 i/o/z ipu host-port data pin 5 ( i/o/z ) [ default] or mcasp1 transmit high-frequency master clock (i/o/z). hhwil/afsr1 139 h20 i/o/z ipu host half-word select ? first or second half-word (not necessarily high or low order) ( i ) [default] or mcasp1 receive frame sync or left/right clock (lrclk) (i/o/z). hd2/afsx1 155 d18 i/o/z ipu host-port data pin 2 ( i/o/z ) [ default] or mcasp1 transmit frame sync or left/ right clock (lrclk) (i/o/z). hd1/axr1[7] 152 d20 i/o/z ipu host-port data pin 1 ( i/o/z ) [ default] or mcasp1 tx/rx data pin 7 (i/o/z). hds1 /axr1[6] 151 e19 i/o/z ipu host data strobe 1 ( i ) [default] or mcasp1 tx/rx data pin 6 (i/o/z). hds2 /axr1[5] 150 f18 i/o/z ipu host data strobe 2 ( i ) [default] or mcasp1 tx/rx data pin 5 (i/o/z). hd0/axr1[4] 147 e20 i/o/z ipu host-port data pin 0 ( i/o/z ) [ default] or mcasp1 tx/rx data pin 4 (i/o/z). ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. [these ipd/ipu signal pins feature a 13-k ? resistor (approximate) for the ipd or 18-k ? resistor (approximate) for the ipu. an external pullup or pulldown resistor no greater than 4.4 k ? and 2.0 k ? , respectively, should be used to pull a signal to the opposite supply rail.] ? to maintain signal integrity for the emif signals, serial termination resistors should be inserted into all emif output signal lines.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 51 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? ipd/ ipu? description multichannel audio serial port 1 (mcasp1) (continued) hcntl0/axr1[3] 146 g18 i/o/z ipu host control ? selects between control, address, or data registers ( i ) [default] or mcasp1 tx/rx data pin 3 (i/o/z). hcs /axr1[2] 145 f20 i/o/z ipu host chip select ( i ) [default] or mcasp1 tx/rx data pin 2 (i/o/z). hcntl1/axr1[1] 144 g19 i/o/z ipu host control ? selects between control, address, or data registers ( i ) [default] or mcasp1 tx/rx data pin 1 (i/o/z). hr/w /axr1[0] 143 g20 i/o/z ipu host read or write select ( i ) [default] or mcasp1 tx/rx data pin 0 (i/o/z). multichannel audio serial port 0 (mcasp0) gp[5](ext_int5)/ amutein0 6 c1 i/o/z ipu general-purpose input/output pin 5 and external interrupt 5 ( i/o/z ) [default] or mcasp0 mute input (i/o/z). clkx1/amute0 33 l3 i/o/z ipd mcbsp1 transmit clock ( i/o/z ) [default] or mcasp0 mute output (o/z). clkr0/aclkr0 19 h3 i/o/z ipd mcbsp0 receive clock ( i/o/z ) [default] or mcasp0 receive bit clock (i/o/z). tinp1/ahclkx0 12 f2 i/o/z ipd timer 1 input ( i ) [default] or mcbsp0 transmit high-frequency master clock (i/o/z). clkx0/aclkx0 16 g3 i/o/z ipd mcbsp0 transmit clock ( i/o/z ) [default] or mcasp0 transmit bit clock (i/o/z). clks0/ahclkr0 28 k3 i/o/z ipd mcbsp0 external clock source (as opposed to internal) ( i ) [default] or mcasp0 receive high-frequency master clock (i/o/z). fsr0/afsr0 24 j3 i/o/z ipd mcbsp0 receive frame sync ( i/o/z ) [default] or mcasp0 receive frame sync or left/right clock (lrclk) (i/o/z). fsx0/afsx0 21 h1 i/o/z ipd mcbsp0 transmit frame sync ( i/o/z ) [default] or mcasp0 transmit frame sync or left/right clock (lrclk) (i/o/z). fsr1/axr0[7] 38 m3 i/o/z ipd mcbsp1 receive frame sync ( i/o/z ) [default] or mcasp0 tx/rx data pin 7 (i/o/z). clkr1/axr0[6] 36 m1 i/o/z ipd mcbsp1 receive clock ( i/o/z ) [default] or mcasp0 tx/rx data pin 6 (i/o/z). dx1/axr0[5] 32 l2 i/o/z ipu mcbsp1 transmit data ( o/z ) [default] or mcasp0 tx/rx data pin 5 (i/o/z). tout1/axr0[4] 13 f1 i/o/z ipd timer 1 output ( o ) [default] or mcasp0 tx/rx data pin 4 (i/o/z). tinp0/axr0[3] 17 g2 i/o/z ipd timer 0 input ( i ) [default] or mcasp0 tx/rx data pin 3 (i/o/z). tout0/axr0[2] 18 g1 i/o/z ipd timer 0 output ( o ) [default] or mcasp0 tx/rx data pin 2 (i/o/z). dx0/axr0[1] 20 h2 i/o/z ipu mcbsp0 transmit data ( o/z ) [default] or mcasp0 tx/rx data pin 1 (i/o/z). dr0/axr0[0] 27 j1 i/o/z ipu mcbsp0 receive data ( i ) [default] or mcasp0 tx/rx data pin 0 (i/o/z). timer 1 tout1/axr0[4] 13 f1 o ipd timer 1 output ( o ) [default] or mcasp0 tx/rx data pin 4 (i/o/z). tinp1/ahclkx0 12 f2 i ipd timer 1 input ( i ) [default] or mcbsp0 transmit high-frequency master clock (i/o/z). timer0 tout0/axr0[2] 18 g1 o ipd timer 0 output ( o ) [default] or mcasp0 tx/rx data pin 2 (i/o/z). tinp0/axr0[3] 17 g2 i ipd timer 0 input ( i ) [default] or mcasp0 tx/rx data pin 3 (i/o/z). ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. [these ipd/ipu signal pins feature a 13-k ? resistor (approximate) for the ipd or 18-k ? resistor (approximate) for the ipu. an external pullup or pulldown resistor no greater than 4.4 k ? and 2.0 k ? , respectively, should be used to pull a signal to the opposite supply rail.]
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 52 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? ipd/ description name pyp gdp type ? ipd/ ipu? description multichannel buffered serial port 1 (mcbsp1) clks1/scl1 8 e1 i ? mcbsp1 external clock source (as opposed to internal) ( i ) [default] or i2c1 clock (i/o/z). this pin does not have an internal pullup or pulldown. when this pin is used as a mcbsp pin, this pin should either be driven externally at all times or be pulled up with a 10-k ? resistor to a valid logic level. because it is common for some ics to 3-state their outputs at times, a 10-k ? pullup resistor may be desirable even when an external device is driving the pin. clkr1/axr0[6] 36 m1 i/o/z ipd mcbsp1 receive clock ( i/o/z ) [default] or mcasp0 tx/rx data pin 6 (i/o/z). clkx1/amute0 33 l3 i/o/z ipd mcbsp1 transmit clock ( i/o/z ) [default] or mcasp0 mute output (o/z). dr1/sda1 37 m2 i ? mcbsp1 receive data ( i ) [default] or i2c1 data (i/o/z). this pin does not have an internal pullup or pulldown. when this pin is used as a mcbsp pin, this pin should either be driven externally at all times or be pulled up with a 10-k ? resistor to a valid logic level. because it is common for some ics to 3-state their outputs at times, a 10-k ? pullup resistor may be desirable even when an external device is driving the pin. dx1/axr0[5] 32 l2 o/z ipu mcbsp1 transmit data ( o/z ) [default] or mcasp0 tx/rx data pin 5 (i/o/z). fsr1/axr0[7] 38 m3 i/o/z ipd mcbsp1 receive frame sync ( i/o/z ) [default] or mcasp0 tx/rx data pin 7 (i/o/z). fsx1 31 l1 i/o/z ipd mcbsp1 transmit frame sync multichannel buffered serial port 0 (mcbsp0) clks0/ahclkr0 28 k3 i ipd mcbsp0 external clock source (as opposed to internal) ( i ) [default] or mcasp0 receive high-frequency master clock (i/o/z). clkr0/aclkr0 19 h3 i/o/z ipd mcbsp0 receive clock ( i/o/z ) [default] or mcasp0 receive bit clock (i/o/z). clkx0/aclkx0 16 g3 i/o/z ipd mcbsp0 transmit clock ( i/o/z ) [default] or mcasp0 transmit bit clock (i/o/z). dr0/axr0[0] 27 j1 i ipu mcbsp0 receive data ( i ) [default] or mcasp0 tx/rx data pin 0 (i/o/z). dx0/axr0[1] 20 h2 o/z ipu mcbsp0 transmit data ( o/z ) [default] or mcasp0 tx/rx data pin 1 (i/o/z). fsr0/afsr0 24 j3 i/o/z ipd mcbsp0 receive frame sync ( i/o/z ) [default] or mcasp0 receive frame sync or left/right clock (lrclk) (i/o/z). fsx0/afsx0 21 h1 i/o/z ipd mcbsp0 transmit frame sync ( i/o/z ) [default] or mcasp0 transmit frame sync or left/right clock (lrclk) (i/o/z). inter-integrated circuit 1 (i2c1) clks1/scl1 8 e1 i/o/z ? mcbsp1 external clock source (as opposed to internal) ( i ) [default] or i2c1 clock (i/o/z). this pin must be externally pulled up. when this pin is used as an i2c pin, the value of the pullup resistor is dependent on the number of devices connected to the i2c bus. for more details, see the philips i 2 c specification revision 2.1 (january 2000). dr1/sda1 37 m2 i/o/z ? mcbsp1 receive data ( i ) [default] or i2c1 data (i/o/z). this pin must be externally pulled up. when this pin is used as an i2c pin, the value of the pullup resistor is dependent on the number of devices connected to the i2c bus. for more details, see the philips i 2 c specification revision 2.1 (january 2000). ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. [these ipd/ipu signal pins feature a 13-k ? resistor (approximate) for the ipd or 18-k ? resistor (approximate) for the ipu. an external pullup or pulldown resistor no greater than 4.4 k ? and 2.0 k ? , respectively, should be used to pull a signal to the opposite supply rail.]
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 53 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? ipd/ description name pyp gdp type ? ipd/ ipu? description inter-integrated circuit 0 (i2c0) scl0 41 n1 i/o/z ? i2c0 clock. this pin must be externally pulled up. the value of the pullup resistor on this pin is dependent on the number of devices connected to the i2c bus. for more details, see the philips i 2 c specification revision 2.1 (january 2000). sda0 42 n2 i/o/z ? i2c0 data. this pin must be externally pulled up. the value of the pullup resistor on this pin is dependent on the number of devices connected to the i2c bus. for more details, see the philips i 2 c specification revision 2.1 (january 2000). general-purpose input/output (gpio) hd15/gp[15] 174 b14 ipu host-port data pins ( i/o/z ) [default] or general-purpose input/output pins (i/o/z) and some function as boot configuration pins at reset. hd14/gp[14] 173 c14 ipu (i/o/z) and some function as boot configuration pins at reset . ? used for transfer of data, address, and control ? also controls initialization of dsp modes at reset via p ullu p / p ulldown hd13/gp[13] 172 a15 ipu ? also controls initialization of dsp modes at reset via pullup/pulldown resistors hd12/gp[12] 168 c15 i/o/z ipu as general-purpose input/output (gp[x]) functions, these pins are software-con- figurable through registers. the ?gpxen? bits in the gp enable register and the gpxdir bits in the gp direction register must be properly configured: hd11/gp[11] 167 a16 i/o/z ipu gpxdir bits in the gp direction register must be properly configured: gpxen = 1; gp[x] pin is enabled hd10/gp[10] 166 b16 ipu gp x en = 1 ; gp[ x ] p i n i s ena bl e d . gpxdir = 0; gp[x] pin is an input. gpxdir = 1 ; gp [ x ] p in is an out p ut. hd9/gp[9] 165 c16 ipu gpxdir = 1; gp[x] pin is an output . for the functionality description of the host-port data pins or the boot configura- hd8/gp[8] 160 b17 ipu for the functionality description of the host port data pins or the boot configura tion pins, see the host-port interface (hpi) portion of this table. gp[7](ext_int7) 7 e3 general-purpose input/output pins ( i/o/z ) which also function as external interrupts gp[6](ext_int6) 2 d2 interrupts ? edge-driven polarit independentl selected ia the e ternal interr pt polarit register gp[5](ext_int5)/ amutein0 6 c1 i/o/z ipu ? polarity independently selected via the external interrupt polarity register bits (extpol.[3:0]) gp[4] d gp[5] i l f ti amutein1 m asp1 t i t d gp[4](ext_int4)/ amutein1 1 c2 gp[4] and gp[5] pins also function as amutein1 mcasp1 mute input and amutein0 mcasp0 mute input, respectively, if enabled by the inen bit in the associated mcasp amute register. hd7/gp[3] 164 a18 i/o/z ipu host-port data pin 7 ( i/o/z ) [default] or general-purpose input/output pin 3 (i/o/z) clkout2/gp[2] 82 y12 i/o/z ipd clock output at half of device speed ( o/z ) [default] or this pin can be programmed as gp[2] pin. hint /gp[1] 135 j20 o ipu host interrupt (from dsp to host) ( o ) [default] or this pin can be programmed as a gp[1] pin (i/o/z). hd4/gp[0] 156 c19 i/o/z ipd host-port data pin 4 ( i/o/z ) [ default] or this pin can be programmed as a gp[0] pin (i/o/z). ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. [these ipd/ipu signal pins feature a 13-k ? resistor (approximate) for the ipd or 18-k ? resistor (approximate) for the ipu. an external pullup or pulldown resistor no greater than 4.4 k ? and 2.0 k ? , respectively, should be used to pull a signal to the opposite supply rail.]
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 54 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? ipd/ description name pyp gdp type ? ipd/ ipu? description reserved for test rsv 198 a5 o/z ipu reserved. (leave unconnected, do not connect to power or ground) rsv 200 b5 a reserved. (leave unconnected, do not connect to power or ground) rsv 179 c12 o ? reserved. (leave unconnected, do not connect to power or ground) rsv ? d7 o/z ipd reserved. (leave unconnected, do not connect to power or ground) rsv 178 d12 i ? reserved. this pin does not have an ipu. for proper c6713 device operation, the d12 pin must be externally pulled down with a 10-k ? resistor. rsv 181 a12 ? reserved. (leave unconnected, do not connect to power or ground) rsv 180 b11 ? reserved. (leave unconnected, do not connect to power or ground) ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground ? ipd = internal pulldown, ipu = internal pullup. [these ipd/ipu signal pins feature a 13-k ? resistor (approximate) for the ipd or 18-k ? resistor (approximate) for the ipu. an external pullup or pulldown resistor no greater than 4.4 k ? and 2.0 k ? , respectively, should be used to pull a signal to the opposite supply rail.] a = analog signal
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 55 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? description name pyp gdp type ? description supply voltage pins ? a17 ? b3 ? b8 ? b13 ? c10 ? d1 ? d16 ? d19 ? f3 ? h18 ? j2 ? m18 ? r1 ? r18 ? t3 ? u5 ? u7 ? u12 ? u16 dv ? v13 s 3.3-v supply voltage dv dd ? v15 s 3 . 3 v supply voltage (see the power-supply decoupling portion of this data sheet) ? v19 ? w3 ? w9 ? w12 ? y7 ? y17 5 ? 9 ? 25 ? 44 ? 47 ? 55 ? 58 ? 65 ? 72 ? 84 ? 87 ? 98 ? 107 ? ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 56 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? description name pyp gdp type ? description supply voltage pins (continued) 114 ? 126 ? 141 ? 3 3 v l lt dv dd 162 ? s 3.3-v supply voltage (see the power - supply decoupling portion of this data sheet) dv dd 183 ? s ( see th e power-supp l y d ecoup li ng por ti on o f thi s d a t a s h ee t) 188 ? 206 ? ? a4 ? a9 ? a10 ? b2 ? b19 ? c3 ? c7 ? c18 ? d5 ? d6 ? d11 ? d14 ? d15 ? f4 ? f17 cv ? k1 s 1.2-v supply voltage [pyp package] 1 26 v supply voltage [gdp package] cv dd ? k4 s 1.26-v supply voltage [gdp package] (see th e po w e r- s u pp l y deco u p lin g po rti o n o f thi s da t a s h ee t ) ? k17 (see the power - supply decoupling portion of this data sheet) ? l4 ? l17 ? l20 ? r4 ? r17 ? u6 ? u10 ? u11 ? u14 ? u15 ? v3 ? v18 ? w2 ? w19 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 57 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? description name pyp gdp type ? description supply voltage pins (continued) 3 ? 11 ? 14 ? 22 ? 29 ? 35 ? 40 ? 43 ? 46 ? 50 ? 51 ? 53 ? 60 ? 67 ? 80 ? cv 89 ? s 1.2-v supply voltage [pyp package] 1 26 v supply voltage [gdp package] cv dd 96 ? s 1.26-v supply voltage [gdp package] (see t h e po w e r- supp l y decoup lin g po r t i o n o f t hi s data s h eet) 104 ? (see the power - supply decoupling portion of this data sheet) 105 ? 116 ? 124 ? 133 ? 149 ? 157 ? 169 ? 171 ? 177 ? 190 ? 195 ? 196 ? 201 ? 208 ? ground pins ? a1 ? a2 ? a11 v ? a14 gnd ground pins v ss ? a19 gnd ground pins ? a20 ? b1 ? b4 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 58 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? description name pyp gdp type ? description ground pins (continued) ? b15 ? b20 ? c6 ? c8 ? c9 ? d4 ? d8 ? d13 ? d17 ? e2 ? e4 ? e17 ? f19 ? g4 ? g17 ? h4 ? h17 ? j4 # v ? j9 gnd ground pins # the center thermal balls (j9 j12 k9 k12 l9 l12 m9 m12) [shaded] are all tied to ground v ss ? j10 gnd the center thermal balls (j9 ? j12, k9 ? k12, l9 ? l12, m9 ? m12) [shaded] are all tied to ground a n d ac t as bo th e l ec tri ca l g r o un ds a n d th e rm a l r e li e f ( th e rm a l d i ss i pa ti o n ) . ? j11 and act as both electrical grounds and thermal relief (thermal dissipation) . ? j12 ? k2 ? k9 ? k10 ? k11 ? k12 ? k20 ? l9 ? l10 ? l11 ? l12 ? m4 ? m9 ? m10 ? m11 ? m12 ? m17 ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground # shaded pin numbers denote the center thermal balls.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 59 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? description name pyp gdp type ? description ground pins (continued) ? n4 ? n17 ? p4 ? p17 ? p19 ? t4 ? t17 ? u4 ? u8 ? u9 ? u13 ? u17 ? u20 ? w1 ? w5 ? w11 ? w16 ? w20 ? y1 v ? y2 gnd ground pins v ss ? y13 gnd ground pins ? y19 ? y20 4 ? 10 ? 15 ? 23 ? 26 ? 30 ? 34 ? 39 ? 45 ? 48 ? 49 ? 52 ? 54 ? 59 ? 66 ? 73 ? 81 ? ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 60 post office box 1443 ? houston, texas 77251 ? 1443 terminal functions (continued) signal pin no. type ? description name pyp gdp type ? description ground pins (continued) 85 ? 88 ? 97 ? 106 ? 115 ? 125 ? 134 ? 142 ? v 148 ? gnd ground pins v ss 158 ? gnd ground pins 163 ? 170 ? 182 ? 189 ? 194 ? 199 ? 203 ? 207 ? ? i = input, o = output, z = high impedance, s = supply voltage, gnd = ground
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 61 post office box 1443 ? houston, texas 77251 ? 1443 development support ti offers an extensive line of development tools for the tms320c6000 ? dsp platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development of c6000 ? dsp-based applications: software development tools: code composer studio ? integrated development environment (ide): including editor c/c++/assembly code generation, and debug plus additional development tools scalable, real-time foundation software (dsp/bios ? ), which provides the basic run-time target software needed to support any dsp application. hardware development tools: extended development system (xds ? ) emulator (supports c6000 ? dsp multiprocessor system debug) evm (evaluation module) for a complete listing of development-support tools for the tms320c6000 ? dsp platform, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url). for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. ti offers an extensive line of development tools for the tms320c6000 ? dsp platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. c6000 and xds are trademarks of texas instruments.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 62 post office box 1443 ? houston, texas 77251 ? 1443 device and development-support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all tms320 ? dsp devices and support tools. each tms320 ? dsp commercial family member has one of three prefixes: tmx, tmp, or tms. texas instruments recommends two of three possible prefix designators for support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx/tmdx) through fully qualified p roduction devices/tools (tms/tmds). device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device?s electrical specifications tmp final silicon die that conforms to the device?s electrical specifications but has not completed quality and reliability verification tms fully qualified production device support tool development evolutionary flow: tmdx development-support product that has not yet completed texas instruments internal qualification testing. tmds fully qualified development-support product tmx and tmp devices and tmdx development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. experimental devices (tmx) may not be representative of a final product and texas instruments reserves the right to change or discontinue these products without notice. tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti?s standard warranty applies. predictions show that prototype devices (tmx or tmp) have a greater failure rate than the standard production devices. t exas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suf fix indicates the package type (for example, gdp), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -225 is 225 mhz). figure 12 provides a legend for reading the complete device name for any tms320c6000 ? dsp family member. tms320 is a trademark of texas instruments.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 63 post office box 1443 ? houston, texas 77251 ? 1443 device and development-support tool nomenclature (continued) table 24. tms320c6713 device part numbers (p/ns) and ordering information device orderable p/n device speed core and i/o voltage operating case temperature device orderable p/n device speed cv dd (core) dv dd (i/o) temperature range tms320c6713gdp225 225 mhz/1350 mflops 1.26 v 3.3 v 0 c to 90 c tms320c6713gdpa200 200 mhz/1200 mflops 1.26 v 3.3 v ? 40 c to 105 c tms320c6713pyp200 200 mhz/1200 mflops 1.2 v 3.3 v 0 c to 90 c tms320c6713pypa167 167 mhz/1000 mflops 1.2 v 3.3 v ? 40 c to 105 c prefix device speed range tms 320 c 6713 gdp 225 tmx = experimental device tmp = prototype device tms = qualified device smj = mil-prf-38535, qml sm = high rel (non-38535) device family 320 = tms320 ? dsp family technology package type ? c = cmos device ? bga = ball grid array qfp = quad flatpack temperature range (default: 0 c to 90 c) ( ) blank = 0 c to 90 c, commercial temperature a= ? 40 c to 105 c, extended temperature c6000 dsps: c6201 c6205 c6415 c6711b c6202 c6211 c6416 c6711c c6202b c6211b dm642 c6712 c6203b c6411 c6701 c6712c c6204 c6414 c6711 c6713 gdp = 272-pin plastic bga gfn = 256-pin plastic bga ggp = 352-pin plastic bga gjc = 352-pin plastic bga gjl = 352-pin plastic bga gls = 384-pin plastic bga glw = 340-pin plastic bga gny = 384-pin plastic bga gnz = 352-pin plastic bga glz = 532-pin plastic bga ghk = 288-pin plastic microstar bga pyp = 208-pin powerpad plastic qfp 100 mhz 120 mhz 150 mhz 167 mhz 200 mhz 225 mhz 233 mhz 250 mhz 300 mhz 400 mhz 500 mhz 600 mhz figure 12. tms320c6000 ? dsp device nomenclature (including the tms320c6713 device) microstar bga and powerpad are trademarks of texas instruments.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 64 post office box 1443 ? houston, texas 77251 ? 1443 documentation support extensive documentation supports all tms320 ? dsp family generations of devices from product announcement through applications development. the types of documentation available include: data sheets, such as this document, with design specifications; complete user?s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. the following is a brief, descriptive list of support documentation specific to the c6000 ? dsp devices: the tms320c6000 cpu and instruction set reference guide (literature number spru189) describes the c6000 ? cpu (dsp core) architecture, instruction set, pipeline, and associated interrupts. the tms320c6000 peripherals reference guide (literature number spru190) describes the functionality of the peripherals available on the c6000 ? dsp platform of devices, such as the external memory interface (emif), host-port interface (hpi), multichannel buffered serial ports (mcbsps), enhanced direct-memory-access (edma) controller, and power-down modes. this guide also includes information on internal data and program memories. these c6713 peripherals are similar to the peripherals on the tms320c6711 and tms320c64x devices; therefore, see the tms320c6711 (c6711 or c67x) peripheral information, and in some cases, where indicated, see the c64x information in the tms320c6000 peripherals reference guide (literature number spru190). the tms320da6000 dsp multichannel audio serial port (mcasp) reference guide (literature number spru041) describes the functionality of the mcasp peripherals available on the c6713 device. tms320c6000 dsp phase ? locked loop (pll) controller peripheral reference guide (literature number spru233) describes the functionality of the pll peripheral available on the c6713 device. tms320c6000 dsp inter-integrated circuit (i2c) module reference guide (literature number spru175) describes the functionality of the i2c peripherals available on the c6713 device. the powerpad thermally enhanced package technical brief (literature number slma002) focuses on the specifics of integrating a powerpad package into the printed circuit board design to make optimum use of the thermal efficiencies designed into the powerpad package. the tms320c6000 technical brief (literature number spru197) gives an introduction to the c62x ? /c67x ? devices, associated development tools, and third-party support. the migrating from tms320c6211(b)/c6711(b) to tms320c6713 application report (literature number spra851) indicates the differences and describes the issues of interest related to the migration from the t exas instruments tms320c6211(b)/c6711(b), gfn package, to the tms320c6713, gdp package. the tms320c6713 digital signal processor silicon errata (literature number sprz191) describes the known exceptions to the functional specifications for particular silicon revisions of the tms320c6713 device . the tms320c6713/12c/11c power consumption summary application report (literature number spra889) discusses the power consumption for user applications with the tms320c6713, tms320c6712c, and tms320c6711c dsp devices. the using ibis models for timing analysis application report (literature number spra839) describes how to properly use ibis models to attain accurate timing analysis for a given system. the tools support documentation is electronically available within the code composer studio ? integrated development environment (ide). for a complete listing of c6000 ? dsp latest documentation, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url). see the worldwide web url for the application report how to begin development today with the tms320c6713 floating-point dsp (literature number spra809), which describes in more detail the similarities/differences between the c6713 and c6711 c6000 ? dsp devices. c62x is a trademark of texas instruments.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 65 post office box 1443 ? houston, texas 77251 ? 1443 cpu csr register description the cpu control status register (csr) contains the cpu id and cpu revision id (bits 16 ? 31) as well as the status of the device power-down modes [pwrd field (bits 15 ? 10)], program and data cache control modes, the endian bit (en, bit 8) and the global interrupt enable (gie, bit 0) and previous gie (pgie, bit 1). figure 13 and table 25 identify the bit fields in the cpu csr register. for more detailed information on the bit fields in the cpu csr register, see the tms320c6000 peripherals reference guide (literature number spru190) and the tms320c6000 cpu and instruction set reference guide (literature number spru189). 31 24 23 16 cpu id revision id r-0x02 r-0x03 15 10 9 8 7 6 5 4 2 1 0 pwrd sat en pcc dcc pgie gie r/w-0 r/c-0 r-1 r/w-0 r/w-0 r/w-0 r/w-0 legend: r = readable by the mvc instruction, r/w = readable/writeable by the mvc instruction; w = read/write; - n = value after reset, -x = undefined value after reset, c = clearable by the mvc instruction figure 13. cpu control status register (cpu csr)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 66 post office box 1443 ? houston, texas 77251 ? 1443 cpu csr register description (continued) table 25. cpu csr register bit field description bit # name description 31:24 cpu id cpu id + rev id. read only. identifies which cpu is used and defines the silicon revision of the cpu. 23:16 revision id identifies which cpu is used and defines the silicon revision of the cpu . cpu id + revision id (31:16) are combined for a value of: 0x0203 for c6713 15:10 pwrd control power-down modes. the values are always read as zero. 000000 = no power-down (default) 001001 = pd1, wake-up by an enabled interrupt 010001 = pd1, wake-up by an enabled or not enabled interrupt 011010 = pd2, wake-up by a device reset 011100 = pd3, wake-up by a device reset others = reserved 9 sat saturate bit. set when any unit performs a saturate. this bit can be cleared only by the mvc instruction and can be set only by a functional unit. the set by the a functional unit has priority over a clear (by the mvc instruction) if they occur on the same cycle. the saturate bit is set one full cycle (one delay slot) after a saturate occurs. this bit will not be modified by a conditional instruction whose condition is false. 8 en endian bit. this bit is read-only. depicts the device endian mode. 0 = big endian mode. 1 = little endian mode [default]. 7:5 pcc program cache control mode. l1d, level 1 program cache 000/010 = cache enabled / cache accessed and updated on reads. all other pcc values reserved. 4:2 dcc data cache control mode. l1d, level 1 data cache 000/010 = cache enabled / 2-way cache all other dcc values reserved 1 pgie previous gie (global interrupt enable); saves the global interrupt enable (gie) when an interrupt is taken. allows for proper nesting of interrupts. 0 = previous gie value is 0. (default) 1 = previous gie value is 1. 0 gie global interrupt enable bit. enables (1) or disables (0) all interrupts except the reset interrupt and nmi (nonmaskable interrupt). 0 = disables all interrupts (except the reset interrupt and nmi) [default] 1 = enables all interrupts (except the reset interrupt and nmi)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 67 post office box 1443 ? houston, texas 77251 ? 1443 interrupts and interrupt selector the c67x dsp core supports 16 prioritized interrupts, which are listed in table 26. the highest priority interrupt is int_00 (dedicated to reset) while the lowest priority is int_15. the first four interrupts are non-maskable and fixed. the remaining interrupts (4 ? 15) are maskable and default to the interrupt source listed in table 26. however, their interrupt source may be reprogrammed to any one of the sources listed in table 27 (interrupt selector). t able 27 lists the selector value corresponding to each of the alternate interrupt sources. the selector choice for interrupts 4 ? 15 is made by programming the corresponding fields (listed in table 26) in the muxh (address 0x019c0000) and muxl (address 0x019c0004) registers.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 68 post office box 1443 ? houston, texas 77251 ? 1443 table 26. dsp interrupts table 27. interrupt selector dsp interrupt number interrupt selector control register default selector value (binary) default interrupt event interrupt selector value (binary) interrupt event module int_00 ? ? reset 00000 dspint hpi int_01 ? ? nmi 00001 tint0 timer 0 int_02 ? ? reserved 00010 tint1 timer 1 int_03 ? ? reserved 00011 sdint emif int_04 muxl[4:0] 00100 gpint4 ? 00100 gpint4 ? gpio int_05 muxl[9:5] 00101 gpint5 ? 00101 gpint5 ? gpio int_06 muxl[14:10] 00110 gpint6 ? 00110 gpint6 ? gpio int_07 muxl[20:16] 00111 gpint7 ? 00111 gpint7 ? gpio int_08 muxl[25:21] 01000 edmaint 01000 edmaint edma int_09 muxl[30:26] 01001 emudtdma 01001 emudtdma emulation int_10 muxh[4:0] 00011 sdint 01010 emurtdxrx emulation int_11 muxh[9:5] 01010 emurtdxrx 01011 emurtdxtx emulation int_12 muxh[14:10] 01011 emurtdxtx 01100 xint0 mcbsp0 int_13 muxh[20:16] 00000 dspint 01101 rint0 mcbsp0 int_14 muxh[25:21] 00001 tint0 01110 xint1 mcbsp1 int_15 muxh[30:26] 00010 tint1 01111 rint1 mcbsp1 10000 gpint0 gpio 10001 reserved ? 10010 reserved ? 10011 reserved ? 10100 reserved ? 10101 reserved ? 10110 i2cint0 i2c0 10111 i2cint1 i2c1 11000 reserved ? 11001 reserved ? 11010 reserved ? 11011 reserved ? 11100 axint0 mcasp0 11101 arint0 mcasp0 11110 axint1 mcasp1 11111 arint1 mcasp1 ? interrupt events gpint4, gpint5, gpint6, and gpint7 are outputs from the gpio module (gp). they originate from the device pins gp[4](ext_int4)/amutein1, gp[5](ext_int5)/amutein0, gp[6](ext_int6), and gp[7](ext_int7). these pins can be used as edge-sensitive ext_intx with polarity controlled by the external interrupt polarity register (extpol.[3:0]). the corresponding pins must first be enabled in the gpio module by setting the corresponding enable bits in the gp enable register (gpen.[7:4]), and configuring them as inputs in the gp direction register (gpdir.[7:4]). these interrupts can be controlled through the gpio module in addition to the simp le extpol.[3:0] bits. for more information on interrupt control via the gpio module, see the gpio module section of the the tms320c6000 peripherals reference guide (literature number spru190).
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 69 post office box 1443 ? houston, texas 77251 ? 1443 external interrupt sources the c6713 device supports many external interrupt sources as indicated in table 28. control of the interrupt source is done by the associated module and is made available by enabling the corresponding binary interrupt selector value (see table 27 interrupt selector shaded rows). due to pin muxing and module usage, not all external interrupt sources are available at the same time. table 28. external interrupt sources and peripheral module control pin name interrupt event module gp[15] gpint0 gpio gp[14] gpint0 gpio gp[13] gpint0 gpio gp[12] gpint0 gpio gp[11] gpint0 gpio gp[10] gpint0 gpio gp[9] gpint0 gpio gp[8] gpint0 gpio gp[7] gpint0 or gpint7 gpio gp[6] gpint0 or gpint6 gpio gp[5] gpint0 or gpint5 gpio gp[4] gpint0 or gpint4 gpio gp[3] gpint0 gpio gp[2] gpint0 gpio gp[1] gpint0 gpio gp[0] gpint0 gpio
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 70 post office box 1443 ? houston, texas 77251 ? 1443 edma module and edma selector the c67x edma supports up to 16 edma channels. four of the sixteen channels (channels 8 ? 11) are reserved for edma chaining, leaving 12 edma channels available to service peripheral devices. the edma selector registers that control the edma channels servicing peripheral devices are located at addresses 0x01a0ff00 (esel0), 0x01a0ff04 (esel1), and 0x01a0ff0c (esel3). these edma selector registers control the mapping of the edma events to the edma channels. each edma event has an assigned edma selector code (see table 30). by loading each evtselx register field with an edma selector code, users can map any desired edma event to any specified edma channel. table 29 lists the default edma selector value for each edma channel. see table 31 and table 32 for the edma event selector registers and their associated bit descriptions.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 71 post office box 1443 ? houston, texas 77251 ? 1443 edma module and edma selector (continued) table 29. edma channels table 30. edma selector edma channel edma selector control register default selector value (binary) default edma event edma selector code (binary) edma event module 0 esel0[5:0] 000000 dspint 000000 dspint hpi 1 esel0[13:8] 000001 tint0 000001 tint0 timer0 2 esel0[21:16] 000010 tint1 000010 tint1 timer1 3 esel0[29:24] 000011 sdint 000011 sdint emif 4 esel1[5:0] 000100 gpint4 000100 gpint4 gpio 5 esel1[13:8] 000101 gpint5 000101 gpint5 gpio 6 esel1[21:16] 000110 gpint6 000110 gpint6 gpio 7 esel1[29:24] 000111 gpint7 000111 gpint7 gpio 8 ? ? tcc8 (chaining) 001000 gpint0 gpio 9 ? ? tcc9 (chaining) 001001 gpint1 gpio 10 ? ? tcc10 (chaining) 001010 gpint2 gpio 11 ? ? tcc11 (chaining) 001011 gpint3 gpio 12 esel3[5:0] 001100 xevt0 001100 xevt0 mcbsp0 13 esel3[13:8] 001101 revt0 001101 revt0 mcbsp0 14 esel3[21:16] 001110 xevt1 001110 xevt1 mcbsp1 15 esel3[29:24] 001111 revt1 001111 revt1 mcbsp1 010000 ? 011111 reserved 100000 axevte0 mcasp0 100001 axevto0 mcasp0 100010 axevt0 mcasp0 100011 arevte0 mcasp0 100100 arevto0 mcasp0 100101 arevt0 mcasp0 100110 axevte1 mcasp1 100111 axevto1 mcasp1 101000 axevt1 mcasp1 101001 arevte1 mcasp1 101010 arevto1 mcasp1 101011 arevt1 mcasp1 101100 i2crevt0 i2c0 101101 i2cxevt0 i2c0 101110 i2crevt1 i2c1 101111 i2cxevt1 i2c1 110000 gpint8 gpio 110001 gpint9 gpio 110010 gpint10 gpio 110011 gpint11 gpio 110100 gpint12 gpio 110101 gpint13 gpio 110110 gpint14 gpio 110111 gpint15 gpio 111000 ? 111111 reserved
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 72 post office box 1443 ? houston, texas 77251 ? 1443 edma module and edma selector (continued) table 31. edma event selector registers (esel0, esel1, and esel3) esel0 register (0x01a0 ff00) 31 30 29 28 27 24 23 22 21 20 19 16 reserved evtsel3 reserved evtsel2 r ? 0 r/w ? 00 0011b r ? 0 r/w ? 00 0010b 15 14 13 12 11 87 65 43 0 reserved evtsel1 reserved evtsel0 r ? 0 r/w ? 00 0001b r ? 0 r/w ? 00 0000b legend: r = read only, r/w = read/write; -n = value after reset esel1 register (0x01a0 ff04) 31 30 29 28 27 24 23 22 21 20 19 16 reserved evtsel7 reserved evtsel6 r ? 0 r/w ? 00 0111b r ? 0 r/w ? 00 0110b 15 14 13 12 11 87 6 543 0 reserved evtsel5 reserved evtsel4 r ? 0 r/w ? 00 0101b r ? 0 r/w ? 00 0100b legend: r = read only, r/w = read/write; -n = value after reset esel3 register (0x01a0 ff0c) 31 30 29 28 27 24 23 22 21 20 19 16 reserved evtsel15 reserved evtsel14 r ? 0 r/w ? 00 1111b r ? 0 r/w ? 00 1110b 15 14 13 12 11 87 65 43 0 reserved evtsel13 reserved evtsel12 r ? 0 r/w ? 00 1101b r ? 0 r/w ? 00 1100b legend: r = read only, r/w = read/write; -n = value after reset table 32. edma event selection registers (esel0, esel1, and esel3) description bit # name description 31:30 23:22 15:14 7:6 reserved reserved. read-only, writes have no effect. 29:24 21:16 13:8 5:0 evtselx edma event selection bits for channel x. allows mapping of the edma events to the edma channels. the evtsel0 through evtsel15 bits correspond to the channels 0 to 15, respectively. these evtselx fields are user ? selectable. by configuring the evtselx fields to the edma selector value of the desired edma sync event number (see table 30), users can map any edma event to the edma channel. for example, if evtsel15 is programmed to 00 0001b (the edma selector code for tint0), then channel 15 is triggered by timer0 tint0 events.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 73 post office box 1443 ? houston, texas 77251 ? 1443 pll and pll controller the tms320c6713 includes a pll and a flexible pll controller peripheral consisting of a prescaler (d0) and four dividers (oscdiv1, d1, d2, and d3). the pll controller is able to generate different clocks for different parts of the system (i.e., dsp core, peripheral data bus, external memory interface, mcasp, and other peripherals). figure 14 illustrates the pll, the pll controller, and the clock generator logic. clkin clkout3 for use in system /1, /2, ..., /32 ..., /32 /1, /2, pll x4 to x25 pllen (pll_csr.[0]) ..., /32 /1, /2, /1, /2, ..., /32 /1, /2, ..., /32 (dsp core) sysclk1 (peripherals) sysclk2 eclkin eksrc bit (devcfg.[4]) emif ? dividers d1 and d2 must never be disabled. never write a ?0? to the d1en or d2en bits in the plldiv1 and plldiv2 registers. sysclk3 clkmode0 (emif clock input) c6713 dsp pllout pllref divider d0 oscdiv1 divider d1 ? divider d2 ? divider d3 eclkout auxclk (internal clock source to mcasp0 and mcasp1) 1 0 1 0 1 0 pllhv c2 c1 emi filter +3.3 v 10 f 0.1 f d0en (plldiv0.[15]) ena ena od1en (oscdiv1.[15]) ena ena ena d1en (plldiv1.[15]) ena d2en (plldiv2.[15]) ena d3en (plldiv3.[15]) reserved notes: a. place all pll external components (c1, c2, and the emi filter) as close to the c67x ? dsp device as possible. for the best performance, ti recommends that all the pll external components be on a single side of the board without jumpers, switches, or components other than the ones shown. b. for reduced pll jitter, maximize the spacing between switching signals and the pll external components (c1, c2, and the emi filter). c. the 3.3-v supply for the emi filter must be from the same 3.3-v power plane supplying the i/o voltage, dv dd . d. emi filter manufacturer tdk part number acf451832-333, -223, -153, -103. panasonic part number exccet103u. figure 14. pll and clock generator logic
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 74 post office box 1443 ? houston, texas 77251 ? 1443 pll and pll controller (continued) the pll reset time is the amount of wait time needed when resetting the pll (writing pllrst=1), in order for the pll to properly reset, before bringing the pll out of reset (writing pllrst = 0). for the pll reset time value, see table 33. the pll lock time is the amount of time from when pllrst = 0 with pllen = 0 (pll out of reset, but still bypassed) to when the pllen bit can be safely changed to ?1? (switching from bypass to the pll path), see table 33 and figure 14. under some operating conditions, the maximum pll lock time may vary from the specified typical value. for the pll lock time values, see table 33. table 33. pll lock and reset times min typ max unit pll lock time 75 187.5 s pll reset time 125 ns table 34 shows the c6713 device?s clkout signals, how they are derived and by what register control bits, and what is the default settings. for more details on the pll, see the pll and clock generator logic diagram (figure 14). table 34. clkout signals, default settings, and control clock output signal name default setting (enabled or disabled) control bit(s) (register) description clkout2 on (enabled) d2en = 1 (plldiv2.[15]) ck2en = 1 (emif gblctl.[3]) sysclk2 selected [default] clkout3 on (enabled) od1en = 1 (oscdiv1.[15]) derived from clkin eclkout on (enabled); derived from sysclk3 eksrc = 0 (devcfg.[4]) eken = 1 (emif gblctl.[5]) sysclk3 selected [default]. to select eclkin source: eksrc = 1 (devcfg.[4]) and eken = 1 (emif gblctl.[5]) the input clock (clkin) is directly available to the mcasp modules as auxclk for use as an internal high-frequency clock source. the input clock (clkin) may also be divided down by a programmable divider oscdiv1 (/1, /2, /3, ..., /32) and output on the clkout3 pin for other use in the system. figure 14 shows that the input clock source may be divided down by divider plldiv0 (/1, /2, ..., /32) and then multiplied up by a factor of x4, x5, x6, and so on, up to x25. either the input clock (pllen = 0) or the pll output (pllen = 1) then serves as the high-frequency reference clock for the rest of the dsp system. the dsp core clock, the peripheral bus clock, and the emif clock may be divided down from this high-frequency clock (each with a unique divider) . for example, with a 30 mhz input if the pll output is configured for 450 mhz, the dsp core may be operated at 225 mhz (/2) while the emif may be configured to operate at a rate of 75 mhz (/6). note that there is a specific minimum and maximum reference clock (pllref) and output clock (pllout) for the block labeled pll in figure 14, as well as for the dsp core, peripheral bus, and emif. the clock generator must not be configured to exceed any of these constraints (certain combinations of external clock input, internal dividers, and pll multiply ratios might not be supported). see table 35 for the pll clocks input and output frequency ranges.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 75 post office box 1443 ? houston, texas 77251 ? 1443 pll and pll controller (continued) table 35. pll clock frequency ranges ?? clock signal gdp-225 gdpa-200 pyp-200 pypa-167 unit min max pllref (pllen = 1) 12 100 mhz pllout 140 600 mhz sysclk1 ? device speed (dsp core) mhz sysclk3 (eksrc = 0) ? 100 mhz auxclk ? 50 mhz ? sysclk2 rate must be exactly half of sysclk1. ? also see the electrical specification (timing requirements and switching characteristics parameters) in the input and output clocks section of this data sheet. when the mcasp module is not used, the auxclk maximum frequency can be any frequency up to the clkin maximum frequency. the emif itself may be clocked by an external reference clock via the eclkin pin or can be generated on-chip as sysclk3. sysclk3 is derived from divider d3 off of pllout (see figure 14, pll and clock generator logic). the emif clock selection is programmable via the eksrc bit in the devcfg register. the settings for the pll multiplier and each of the dividers in the clock generation block may be reconfigured via software at run time. if either the input to the pll changes due to d0, clkmode0, or clkin, or if the pll multiplier is changed, then software must enter bypass first and stay in bypass until the pll has had enough time to lock (see electrical specifications). for the programming procedure, see the tms320c6000 dsp phase-locked loop (pll) controller peripheral reference guide (literature number spru233). sysclk2 is the internal clock source for peripheral bus control. sysclk2 (divider d2) must be programmed to be half of the sysclk1 rate. for example, if d1 is configured to divide-by-2 mode (/2), then d2 must be programmed to divide-by-4 mode (/4). sysclk2 is also tied directly to clkout2 pin (see figure 14). during the programming transition of divider d1 and divider d2 (resulting in sysclk1 and sysclk2 output clocks, see figure 14), the order of programming the plldiv1 and plldiv2 registers must be observed to ensure that sysclk2 always runs at half the sysclk1 rate or slower. for example, if the divider ratios of d1 and d2 are to be changed from /1, /2 (respectively) to /5, /10 (respectively) then, the plldiv2 register must be programmed before the plldiv1 register. the transition ratios become /1, /2; /1, /10; and then /5, /10. if the divider ratios of d1 and d2 are to be changed from /3, /6 to /1, /2 then, the plldiv1 register must be programmed before the plldiv2 register. the transition ratios, for this case, become /3, /6; /1, /6; and then /1, /2. the final sysclk2 rate must be exactly half of the sysclk1 rate. note that divider d1 and divider d2 must always be enabled (i. e., d1en and d2en bits are set to ?1? in the plldiv1 and plldiv2 registers). the pll controller registers should be modified only by the cpu or via emulation. the hpi should not be used to directly access the pll controller registers. for detailed information on the clock generator (pll controller registers) and their associated software bit descriptions, see table 37 through table 43.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 76 post office box 1443 ? houston, texas 77251 ? 1443 pll and pll controller (continued) table 36. pll control/status register (pllcsr) [0x01b7 c100] 31 28 27 24 23 20 19 16 reserved r ? 0 15 12 11 87 6543 21 0 reserved stable reserved pllrst reserved pllpwrdn pllen r ? 0r ? x r ? 0 rw ? 1 r/w ? 0 r/w ? 0b rw ? 0 legend: r = read only, r/w = read/write; -n = value after reset table 37. pll control/status register (pllcsr) description bit # name description 31:7 reserved reserved. read-only, writes have no effect. 6 stable clock input stable. this bit indicates if the clock input has stabilized. 0 ? clock input not yet stable. clock counter is not finished counting (default). 1 ? clock input stable. 5:4 reserved reserved. read-only, writes have no effect. 3 pllrst asserts reset to pll 0 ? pll reset released. 1 ? pll reset asserted (default). 2 reserved reserved. the user must write a ?0? to this bit. 1 pllpwrdn select pll power down 0 ? pll operational (default). 1 ? pll placed in power-down state. 0 pllen pll mode enable 0 ? bypass mode (default). pll disabled. divider d0 and pll are bypassed. sysclk1/sysclk2/sysclk3 are divided down directly from input reference clock. 1 ? pll enabled. divider d0 and pll are not bypassed. sysclk1/sysclk2/sysclk3 are divided down from pll output.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 77 post office box 1443 ? houston, texas 77251 ? 1443 pll and pll controller (continued) table 38. pll multiplier control register (pllm) [0x01b7 c110] 31 28 27 24 23 20 19 16 reserved r ? 0 15 12 11 87 6543 21 0 reserved pllm r ? 0 r/w ? 0 0111 legend: r = read only, r/w = read/write; -n = value after reset table 39. pll multiplier control register (pllm) description bit # name description 31:5 reserved reserved. read-only, writes have no effect. 4:0 pllm pll multiply mode [default is x7 (0 0111)]. 00000 = reserved 10000 = x16 00001 = reserved 10001 = x17 00010 = reserved 10010 = x18 00011 = reserved 10011 = x19 00100 = x4 10100 = x20 00101 = x5 10101 = x21 00110 = x6 10110 = x22 00111 = x7 10111 = x23 01000 = x8 11000 = x24 01001 = x9 11001 = x25 01010 = x10 11010 = reserved 01011 = x11 11011 = reserved 01100 = x12 11100 = reserved 01101 = x13 11101 = reserved 01110 = x14 11110 = reserved 01111 = x15 11111 = reserved pllm select values 00000 through 00011 and 11010 through 11111 are not supported.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 78 post office box 1443 ? houston, texas 77251 ? 1443 pll and pll controller (continued) table 40. pll wrapper divider x registers (plldiv0, plldiv1, plldiv2, and plldiv3) [0x01b7 c114, 0x01b7 c118, 0x01b7 c11c, and 0x01b7 c120, respectively] 31 28 27 24 23 20 19 16 reserved r ? 0 15 14 12 11 87 54 3 21 0 dxen reserved plldivx r/w ? 1r ? 0 r/w ? x xxxx ? legend: r = read only, r/w = read/write; -n = value after reset ? default values for the plldiv0, plldiv1, plldiv2, and plldiv3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001), respectively. caution: d1 and d2 should never be disabled. d3 should only be disabled if eclkin is used. table 41. pll wrapper divider x registers (prescaler divider d0 and post-scaler dividers d1, d2, and d3) description ? bit # name description 31:16 reserved reserved. read-only, writes have no effect. 15 dxen divider dx enable (where x denotes 0 through 3). 0 ? divider x disabled. no clock output. 1 ? divider x enabled (default). these divider-enable bits are device-specific and must be set to 1 to enable. 14:5 reserved reserved. read-only, writes have no effect. 4:0 plldivx pll divider ratio [default values for the plldiv0, plldiv1, plldiv2, and plldiv3 bits are /1, /1, /2, and /2, respectively]. 00000 = /1 10000 = /17 00001 = /2 10001 = /18 00010 = /3 10010 = /19 00011 = /4 10011 = /20 00100 = /5 10100 = /21 00101 = /6 10101 = /22 00110 = /7 10110 = /23 00111 = /8 10111 = /24 01000 = /9 11000 = /25 01001 = /10 11001 = /26 01010 = /11 11010 = /27 01011 = /12 11011 = /28 01100 = /13 11100 = /29 01101 = /14 11101 = /30 01110 = /15 11110 = /31 01111 = /16 11111 = /32 ? note that sysclk2 must run at half the rate of sysclk1. therefore, the divider ratio of d2 must be two times slower than d1. for example, if d1 is set to /2, then d2 must be set to /4.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 79 post office box 1443 ? houston, texas 77251 ? 1443 pll and pll controller (continued) table 42. oscillator divider 1 register (oscdiv1) [0x01b7 c124] 31 28 27 24 23 20 19 16 reserved r ? 0 15 14 12 11 87 54 3 21 0 od1en reserved oscdiv1 r/w ? 1r ? 0 r/w ? 0 0111 legend: r = read only, r/w = read/write; -n = value after reset the oscdiv1 register controls the oscillator divider 1 for clkout3. the clkout3 signal does not go through the pll path. table 43. oscillator divider 1 register (oscdiv1) description bit # name description 31:16 reserved reserved. read-only, writes have no effect. 15 od1en oscillator divider 1 enable. 0 ? oscillator divider 1 disabled. 1 ? oscillator divider 1 enabled (default). 14:5 reserved reserved. read-only, writes have no effect. 4:0 oscdiv1 oscillator divider 1 ratio [default is /8 (0 0111)]. 00000 = /1 10000 = /17 00001 = /2 10001 = /18 00010 = /3 10010 = /19 00011 = /4 10011 = /20 00100 = /5 10100 = /21 00101 = /6 10101 = /22 00110 = /7 10110 = /23 00111 = /8 10111 = /24 01000 = /9 11000 = /25 01001 = /10 11001 = /26 01010 = /11 11010 = /27 01011 = /12 11011 = /28 01100 = /13 11100 = /29 01101 = /14 11101 = /30 01110 = /15 11110 = /31 01111 = /16 11111 = /32
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 80 post office box 1443 ? houston, texas 77251 ? 1443 multichannel audio serial port (mcasp) peripherals the tms320c6713 device includes two multi-channel audio serial port (mcasp) interface peripherals (mcasp1 and mcasp0). the mcasp is a serial port optimized for the needs of multi-channel audio applications. with two mcasp peripherals, the tms320c6713 device is capable of supporting two completely independent audio zones simultaneously. each mcasp consists of a transmit and receive section. these sections can operate completely independently with dif ferent data formats, separate master clocks, bit clocks, and frame syncs or alternative ly, the transmit and receive sections may be synchronized. each mcasp module also includes a pool of 16 shift registers that may be configured to operate as either transmit data, receive data, or general-purpose i/o (gpio). the transmit section of the mcasp can transmit data in either a time-division-multiplexed (tdm) synchronous serial format or in a digital audio interface (dit) format where the bit stream is encoded for s/pdif, aes-3, iec-60958, cp-430 transmission. the receive section of the mcasp supports the tdm synchronous serial format. each mcasp can support one transmit data format (either a tdm format or dit format) and one receive format at a time. all transmit shift registers use the same format and all receive shift registers use the same format. however, the transmit and receive formats need not be the same. both the transmit and receive sections of the mcasp also support burst mode which is useful for non-audio data (for example, passing control information between two dsps). the mcasp peripherals have additional capability for flexible clock generation, and error detection/handling, as well as error management. mcasp block diagram figure 15 illustrates the major blocks along with external signals of the tms320c6713 mcasp1 and mcasp0 peripherals; and shows the 8 serial data [axr] pins for each mcasp. each mcasp also includes full general-purpose i/o (gpio) control, so any pins not needed for serial transfers can be used for general-purpose i/o.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 81 post office box 1443 ? houston, texas 77251 ? 1443 multichannel audio serial port (mcasp) peripherals (continued) receive clock generator ahclkr0 aclkr0 clock check transmit generator clock transmit aclkx0 ahclkx0 dit ram transmit generator frame sync afsx0 detect error receive frame sync generator formatter transmit data amute0 amutein0 afsr0 serializer 0 serializer 1 serializer 3 serializer 2 serializer 6 serializer 7 serializer 5 serializer 4 (high- frequency) receive clock check (high- frequency) receive formatter data formatter data receive serializer 4 serializer 3 serializer 7 serializer 6 serializer 5 serializer 0 serializer 1 frame sync generator receive frame sync generator transmit transmit generator receive generator serializer 2 error transmit formatter data clock check frequency) (high- receive detect frequency) clock check (high- transmit ram dit amute1 afsr1 aclkr1 amutein1 ahclkr1 clock afsx1 aclkx1 ahclkx1 clock axr1[0] axr1[1] axr1[3] axr1[2] axr1[6] axr1[7] axr1[5] axr1[4] mcasp0 mcasp1 dma transmit dma transmit dma receive dma receive individually programmable tx/rx/gpio individually programmable tx/rx/gpio control gpio control gpio axr0[0] axr0[1] axr0[3] axr0[2] axr0[6] axr0[7] axr0[5] axr0[4] figure 15. mcasp0 and mcasp1 configuration
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 82 post office box 1443 ? houston, texas 77251 ? 1443 multichannel audio serial port (mcasp) peripherals (continued) multichannel time division multiplexed (tdm) synchronous transfer mode the mcasp supports a multichannel, time-division-multiplexed (tdm) synchronous transfer mode for both transmit and receive. within this transfer mode, a wide variety of serial data formats are supported, including formats compatible with devices using the inter-integrated sound (iis) protocol. tdm synchronous transfer mode is typically used when communicating between integrated circuits such as between a dsp and one or more adc, dac, codec, or s/pdif receiver devices. in multichannel applications, it is typical to find several devices operating synchronized with each other. for example, to provide six analog outputs, three stereo dac devices would be driven with the same bit clock and frame sync, but each stereo dac would use a different mcasp serial data pin carrying stereo data (2 tdm time slots, left and right). the tdm synchronous serial transfer mode utilizes several control signals and one or more serial data signals: a bit clock signal (aclkx for transmit, acklr for receive) a frame sync signal (afsx for transmit, afsr for receive) an (optional) high frequency master clock (ahclkx for transmit, ahclkr for receive) from which the bit clock is derived one or more serial data pins (axr for transmit and for receive). except for the optional high-frequency master clock, all of the signals in the tdm synchronous serial transfer mode protocol are synchronous to the bit clocks (aclkx and aclkr). in the tdm synchronous transfer mode, the mcasp continually transmits and receives data periodically (since audio adcs and dacs operate at a fixed-data rate). the data is organized into frames, and the beginning of a frame is marked by a frame sync pulse on the afsx, afsr pin. in a typical audio system, one frame is transferred per sample period. to support multiple channels, the choices are to either include more time slots per frame (and therefore operate with a higher bit clock) or to keep the bit clock period constant and use additional data pins to transfer the same number of channels. for example, a particular six-channel dac might require three mcasp serial data pins; transferring two channels of data on each serial data pin during each sample period (frame). another similar dac may be designed to use only a single mcasp serial data pin, but clocked three times faster and transferring six channels of data per sample period. the mcasp is flexible enough to support either type of dac but a transmitter cannot be configured to do both at the same time. for multiprocessor applications, the mcasp supports any number of time slots per frame (between 2 and 32), and includes the ability to ?disable? transfers during specific time slots. in addition, to support of s/pdif, aes-3, iec-60958, cp-430 receivers chips whose natural block (mcasp frame) size is 384 samples; the mcasp receiver supports a 384 time slot mode. the advantage to using the 384 time slot mode is that interrupts may be generated synchronous to the s/pdif, aes-3, iec-60958, cp-430 receivers, for example the ?last slot? interrupt. burst transfer mode the mcasp also supports a burst transfer mode, which is useful for non-audio data (for example, passing control in formation between two dsps). burst transfer mode uses a synchronous serial format similar to tdm, except the frame sync is generated for each data word transferred. in addition, frame sync generation is not periodic or time-driven as in tdm mode but rather data-driven.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 83 post office box 1443 ? houston, texas 77251 ? 1443 multichannel audio serial port (mcasp) peripherals (continued) supported bit stream formats for tdm and burst transfer modes the serial data pins support a wide variety of formats. in the tdm and burst synchronous modes, the data may be transmitted / received with the following options: time slots per frame: 1 (burst/data driven), or 2,3...32 (tdm/time-driven). time slot size: 8, 12, 16, 20, 24, 28, 32 bits per time slot data size: 8, 12, 16, 20, 24, 28, 32 bits (must be less than or equal to time slot) data alignment within time slot: left- or right-justified bit order: msb or lsb first. unused bits in time slot: padded with 0, 1 or extended with value of another bit. time slot delay from frame sync: 0,1, or 2 bit delay the data format can be programmed independently for transmit and receive, and for mcasp0 vs. mcasp1. in addition, the mcasp can automatically re-align the data as processed natively by the dsp (any format on a nibble boundary) adjusting the data in hardware to any of the supported serial bit stream formats (tdm, burst, and dit modes). this reduces the amount of bit manipulation that the dsp must perform and simplifies software architecture. digital audio interface transmitter (dit) transfer mode (transmitter only) the mcasp transmit section may also be configured in digital audio interface transmitter (dit) mode where it outputs data formatted for transmission over an s/pdif, aes-3, iec-60958, or cp-430 standard link. these standards encode the serial data such that the equivalent of ?clock? and ?frame sync? are embedded within the data stream. dit transfer mode is used as an interconnect between audio components and can transfer multichannel digital audio data over a single optical or coaxial cable. from an internal dsp standpoint, the mcasp operation in dit transfer mode is similar to the two time slot tdm mode, but the data transmitted is output as a bi-phase mark encoded bit stream with preamble, channel status, user data, validity, and parity automatically stuffed into the bit stream by the mcasp module. the mcasp includes separate validity bits for even/odd subframes and two 384-bit register file modules to hold channel status and user data bits. dit mode requires at minimum: one serial data pin (if the auxclk is used as the reference [see the pll and clock generator logic figure 14]) or one serial data pin plus either the ahclkx or aclkx pin (if an external clock is needed). if additional serial data pins are used, each mcasp may be used to transmit multiple encoded bit streams (one per pin). however, the bit streams will all be synchronized to the same clock and the user data, channel status, and validity information carried by each bit stream will be the same for all bit streams transmitted by the same mcasp module. the mcasp can also automatically re-align the data as processed by the dsp (any format on a nibble boundary) in dit mode; reducing the amount of bit manipulation that the dsp must perform and simplifies software architecture.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 84 post office box 1443 ? houston, texas 77251 ? 1443 multichannel audio serial port (mcasp) peripherals (continued) mcasp flexible clock generators the mcasp transmit and receive clock generators are identical. each clock generator can accept a high-frequency master clock input (on the ahclkx and ahclkr pins). the transmit and receive bit clocks (on the aclkx and aclkr pins) can also be sourced externally or can be sourced internally by dividing down the high-frequency master clock input (programmable factor /1, /2, /3, ... /4096). the polarity of each bit clock is individually programmable. the frame sync pins are afsx (transmit) and afsr (receive). a typical usage for these pins is to carry the left-right clock (lrclk) signal when transmitting and receiving stereo data. the frame sync signals are individually programmable for either internal or external generation, either bit or slot length, and either rising or falling edge polarity. some examples of the things that a system designer can use the mcasp clocking flexibility for are: input a high-frequency master clock (for example, 512f s of the receiver), receive with an internally generated bit clock ratio of /8, while transmitting with an internally generated bit clock ratio of /4 or /2. [an example application would be to receive data from a dvd at 48 khz but output up-sampled or decoded audio at 96 khz or 192 khz.] transmit/receive data based one sample rate (for example, 44.1 khz) using mcasp0 while transmitting and receiving at a different sample rate (for example, 48 khz) on mcasp1. use the dsp?s on-board auxclk to supply the system clock when the input source is an a/d converter. mcasp error handling and management to support the design of a robust audio system, the mcasp module includes error-checking capability for the serial protocol, data underrun, and data overrun. in addition, each mcasp includes a timer that continually measures the high-frequency master clock every 32-sysclk2 clock cycles. the timer value can be read to get a measurement of the high-frequency master clock frequency and has a min-max range setting that can raise an error flag if the high-frequency master clock goes out of a specified range. the user would read the high-frequency transmit master clock measurement (ahclkx0 or ahclkx1) by reading the xcnt field of the xclkchk register and the user would read the high-frequency receive master clock measurement (ahclkr0 or ahclkr1) by reading the rcnt field of the rclkchk register. upon the detection of any one or more of the above errors (software selectable), or the assertion of the amute_in pin, the amute output pin may be asserted to a high or low level (selectable) to immediately mute the audio output. in addition, an interrupt may be generated if enabled based on any one or more of the error sources. mcasp interrupts and edma events the mcasp transmitter and receiver sections each generate an event on every time slot. this event can be serviced by an interrupt or by the edma controller. when using interrupts to service the mcasp, each shift register buffer has a unique address in the mcasp registers space (see table 3). when using the edma to service the mcasp, the mcasp data port space in table 3 is accessed. in this case, the address least-significant bits are ignored. writes to any address in this range access the transmitting buf fers in order from lowest (serializer 0) to highest (serializer 15), skipping over disabled and receiving serializers. likewise, reads from any address in this space access the receiving buffers in the same order but skip over disabled and transmitting buffers.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 85 post office box 1443 ? houston, texas 77251 ? 1443 i2c having two i2c modules on the tms320c6713 simplifies system architecture, since one module may be used by the dsp to control local peripherals ics (dacs, adcs, etc.) while the other may be used to communicate with other controllers in a system or to implement a user interface. the tms320c6713 also includes two i2c serial ports for control purposes. each i2c port supports: compatible with philips i 2 c specification revision 2.1 (january 2000) fast mode up to 400 kbps (no fail-safe i/o buffers) noise filter to remove noise 50 ns or less seven- and ten-bit device addressing modes master (transmit/receive) and slave (transmit/receive) functionality events: dma, interrupt, or polling slew-rate limited open-drain output buffers figure 16 is a block diagram of the i2cx module. clock prescale i2cpscx sysclk2 from pll clock generator i2cclkhx generator bit clock i2cclklx noise filter i2c clock scl i2cxsrx i2cdxrx transmit transmit shift transmit buffer i2cdrrx shift i2crsrx receive buffer receive receive filter sda i2c data noise i2coarx i2csarx slave address control address own i2cmdrx i2ccntx mode data count source interrupt interrupt status i2cisrcx i2cstrx enable interrupt i2cierx interrupt/dma i2cx module note a: shading denotes control/status registers. figure 16. i2cx module block diagram
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 86 post office box 1443 ? houston, texas 77251 ? 1443 general-purpose input/output (gpio) to use the gp[15:0] software-configurable gpio pins, the gpxen bits in the gp enable (gpen) register and the gpxdir bits in the gp direction (gpdir) register must be properly configured. gpxen = 1 gp[x] pin is enabled gpxdir = 0 gp[x] pin is an input gpxdir = 1 gp[x] pin is an output where ?x? represents one of the 15 through 0 gpio pins figure 17 shows the gpio enable bits in the gpen register for the c6713 device. to use any of the gpx pins as general-purpose input/output functions, the corresponding gpxen bit must be set to ?1? (enabled). default values are device-specific, so refer to figure 17 for the c6713 default configuration. 31 24 23 16 reserved r-0 15 14 13 12 11 10 9 8 7 6543 210 gp15 en gp14 en gp13 en gp12 en gp11 en gp10 en gp9 en gp8 en gp7 en gp6 en gp5 en gp4 en gp3 en gp2 en gp1 en gp0 en r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 legend: r/w = readable/w riteable; - n = value after reset, -x = undefined value after reset figure 17. gpio enable register (gpen) [hex address: 01b0 0000] figure 18 shows the gpio direction bits in the gpdir register. this register determines if a given gpio pin is an input or an output providing the corresponding gpxen bit is enabled (set to ?1?) in the gpen register. by default, all the gpio pins are configured as input pins. 31 24 23 16 reserved r-0 15 14 13 12 11 10 9 8 7 6543 210 gp15 dir gp14 dir gp13 dir gp12 dir gp11 dir gp10 dir gp9 dir gp8 dir gp7 dir gp6 dir gp5 dir gp4 dir gp3 dir gp2 dir gp1 dir gp0 dir r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 legend: r/w = readable/w riteable; - n = value after reset, -x = undefined value after reset figure 18. gpio direction register (gpdir) [hex address: 01b0 0004] for more detailed information on general-purpose inputs/outputs (gpios), see the general purpose input/output chapter of the tms320c6000 peripherals reference guide (literature number spru190).
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 87 post office box 1443 ? houston, texas 77251 ? 1443 power-supply sequencing ti dsps do not require specific power sequencing between the core supply and the i/o supply. however, systems should be designed to ensure that neither supply is powered up for extended periods of time ( > 1 second) if the other supply is below the proper operating voltage. system-level design considerations system-level design considerations, such as bus contention, may require supply sequencing to be implemented. in this case, the core supply should be powered up prior to (and powered down after), the i/o buffers. this is to ensure that the i/o buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. power-supply design considerations a dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and i/o power up. a schottky diode can also be used to tie the core rail to the i/o rail (see figure 19). dv dd cv dd v ss c6000 dsp schottky diode i/o supply core supply gnd figure 19. schottky diode diagram core and i/o supply voltage regulators should be located close to the dsp (or dsp array) to minimize inductance and resistance in the power delivery path. additionally, when designing for high-performance applications utilizing the c6000 ? platform of dsps, the pc board should include separate power planes for core, i/o, and ground, all bypassed with high-quality low-esl/esr capacitors. power-supply decoupling in order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the dsp. assuming 0603 caps, the user should be able to fit a total of 60 caps ? 30 for the core supply and 30 for the i/o supply. these caps need to be close (no more than 1.25 cm maximum distance) to the dsp to be effective. physically smaller caps are better, such as 0402, but the size needs to be evaluated from a yield/manufacturing point-of-view. parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. as with the selection of any component, verification of capacitor availability over the product?s production lifetime needs to be considered.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 88 post office box 1443 ? houston, texas 77251 ? 1443 ieee 1149.1 jtag compatibility statement the tms320c6713 dsp requires that both trst and reset resets be asserted upon power up to be properly initialized. while reset initializes the dsp core, trst initializes the dsp?s emulation logic. both resets are required for proper operation. while both trst and reset need to be asserted upon power up, only reset needs to be released for the dsp to boot properly. trst may be asserted indefinitely for normal operation, keeping the jtag port interface and dsp?s emulation logic in the reset state. trst only needs to be released when it is necessary to use a jtag controller to debug the dsp or exercise the dsp?s boundary scan functionality. for maximum reliability, the tms320c6713 dsp includes an internal pulldown (ipd) on the trst pin to ensure that trst will always be asserted upon power up and the dsp?s internal emulation logic will always be properly initialized. jtag controllers from t exas instruments actively drive trst high. however, some third-party jt ag controllers may not drive trst high but expect the use of an external pullup resistor on trst . when using this type of jtag controller, assert trst to initialize the dsp after powerup and externally drive trst high before attempting any emulation or boundary scan operations. following the release of reset , the low-to-high transition of trst must be ?seen? to latch the state of emu1 and emu0. the emu[1:0] pins configure the device for either boundary scan mode or emulation mode. for more detailed information, see the terminal functions section of this data sheet.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 89 post office box 1443 ? houston, texas 77251 ? 1443 emif device speed the maximum emif speed on the c6713 device is 100 mhz. ti recommends utilizing i/o buffer information specification (ibis) to analyze all ac timings to determine if the maximum emif speed is achievable for a given board layout. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spra839). for ease of design evaluation, table 44 contains ibis simulation results showing the maximum emif-sdram interface speeds for the given example boards (type) and sdram speed grades. timing analysis should be performed to verify that all ac timings are met for the specified board layout. other configurations are also possible, but again, timing analysis must be done to verify proper ac timings. to maintain signal integrity, serial termination resistors should be inserted into all emif output signal lines (see the terminal functions table for the emif output signals). table 44. c6713 example boards and maximum emif speed board configuration maximum achievable type emif interface components board trace sdram speed grade maximum achievable emif-sdram interface speed 143 mhz 32-bit sdram ( ? 7) 100 mhz 1 - load one bank of one 1 to 3-inch traces with proper 166 mhz 32-bit sdram ( ? 6) for short traces, sdram data output hold time on these 1 - l oa d short traces o ne b an k o f one 32-bit sdram pp termination resistors; trace impedance ~ 50 ? 183 mhz 32-bit sdram ( ? 55) output hold time on these sdram speed grades cannot meet emif inp t hold time trace impedance ~ 50 ? ? 5) meet emif input hold time requirement (see note 1). 125 mhz 16-bit sdram ( ? 8e) 100 mhz 2l d o bk f t 1.2 to 3 inches from emif to h l d i h 133 mhz 16-bit sdram ( ? 75) 100 mhz 2-loads short traces one bank of two 16 - bit sdrams each load, with proper termination resistors; 143 mhz 16-bit sdram ( ? 7e) 100 mhz sh or t t races 16 - bit sdram s t erm i na ti on res i s t ors; trace im p edance ~ 78 ? 167 mhz 16-bit sdram ( ? 6a) 100 mhz trace impedance ~ 78 ? ? 6) 100 mhz 125 mhz 16-bit sdram ( ? 8e) for short traces, emif cannot meet sdram input hold requirement (see note 1). 3l d one bank of two 1.2 to 3 inches from emif to h l d i h 133 mhz 16-bit sdram ( ? 75) 100 mhz 3-loads short traces one bank of two 32-bit sdrams each load, with proper termination resistors; 143 mhz 16-bit sdram ( ? 7e) 100 mhz sh or t t races 32 bit sdrams one bank of buffer t erm i na ti on res i s t ors; trace im p edance ~ 78 ? 167 mhz 16-bit sdram ( ? 6a) 100 mhz trace impedance ~ 78 ? ? 6) for short traces, emif cannot meet sdram input hold requirement (see note 1). 143 mhz 32-bit sdram ( ? 7) 83 mhz one bank of one 32 bit sdram 166 mhz 32-bit sdram ( ? 6) 83 mhz 3-loads l t 32-bit sdram o n e ba nk o f o n e 4 to 7 inches from emif; t i d 63 ? ? 55) 83 mhz long traces one bank of one 32-bit sbsram one bank of buffer trace impedance ~ 63 ? 200 mhz 32-bit sdram ( ? 5) sdram data output hold time cannot meet emif input hold requirement (see note 1). note 1: results are based on ibis simulations for the given example boards ( type ). timing analysis should be performed to determine if timing requirements can be met for the particular system.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 90 post office box 1443 ? houston, texas 77251 ? 1443 bootmode the c6713 device resets using the active-low signal reset and the internal reset signal. while reset is low, the internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset state. refer to reset timing for reset timing characteristics and states of device pins during reset. the release of the internal reset signal (see the reset phase 3 discussion in the reset timing section of this data sheet) starts the processor running with the prescribed device configuration and boot mode. the c6713 has three types of boot modes: host boot if host boot is selected, upon release of internal reset, the cpu is internally ?stalled? while the remainder of the device is released. during this period, an external host can initialize the cpu?s memory space as necessary through the host interface, including internal configuration registers, such as those that control the emif or other peripherals. once the host is finished with all necessary initialization, it must set the dspint bit in the hpic register to complete the boot process. this transition causes the boot configuration logic to bring the cpu out of the ?stalled? state. the cpu then begins execution from address 0. the dspint condition is not latched by the cpu, because it occurs while the cpu is still internally ?stalled?. also, dspint brings the cpu out of the ?stalled? state only if the host boot process is selected. all memory may be written to and read by the host. this allows for the host to verify what it sends to the dsp if required. after the cpu is out of the ?stalled? state , the cpu needs to clear the dspint, otherwise, no more dspints can be received. emulation boot emulation boot mode is a variation of host boot. in this mode, it is not necessary for a host to load code or to set dspint to release the cpu from the ?stalled? state. instead, the emulator will set dspint if it has not been previously set so that the cpu can begin executing code from address 0. prior to beginning execution, the emulator sets a breakpoint at address 0. this prevents the execution of invalid code by halting the cpu prior to executing the first instruction. emulation boot is a good tool in the debug phase of development. emif boot (using default rom timings) upon the release of internal reset, the 1k-byte rom code located in the beginning of ce1 is copied to address 0 by the edma using the default rom timings, while the cpu is internally ?stalled?. the data should be stored in the endian format that the system is using. the boot process also lets you choose the width of the rom. in this case, the emif automatically assembles consecutive 8-bit bytes or 16-bit half-words to form the 32-bit instruction words to be copied. the transfer is automatically done by the edma as a single-frame block transfer from the rom to address 0. after completion of the block transfer, the cpu is released from the ?stalled? state and start running from address 0.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 91 post office box 1443 ? houston, texas 77251 ? 1443 absolute maximum ratings over operating case temperature range (unless otherwise noted) ? supply voltage range, cv dd (see note 2) ? 0.3 v to 1.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, dv dd (see note 2) ? 0.3 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range ? 0.3 v to dv dd + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range ? 0.3 v to dv dd + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating case temperature ranges, t c : (default) 0 c to 90 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a version) [gdpa-200 and pypa-167] ? 40 c to105 c . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 2: all voltage values are with respect to v ss . recommended operating conditions ? min nom max unit cv supply voltage core referenced to v pyp packages only 1.14 1.2 1.32 v cv dd supply voltage, core referenced to v ss gdp packages only 1.2 1.26 1.32 v dv dd supply voltage, i/o referenced to v ss 3.13 3.3 3.47 v v (c ? d) maximum supply voltage difference cv dd ? dv dd 1.32 v v (d ? c) maximum supply voltage difference dv dd ? cv dd 2.75 v v high level input voltage all signals except clks1/scl1, dr1/sda1, scl0, sda0, and reset 2 v v ih high-level input voltage clks1/scl1, dr1/sda1, scl0, sda0, and reset 2 v v low level input voltage all signals except clks1/scl1, dr1/sda1, scl0, sda0, and reset 0.8 v v il low-level input voltage clks1/scl1, dr1/sda1, scl0, sda0, and reset 0.3*dv dd v i oh high-level output current all signals except eclkout, clkout2, clks1/scl1, dr1/sda1, scl0, and sda0 ? 8 ma eclkout and clkout2 ? 16 ma all signals except eclkout, clkout2, clks1/scl1, dr1/sda1, scl0, and sda0 8 ma i ol low-level output current eclkout and clkout2 16 ma clks1/scl1, dr1/sda1, scl0, and sda0 3 ma t operating case temperature default 0 90 c t c operating case temperature a version (gdpa-200 and pypa-167) ?40 105 c ? the core supply should be powered up prior to (and powered down after), the i/o supply. systems should be designed to ensure th at neither supply is powered up for an extended period of time if the other supply is below the proper operating voltage. refers to dc (or steady state) currents only, actual switching currents are higher. for more details, see the device-specific i bis models.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 92 post office box 1443 ? houston, texas 77251 ? 1443 electrical characteristics over recommended ranges of supply voltage and operating case temperature ? (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage all signals except scl1, sda1, scl0, and sda0 i oh =max 2.4 v v o l low-level output lt all signals except scl1, sda1, scl0, and sda0 i ol = max 0.4 v v ol voltage scl1, sda1, scl0, and sda0 i ol = max 0.4 v i i input current all signals except scl1, sda1, scl0, and sda0 v i = v ss to dv dd 170 ua i i input current scl1, sda1, scl0, and sda0 v i = v ss to dv dd 10 ua i o z off-state output t all signals except scl1, sda1, scl0, and sda0 v o = dv dd or 0 v 170 ua i oz current scl1, sda1, scl0, and sda0 v o = dv dd or 0 v 10 ua gdp, cv dd = 1.26 v, cpu clock = 225 mhz 625 ma i core supply current ? gdpa, cv dd = 1.26 v, cpu clock = 200 mhz 560 ma i dd2v core supply current ? pyp, cv dd = 1.2 v, cpu clock = 200 mhz 565 ma pypa, cv dd = 1.2 v, cpu clock = 167 mhz 480 ma i dd3v i/o supply current ? c6713, dv dd = 3.3 v, emif speed = 100 mhz 75 ma c i input capacitance 7 pf c o output capacitance 7 pf ? for test conditions shown as min, max, or nom, use the appropriate value specified in the recommended operating conditions tabl e. ? measured with average activity (50% high/50% low power) at 25 c case temperature and 100-mhz emif. this model represents a device performing high-dsp-activity operations 50% of the time, and the remainder performing low-dsp-activity operations. the high/low -dsp-activity models are defined as follows: high-dsp-activity model: cpu: 8 instructions/cycle with 2 lddw instructions [l1 data memory: 128 bits/cycle via lddw instructions; l1 program memory: 256 bits/cycle; l2/emif edma: 50% writes, 50% reads to/from sdram (50% bit-switching)] mcbsp: 2 channels at e1 rate timers: 2 timers at maximum rate low-dsp-activity model: cpu: 2 instructions/cycle with 1 ldh instruction [l1 data memory: 16 bits/cycle; l1 program memory: 256 bits per 4 cycles; l2/emif edma: none] mcbsp: 2 channels at e1 rate timers: 2 timers at maximum rate the actual current draw is highly application-dependent. for more details on core and i/o activity, refer to the tms320c6713/12c/11c power consumption summary application report (literature number spra889).
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 93 post office box 1443 ? houston, texas 77251 ? 1443 parameter measurement information transmission line 4.0 pf 1.85 pf z0 = 50 (see note) tester pin electronics data sheet timing reference point output under test note: the data sheet provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmiss ion line effects must be taken into account. a transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line eff ect. the transmission line is intended as a load only. it is not necessary to add or subtract the transmission line delay (2 ns or l onger) from the data sheet timings. 42 3.5 nh device pin (see note) input requirements in this data sheet are tested with an input slew rate of < 4 volts per nanosecond (4 v/ns) at the device pin . figure 20. test load circuit for ac timing measurements signal transition levels all input and output timing parameters are referenced to 1.5 v for both ?0? and ?1? logic levels. v ref = 1.5 v figure 21. input and output voltage reference levels for ac timing measurements all rise and fall transition timing parameters are referenced to v il max and v ih min for input clocks, v ol max and v oh min for output clocks. v ref = v il max (or v ol max) v ref = v ih min (or v oh min) figure 22. rise and fall transition time voltage reference levels
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 94 post office box 1443 ? houston, texas 77251 ? 1443 parameter measurement information (continued) timing parameters and board routing analysis the timing parameter values specified in this data sheet do not include delays by board routings. as a good board design practice, such delays must always be taken into account. timing values may be adjusted by increasing/decreasing such delays. ti recommends utilizing the available i/o buffer information specification (ibis) models to analyze the timing characteristics correctly. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spra839). if needed, external logic hardware such as buffers may be used to compensate any timing differences. for inputs, timing is most impacted by the round-trip propagation delay from the dsp to the external device and from the external device to the dsp. this round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see table 45 and figure 23). figure 23 represents a general transfer between the dsp and an external device. the figure also represents board route delays and how they are perceived by the dsp and the external device.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 95 post office box 1443 ? houston, texas 77251 ? 1443 parameter measurement information (continued) table 45. board-level timings example (see figure 23) no. description 1 clock route delay 2 minimum dsp hold time 3 minimum dsp setup time 4 external device hold time requirement 5 external device setup time requirement 6 control signal route delay 7 external device hold time 8 external device access time 9 dsp hold time requirement 10 dsp setup time requirement 11 data route delay 1 2 3 4 5 6 7 8 10 11 eclkout (output from dsp) eclkout (input to external device) control signals ? (output from dsp) control signals (input to external device) data signals ? (output from external device) data signals ? (input to dsp) 9 ? control signals include data for writes. ? data signals are generated during reads from an external device. figure 23. board-level input/output timings
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 96 post office box 1443 ? houston, texas 77251 ? 1443 input and output clocks timing requirements for clkin for c6713pyp-200 and c6713gdp-225 ?? (see figure 24) pyp ? 200 gdp ? 225 no. pll mode (pllen = 1) bypass mode (pllen = 0) pll mode (pllen = 1) bypass mode (pllen = 0) unit min max min max min max min max 1 t c(clkin) cycle time, clkin 5 83.3 5 4.4 83.3 4.4 ns 2 t w(clkinh) pulse duration, clkin high 0.4c 0.4c 0.4c 0.4c ns 3 t w(clkinl) pulse duration, clkin low 0.4c 0.4c 0.4c 0.4c ns 4 t t(clkin) transition time, clkin 5 5 5 5 ns ? the reference points for the rise and fall transitions are measured at v il max and v ih min. ? c = clkin cycle time in nanoseconds (ns). for example, when clkin frequency is 40 mhz, use c = 25 ns. see the pll and pll controller section of this data sheet. timing requirements for clkin for c6713pypa-167 and c6713gdpa-200 ?? (see figure 24) pypa ? 167 gdpa ? 200 no. pll mode (pllen = 1) bypass mode (pllen = 0) pll mode (pllen = 1) bypass mode (pllen = 0) unit min max min max min max min max 1 t c(clkin) cycle time, clkin 6 83.3 6 5 83.3 5 ns 2 t w(clkinh) pulse duration, clkin high 0.4c 0.4c 0.4c 0.4c ns 3 t w(clkinl) pulse duration, clkin low 0.4c 0.4c 0.4c 0.4c ns 4 t t(clkin) transition time, clkin 5 5 5 5 ns ? the reference points for the rise and fall transitions are measured at v il max and v ih min. ? c = clkin cycle time in nanoseconds (ns). for example, when clkin frequency is 40 mhz, use c = 25 ns. see the pll and pll controller section of this data sheet. clkin 1 2 3 4 4 figure 24. clkin timings
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 97 post office box 1443 ? houston, texas 77251 ? 1443 input and output clocks (continued) switching characteristics over recommended operating conditions for clkout2 ?? (see figure 25) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t c(cko2) cycle time, clkout2 c2 ? 0.8 c2 + 0.8 ns 2 t w(cko2h) pulse duration, clkout2 high (c2/2) ? 0.8 (c2/2) + 0.8 ns 3 t w(cko2l) pulse duration, clkout2 low (c2/2) ? 0.8 (c2/2) + 0.8 ns 4 t t(cko2) transition time, clkout2 2 ns ? the reference points for the rise and fall transitions are measured at v ol max and v oh min. ? c2 = clkout2 period in ns. clkout2 period is determined by the pll controller output sysclk2 period, which must be set to cpu period divide-by-2. clkout2 1 2 3 4 4 figure 25. clkout2 timings switching characteristics over recommended operating conditions for clkout3 ? (see figure 26) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t c(cko3) cycle time, clkout3 c3 ? 0.6 c3 + 0.6 ns 2 t w(cko3h) pulse duration, clkout3 high (c3/2) ? 0.6 (c3/2) + 0.6 ns 3 t w(cko3l) pulse duration, clkout3 low (c3/2) ? 0.6 (c3/2) + 0.6 ns 4 t t(cko3) transition time, clkout3 2 ns 5 t d(clkinh-cko3v) delay time, clkin high to clkout3 valid 1.5 6.5 ns ? the reference points for the rise and fall transitions are measured at v ol max and v oh min. c3 = clkout3 period in ns. clkout3 period is a divide-down of the cpu clock, configurable via the ratio field in the plldiv3 re gister. clkin clkout3 note a: for this example, the clkout3 frequency is clkin divide-by-2. 3 1 2 4 4 5 5 figure 26. clkout3 timings
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 98 post office box 1443 ? houston, texas 77251 ? 1443 input and output clocks (continued) timing requirements for eclkin ? (see figure 27) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t c(eki) cycle time, eclkin 10 ns 2 t w(ekih) pulse duration, eclkin high 4.5 ns 3 t w(ekil) pulse duration, eclkin low 4.5 ns 4 t t(eki) transition time, eclkin 3 ns ? the reference points for the rise and fall transitions are measured at v il max and v ih min. eclkin 1 2 3 4 4 figure 27. eclkin timings switching characteristics over recommended operating conditions for eclkout ?# (see figure 28) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t c(eko) cycle time, eclkout e ? 0.9 e + 0.9 ns 2 t w(ekoh) pulse duration, eclkout high eh ? 0.9 eh + 0.9 ns 3 t w(ekol) pulse duration, eclkout low el ? 0.9 el + 0.9 ns 4 t t(eko) transition time, eclkout 2 ns 5 t d(ekih-ekoh) delay time, eclkin high to eclkout high 1 6.5 ns 6 t d(ekil-ekol) delay time, eclkin low to eclkout low 1 6.5 ns ? the reference points for the rise and fall transitions are measured at v ol max and v oh min. e = eclkin period in ns ? eh is the high period of eclkin in ns and el is the low period of eclkin in ns. 5 6 1 2 3 eclkin eclkin eclkout 4 4 figure 28. eclkout timings
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 99 post office box 1443 ? houston, texas 77251 ? 1443 asynchronous memory timing timing requirements for asynchronous memory cycles ?? (see figure 29 ? figure 30) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 3 t su(edv-areh) setup time, edx valid before are high 6.5 ns 4 t h(areh-edv) hold time, edx valid after are high 1 ns 6 t su(ardy-ekoh) setup time, ardy valid before eclkout high 3 ns 7 t h(ekoh-ardy) hold time, ardy valid after eclkout high 2.3 ns ? to ensure data setup time, simply program the strobe width wide enough. ardy is internally synchronized. the ardy signal is rec ognized in the cycle for which the setup and hold time is met. to use ardy as an asynchronous input, the pulse width of the ardy signal sh ould be wide enough (e.g., pulse width = 2e) to ensure setup and hold time is met. ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. e = eclkout period in ns switching characteristics over recommended operating conditions for asynchronous memory cycles ?? (see figure 29 ? figure 30) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t osu(selv-arel) output setup time, select signals valid to are low rs*e ? 1.7 ns 2 t oh(areh-seliv) output hold time, are high to select signals invalid rh*e ? 1.7 ns 5 t d(ekoh-arev) delay time, eclkout high to are valid 1.5 7 ns 8 t osu(selv-awel) output setup time, select signals valid to awe low ws*e ? 1.7 ns 9 t oh(aweh-seliv) output hold time, awe high to select signals invalid wh*e ? 1.7 ns 10 t d(ekoh-awev) delay time, eclkout high to awe valid 1.5 7 ns ? rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold. these parameters are programmed via the emif ce space control registers. e = eclkout period in ns ? select signals include: cex , be[3:0] , ea[21:2], aoe; and for writes, include ed[31:0].
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 100 post office box 1443 ? houston, texas 77251 ? 1443 asynchronous memory timing (continued) setup = 2 strobe = 3 not ready hold = 2 be address read data 2 1 2 1 2 1 2 1 5 4 3 ardy 77 6 6 5 eclkout cex ea[21:2] ed[31:0] aoe /sdras /ssoe ? are /sdcas /ssads ? be[3:0] awe /sdwe /sswe ? ? aoe /sdras /ssoe , are /sdcas /ssads , and awe /sdwe /sswe operate as aoe (identified under select signals), are , and awe , respectively, during asynchronous memory accesses. figure 29. asynchronous memory read timing
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 101 post office box 1443 ? houston, texas 77251 ? 1443 asynchronous memory timing (continued) setup = 2 strobe = 3 not ready hold = 2 be address write data 10 10 9 8 9 8 9 8 9 8 7 7 6 6 eclkout cex ea[21:2] ed[31:0] be[3:0] ardy aoe /sdras /ssoe ? are /sdcas /ssads ? awe /sdwe /sswe ? ? aoe /sdras /ssoe , are /sdcas /ssads , and awe /sdwe /sswe operate as aoe (identified under select signals), are , and awe , respectively, during asynchronous memory accesses. figure 30. asynchronous memory write timing
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 102 post office box 1443 ? houston, texas 77251 ? 1443 synchronous-burst memory timing timing requirements for synchronous-burst sram cycles ? (see figure 31) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 6 t su(edv-ekoh) setup time, read edx valid before eclkout high 1.5 ns 7 t h(ekoh-edv) hold time, read edx valid after eclkout high 2.5 ns ? the c6713 sbsram interface takes advantage of the internal burst counter in the sbsram. accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. all burst types can sustain continuous d ata flow. switching characteristics over recommended operating conditions for synchronous-burst sram cycles ?? (see figure 31 and figure 32) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t d(ekoh-cev) delay time, eclkout high to cex valid 1.2 7 ns 2 t d(ekoh-bev) delay time, eclkout high to bex valid 7 ns 3 t d(ekoh-beiv) delay time, eclkout high to bex invalid 1.2 ns 4 t d(ekoh-eav) delay time, eclkout high to eax valid 7 ns 5 t d(ekoh-eaiv) delay time, eclkout high to eax invalid 1.2 ns 8 t d(ekoh-adsv) delay time, eclkout high to are /sdcas /ssads valid 1.2 7 ns 9 t d(ekoh-oev) delay time, eclkout high to, aoe /sdras /ssoe valid 1.2 7 ns 10 t d(ekoh-edv) delay time, eclkout high to edx valid 7 ns 11 t d(ekoh-ediv) delay time, eclkout high to edx invalid 1.2 ns 12 t d(ekoh-wev) delay time, eclkout high to awe /sdwe /sswe valid 1.2 7 ns ? the c6713 sbsram interface takes advantage of the internal burst counter in the sbsram. accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. all burst types can sustain continuous d ata flow. ? are /sdcas /ssads , aoe /sdras /ssoe , and awe /sdwe /sswe operate as ssads , ssoe , and sswe , respectively, during sbsram accesses.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 103 post office box 1443 ? houston, texas 77251 ? 1443 synchronous-burst memory timing (continued) eclkout cex be[3:0] ea[21:2] ed[31:0] are /sdcas /ssads ? aoe /sdras /ssoe ? awe /sdwe /sswe ? be1 be2 be3 be4 ea q1 q2 q3 q4 9 1 4 5 8 8 9 6 7 3 1 2 ? are /sdcas /ssads , aoe /sdras /ssoe , and awe /sdwe /sswe operate as ssads , ssoe , and sswe , respectively, during sbsram accesses. figure 31. sbsram read timing eclkout cex be[3:0] ea[21:2] ed[31:0] are /sdcas /ssads ? aoe /sdras /ssoe ? awe /sdwe /sswe ? be1 be2 be3 be4 q1 q2 q3 q4 12 11 3 1 8 12 10 4 2 1 8 5 ea ? are /sdcas /ssads , aoe /sdras /ssoe , and awe /sdwe /sswe operate as ssads , ssoe , and sswe , respectively, during sbsram accesses. figure 32. sbsram write timing
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 104 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing timing requirements for synchronous dram cycles ? (see figure 33) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 6 t su(edv-ekoh) setup time, read edx valid before eclkout high 1.5 ns 7 t h(ekoh-edv) hold time, read edx valid after eclkout high 2.5 ns ? the c6713 sdram interface takes advantage of the internal burst counter in the sdram. accesses default to incrementing 4-word b ursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. all burst types can sustain continuous data flow. switching characteristics over recommended operating conditions for synchronous dram cycles ?? (see figure 33 ? figure 39) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t d(ekoh-cev) delay time, eclkout high to cex valid 1.5 7 ns 2 t d(ekoh-bev) delay time, eclkout high to bex valid 7 ns 3 t d(ekoh-beiv) delay time, eclkout high to bex invalid 1.5 ns 4 t d(ekoh-eav) delay time, eclkout high to eax valid 7 ns 5 t d(ekoh-eaiv) delay time, eclkout high to eax invalid 1.5 ns 8 t d(ekoh-casv) delay time, eclkout high to are /sdcas /ssads valid 1.5 7 ns 9 t d(ekoh-edv) delay time, eclkout high to edx valid 7 ns 10 t d(ekoh-ediv) delay time, eclkout high to edx invalid 1.5 ns 11 t d(ekoh-wev) delay time, eclkout high to awe /sdwe /sswe valid 1.5 7 ns 12 t d(ekoh-ras) delay time, eclkout high to, aoe /sdras /ssoe valid 1.5 7 ns ? the c6713 sdram interface takes advantage of the internal burst counter in the sdram. accesses default to incrementing 4-word b ursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. all burst types can sustain continuous data flow. ? are /sdcas /ssads , awe /sdwe /sswe , and aoe /sdras /ssoe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 105 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) eclkout cex be[3:0] ea[11:2] ed[31:0] ea12 aoe /sdras /ssoe ? are /sdcas /ssads ? awe /sdwe /sswe ? ea[21:13] be1 be2 be3 be4 bank column d1 d2 d3 d4 8 7 6 5 5 5 1 3 2 8 4 4 4 1 read ? are /sdcas /ssads , awe /sdwe /sswe , and aoe /sdras /ssoe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 33. sdram read command (cas latency 3)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 106 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) eclkout cex be[3:0] ea[11:2] ed[31:0] aoe /sdras /ssoe ? are /sdcas /ssads ? awe /sdwe /sswe ? ea12 ea[21:13] be1 be2 be3 be4 bank column d1 d2 d3 d4 11 8 9 5 5 5 2 1 11 8 9 4 4 2 1 10 3 4 write ? are /sdcas /ssads , awe /sdwe /sswe , and aoe /sdras /ssoe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 34. sdram write command
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 107 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) eclkout cex be[3:0] ea[21:13] ed[31:0] ea12 aoe /sdras /ssoe ? are /sdcas /ssads ? awe /sdwe /sswe ? bank activate row address row address 12 5 5 5 1 ea[11:2] actv 12 4 4 4 1 ? are /sdcas /ssads , awe /sdwe /sswe , and aoe /sdras /ssoe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 35. sdram actv command eclkout cex be[3:0] ea[21:13, 11:2] ed[31:0] ea12 aoe /sdras /ssoe ? are /sdcas /ssads ? awe /sdwe /sswe ? 11 12 5 1 dcab 11 12 4 1 ? are /sdcas /ssads , awe /sdwe /sswe , and aoe /sdras /ssoe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 36. sdram dcab command
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 108 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) eclkout cex be[3:0] ea[21:13] ed[31:0] ea12 aoe /sdras /ssoe ? are /sdcas /ssads ? awe /sdwe /sswe ? ea[11:2] bank 11 12 5 5 1 deac 11 12 4 4 1 ? are /sdcas /ssads , awe /sdwe /sswe , and aoe /sdras /ssoe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 37. sdram deac command eclkout cex be[3:0] ea[21:2] ed[31:0] ea12 aoe /sdras /ssoe ? are /sdcas /ssads ? awe /sdwe /sswe ? 8 12 1 refr 8 12 1 ? are /sdcas /ssads , awe /sdwe /sswe , and aoe /sdras /ssoe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 38. sdram refr command
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 109 post office box 1443 ? houston, texas 77251 ? 1443 synchronous dram timing (continued) eclkout cex be[3:0] ea[21:2] ed[31:0] aoe /sdras /ssoe ? are /sdcas /ssads ? awe /sdwe /sswe ? mrs value 11 8 12 5 1 mrs 11 8 12 4 1 ? are /sdcas /ssads , awe /sdwe /sswe , and aoe /sdras /ssoe operate as sdcas , sdwe , and sdras , respectively, during sdram accesses. figure 39. sdram mrs command
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 110 post office box 1443 ? houston, texas 77251 ? 1443 hold /holda timing timing requirements for the hold /holda cycles ? (see figure 40) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 3 t h(holdal-holdl) hold time, hold low after holda low e ns ? e = eclkout period in ns switching characteristics over recommended operating conditions for the hold /holda cycles ?? (see figure 40) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t d(holdl-emhz) delay time, hold low to emif bus high impedance 2e ns 2 t d(emhz-holdal) delay time, emif bus high impedance to holda low 0 2e ns 4 t d(holdh-emlz) delay time, hold high to emif bus low impedance 2e 7e ns 5 t d(emlz-holdah) delay time, emif bus low impedance to holda high 0 2e ns ? e = eclkout period in ns ? emif bus consists of ce[3:0] , be[3:0] , ed[31:0], ea[21:2], are/sdcas /ssads , aoe/sdras /ssoe , and awe/sdwe /sswe . all pending emif transactions are allowed to complete before holda is asserted. if no bus transactions are occurring, then the minimum delay time can be achieved. also, bus hold can be indefinitely delayed by setting nohold = 1. hold holda emif bus ? dsp owns bus external requestor owns bus dsp owns bus c6713 c6713 1 3 25 4 ? emif bus consists of ce[3:0] , be[3:0] , ed[31:0], ea[21:2], are/sdcas /ssads , aoe/sdras /ssoe , and awe/sdwe /sswe . figure 40. hold /holda timing
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 111 post office box 1443 ? houston, texas 77251 ? 1443 busreq timing switching characteristics over recommended operating conditions for the busreq cycles (see figure 41) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t d(ekoh-busrv) delay time, eclkout high to busreq valid 1.5 7.2 ns eclkout 1 busreq 1 figure 41. busreq timing
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 112 post office box 1443 ? houston, texas 77251 ? 1443 reset timing timing requirements for reset ?? (see figure 42) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t w(rst) pulse duration, reset 100 ns 13 t su(hd) setup time, hd boot configuration bits valid before reset high 2p ns 14 t h(hd) hold time, hd boot configuration bits valid after reset high 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? for the c6713 device, the pll is bypassed immediately after the device comes out of reset. the pll controller can be programmed to change the pll mode in software. for more detailed information on the pll controller, see the tms320c6000 dsp phase-lock loop (pll) controller peripheral reference guide (literature number spru233). the boot and device configurations bits are latched asynchronously when reset is transitioning high. the boot and device config urations bits consist of: hd[14, 8, 4:3]. switching characteristics over recommended operating conditions during reset ? (see figure 42) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 2 t d(rsth-zv) delay time, external reset high to internal reset high and all signal groups valid #|| clkmode0 = 1 512 x clkin period ns 3 t d(rstl-eckol) delay time, reset low to eclkout low 0 ns 4 t d(rsth-eckov) delay time, reset high to eclkout valid 6p ns 5 t d(rstl-cko2iv) delay time, reset low to clkout2 invalid 0 ns 6 t d(rsth-cko2v) delay time, reset high to clkout2 valid 6p ns 7 t d(rstl-cko3l) delay time, reset low to clkout3 low 0 ns 8 t d(rsth-cko3v) delay time, reset high to clkout3 valid 6p ns 9 t d(rstl-emifzhz) delay time, reset low to emif z group high impedance || 0 ns 10 t d(rstl-emifliv) delay time, reset low to emif low group (busreq) invalid || 0 ns 11 t d(rstl-z1hz) delay time, reset low to z group 1 high impedance || 0 ns 12 t d(rstl-z2hz) delay time, reset low to z group 2 high impedance || 0 ns ? p = 1/cpu clock frequency in ns. note that while internal reset is asserted low, the cpu clock (sysclk1) period is equal to the input clock (clkin) period multi plied by 8. for example, if the clkin period is 20 ns, then the cpu clock (sysclk1) period is 20 ns x 8 = 160 ns. therefore, p = sysclk1 = 160 ns while internal reset is asserted. # the internal reset is stretched exactly 512 x clkin cycles if clkin is used (clkmode0 = 1). if the input clock (clkin) is not s table when reset is deasserted, the actual delay time may vary. || emif z group consists of: ea[21:2], ed[31:0], ce[3:0] , be[3:0] , are /sdcas /ssads , awe /sdwe /sswe , aoe /sdras /ssoe and holda emif low group consists of: busreq z group 1 consists of: clkr0/aclkr0, clkr1/axr0[6], clkx0/aclkx0, clkx1/amute0, fsr0/afsr0, fsr1/axr0[7], fsx0/afsx0, fsx1, dx0/axr0[1], dx1/axr0[5], tout0/axr0[2], tout1/axr0[4], sda0 and scl0. z group 2 consists of: all other hpi, mcasp0/1, gpio, and i2c1 signals.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 113 post office box 1443 ? houston, texas 77251 ? 1443 reset timing (continued) phase 1 phase 2 12 11 10 9 8 7 6 5 4 3 14 13 2 1 1 clkin eclkin internal reset internal sysclk1 internal sysclk2 internal sysclk3 eclkout clkout2 clkout3 reset phase 3 emif z group ? emif low group ? z group 1 ? z group 2 ? boot and device configuration pins? 2 2 2 2 ? emif z group consists of: ea[21:2], ed[31:0], ce[3:0] , be[3:0] , are /sdcas /ssads , awe /sdwe /sswe , aoe /sdras /ssoe and holda emif low group consists of: busreq z group 1 consists of: clkr0/aclkr0, clkr1/axr0[6], clkx0/aclkx0, clkx1/amute0, fsr0/afsr0, fsr1/axr0[7], fsx0/afsx0, fsx1, dx0/axr0[1], dx1/axr0[5], tout0/axr0[2], tout1/axr0[4], sda0 and scl0. z group 2 consists of: all other hpi, mcasp0/1, gpio, and i2c1 signals. ? boot and device configurations consist of: hd[14, 8, 4:3]. figure 42. reset timing reset phase 1 : the reset pin is asserted. during this time, all internal clocks are running at the clkin frequency divide-by-8. the cpu is also running at the clkin frequency divide-by-8. reset phase 2 : the reset pin is deasserted but the internal reset is stretched. during this time, all internal clocks are running at the clkin frequency divide-by-8. the cpu is also running at the clkin frequency divide-by-8. reset phase 3 : both the reset pin and internal reset are deasserted. during this time, all internal clocks are running at their default divide-down frequency of clkin. the cpu clock (sysclk1) is running at clkin frequency. the peripheral clock (sysclk2) is running at clkin frequency divide-by-2. the emif internal clock source (sysclk3) is running at clkin frequency divide-by-2. sysclk3 is reflected on the eclkout pin (when eksrc bit = 0 [default]). clkout3 is running at clkin frequency divide-by-8.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 114 post office box 1443 ? houston, texas 77251 ? 1443 external interrupt timing timing requirements for external interrupts ? (see figure 43) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t width of the nmi interrupt pulse low 2p ns 1 t w(ilow) width of the ext_int interrupt pulse low 4p ns 2 t (g) width of the nmi interrupt pulse high 2p ns 2 t w(ihigh) width of the ext_int interrupt pulse high 4p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. 2 1 ext_int, nmi figure 43. external/nmi interrupt timing
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 115 post office box 1443 ? houston, texas 77251 ? 1443 multichannel audio serial port (mcasp) timing timing requirements for mcasp (see figure 44 and figure 45) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t c(ahckrx) cycle time, ahclkr/x 20 ns 2 t w(ahckrx) pulse duration, ahclkr/x high or low 7.5 ns 3 t c(ackrx) cycle time, aclkr/x aclkr/x ext 33 ns 4 t w(ackrx) pulse duration, aclkr/x high or low aclkr/x ext 14 ns 5 t setup time afsr/x input valid before aclkr/x latches data aclkr/x int 6 ns 5 t su(afrxc-ackrx) setup time, afsr/x input valid before aclkr/x latches data aclkr/x ext 3 ns 6 t hold time afsr/x input valid after aclkr/x latches data aclkr/x int 0 ns 6 t h(ackrx-afrx) hold time, afsr/x input valid after aclkr/x latches data aclkr/x ext 3 ns 7 t setup time axr input valid before aclkr/x latches data aclkr/x int 8 ns 7 t su(axr-ackrx) setup time, axr input valid before aclkr/x latches data aclkr/x ext 3 ns 8 t hold time axr input valid after aclkr/x latches data aclkr/x int 1 ns 8 t h(ackrx-axr) hold time, axr input valid after aclkr/x latches data aclkr/x ext 3 ns switching characteristics over recommended operating conditions for mcasp ? (see figure 44 and figure 45) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 9 t c(ahckrx) cycle time, ahclkr/x 20 ns 10 t w(ahckrx) pulse duration, ahclkr/x high or low (ah/2) ? 2.5 ns 11 t c(ackrx) cycle time, aclkr/x aclkr/x int 33 ns 12 t w(ackrx) pulse duration, aclkr/x high or low aclkr/x int (a/2) ? 2.5 ns 13 t delay time, aclkr/x transmit edge to afsx/r output aclkr/x int ? 1 5 ns 13 t d(ackrx-afrx) delay time , aclkr/x transmit edge to afsx/r output valid aclkr/x ext 0 10 ns 14 t delay time aclkx transmit edge to axr output valid aclkr/x int ? 1 5 ns 14 t d(ackx-axrv) delay time, aclkx transmit edge to axr output valid aclkr/x ext 0 10 ns 15 t disable time, axr high impedance following last data aclkr/x int ? 1 10 ns 15 t dis(ackrx ? axrhz) disable time , axr high impedance following last data bit from aclkr/x transmit edge aclkr/x ext ? 1 10 ns ? ah = ahclkr/x period in ns. a = aclkr/x period in ns.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 116 post office box 1443 ? houston, texas 77251 ? 1443 multichannel audio serial port (mcasp) timing (continued) 8 7 4 4 3 2 2 1 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) aclkr/x (falling edge polarity) aclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay) afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay) afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data in/receive) 6 5 figure 44. mcasp input timings
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 117 post office box 1443 ? houston, texas 77251 ? 1443 multichannel audio serial port (mcasp) timing (continued) 15 14 14 14 14 14 14 13 13 13 13 13 13 13 12 12 11 10 10 9 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) aclkr/x (falling edge polarity) aclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay) afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay) afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data out/transmit) figure 45. mcasp output timings
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 118 post office box 1443 ? houston, texas 77251 ? 1443 inter-integrated circuits (i2c) timing timing requirements for i2c timings ? (see figure 46) no pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit no . standard mode fast mode unit min max min max 1 t c(scl) cycle time, scl 10 2.5 s 2 t su(sclh-sdal) setup time, scl high before sda low (for a repeated start condition) 4.7 0.6 s 3 t h(scll-sdal) hold time, scl low after sda low (for a start and a repeated start condition) 4 0.6 s 4 t w(scll) pulse duration, scl low 4.7 1.3 s 5 t w(sclh) pulse duration, scl high 4 0.6 s 6 t su(sdav-sdlh) setup time, sda valid before scl high 250 100 ? ns 7 t h(sda-sdll) hold time, sda valid after scl low (for i 2 c bus ? devices) 0 0 0.9 ? s 8 t w(sdah) pulse duration, sda high between stop and start conditions 4.7 1.3 s 9 t r(sda) rise time, sda 1000 20 + 0.1c b # 300 ns 10 t r(scl) rise time, scl 1000 20 + 0.1c b # 300 ns 11 t f(sda) fall time, sda 300 20 + 0.1c b # 300 ns 12 t f(scl) fall time, scl 300 20 + 0.1c b # 300 ns 13 t su(sclh-sdah) setup time, scl high before sda high (for stop condition) 4 0.6 s 14 t w(sp) pulse duration, spike (must be suppressed) 0 50 ns 15 c b # capacitive load for each bus line 400 400 pf ? the i 2 c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered d own. ? a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su(sda ? sclh) 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch t he low period of the scl signal, it must output the next data bit to the sda line t r max + t su(sda ? sclh) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. ? the maximum t h(sda ? scll) has only to be met if the device does not stretch the low period [t w(scll) ] of the scl signal. # c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. 10 8 4 3 7 12 5 6 14 2 3 13 stop start repeated start stop sda scl 1 11 9 figure 46. i 2 c receive timings
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 119 post office box 1443 ? houston, texas 77251 ? 1443 inter-integrated circuits (i2c) timing (continued) switching characteristics for i2c timings ? (see figure 47) no parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit no . parameter standard mode fast mode unit min max min max 16 t c(scl) cycle time, scl 10 2.5 s 17 t d(sclh-sdal) delay time, scl high to sda low (for a repeated start condition) 4.7 0.6 s 18 t d(sdal-scll) delay time, sda low to scl low (for a start and a repeated start condition) 4 0.6 s 19 t w(scll) pulse duration, scl low 4.7 1.3 s 20 t w(sclh) pulse duration, scl high 4 0.6 s 21 t d(sdav-sdlh) delay time, sda valid to scl high 250 100 ns 22 t v(sdll-sdav) valid time, sda valid after scl low (for i 2 c bus ? devices) 0 0 0.9 s 23 t w(sdah) pulse duration, sda high between stop and start conditions 4.7 1.3 s 24 t r(sda) rise time, sda 1000 20 + 0.1c b ? 300 ns 25 t r(scl) rise time, scl 1000 20 + 0.1c b ? 300 ns 26 t f(sda) fall time, sda 300 20 + 0.1c b ? 300 ns 27 t f(scl) fall time, scl 300 20 + 0.1c b ? 300 ns 28 t d(sclh-sdah) delay time, scl high to sda high (for stop condition) 4 0.6 s 29 c p capacitance for each i2c pin 10 10 pf ? c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. 25 23 19 18 22 27 20 21 17 18 28 stop start repeated start stop sda scl 16 26 24 figure 47. i 2 c transmit timings
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 120 post office box 1443 ? houston, texas 77251 ? 1443 host-port interface timing timing requirements for host-port interface cycles ?? (see figure 48, figure 49, figure 50, and figure 51) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t su(selv-hstbl) setup time, select signals valid before hstrobe low 5 ns 2 t h(hstbl-selv) hold time, select signals valid after hstrobe low 4 ns 3 t w(hstbl) pulse duration, hstrobe low 4p ns 4 t w(hstbh) pulse duration, hstrobe high between consecutive accesses 4p ns 10 t su(selv-hasl) setup time, select signals valid before has low 5 ns 11 t h(hasl-selv) hold time, select signals valid after has low 3 ns 12 t su(hdv-hstbh) setup time, host data valid before hstrobe high 5 ns 13 t h(hstbh-hdv) hold time, host data valid after hstrobe high 3 ns 14 t h(hrdyl-hstbl) hold time, hstrobe low after hrdy low. hstrobe should not be inactivated until hrdy is active (low); otherwise, hpi writes will not complete properly. 2 ns 18 t su(hasl-hstbl) setup time, has low before hstrobe low 2 ns 19 t h(hstbl-hasl) hold time, has low after hstrobe low 2 ns ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. select signals include: hcntl[1:0], hr/w , and hhwil. switching characteristics over recommended operating conditions during host-port interface cycles ?? (see figure 48, figure 49, figure 50, and figure 51) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 5 t d(hcs-hrdy) delay time, hcs to hrdy ? 1 12 ns 6 t d(hstbl-hrdyh) delay time, hstrobe low to hrdy high # 3 12 ns 7 t d(hstbl-hdlz) delay time, hstrobe low to hd low impedance for an hpi read 2 ns 8 t d(hdv-hrdyl) delay time, hd valid to hrdy low 2p ? 4 ns 9 t oh(hstbh-hdv) output hold time, hd valid after hstrobe high 3 12 ns 15 t d(hstbh-hdhz) delay time, hstrobe high to hd high impedance 3 12 ns 16 t d(hstbl-hdv) delay time, hstrobe low to hd valid 3 12 ns 17 t d(hstbh-hrdyh) delay time, hstrobe high to hrdy high || 3 12 ns ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? hcs enables hrdy , and hrdy is always low when hcs is high. the case where hrdy goes high when hcs falls indicates that hpi is busy completing a previous hpid write or read with autoincrement. # this parameter is used during an hpid read. at the beginning of the first half-word transfer on the falling edge of hstrobe , the hpi sends the request to the edma internal address generation hardware, and hrdy remains high until the edma internal address generation hardware loads the requested data into hpid. || this parameter is used after the second half-word of an hpid write or autoincrement read. hrdy remains low if the access is not an hpid write or autoincrement read. reading or writing to hpic or hpia does not affect the hrdy signal.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 121 post office box 1443 ? houston, texas 77251 ? 1443 host-port interface timing (continued) 1st halfword 2nd halfword 5 17 8 6 5 17 8 5 15 9 16 15 9 7 4 3 2 1 2 1 2 1 2 1 2 1 2 1 has hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (output) hrdy (case 1) hrdy (case 2) 3 ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 48. hpi read timing (has not used, tied high) has ? hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (output) hrdy (case 1) hrdy (case 2) 1st half-word 2nd half-word 5 17 8 5 17 8 5 15 9 16 15 9 7 4 3 11 10 11 10 11 10 11 10 11 10 11 10 19 19 18 18 ? for correct operation, strobe the has signal only once per hstrobe active cycle. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 49. hpi read timing (has used)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 122 post office box 1443 ? houston, texas 77251 ? 1443 host-port interface timing (continued) 1st halfword 2nd halfword 5 17 5 13 12 13 12 4 14 3 2 1 2 1 2 1 2 1 2 1 2 1 has hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (input) hrdy 3 ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 50. hpi write timing (has not used, tied high) 1st half-word 2nd half-word 5 17 5 13 12 13 12 4 14 3 11 10 11 10 11 10 11 10 11 10 11 10 has ? hcntl[1:0] hr/w hhwil hstrobe ? hcs hd[15:0] (input) hrdy 19 19 18 18 ? for correct operation, strobe the has signal only once per hstrobe active cycle. ? hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . figure 51. hpi write timing (has used)
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 123 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing timing requirements for mcbsp ?? (see figure 52) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 2 t c(ckrx) cycle time, clkr/x clkr/x ext 2p ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext 0.5 * t c(ckrx) ? 1 ? ns 5 t setup time external fsr high before clkr low clkr int 9 ns 5 t su(frh-ckrl) setup time, external fsr high before clkr low clkr ext 1 ns 6 t hold time external fsr high after clkr low clkr int 6 ns 6 t h(ckrl-frh) hold time, external fsr high after clkr low clkr ext 3 ns 7 t setup time dr valid before clkr low clkr int 8 ns 7 t su(drv-ckrl) setup time, dr valid before clkr low clkr ext 0 ns 8 t hold time dr valid after clkr low clkr int 3 ns 8 t h(ckrl-drv) hold time, dr valid after clkr low clkr ext 4 ns 10 t setup time external fsx high before clkx low clkx int 9 ns 10 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx ext 1 ns 11 t hold time external fsx high after clkx low clkx int 6 ns 11 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx ext 3 ns ? clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are a lso inverted. ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. the minimum clkr/x period is twice the cpu cycle time (2p) and not faster than 75 mbps (13.3 ns). this means that the maximum b it rate for communications between the mcbsp and other devices is 75 mbps for 167-mhz and 225-mhz cpu clocks or 50 mbps for 100-mhz cpu clock; where the mcbsp is either the master or the slave. care must be taken to ensure that the ac timings specified in this data shee t are met. the maximum bit rate for mcbsp-to-mcbsp communications is 67 mbps; therefore, the minimum clkr/x clock cycle is either twice the cp u cycle time (2p), or 15 ns (67 mhz), whichever value is larger. for example, when running parts at 150 mhz (p = 6.7 ns), use 15 ns as the minimum clkr/x clock cycle (by setting the appropriate clkgdv ratio or external clock source). when running parts at 60 mhz (p = 16.67 ns), us e 2p = 33 ns (30 mhz) as the minimum clkr/x clock cycle. the maximum bit rate for mcbsp-to-mcbsp communications applies when the seria l port is a master of the clock and frame syncs (with clkr connected to clkx, fsr connected to fsx, clkxm = fsxm = 1, and clkrm = fsrm = 0) in data delay 1 or 2 mode (r/xdatdly = 01b or 10b) and the other device the mcbsp communicates to is a slave. ? this parameter applies to the maximum mcbsp frequency. operate serial clocks (clkr/x) in the resonable range of 40/60 duty cycl e.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 124 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) switching characteristics over recommended operating conditions for mcbsp ?? (see figure 52) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t d(cksh-ckrxh) delay time, clks high to clkr/x high for internal clkr/x generated from clks input 1.8 10 ns 2 t c(ckrx) cycle time, clkr/x clkr/x int 2p ? ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x int c ? 1 # c + 1 # ns 4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int ? 2 3 ns 9 t delay time clkx high to internal fsx valid clkx int ? 2 3 ns 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx ext 2 9 ns 12 t disable time, dx hi g h impedance followin g last data bit clkx int ? 1 4 ns 12 t dis(ckxh-dxhz) disable time , dx high impedance following last data bit from clkx high clkx ext 1.5 10 ns 13 t delay time clkx high to dx valid clkx int ? 3.2 + d1 || 4 + d2 || ns 13 t d(ckxh-dxv) delay time, clkx high to dx valid clkx ext 0.5 + d1 || 10+ d2 || ns 14 t delay time, fsx high to dx valid fsx int ? 1 4.5 ns 14 t d(fxh-dxv) only applies when in data delay 0 (xdatdly = 00b) mode fsx ext 2 9 ns ? clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are a lso inverted. ? minimum delay times also represent minimum output hold times. p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? the minimum clkr/x period is twice the cpu cycle time (2p) and not faster than 75 mbps (13.3 ns). this means that the maximum b it rate for communications between the mcbsp and other devices is 75 mbps for 167-mhz and 225-mhz cpu clocks or 50 mbps for 100-mhz cpu clock; where the mcbsp is either the master or the slave. care must be taken to ensure that the ac timings specified in this data shee t are met. the maximum bit rate for mcbsp-to-mcbsp communications is 67 mbps; therefore, the minimum clkr/x clock cycle is either twice the cp u cycle time (2p), or 15 ns (67 mhz), whichever value is larger. for example, when running parts at 150 mhz (p = 6.7 ns), use 15 ns as the minimum clkr/x clock cycle (by setting the appropriate clkgdv ratio or external clock source). when running parts at 60 mhz (p = 16.67 ns), us e 2p = 33 ns (30 mhz) as the minimum clkr/x clock cycle. the maximum bit rate for mcbsp-to-mcbsp communications applies when the seria l port is a master of the clock and frame syncs (with clkr connected to clkx, fsr connected to fsx, clkxm = fsxm = 1, and clkrm = fsrm = 0) in data delay 1 or 2 mode (r/xdatdly = 01b or 10b) and the other device the mcbsp communicates to is a slave. # c = h or l s = sample rate generator input clock = 2p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero clkgdv should be set appropriately to ensure the mcbsp bit rate does not exceed the maximum limit (see ? footnote above). || extra delay from clkx high to dx valid applies only to the first data bit of a device, if and only if dxena = 1 in spcr. if dxena = 0, then d1 = d2 = 0 if dxena = 1, then d1 = 2p, d2 = 4p
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 125 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit(n-1) (n-2) (n-3) bit 0 bit(n-1) (n-2) (n-3) 14 13 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 clks clkr fsr (int) fsr (ext) dr clkx fsx (int) fsx (ext) fsx (xdatdly=00b) dx 13 figure 52. mcbsp timings
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 126 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for fsr when gsync = 1 (see figure 53) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t su(frh-cksh) setup time, fsr high before clks high 4 ns 2 t h(cksh-frh) hold time, fsr high after clks high 4 ns 2 1 clks fsr external clkr/x (no need to resync) clkr/x (needs resync) figure 53. fsr timing when gsync = 1
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 127 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 ?? (see figure 54) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit master slave min max min max 4 t su(drv-ckxl) setup time, dr valid before clkx low 12 2 ? 6p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 12p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 ?? (see figure 54) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit master slave min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? t ? 2 t + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # l ? 2 l + 3 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ? 3 4 6p + 2 10p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low l ? 2 l + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high 2p + 3 6p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 4p + 2 8p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 2p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 128 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 54. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 129 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 ?? (see figure 55) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit master slave min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 6p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 12p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 ?? (see figure 55) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit master slave min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low ? l ? 2 l + 3 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high # t ? 2 t + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ? 3 4 6p + 2 10p + 17 ns 6 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low ? 2 4 6p + 3 10p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid h ? 2 h + 4 4p + 2 8p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 2p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 clkx fsx dx dr 5 figure 55. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 130 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 ?? (see figure 56) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit master slave min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 6p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 12p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 ?? (see figure 56) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit master slave min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? t ? 2 t + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # h ? 2 h + 3 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid ? 3 4 6p + 2 10p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high h ? 2 h + 3 ns 7 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high 2p + 3 6p + 17 ns 8 t d(fxl-dxv) delay time, fsx low to dx valid 4p + 2 8p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 2p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 131 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr figure 56. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 132 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 ?? (see figure 57) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit master slave min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 12 2 ? 6p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 12p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 ?? (see figure 57) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit master slave min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high ? h ? 2 h + 3 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low # t ? 2 t + 3 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid ? 3 4 6p + 2 10p + 17 ns 6 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high ? 2 4 6p + 3 10p + 17 ns 7 t d(fxl-dxv) delay time, fsx low to dx valid l ? 2 l + 4 4p + 2 8p + 17 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. s = sample rate generator input clock = 2p if clksm = 1 (p = 1/cpu clock frequency) = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even = (clkgdv + 1)/2 * s if clkgdv is odd or zero ? fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp # fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of t he master clock (clkx).
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 133 post office box 1443 ? houston, texas 77251 ? 1443 multichannel buffered serial port timing (continued) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 clkx fsx dx dr figure 57. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 134 post office box 1443 ? houston, texas 77251 ? 1443 timer timing timing requirements for timer inputs ? (see figure 58) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t w(tinph) pulse duration, tinp high 2p ns 2 t w(tinpl) pulse duration, tinp low 2p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. switching characteristics over recommended operating conditions for timer outputs ? (see figure 58) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 3 t w(touth) pulse duration, tout high 4p ? 3 ns 4 t w(toutl) pulse duration, tout low 4p ? 3 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. tinpx toutx 4 3 2 1 figure 58. timer timing
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 135 post office box 1443 ? houston, texas 77251 ? 1443 general-purpose input/output (gpio) port timing timing requirements for gpio inputs ?? (see figure 59) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t w(gpih) pulse duration, gpix high 4p ns 2 t w(gpil) pulse duration, gpix low 4p ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. ? the pulse width given is sufficient to generate a cpu interrupt or an edma event. however, if a user wants to have the dsp reco gnize the gpix changes through software polling of the gpio register, the gpix duration must be extended to at least 24p to allow the dsp enough time to access the gpio register through the cfgbus. switching characteristics over recommended operating conditions for gpio outputs ? (see figure 59) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 3 t w(gpoh) pulse duration, gpox high 12p ? 3 ns 4 t w(gpol) pulse duration, gpox low 12p ? 3 ns ? p = 1/cpu clock frequency in ns. for example, when running parts at 225 mhz, use p = 4.4 ns. the number of cfgbus cycles between two back-to-back cfgbus writes to the gpio register is 12 sysclk1 cycles; therefore, the mi nimum gpox pulse width is 12p. gpix gpox 4 3 2 1 figure 59. gpio port timing
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 136 post office box 1443 ? houston, texas 77251 ? 1443 jtag test-port timing timing requirements for jtag test port (see figure 60) no. pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 1 t c(tck) cycle time, tck 35 ns 3 t su(tdiv-tckh) setup time, tdi/tms/trst valid before tck high 10 ns 4 t h(tckh-tdiv) hold time, tdi/tms/trst valid after tck high 7 ns switching characteristics over recommended operating conditions for jtag test port (see figure 60) no. parameter pypa ? 167 pyp ? 200 gdpa ? 200 gdp ? 225 unit min max 2 t d(tckl-tdov) delay time, tck low to tdo valid 0 15 ns tck tdo tdi/tms/trst 1 2 3 4 2 figure 60. jtag test-port timing
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 137 post office box 1443 ? houston, texas 77251 ? 1443 mechanical data gdp (s ? pbga ? n272) plastic ball grid array 2468 20 18 16 14 12 10 m e a 1 c b d g f h k j l w r n p u t v y 3 57 9 11 17 15 13 19 0,635 0,635 26,80 sq 23,80 24,20 sq 27,20 24,13 typ 0,57 0,65 0,60 0,90 seating plane 0,50 0,70 2,57 max 0,15 0,10 a1 corner 1,27 1,27 4204396/a 04/02 bottom view 1,12 1,22 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec mo-151 thermal resistance characteristics (s-pbga package) no c/w air flow (m/s) ? two signals, two planes (4-layer board) 1 r jc junction-to-case 9.7 n/a 2 psi jt junction-to-package top 1.5 0.0 3 r jb junction-to-board 19 n/a 4 r ja junction-to-free air 22 0.0 5 r ja junction-to-free air 21 0.5 6 r ja junction-to-free air 20 1.0 7 r ja junction-to-free air 19 2.0 8 r ja junction-to-free air 18 4.0 9 psi jb junction-to-board 16 0.0 ? m/s = meters per second
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 138 post office box 1443 ? houston, texas 77251 ? 1443 mechanical data tms320c6713 device-specific pyp (s-pqfp-g208) powerpad ? plastic quad flatpack 0,13 nom 105 thermal pad (see note d) 104 0,17 53 0,27 0,25 0,45 0,75 0,15 0,05 52 seating plane 4/17/02 gage plane 157 208 156 sq sq 28,05 29,90 30,10 27,95 25,50 typ 1 1,45 1,35 1,60 max 0,08 0,50 m 0,08 0 ? 7 sq 8,25 7,15 thermal pad externally flush with mold compound notes: a. all linear dimensions are in millimeters. b. the generic drawing (ecn# 4146966) is subject to change without notice and will affect this drawing. c. body dimensions include mold flash or protrusions. d. for proper device thermal performance, the thermal pad must be soldered to an external thermal plane. this pad is electrically and thermally connected to the backside of the die. for the tms320c6713 208-pin powerpad plastic quad flatpack, the external thermal pad dimensions are: 7.2 x 7.2 mm and the thermal pad is externally flush with the mold compound. e. falls within jedec ms-026 powerpad is a trademark of texas instruments.
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 139 post office box 1443 ? houston, texas 77251 ? 1443 mechanical data (continued) thermal resistance characteristics (s-pqfp-g208 package) no c/w junction-to-pad two signals, two planes (4-layer board) ? 208-pin pyp 1 r jp junction-to-pad, 26 x 26 copper pad on top and bottom of pcb with solder connection and vias going to gnd plane, isolated from power plane. 0.2 junction-to-package top two signals, two planes (4-layer board) ? 208-pin pyp 2 psi jt junction-to-package top, 26 x 26 copper pad on top and bottom of pcb with solder connection and vias going to gnd plane, isolated from power plane. 0.18 3 psi jt junction-to-package top, 7.5 x 7.5 copper pad on top and bottom of pcb with solder connection and vias going to gnd plane, isolated from power plane. 0.23 two signals (2-layer board) 4 psi jt junction-to-package top, 26 x 26 copper pad on top of pcb with solder connection and vias going to copper plane on bottom of board. 0.18 5 psi jt junction-to-package top, 7.5 x 7.5 copper pad on top of pcb with solder connection and vias going to copper plane on bottom of board. 0.23 junction-to-still air two signals, two planes (4-layer board) ? 208-pin pyp 6 r ja junction-to-still air, 26 x 26 copper pad on top and bottom of pcb with solder connection and vias going to gnd plane, isolated from power plane. 13 7 r ja junction-to-still air, 7.5 x 7.5 copper pad on top and bottom of pcb with solder connection and vias going to gnd plane, isolated from power plane. 20 two signals (2-layer board) 8 r ja junction-to-still air, 26 x 26 copper pad on top of pcb with solder connection and vias going to copper plane on bottom of board. 14 9 r ja junction-to-still air, 7.5 x 7.5 copper pad on top of pcb with solder connection and vias going to copper plane on bottom of board. 20
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 140 post office box 1443 ? houston, texas 77251 ? 1443 revision history this data sheet revision history highlights the technical changes made to the sprs186d device-specific data sheet to make it an sprs186e revision. scope: applicable updates to the c67x device family, specifically relating to the c6713 devices, have been incorporated. added and updated device-specific information to support the characterization of the c6713 devices which are at the production data (pd) stage of development. page(s) no. additions/changes/deletions 9 description section: deleted ?boot from a serial eeprom? from the ?the two i2c ports on the tms320c6713 allow the dsp ...? paragraph 10 device characteristics section; table 2, characteristics of the c6713 processor: changed the 32-bit timers, ?internal clock source? from ?1/4 of sysclk1? to ?1/ 2 of sysclk 2 ? 30 table 18, device configurations pins at device reset (hd[4:3], hd8, and clkmode0): added the hd[6, 5, 2] exclusion to the ?all other hd pins (hd [15, 13:9, 7:5, 2:0])? footnote 44 debugging considerations section: added the hd[6, 5, 2] exclusion to the ?internal pullup/pulldown resistors ...? paragraph 47 terminal functions table, host-port interface (hpi), host-port data pins description: added the hd[6, 5, 2] exclusion to the ?other hd pins ...? paragraph 64 documentation support section: added reference to the tms320c6713/12c/11c power consumption summary application report (literature number spra889). 71 edma module and edma selector section, table 29, edma channels: changed the ?default selector value (binary)? value for xevt0 from ?001000? to ?001 1 00? changed the ?default selector value (binary)? value for revt0 from ?001001? to ?001 1 01? changed the ?default selector value (binary)? value for xevt1 from ?001010? to ?001 1 10? changed the ?default selector value (binary)? value for revt1 from ?001011? to ?001 1 11? 75 pll and pll controller section: deleted sysclk2 row along with max value from table 35, pll clock frequency ranges: added footnote stating ?sysclk2 rate must be exactly half of sysclk1? added footnote stating ?when the mcasp module is not used, the auxclk maximum frequency can be any frequency up to the clkin maximum frequency.? added new ending sentence to the ?during the programming transition of divider d1 ...? paragraph 86 general-purpose input/output (gpio) section: added new gpio section with device-specific gpen register 88 ieee 1149.1 jtag compatibility statement section: replaced paragraph ?it is recommended that when using this type of jtag controller, ...? with new paragraph ?when using this type of jtag controller, assert ...? 89 emif device speed section: replaced/updated all ?emif device speed? paragraphs added new table 44, ?c6713 example boards and maximum emif speed? 90 bootmode section: updated/changed the paragraph explanation for all three boot modes: host boot, emulation boot, and emif boot to reflect the internally ?stalled? state of the cpu
tms320c6713 floating-point digital signal processor sprs186e ? december 2001 ? revised july 2003 141 post office box 1443 ? houston, texas 77251 ? 1443 page(s) no. additions/changes/deletions 91 absolute maximum ratings over operating case temperature range section: changed the supply voltage range, cv dd from ? ? 0.3 v to 1.35 v? to ? ? 0.3 v to 1.8 v? 92 electrical characteristics over recommended ranges of supply voltage and operating case temperature table: added ?the actual current draw is highly application-dependent. for more details on core and i/o activity, refer to the tms320c6713/12c/11c power consumption summary application report (literature number spra889).? to the end of the ?measured with average activity (50% high/50% low power) at 25 c case temperature and 100-mhz emif. ...? paragraph 112 reset timing, timing requirements for reset table changed the boot and device configurations bits footnote to ?the boot and device configurations bits are latched asynchronously when reset is transitioning high . ...? 114 external interrupt timing section timing requirements for external interrupts table: split the descriptions of nmi and ext_int interrupts pulse low/high changed min value of ?width of the ext_int interrupt pulse low? (parameter #1) from ?2p? to ?4p? changed min value of ?width of the ext_int interrupt pulse high? (parameter #2) from ?2p? to ?4p?
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2003, texas instruments incorporated

▲Up To Search▲

Price & Availability of TMS320C6713-225

	To Download TMS320C6713-225 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .