final product specification p2065 jan., 2001 revision d 3160 de la cruz blvd., suite 200 santa clara ca 95054 t el (408) 748 -6 98 8 fax (408) 748 -0 00 9 1 of 6 http ://www.pulsecore.com low spread lcd panel emi reduction ic features ? provides up to 20 db of emi suppression ? fcc approved method of emi attenuation ? generates a low emi spread spectrum clock of the input frequency ? 40 mhz to 85 mhz input frequency range ? optimized for vga, svga and high resolution xga lcd panels ? internal loop filter minimizes external components and board space ? 6 selectable low spread ranges, under +/- 1% ? sson control pin for spread spectrum enable and disable options ? 2 selectable modulation rates ? low cycle-to-cycle jitter ? 3.3v or 5.0 v operating range ? 16 ma output drives ? ttl or cmos compatible outputs ? low power cmos design ? supports most mobile graphic accelerator specifications ? available in 8 pin soic and tssop product description the p2065 is a selectable spread spectrum frequency modulator designed specifically for digital flat panel applications. the p2065 reduces electromagnetic interference (emi) at the clock source which provides system wide reduction of emi of all clock dependent signals. the p2065 allows significant system cost savings by reducing the number of circuit board layers and shielding that are traditionally required to pass emi regulations. the p2065 uses the most efficient and optimized modulation profile approved by the fcc and is implemented in a proprietary all- digital method. the p2065 modulates the output of a single pll in order to ?spread? the bandwidth of a synthesized clock and, more importantly, decreases the peak amplitudes of its harmonics. this results in significantly lower system emi compared to the typical narrow band signal produced by oscillators and most frequency generators. lowering emi by increasing a signal?s bandwidth is called ?spread spectrum clock generation?. applications the p2065 is targeted towards digital flat panel applications for notebook pcs, palm-size pcs, office automation equipments, and lcd monitors. figure 1 ? p2065 pin diagram 1 8 2 7 3 6 4 5 clkin mra sr1 vss vdd sr0 modout sson
final product specification p2065 jan., 2001 revision d 3160 de la cruz blvd., suite 200 santa clara ca 95054 t el (408) 748 - 69 88 fax (408) 74 8- 000 9 2 of 7 http: //www.pulsecore.com figure 2 ? p2065 block diagram modulation phase detector frequency divider feedback divider loop filter vco output divider pll sr0 sr1 mra sson clkin vdd vss modout p2065 block diagram table 1 ? modulation selection mra sr1 sr0 spreading range modulation rate 0 0 0 +/- 0.3% (fin/40) * 34.72 khz ** 0 0 1 +/- 0.6% (fin/40) * 34.72 khz ** 0 1 0 +/- 0.4% (fin/40) * 34.72 khz ** 0 1 1 +/- 0.8% (fin/40) * 34.72 khz 1 0 0 +/- 0.5% (fin/40) * 20.83 khz 1 0 1 +/- 1.00% (fin/40) * 20.83 khz 1 1 0 reserved reserved 1 1 1 reserved reserved **note: these settings are not recommended for 5.0v operation pin description pin # name type description 1 clkin i external reference frequency input. connect to externally generated reference signal. select appropriate part for the intended input frequency (see table 1). 2 mra i digital logic input used to select modulation rate (see table 3). this pin has a 100k ohm internal pull-up resistor. 3 sr1 i digital logic input used to select spreading range (see table 2). this pin has a 100k ohm internal pull-up resistor. 4 vss p ground connection. connect to system ground. 5 sson i digital logic input used to enable spread spectrum function (active low). spread spectrum function enable when low. this pin has a 100k ohm internal pull-low resistor. 6 modout o spread spectrum clock output. 7 sr0 i digital logic input used to select spreading range (see table 1). this pin has a 100k ohm internal pull-up resistor. 8 vdd p connect to +3.3v or +5.0v
final product specification p2065 jan., 2001 revision d 3160 de la cruz blvd., suite 200 santa clara ca 95054 t el (408) 74 8- 69 88 fax (408) 74 8- 000 9 3 of 7 http: //www.pulsecore.com spread spectrum selection table 1 illustrates the possible spread spectrum options. the optimal setting should minimize system emi to the fullest without affecting system performance. the spreading is described as a percentage deviation of the center frequency (note: the center frequency is the frequency of the external reference input on clkin, pin 1). example : p2065 is designed for high resolution flat panel applications and is able to support xga (1024 x 768) flat panel that operates on 65mhz (fin) clock speed. a spreading selection of sr1=0, sr0=1 and modulation rate selection mra=1 provides a percentage deviation of +/-1.00% (see table 1) of fin. this results in frequency on modout being swept from 64.35 mhz to 65.65 mhz at a modulation rate of 33.85khz (see table 1). this particular example (see figure 3) given here is a common emi reduction method for notebook lcd panel and has already been implemented by most of the leading oem and mobile graphic accelerator manufacturers. figure 3 ? p2065 application schematic for mobile lcd graphics controllers p2065 this signal is connected back to the spread spectrum input pin (ssin) of the graphics accelerator. vdd 1 8 6 4 3 2 7 5 clkin mra sr1 vss vdd sson modout sr0 0.1uf 65 mhz from graphics accelerator digital control for ss enable or disable emc software simulation by using pulsecore semiconductor, inc.?s proprietary emc simulation software ? emi-lator ? , radiated system level emi analysis can be made easier to allow a quantitative assessment on pulsecore?s emi reduction products. the simulation engine of this emc software has already been characterized to correlate with the electrical characteristics of pulsecore emi reduction ic?s. figure 4 below is an example of the simulation result. please visit our web site at www.pulsecore.com for information on how to obtain a free copy and demonstration of emi-lator ? .
final product specification p2065 jan., 2001 revision d 3160 de la cruz blvd., suite 200 santa clara ca 95054 t el (408) 74 8 - 69 88 fax (408) 74 8- 000 9 4 of 7 http: //www.pulsecore.com figure 4 ?simulation result from emi-lator ?
final product specification p2065 jan., 2001 revision d 3160 de la cruz blvd., suite 200 santa clara ca 95054 t el (408) 74 8- 698 8 fax (408) 74 8- 000 9 5 of 7 http: //www.pulsecore.com absolute maximum ratings symbol parameter rating unit v dd , v in voltage on any pin with respect to gnd -0.5 to +7.0 v t stg storage temperature -65 to +125 oc t a operating temperature 0 to +70 oc dc electrical characteristics symbol parameter min typ max unit v il input low voltage gnd ? 0.3 - 0.8 v v ih input high voltage 2.0 - v dd + 0.3 v i il input low current (100 k ? input pull-up resistor on inputs sr0,1 and mra) - - -35 a i ih input high current (100 k ? input pull- down resistor on input sson) - - 35 a v ol output low voltage (v dd =3.3v, i ol = 20 ma) - - 0.4 v v oh output high voltage (v dd =3.3v, i oh = 20 ma) 2.5 - - v i dd static supply current - 0.6 - ma i cc dynamic supply current (3.3v and 15 pf loading) 7 9 13 ma v dd operating voltage 2.7 3.3 5.5 v t on power up time (first locked clock cycle after power up) 0.18 ms z out clock output impedance 50 ? ac electrical characteristics symbol parameter min typ max unit f in input frequency 3.3v (5.0 v) 40 (40) 65 (65) 85 (70) mhz t lh note 1 output rise time (measured at 0.8v to 2.0v) 0.7 0.9 1.1 ns t hl note 1 output fall time (measured at 2.0v to 0.8v) 0.6 0.8 1.0 ns t jc jitter (cycle to cycle) - - 360 ps t d output duty cycle 45 50 55 % notes1. t lh and t hl are measured into a capacitive load of 15pf
final product specification p2065 jan., 2001 revision d 3160 de la cruz blvd., suite 200 santa clara ca 95054 t el (408) 74 8 - 69 88 fax (408) 74 8- 00 0 9 6 of 7 http: //www.pulsecore.com figure 6 ? mechanical package outline, (8 pin soic) d a1 e b a a2 p2065a lot number yyww h a c l e figure 7 ? mechanical package outline, (8 pin tssop) d a1 e b a a2 h a c l e p 2065a lot # yyww inches millimeters symbol min nor max min nor max a 0.057 0.064 0.071 1.45 1.63 1.80 a1 0.004 0.007 0.010 0.10 0.18 0.25 a2 0.053 0.061 0.069 1.35 1.55 1.75 b 0.012 0.016 0.020 0.51 0.41 0.31 c 0.004 0.006 0.001 0.10 0.15 0.25 d 0.186 0.194 0.202 4.72 4.92 5.12 e 0.148 0.156 0.164 3.75 3.95 4.15 e 0.050 bsc 1.27 bsc h 0.224 0.236 0.248 5.70 6.00 6.30 l 0.012 0.020 0.028 0.30 0.50 0.70 a 0 5 8 0 5 8 inches millimeters symbol min nor max min nor max a - - 0.047 - - 1.10 a1 0.002 - 0.006 0.05 - 0.15 a2 0.031 0.039 0.041 0.80 1.00 1.05 b 0.007 - 0.012 0.19 - 0.30 c 0.004 - 0.008 0.09 - 0.20 d 0.114 0.118 0.122 2.90 3.00 3.10 e 0.169 0.173 0.177 4.30 4.40 4.50 e 0.026 bsc 0.65 bsc h 0.244 0.252 0.260 6.20 6.40 6.60 l 0.018 0.024 0.030 0.45 0.60 0.75 a 0 - 8 0 - 8
final product specification p2065 jan., 2001 revision d 3160 de la cruz blvd., suite 200 santa clara ca 95054 t el (408) 74 8 -6 98 8 fax (408) 74 8- 000 9 7 of 7 http: //www.pulsecore.com ordering information ordering number marking package type temperature p2065a-08st p2065a 8 pin soic, tube 0c to 70c p2065a-08sr p2065a 8 pin soic, tape & reel 0c to 70c P2065A-08TT p2065a 8 pin tssop, tube 0c to 70c p2065a-08tr p2065a 8 pin tssop, tape & reel 0c to 70c "licensed under u.s. patent nos. 5,488,627 and 5,631,920"
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