View L6725TR_2232474.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

june 2006 rev 3 1/27 27 l6725 low cost adjustable step-down controller features input voltage range from 1.8v to 14v supply voltage range from 4.5v to 14v adjustable output voltage down to 0.6v with 0.8% accuracy over line voltage and temperature (0c~125c) fixed frequency voltage mode control 0% to 100% duty cycle external input voltage reference soft-start and inhibit high current embedded drivers predictive anti-cross conduction control programmable high-side and low-side r ds(on) sense over-current-protection sink current capability selectable switching frequency 250khz/ 500khz pre-bias start up capability over voltage protection thermal shut-down package: so16n applications low voltage distributed dc-dc graphic cards so16n (narrow) www.st.com order codes part number package packing l6725 so16n tube L6725TR so16n tape & reel
contents l6725 2/27 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 pin connections and f unctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 internal ldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 bypassing the ldo to avoid the voltage drop with low vcc . . . . . . . . . . . . . 11 5.4 internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.6 soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.8 monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.9 hiccup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.10 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
l6725 contents 3/27 6 application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 l6725 demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
summary description l6725 4/27 1 summary description the device is a low cost pwm controller dedicated for low voltage distributed dc-dc. the input voltage can range from 1.8v to 14v, while the supply voltage can range from 4.5v to 14v. the output voltage is adjustable down to 0.6v. high peak current gate drivers provide for fast switching to the external power section, and the output current can be in excess of 20a. the device is capable to manage minimum on-times (t on ) shorter than 100ns making possible conversions with very low duty cycle and very high switching frequency. in order to guarantee a real overcurrent protection, also with very narrow t on , the current sense is realized both on the high-side and low-side mosfets. when necessary, two different current limit protections can be externally set through an external resistor. the device can sink current after the soft-start phase while, during the soft-start, the sink mode capability is disabled in order to allow a pr oper start-up also in pre-biased output voltage conditions. other features are over-voltage-protection and thermal shutdown. 1.1 functional description figure 1. block diagram
l6725 electrical data 5/27 2 electrical data 2.1 maximum rating table 1. absolute maximum ratings 2.2 thermal data table 2. thermal data symbol parameter value unit v cc v cc to gnd and pgnd, och -0.3 to 18 v v boot - v phase boot voltage 0 to 6 \ v hgate - v phase 0 to v boot - v phase v v boot boot -0.3 to 24 v v phase phase -1 to 18 v phase spike, transient < 50ns (f sw = 500khz) -3 +24 ss, fb, earef, ocl, lgate, comp, v ccdr -0.3 to 6 v och pin maximum withstanding voltage range test condition: cdf-aec-q10 0-002 "human body model" acceptance criteria: "normal performance" 1500 v other pins 2000 symbol description value unit r thja (1) 1. package mounted on demoboard max. thermal resistance junction to ambient 50 c/w t stg storage temperature range -40 to 150 c t j junction operating temperature range -40 to 125 c t a ambient operating temperature range -40 to +85 c
pin connections and functions l6725 6/27 3 pin connections and functions figure 2. pins connection (top view) table 3. pin functions pin n. name function 15 sgnd all the internal references are referred to this pin. 16 fb this pin is connected to the error amplifier inverting input. connect it to v out through the compensation network. this pin is also used to sense the output voltage in order to manage the over voltage protection. 1comp this pin is connected to the error amplif ier output and is used to compensate the voltage control feedback loop. 2 ss/inh the soft-start time is programmed connecting an external capacitor from this pin to gnd. the internal current generator forces a current of 10 a through the capacitor. when the voltage at this pin is lower than 0.5v the device is disabled. 3 earef by setting the voltage at this pin is possibl e to select the internal/external reference and the switching frequency: v earef 0-80% of v ccdr -> external reference/f sw = 250khz v earef = 80% - 95% of v ccdr -> v ref = 0.6v/f sw = 500khz v earef = 95% - 100% of v ccdr ->v ref = 0.6v/f sw = 250khz an internal clamp limits the maximum v earef at 2.5v (typ.). the device captures the analog value present at this pin at the start-up when v cc meets the uvlo threshold. 1 2 3 4 5 6 11 12 so16n 13 14 15 16 earef hgate ocl ss/inh comp och fb n.c. lgate phase n.c. 7 10 sgnd vcc vccdr boot 8 9 pgnd
l6725 pin connections and functions 7/27 4ocl a resistor connected from this pin to ground sets the valley- current-limit. the valley current is sensed through the low-side mo sfet(s). the internal current generator sources a current of 100 a (i ocl ) from this pin to ground through the external resistor (r ocl ). the over-current threshold is given by the following equation: 5och a resistor connected from this pin and th e high-side mosfet(s) drain sets the peak- current-limit. the peak current is sensed through the high-side mosfet(s). the internal 100 a current generator (i och ) sinks a current from the drain through the external resistor (r och ). the over-current threshold is given by the following equation: 6 phase this pin is connected to the source of the high-side mosfet(s) and provides the return path for the high-side driver. this pin monitors the drop across both the upper and lower mosfet(s) for the current limit together with och and ocl. 7 hgate this pin is connected to the high-side mosfet(s) gate. 8boot through this pin is supplied the high-side driver. connect a capacitor from this pin to the phase pin and a diode from v ccdr to this pin (cathode versus boot). 9pgnd this pin has to be connected closely to the low-side mosfet(s) source in order to reduce the noise injection into the device. 10 lgate this pin is connected to the low-side mosfet(s) gate. 11 v ccdr 5v internally regulated voltage. it is used to supply the internal drivers. filter it to ground with a 1uf ceramic cap. 12 v cc supply voltage pin. the operative supply voltage range is from 4.5v to 14v. table 3. pin functions dsonls r 2 ocl r ocl i valley i ? ? = dsonhs r och r och i peak i ? =
electrical characteristics l6725 8/27 4 electrical characteristics v cc = 12v, t a = 25c unless otherwise specified. table 4. electrical characteristics symbol parameter test condition min. typ. max. unit v cc supply current i cc v cc stand by current ss to gnd 7 9 ma v cc quiescent current hg = open, lg = open, ph=open 8.5 10 power-on v cc tu r n - o n v cc threshold v och = 1.7v 4.0 4.2 4.4 v tu r n - o f f v cc threshold v och = 1.7v 3.6 3.8 4.0 v v in ok tu r n - o n v och threshold 1.1 1.25 1.47 v tu r n - o f f v och threshold 0.9 1.05 1.27 v v ccdr regulation v ccdr voltage v cc =5.5v to 14v i dr = 1ma to 100ma 4.555.5v soft start and inhibit i ss soft start current ss = 2v 7 10 13 a ss = 0 to 0.5v 20 30 45 oscillator f osc accuracy 237 250 263 khz 450 500 550 khz ? v osc ramp amplitude 2.1 v output voltage v fb output voltage 0.597 0.6 0.603 v
l6725 electrical characteristics 9/27 symbol parameter test condition min. typ. max. unit error amplifier r earef earef input resistance vs. gnd 70 100 150 k ? i fb i.i. bias current v f = 0v 0.290 0.5 a ext ref clamp 2.3 v v offset error amplifier offset vref = 0.6v -5 +5 mv g v open loop voltage gain guaranteed by design 100 db gbwp gain-bandwidth product guaranteed by design 10 mhz sr slew-rate comp = 10pf guaranteed by design 5v/ s gate drivers r hgate_on high side source resistance v boot - v phase = 5v 1.7 ? r hgate_off high side sink resistance v boot - v phase = 5v 1.12 ? r lgate_on low side source resistance v ccdr = 5v 1.15 ? r lgate_off low side sink resistance v ccdr = 5v 0.6 ? protections i och och current source v och = 1.7v 90 100 110 ? i ocl ocl current source 90 100 110 ? ovp over voltage trip (v fb / v earef ) v fb rising v earef = 0.6v 120 % v fb falling v earef = 0.6v 117 % table 4. electrical characteristics
l6725 device description 10/27 5 device description the controller provides complete control logic and protec tion for flexible and cost-effective dc- dc converters. it is designed to drive n-chan nel mosfets in a synchronous rectified buck topology. the output voltage of the converter can be precisely regulated down to 600mv with a maximum tolerance of 0.8%, when the internal reference is used. the device allows also using an external reference (0v to 2.5v) for th e regulation. the device provides voltage-mode control. the switching frequency can be set at two different values: 250khz or 500khz. the error amplifier features a 10mhz gain-bandwidth -product and 5v/s slew-rate that permits to realize high converter bandwidth for fast transient response. the pwm duty cycle can range from 0% to 100%. the device protects against over current conditions providing a constant- current-protection during the soft-start phase and entering in hiccup mode in all the other conditions. the device monitors the current by using the r ds(on) of both the high-side and low- side mosfet(s), eliminating the need for a current sensing resistor and guaranteeing an effective over-current-protectio n in all the application conditi ons. other features are over- voltage-protection and thermal shutdown. the device is available in so16n package. 5.1 oscillator the switching frequency can be fixed to two values: 250khz or 500khz by setting the proper voltage at the earef pin (see table 3. pins function and section 4.3 internal and external reference). 5.2 internal ldo an internal ldo supplies the internal circuitry of the device. the input of this stage is the v cc pin and the output (5v) is the v ccdr pin. the ldo can be by-pass ed, providing directly a 5v voltage to v ccdr . in this case v cc and v ccdr pins must be shorted together as shown in figure 3 . v ccdr pin must be filtered with a 1uf capacitor to sustain the internal ldo during the recharge of the bootstrap capacitor.
l6725 device description 11/27 5.3 bypassing the ldo to avoid the voltage drop with low vcc if v cc 5v the internal ldo works in dropout with an output resistance of about 1 ? . the maximum ldo output current is about 100ma and so the output voltage drop is 100mv, to avoid this the ldo can be bypassed. 5.4 internal and external references it is possible to set the internal/external reference and the switching frequency by setting the proper voltage at the earef pin. the maximum value of the external reference depends on the v cc : with v cc = 4v the clamp operates at about 2v (typ.), while with v cc greater than 5v the maximum external reference is 2.5v (typ.). v earef from 0% to 80% of v ccdr -> external reference/fsw=250khz v earef from 80% to 95% of v ccdr -> v ref = 0.6v/fsw=500khz v earef from 95% to 100% of v ccdr -> v ref = 0.6v/fsw=250khz providing an external reference from 0v to 450mv the output voltage will be regulated but some restrictions must be considered: the minimum ovp threshold is set at 300mv; the under-voltage-protection doesn't work; to set the resistor divider it must be considered that a 100k pull-down resistor is integrated into the device (see figure 4. ). finally it must be taken into account that the voltage at the earef pin is captured by the device at the start-up when v cc is about 4v. figure 3. bypassing the ldo
device description l6725 12/27 5.5 error amplifier 5.6 soft start when both v cc and v in are above their turn-on thresholds (v in is monitored by the och pin) the start-up phase takes place. otherwise the ss pin is internally shorted to gnd. at start-up, a ramp is generated charging the external capacitor c ss with an internal current generator. the initial value for this current is 35a and charges the capacitor up to 0.5v. after that it becomes 10a until the final charge value of approximately 4v (see figure 5. ). figure 4. error amplifier reference figure 5. soft-start phase. t t 0.5v 4v v cc v in v ss 4.2v 1.25v
l6725 device description 13/27 the output of the error amplifier is clamped with this voltage (v ss ) until it reaches the programmed value. no switching activity is observable if v ss is lower than 0.5v and both mosfets are off. when v ss is between 0.5v and 1.1v the low-side mosfet is turned on. as v ss reaches 1.1v (i.e. the oscillator triangul ar wave inferior limit) even the high-side mosfet begins to switch and the output voltage starts to increase. during the soft-start phase the current can?t be reversed in order to allow pre-biased start-up (see figure 6. and figure 7. ). if an over current is detected during the soft-start phase, the device provides a constant- current-protection. in this way, in case of short soft-start time and/or small inductor value and/or high output capacitors value, the converter can start in any case, limiting the current ( chapter 5.8: monitoring and protections on page 14 ). the soft-start phase ends when vss reaches 3.5v. after that the over-current-protection triggers the hiccup mode. figure 6. start-up without pre-bias figure 7. start-up with pre-bias lgate v out i l v ss v ss i l v out lgate
device description l6725 14/27 5.7 driver section the high-side and low-side drivers allow using di fferent types of power mosfets (also multiple mosfets to reduce the r dson ), maintaining fast switching tr ansitions. the low-side driver is supplied by v ccdr while the high-side driver is supplie d by the boot pin. a predictive dead time control avoids mosfets cross-conduction maintaining very short dead time duration in the range of 20ns. the control monitors the ph ase node in order to sense the low-side body diode recirculation. if the phase node voltage is less than a certain threshold (-350mv typ.) during the dead time, it will be reduced in the next pwm cycle. th e predictive dead time control doesn?t work when the high-side body diode is conducting because the phase node doesn?t go negative. this situation happens when the converte r is sinking current for example and, in this case, an adaptive dead time control operates. 5.8 monitoring and protections the output voltage is monitored by means of pin fb. the device provides over-voltage- protection: when the voltage sensed on fb pin reaches a value 20% (typ.) greater than the reference the low-side driver is turned on as long as the over voltage is detected (see figure 8 ). the device realizes the over-current-protection (ocp) sensing the current both on the high-side mosfet(s) and the low-side mosfet(s) and so 2 current limit thresholds can be set (see och pin and ocl pin in table 3: pin functions ): peak current limit valley current limit the peak current protection is active when the high-side mosfet(s) is turned on, after a masking time of 100ns. the valley-current-protection is enabled when the low-side mosfet(s) is turned on after a masking time of 500ns. if, when the soft-start phase is completed, an over current event occurs during the on time (peak-current-protection) or during the off time (valley- current-protection) the device enters in hiccup mode: the high-side and low-side mosfet(s) are turned off, the soft-start capacitor is discharged with a constant current of 10a and when the voltage at the ss pin reaches 0. 5v the soft-start phase restarts (see figure 9 ). figure 8. ovp lgate fb
l6725 device description 15/27 5.9 hiccup mode during the soft-start phase the ocp provides a constant-current-protection. if during the t on the och comparator triggers an over current the high-side mosfet(s) is immediately turned off (after the masking time and the internal dela y) and returned on at the next pwm cycle. the limit of this protection is that the t on cannot be less than masking time plus propagation delay, because during the masking time the peak-current -protection is disabled. in case of very hard short circuit, even with this short t on , the current could escalate. the valley-current-protection is very helpful in this case to limit the current. if during the off-time the ocl comparator triggers an over current, the high-side mosfet(s) is not turned on until the current is over the valley- current-limit. this implie s that, if it is necessary, some pu lses of the high-side mosfet(s) will be skipped, guaranteeing a maximum current due to the following formula: 5.10 thermal shutdown when the junction temperature reaches 150c 10c the device enters in thermal shutdown. both mosfets are turned off and the soft-s tart capacitor is rapidly discharged with an internal switch. the device does not restart until the junction temperature goes down to 120c and, in any case, until the voltage at the soft-start pin reaches 500mv. figure 9. constant current and hiccup mode during an ocp. vss vcomp i l min on valley max t l vout vin i i , ? ? + = (1)
application details l6725 16/27 6 application details 6.1 inductor design the inductance value is defined by a compromi se between the transient response time, the efficiency, the cost and the size. the inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current ( ? i l ) between 20% and 30% of the maximum output current. the inductance value can be calculated with the following relationship: where f sw is the switching frequency, v in is the input voltage and v out is the output voltage. figure 10 shows the ripple current vs. the output voltage for different values of the inductor, with v in = 5v and v in = 12v at a switching frequency of 500khz. increasing the value of the inductance reduces the ripple current but, at the same time, increases the converter response time to a load transient. if the compensation network is well designed, during a load transient the device is able to set the duty cycle to 100% or to 0%. when one of these conditions is reached, the re sponse time is limited by the time required to change the inductor current. during this time the output current is supplied by the output capacitors. minimizing the re sponse time can minimize the output capacitor size. figure 10. inductor current ripple. vin vout i fsw vout vin l l ? ? ? ? ? (2) 0 1 2 3 4 5 6 7 8 01234 output voltage (v) inductor current rippl v in = 5 v , l=500nh v in = 5 v , l = 1 .5 u h v in = 1 2 v , l = 2 u h v in = 1 2 v , l = 1 u h
l6725 application details 17/27 6.2 output capacitors the output capacitors are basic components for the fast transient response of the power supply. for example, during a positive load transi ent, they supply the current to the load until the converter reacts. the controller recognizes imme diately the load transie nt and sets the duty cycle at 100%, but the current slope is limited by the inductor value. the output voltage has a first drop due to the current variation inside t he capacitor (neglecting the effect of the esl): moreover, there is an additional drop due to th e effective capacitor discharge that is given by: where d max is the maximum duty cycle value that in the l6725 is 100%. usually the voltage drop due to the esr is the biggest one while th e drop due to the capacitor discharge is almost negligible. moreover the esr value also af fects the voltage static ripple, that is: 6.3 input capacitors the input capacitors have to sustain the rms current flowing through them, that is: where d is the duty cycle. the equation reaches its maximum value, i out /2 with d = 0.5. the losses in worst case are: esr iout vout esr ? ? = ? (3) ) max min , ( 2 2 vout d vin cout l iout vout cout ? ? ? ? ? ? = ? (4) l i esr vout ? ? = ? (5 ) ) 1 ( d d iout irms ? ? ? = (6) 2 ) 5 . 0 ( iout esr p ? ? = (7)
application details l6725 18/27 6.4 compensation network the loop is based on a voltage mode control ( figure 11 ). the output voltage is regulated to the internal/external reference voltage and scaled by the external resistor divider. the error amplifier output v comp is then compared with the oscillato r triangular waveform to provide a pulse-width modulated (pwm) with an amplitude of v in at the phase node. this waveform is filtered by the output filter. the modulator transfe r function is the small signal transfer function of v out /v comp . this function has a double pole at frequency f lc depending on the l-c out resonance and a zero at f esr depending on the output capacitor?s esr. the dc gain of the modulator is simply the input voltage v in divided by the peak-to-peak oscillator voltage: v osc . the compensation network consists in the internal error amplifier, the impedance networks z in (r3, r4 and c20) and z fb (r5, c18 and c19). the compensation network has to provide a closed loop transfer function with the highest 0db crossing frequency to have fastest transient response (but a lways lower than f sw /10) and the highest gain in dc conditions to minimize the load regulation error. a stable control loop ha s a gain crossing the 0db axis with -20db/decade slope and a phase margin greater than 45. to locate poles and zeroes of the compensation networks, the following suggestions may be used: modulator singularity frequencies: compensation network singularity frequencies: figure 11. compensation network cout l lc ? = 1 cout esr esr ? = 1 (8) (9) ? ? ? ? ? ? ? ? + ? ? = 19 18 19 18 5 1 1 c c c c r p 20 4 2 1 c r p ? = (10) (11) 19 5 1 1 c r z ? = () 4 3 20 2 1 r r c z + ? = (12) (13)
l6725 application details 19/27 compensation network design: ? put the gain r 5 /r 3 in order to obtain the desired converter bandwidth: ? place z1 before the output filter resonance lc ; ? place z2 at the output filter resonance lc ; ? place p1 at the output capacitor esr zero esr ; ? place p2 at one half of the switching frequency; ? check the loop gain considering the error amplifier open loop gain. figure 12. asymptotic bode plot of converter's open loop gain lc c vosc vin r r ? ? ? ? ? = 3 5 (14)
l6725 demoboard l6725 20/27 7 l6725 demoboard 7.1 description l6725 demoboard realizes in a four layer pcb a step-down dc/dc converter and shows the operation of the device in a general purpose app lication. the input voltage can range from 4.5v to 14v and the output voltage is at 3.3v. the mo dule can deliver an output current in excess of 20a. the switching frequency is set at 250 khz (controller free-running f sw ) but it can be set to 500khz acting on the earef pin. figure 13. demoboard schematic table 5. demoboard part list reference value manufacturer package supplier r1 1k ? neohm smd 0603 ifarcad r2 1k ? neohm smd 0603 ifarcad r3 4k7 r4 2k7 neohm smd 0603 ifarcad r5 0 ? neohm smd 0603 ifarcad r6 n.c. neohm smd 0603 ifarcad r7 2k neohm smd 0603 ifarcad r8 10 ? neohm smd 0603 ifarcad r9 1k5 neohm smd 0603 ifarcad r10 2.2 ? neohm smd 0603 ifarcad gout r2 gi n l1 q 1 - 3 q4- 6 d3 5 u1 l6725 vin vout 8 och c11 r9 c9 9 10 6 7 hgat e phas e lgat e pgnd 3 vcc 12 vcc 2 ss c4 boot d1 11 vccdr c1 0 1 vfb comp r3 r1 c1 c2 c3 r4 r7 4 earef c7 r 8 16 15 gnd ocl r10 r11 c12-c13 c16-c19 c5 r 6 r5 c 8 j1 r12 c15 ext ref j2
l6725 l6725 demoboard 21/27 r11 2.2 ? neohm smd 0603 ifarcad r12 n.c. neohm smd 0603 ifarcad c1 4.7nf kemet smd 0603 ifarcad c2 47nf kemet smd 0603 ifarcad c3 1nf kemet smd 0603 ifarcad c4 100nf kemet smd 0603 ifarcad c5 100nf kemet smd 0603 ifarcad c6 n.c. / / / c7 100nf kemet smd 0603 ifarcad c8 4.7uf 20v avx sma6032 ifarcad c9 1nf kemet smd 0603 ifarcad c10 1uf kemet smd 0603 ifarcad c11 220nf kemet smd 0603 ifarcad c12-13 3x 15uf / / st (tdk) c15n.c./// c16-19 2x 330 f / / st (poscap) l1 1.8 h panasonic smd st d1 stps1l30m st do216aa st d3 n.c. / / / q1-q2 sts12nh3ll st so8 st q4-q5 sts25nh3ll st so8 st u1 l6725 st so16n st table 6. other inductor manufacturer manufacturer series inductor va lue (h) saturation current (a) wurth elektronic 744318180 1.8 20 sumida cdep134-2r7mc-h 2.7 15 epcos hpi_13 t640 1.4 22 tdk spm12550t-1r0m220 1 22 toko fda1254 2.2 14 coiltronics hcf1305-1r0 1.15 22 hc5-1r0 1.3 27 table 5. demoboard part list
l6725 demoboard l6725 22/27 table 7. other capacitor manufacturer manufacturer series capacitor value(f) rated voltage (v) tdk c4532x5r1e156m 15 25 c3225x5r0j107m 100 6.3 nippon chemi-con 25ps100mj12 100 25 panasonic ecj4yb0j107m 100 6.3 figure 14. demoboard efficiency figure 15. pcb layout: top layer figure 16. pcb layout: power ground layer fsw =400khz 75.00% 80.00% 85.00% 90.00% 95.00% 13579111315 iout (a) efficien f sw = 500khz v in = 5v v in = 12v l6725
l6725 l6725 demoboard 23/27 figure 17. pcb layout: signal-ground layer figure 18. pcb layout: bottom layer
package mechanical data l6725 24/27 8 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
l6725 package mechanical data 25/27 table 8. so16n mechanical data figure 19. package dimensions dim. mm inch min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.020 c1 45 (typ.) d (1) 1. "d" and "f" do not include mold flash or protrusions -mold flash or protrusions shall not exceed 0.15mm (.006inc.) 9.8 10 0.386 0.394 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f (1) 3.8 4.0 0.150 0.157 g 4.60 5.30 0.181 0.208 l 0.4 1.27 0.150 0.050 m 0.62 0.024 s 8 (max.)
revision history l6725 26/27 9 revision history table 9. revision history date revision changes 20-dec-2005 1 initial release. 30-may-2006 2 new template, thermal data updated 26-jun-2006 3 note page 5 deleted
l6725 27/27 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of L6725TR

	To Download L6725TR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .