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general description the gd16367b and gd16368b is a chip- set intended for use in sdh stm-1/ sonet oc-3 and pdh e4 systems, where electrical cmi coded interface is needed. the chip set is designed to take care of all processing above 78 mhz in an stm-1/oc-3/e4 interface, accommodat - ing both electrical (cmi) and optical (nrz) data format. hence the same board may be configured as stm-1o, stm-1e, e4o, or e4e at system integra - tion level. the encoder - gd16367b the mux/encoder device generates the cmi coded data signal and associated clock at 280/311 mhz. the reference in- put clock for the clock synthesis may be selected from two individual inputs, 70/ 78 mhz or 17/19 mhz allowing for pro- grammable selection between reference inputs for e4 or stm-1/oc-3. the cmi encoder may be switched off when the interface is optical. the decoder - gd16368b the demux/decoder device provides clock and data recovery extracting the 280/311 mhz clock of the incoming cmi signal and a decoder that turns cmi to nrz. cmi code violations are detected and signaled by the codv output. the cmi decoder may be switched off when the interface is optical both devices provide selectable 2, 4 or 8 bit parallel interface to the processing device for maximum flexibility. the phase relation between parallel data and clock is selectable in four phases (0 ,90 , 180 , 270 ) providing flexible timing between the system and the devices. preliminary features l integrates all high-speed signal processing above 78 mhz. l itu-t g.703 cmi encoding/decoding for stm-1 and e4 electrical inter - faces. l meet g.751, g.823 and g.825 for jitter tolerance and jitter generation. l remote and local loops available. l cmi disable function for board level configuration for optical interface. l selectable 2, 4 or 8 bit parallel inter- face for maximum flexibility. l selectable 0 ,90 , 180 , 270 phase relation for parallel data i/o. l 3.3 v lvpecl high speed i/o?s. l cmos interface to system asic. l power consumption typical: ? 400 mw for gd16367b ? 600 mw for gd16368b l 3.3 v supply ; 5 v for vco. l designed for low cost and volume production. l high-speed bicmos technology. l package 52 pin pqfp (10 x 10 mm). applications l tele communication: ? sdh stm-1 ? sonet oc-3 ? pdh e4 140 ? 155 mbit/s cmi encoder/ decoder gd16367b/gd16368b data sheet rev. 14 cmi / nrz cmi / nrz slsop slsip ckrf llsop llson llcop llcon llcin llcip llsin llsip ckru sip sel1 sel2 sel3 llb slb pw1 pw2 llb slb pw1 pw2 icv sel1 sel2 sel3 sel4 sin dou0 din0 dou7 din7 dick dock codv slsin slson sop son cko ckn pdh-ref stm-ref 280 / 311 mhz 140 / 151 mhz 17-78mhz vco lpf gd16368b line interface unit stm-1 processing asic gd16367b f4 stm-1 17-78mhz 2/4/8bitnrz 2/4/8bitnrz
functional details, both devices general the gd16367b/gd16368b chip set pro - vides transmission of 140 mbit/s (e4) and 155 mbit/s (stm-1/oc-3). both optical nrz signal transmission and electrical cmi-coded signal trans - mission are supported by the internal selectable cmi-encoding/decoding circuitry. selectable 2/4/8 bit system interface is provided. 140/155 mbit/s and nrz/cmi clock frequencies the vco tuning range covers the clock frequencies of 280 mhz to 311 mhz. the actual clock frequency is determined by reference clocks and received data. the 280/311 mhz are used for cmi-oper - ation. when operating in nrz-mode the vco clock is divided by 2. nrz/cmi and parallel width selection the devices can operate in different line and system modes; selected by sel1, pw2, and pw1 (see table 1). the bit order at the system site is defined with bit 0 as the first bit transferred (din0 for the transmitter and dou0 for the re - ceiver). line/system loop back connecting the differential line loop sig - nals and clocks (llxxx) from gd16368b to gd16367b allows loop-back of the re - ceived and recovered line signal, when llb is high on both devices. the line loop back is also called remote loop back. connecting the differential system loop signals (slxxx) from gd16367b to gd16368b allows system loop back, when slb is high on both devices. the system loop back is also called a local loop back. loop filters both circuits comprise fully integrated pll functions for re-timing data at the transmit site, and for clock and data re - covery at the receive site. a passive loop filter consisting of a resis - tor and a capacitor is used for each de - vice. the external loop filters are terminated to veea as shown in figure 1 (for the transmitter) and figure 4 (for the receiver). the loop filter values are optimised at the evaluation board gd90367/368. the op- timal values depend on the actual appli- cation. the suggested values in figures 1 and 4 can be used as starting point for the optimisation. data sheet rev. 14 gd16367b/gd16368b page 2 of 14 mode sel1 pw2 pw1 line clock [ frequency/mhz] system clock [frequency/mhz] used bits cmi, 2 bit 0 0 0 280/311 70/78 0 & 1 cmi, 4 bit 0 0 1 280/311 35/39 0...3 cmi, 8 bit 0 1 0 280/311 17/19 0...8 not valid 0 1 1 - - - nrz, 2 bit 1 0 0 140/155 70/78 0 & 1 nrz, 4 bit 1 0 1 140/155 35/39 0...3 nrz, 8 bit 1 1 0 140/155 17/19 0...8 not valid 1 1 1 - - - table 1 nrz/cmi and parallel width selection. this table is common for both devices.
functional details, the transmitter - gd16367b the gd16367b is the encoder/transmit - ter ( see figure 1 ) with: u multiplexer (2/4/8:1) u selectable cmi-encoding u nrz/cmi data and clock differential outputs u selectable system loop back data differential output u selectable line loop back data and clock differential inputs multiplexer the parallel input data (din0...din7) are received by the multiplexer. this is done synchronously with the dick output clock, which is used when counter clock - ing. counter clocking allows 2:1, 4:1 , and 8:1 multiplexing. forward clocking is only possible when operating in the 2:1 mode. a low noise reference clock is recom - mended, as the clock noise within the pll loop bandwidth is transmitted as jit - ter on the serial outputs. the 70/78 mhz clock input (ckr0) is selected when sel4 is low. the 17/19 mhz clock input (ckr1) is selected when sel4 is high. for pdh system rates 17 or 70 mhz is used. for sdh system rates 19 or 78 mhz is used. figure 1. block diagram - gd16367b counter clocking the output clock (dick) is used for clocking out the parallel system data into the mux. the frequency of dick de - pends on the reference clock and the multiplexing mode (see table 1 on page 2 ). four phases timing relation between dinx and dick are provided by the sel2 and sel3 (see ac characteristics on page 11 , and pin list on page 7 ). forward clocking when operated in 2:1 multiplexing mode, a forward clocking scheme can be used: u set pw1=pw2=sel4=0 u connect the forwarded 70/78 mhz clock to ckr0. the control inputs (sel2 and sel3) con - trol the timing relation between dinx and ckr0, see pin list on page 7 . cmi-encoder when the cmi-encoding is enabled (sel1=0), every bit of the 140/155 mbit/s output from the multiplexer is encoded to a 2-bit cmi-word, resulting in a 280/ 311 mbit/s output of the cmi-encoder; and a 280/311 mhz clock (cko/ckn) from the cmi-encoder. see the cmi- coding in table 2. nrz: cmi : note : 0 01 consecutive nrz zeros ?0000..? gives ?01010101...? as cmi-output 1 00/11 consecutive nrz ones ?1111...? gives ?00110011...? as cmi-output table 2 cmi coding. when the cmi-encoding is disabled (sel1=1), the 140/155 mbit/s output from the multiplexer is passed through the cmi-encoder; and a 140/155 mhz clock (cko/ckn) is generated from the cmi-encoder. data sheet rev. 14 gd16367b/gd16368b page 3 of 14 pw1 pw2 icv sel1 llcip llcin llsip llsin clof 2.2 f m 680 w veea llb slb vee vdd vdda slsop sop cko ckru dick slson son ckn sel4 clock synth. mux cmi encoder sel3 sel2 ckr1 ckr0 din7 din0 seltck tck
outputs the outputs from the multiplexer are fed to the lvpecl output stages. see figures 2 and 3 for output termina - tion. the serial data output (sop/son) is ac - companied by a differential clock output (cko/ckn). see ac characteristics on page 11 . slsop/slson is enabled when slb is high. when slb is low slsop=0 and slson=1; thus avoiding noise injection at normal operation. the clock output (ckru) provides a 70/78 mhz clock suitable for driving the gd16368b receiver (connect to ckrf input). figure 2. lvpecl output termination, ac-coupled. figure 3. lvpecl output termination, dc-coupled. data sheet rev. 14 gd16367b/gd16368b page 4 of 14 180 w 50 w 180 w 100nf 100nf 0v (gnd) 2v (vcc -1.3v) 50 w lvpecl output input lvpecl 50 w 1.3v (vcc -2v) 50 w lvpecl output input lvpecl e.g. gd16360 e.g. gd16360
functional details, the receiver - gd16368b the gd16368b is the receiver (see figure 4 ) with: u clock&data recovery (cdr) u selectable cmi-decoding u demultiplexer (1:2/4/8) u selectable system loop back data differential input u selectable line loop back / 1:1 cdr data and clock outputs inputs the serial input is selected by slb. for normal operation, sip/sin is selected when slb is low. for system loop back operation, slsip/slsin is selected when slb is high. the selected serial input data is the input of the cdr, where the clock and data is recovered. the pll constantly attempts to lock to the incoming data stream. in case the in - coming data signal is lost, the vco will drift away from the ckrf reference fre - quency. the vco is monitored by a built-in lock detector. when it drifts more than 500 ppm (or 2000 ppm, selectable) away from the reference frequency, it is ?kicked back? to the reference frequency and starts hunting for incoming data again. ckrf does not have any part in the jitter performance (as long as the incoming data frequency is within 500 ppm of the required 70/78 mhz). figure 4. block diagram - gd16368b cmi-decoder when the cmi-decoding is enabled (sel1=0), 280/311 mbit/s is decoded as 2-bits cmi-words into 1-bit nrz 140/ 155 mbit/s. the internal 140/155 mhz clock is aligned to the cmi-words. see table 2 on page 3 for the cmi-coding. when the cmi-decoding is disabled (sel1=1), the 140/155 mbit/s data signal is passed unchanged through the cmi- decoder. outputs the 140/155 mbit/s recovered (and de - coded) data is de-multiplexed into 2, 4, or 8 parallel data bits (dou0...dou7) se - lected by pw1 and pw2 (see table 1 on page 2 ). dock is the output clock synchronous to the parallel data (see ac characteristics on page 11 ). the phase can be adjusted with sel2 and sel3 (0/90/180/270, see pin list). if the incoming data stream is lost, dock will be floating within a +/-500(2000) ppm window around the ckrf frequency (di- vided by 1, 2, or 4 depending of the par- allel bit rate). in cmi-mode, the codv output will be signalling errors if the sig- nal is lost. data sheet rev. 14 gd16367b/gd16368b page 5 of 14 1f m 20 w ckrf llson llcon llsop llcop clof veea sel1 sel2 sel3 pw1 pw2 dou0 sip seltck tck slsip slb llb lds1 lds2 sin slsin dou7 cdr cmi decoder de- mux dock codv vee vdd vdda
practical considerations general the pcb should be multilayer in order to optimise high-speed signal performance. our evaluation board gd90367/368 uses a standard fr4 pcb. use shortest possible conductors for the signals to the line interfaces. the high- speed serial data lines should be de - signed as transmission lines with con - stant trace width to ensure constant impedance along the transmission line. any coupling capacitors should have foot print width matching the trace width. spe - cial attention must be paid to the layout where the signal trace meets connectors in/out of the board, the solder pads for e.g. sma connectors must be kept very small to ensure good impedance match. de-coupling capacitors should be applied to each power supply pin. care should be taken to reduce ground bounce. the line loop signal and clock must be terminated close to the transmitter device (gd16367b). the decoder/demux has no internal in- put termination. hence the input lines (sip/sin) should be terminated to a de- coupled +2 v dc point close to the gd16368b device. the system loop signal and clock must be terminated close to the receiver de- vice (gd16368b). transmission cable con- nection the high-speed differential lvpecl line interface of the gd16367b/368b devices can easily be interfaced with an e4 or stm-1 transmission cable. a cable re - ceiver/equalizer is required at the re - ceiver site, while a cable driver is required at the transmitter site. giga provides an integrated device (gd16360) which provides cable equal - izer, cable driver, and additionally a los detector ? for two channels. data sheet rev. 14 gd16367b/gd16368b page 6 of 14
pin list, gd16367b mnemonic: pin no.: pin type: description: sop, son 6, 7 lvpecl-out serial differential data output. cko, ckn 9, 10 lvpecl-out differential 140/155 or 280/311 mhz clock out, selected by sel1. din0, din1, din2, din3, din4, din5, din6, din7 38, 37, 36, 34, 33, 31, 30, 29 cmos-in 2, 4 or 8-bit wide data input. din0 is transferred as the first bit, fol - lowed by din1, .... dick 41 cmos-out 70/78, 34/39 or 17/19 mhz clock output selected by pw1 and pw2. ckr0, ckr1 20, 21 cmos-in reference clock inputs for the clock synthesis. ckr0: 70/78 mhz, ckr1: 17/19 mhz. ckr0 can be used for forward clocking (70/78 mhz) in 2-bit mode. sel1 45 cmos-in when low the cmi encoder is enabled and cko/ckn is 280/311 mhz. when high, data is passed unchanged (nrz mode) and cko/ckn is 140/155 mhz. sel4 25 cmos-in when high ckr1 is used as reference for the pll. when low ckr0 is used. sel2, sel3 23, 24 cmos-in dinx input phase versus dick/ckrx select: sel3 sel2 00 t del =0 11 t del =90 10 t del = 180 01 t del = 270 ckru 42 cmos-out 70/78 mhz clock output. may be used as input to the gd16368b ckrf pin. clof 18 anl ext. loop filter pin. connect 2.2 m f in series with 680 w from this pin to the veea pin. llsip, llsin 48, 47 lvpecl-in line loop-back serial differential data, 140/155 mhz. to be connected from llsop/llson of the gd16368b. llcip, llcin 51, 50 lvpecl-in line loop-back serial differential clock, 140/155 mbit/s. to be connected from llcop/llcon of the gd16368b. llb 49 cmos-in when high, line loop-back is enabled. slsop, slson 4, 3 lvpecl-out switch loop-back serial differential data, 140/155 mbit/s. to be connected to slsip/slsin of the gd16368b. slb 2 cmos-in when high, switch loop-back is enabled. pw1, pw2 44, 43 cmos-in parallel port width / parallel clock rate: pw2 pw1 0 0 2 bit, din0..din1 - dick = 70/78 mhz 0 1 4 bit, din0..din3 - dick = 35/38 mhz 1 0 8 bit, din0..din7 - dick = 17/19 mhz 1 1 not valid icv 28 cmos-in insert code violation. when shifted high, one violation is inserted (?1" level toggled). tck 12 anl-in test clock input - for test purpose only. connect to veea for nor - mal operation. seltck 14 anl-in test clock enable - for test purpose only. connect to vdd for nor - mal operation. vdd 5, 8, 11, 22, 26, 32, 35, 40, 46, 52 pwr 3.3 v power. vdda 16, 19 pwr 5 v power for vco. vee 1, 13, 27, 39 pwr 0 v power. veea 15 pwr 0 v power for vco. nc 17 no connected. data sheet rev. 14 gd16367b/gd16368b page 7 of 14
pin list, gd16368b mnemonic: pin no.: pin type: description: sip, sin 4, 5 lvpecl-in differential serial data input. dou0, dou1, dou2, dou3, dou4, dou5, dou6, dou7 38, 37, 35, 34, 32, 31, 29, 28 cmos-out 2, 4 or 8-bit wide data output. dou0 is the first received bit, fol - lowed by dou1, .... dock 24 cmos-out 70/78, 34/39 or 17/19 mhz clock output selected by pw1 and pw2. codv 25 cmos-out code violation output. high for one 70/78 mhz clock period if error detected, otherwise low. disabled (low) in nrz-mode. sel1 44 cmos-in when low the cmi decoder is enabled. when high, data is passed unchanged (nrz mode). sel2, sel3 43, 42 cmos-in doux output phase versus dock select: sel3 sel2 00 t del =0 11 t del =90 10 t del = 180 01 t del = 270 ckrf 41 cmos-in 70/78 mhz reference clock input for the cdr block. used to en - sure fast acquisition to incoming data and to ensure stable dock output clock in absence of data. clof 48 anl ext. loop filter pin. connect 1 m f in series with 20 w from this pin to the neighbour veea pin. llsop, llson 19, 20 lvpecl-out line loop-back serial differential data, 140/155 mhz, cmi or nrz according to sel1. to be connected to llsip/llsin of the gd16367b. llcop, llcon 16, 17 lvpecl-out line loop-back serial differential clock, 140/155 mhz or 280/311 mhz according to sel1. to be connected to llcip/llcin of the gd16367b. llb 18 cmos-in when high, line loop-back is enabled. slsip, slsin 8, 7 lvpecl_in switch loop-back serial differential data, 140/155 mhz. to be connected to slsop/slson of the gd16367b. slb 10 cmos-in when high, switch loop-back is enabled. pw1, pw2 22, 23 cmos-in parallel port width / parallel clock rate: pw1 pw2 0 0 2 bit, dou0..dou1 ? dock = 70/78 mhz 1 0 4 bit, dou0..dou3 ? dock = 35/38 mhz 0 1 8 bit, dou0..dou7 ? dock = 17/19 mhz 1 1 not valid tck 2 anl-in test clock input, for test purpose only. connect to vee. seltck 52 anl-in test clock select, for test purpose only. connect to vdd. lds1, lds2 12, 46 cmos-in lock detect selection: lds1 lds2 lock mode 1 1 auto 2000 ppm (default) 1 0 auto 500 ppm 0 1 manual select bb 0 0 manual select pfc vdd 3, 6, 9,11,15,21,26, 30, 33, 36, 40, 45 pwr 3.3 v power. vdda 47, 50 pwr 5 v power for vco. vee 1, 13, 14, 27, 39 pwr 0 v power. veea 51 pwr 0 v power for vco. nc 49 nc no connected. data sheet rev. 14 gd16367b/gd16368b page 8 of 14
package pinout figure 5. gd16367b, 52 pin pqfp - top view figure 6. gd16368b, 52 pin pqfp - top view data sheet rev. 14 gd16367b/gd16368b page 9 of 14 48 49 50 51 52 47 46 45 44 43 42 41 40 39 36 38 35 37 34 33 32 31 30 29 28 27 23 24 25 26 22 21 20 19 18 17 16 15 14 12 13 11 10 9 8 7 6 5 4 3 2 1 clof nc vdda veea seltck vdda lds2 vdd sel1 sel2 sel3 ckref vdd vee vdd dou0 dou2 dou1 dou3 vdd dou4 dou5 dou6 dou7 vdd vee pw2 dock codv vdd pw1 vdd llson llsop llb llcon llcop vdd vee lds1 vee vdd slb vdd slsip slsin vdd sin sip vdd tck vee 48 49 50 51 52 47 46 45 44 43 42 41 40 39 36 38 35 37 34 33 32 31 30 29 28 27 23 24 25 26 22 21 20 19 18 17 16 15 14 12 13 11 10 9 8 7 6 5 4 3 2 1 llsip llb llcin llcip vdd llsin vdd sel1 pw1 pw2 ckru dick vdd vee din2 din0 vdd din1 din3 din4 vdd din5 din7 icv din6 vee sel2 sel3 sel4 vdd vdd ckr1 ckr0 vdda clof nc vdda veea seltck tck vee vdd ckn cko vdd son sop vdd slsop slson slb vee
maximum ratings these are the limits beyond which the component may be damaged. all voltages are referenced to vee unless otherwise noted. symbol: characteristic: conditions: min.: typ.: max.: unit: v dd ,v dda supply voltage 0 6 v v o max output voltage lvpecl/cmos -0.5 v dd + 0.5 v i o , lvpecl max output current lvpecl 40 ma i o, cmos max output current cmos -10 10 ma v i max input voltage lvpecl/cmos -0.5 v dd + 0.5 v i i max input current lvpecl/cmos -1.0 1.0 ma t o operating temperature junction -55 +150 e c t s storage temperature junction -65 +175 e c dc characteristics t ambient =0 cto75 c. q ja =55 c/w, still air, (gd16367b). q ja =50 c/w, still air, (gd16368b) all voltages in table are referred to vee unless otherwise noted. symbol: characteristic: conditions: min.: typ.: max.: unit: v dd supply voltage note 1 3.15 3.30 3.60 v v dda supply voltage, vco 4.7 5.00 5.25 v i dd,gd16368b supply current, gd16368b note 2 140 210 ma i dda,gd16368b supply current, gd16368b note 2 10 20 ma i dd,gd16367b supply current, gd16367b note 2 95 125 ma i dda,gd16367b supply current, gd16367b note 2 10 20 ma v ih ,lvpecl lvpecl differential input hi voltage note 3 v dd -1.75 v dd -0.45 v v il ,lvpecl lvpecl differential input lo voltage note 3 v dd -2.00 v dd -0.70 v v idiff ,lvpecl lvpecl differential input voltage note 3 0.250 0.500 1.400 v i ih, lvpecl lvpecl input hi current v ih lvpecl, max 100 m a i il, lvpecl lvpecl input lo current v il lvpecl, min -100 m a v oh, lvpecl lvpecl output hi voltage note 4 v dd -1.11 v dd -0.67 v v ol, lvpecl lvpecl output lo voltage note 4 v dd -2.00 v dd -1.50 v v odiff, lvpecl lvpecl output differential voltage note 4 0.390 1.330 v v ih ,cmos cmos input hi voltage note 5 v dd x0.8 v dd v v il ,cmos cmos input lo voltage note 5 0 v dd x0.2 v i ih cmos cmos input hi current v ih cmos, max 100 m a i il cmos cmos input lo current v il cmos, min -100 m a v oh cmos cmos output hi voltage i oh = 1ma v dd - 0.2 v dd v v ol cmos cmos output lo voltage i ol = -1ma 0 0.2 v note 1: supply voltage difference limits: 0.7 v v dda - v dd 1.8 v. note 2: supply currents are measured without loads on the (lvpecl/cmos) outputs. note 3: although v idiff ,lvpecl may vary within v ih ,max and v il ,min , it must not exceed v idiff ,max . note 4: 50 w termination to v dd -2.0 v. note 5: if not connected, the input is pulled high (approximately 2.6 v) by internal pull-up resistor (48k 20 %). data sheet rev. 14 gd16367b/gd16368b page 10 of 14
ac characteristics gd16367b gd16367b frequency range: jitter: [uip-p] period: [s] specification: e4 200 hz - 3.5 mhz 0.05 10 itu-t g.751 stm-1(cmi) 500 hz - 1.3 mhz 65 khz - 1.3 mhz 0.5 0.075 60 60 de/tm-3017-4 stm-1(opt) 500 hz - 1.3 mhz 65 khz - 1.3 mhz 0.5 0.1 60 60 itu-t g.813 oc3 12 khz - 1.3 mhz 0.1 60 the gd16367b will meet the above specifications for jitter gen - eration when tested in appropriate mode with a jitter free input reference clock applied. gd16368b gd16368b f1 [hz] f2 [hz] f3 [hz] f4 [hz] a1 [ui p-p ] a2 [ui p-p ] specification: e4 200 500 10k 3.5m 1.5 0.075 itu-t g.823 stm-1 (cmi) 500 3.25k 65k 1.3m 1.5 0.075 de/tm-03067 stm-1 (opt) 500 6.5k 65k 1.3m 1.5 0.15 itu-t g.825 oc3 300 6.5k 65k 1.5 0.15 the gd16368b will meet the above specifications for jitter toler - ance when tested in the appropriate mode. data sheet rev. 14 gd16367b/gd16368b page 11 of 14 cko sop/son dick dinx(0 ) o t sa t sb t sc t hc t sd t hd t hd t hd t co dinx(90 ) o dinx(180 ) o dinx(270 ) o dock (0 ) o t a t b t c t d a1 [ui] a2 f2 f3 f4 [hz] f1 (90 ) o (180 ) o (270 ) o codv (0 ) o jitter tolerance according to g.823 and g.825 dock doux codv doux codv doux codv doux codv llcop llsop/n t llco
general symbol: characteristic: conditions: min.: typ.: max.: unit: t a dock to doux valid 1 ns t b dock to doux valid note 1 t/4 + 1 ns t c dock to doux valid note 1 t/2 + 1 ns t d dock to doux valid note 1 3*t/4 + 1 ns t co cko to sop/son valid note 2 0.5 ns t llco llcop to llsop/n valid 0.3 ns t sa set-up time before dick 1 ns t sb set-up time after dick note 3 t/4 - 1 ns t sc set-up time after dick note 3 t/2 - 1 ns t sd set-up time after dick note 3 3*t/4 - 1 ns t ha hold time after dick 1 ns t hb hold time after dick note 3 t/4 + 1 ns t hc hold time after dick note 3 t/2 + 1 ns t hd hold time after dick note 3 3*t/4 + 1 ns r duty duty cycle, ckr0/1, ckrf note 4 40/60 60/40 % d ckrf crkf frequency deviation from nominal line frequency -200 +200 ppm f vco vco frequency range 136 158 mhz t acq-pu acquisition time, gd16367b/368b power up 100 m s t acq-int acquisition time, gd16368b inp. interrupt 10 m s l cid number of consecutive identical digits, gd16368b >120 units t r-lvpecl lvpecl rise time note 5 800 ps t f-lvpecl lvpecl fall time note 5 800 ps t r-cmos cmos rise time note 6 5 ns t f-cmos cmos fall time note 6 3 ns note 1: t equals the period time of dock (one bit period). note 2: also valid for llb operation. the typical llb data & clock delay difference for the gd16367b ( t llsip ? sop/n -t llcop/n ? cko/n ) is 0.2 ns. as the t llco of the gd16368b (llcop to llsop/n) is 0.3 ns (typ.), the resulting t co in llb mode mode is 0.5 ns = 0.3 ns (gd16367b) + 0.2 ns (gd16368b). note 3: t equals the period time of dick (one bit period). note 4: duty cycle measured at v th = 1.4 v note 5: 20-80%,50 w to v dd -2.0 v note 6: 20-80%,10pfand100 m a load. typically, t r =0.5ns+cx0.4 ns/pf; t f =1ns+cx 0.16 ns/pf. data sheet rev. 14 gd16367b/gd16368b page 12 of 14
package outline figure 7. package 52 pin pqfp external references gd90367/368 : data sheet for the evaluation board for the gd16367b and gd16368b chip set (latest revision). itu-t g.751 (11/88) : digital multiplex equipments operating at the third order bit rate of 34368 kbit/s. itu-t g.813 (8/96) : timing characteristics of sdh equipment slave clocks. itu-t g.823 (3/93) : the control of jitter and wander within digital networks based on the 2048 kbit/s hierarchy. itu-t g.825 (3/93) : the control of jitter and wander within digital networks based on sdh. de/tm-3017-4 (draft) : transmission and multiplexing; generic requirements for synchronisation networks. de/tm-03067 (draft) : transmission and multiplexing; the control of jitter and wander in transport networks. data sheet rev. 14 gd16367b/gd16368b page 13 of 14 0.88 +0.15 -0.10 +0.10 -0.05 + 0.25 + 0.25 + 0.10 + 0.10 + 0.05 min/max 2.00 0.65 0.30 0.25/0.50 0.17 max all dimensions are in mm. 13.2 13.2 10.0 10.0 1 52 0.25 0-7 oo gage plane 0.20 c -a- -b- -d- -c- 0.18 c a-b d m
device marking figure 8. device marking - top view ordering information to order, please specify as shown below: product name: type: package type: temperature range: GD16367B-52BA encoder 52 pin pqfp 0..75 e c gd16368b-52ba decoder 52 pin pqfp 0..75 e c gd16367b/gd16368b, data sheet rev. 14 - date: 29 february 2000 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.giga.dk please check our internet web site for latest version of this data sheet. distributor: copyright ? 2000 giga a/s all rights reserved gd16367b . gd16368b .

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