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rev 1.1 512kx36 & 1mx18 sram - 1 - jan. 2005 k7d161874b k7d163674b document title 16m ddr synchronous sram revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsun g electronics will evaluate and reply to your requests and questions on the parameter s of this device. if you have any questions, please contact the samsung branch office near your office, call or cortact headquar ters. rev no. rev. 0.0 rev. 0.1 rev. 0.2 rev. 0.3 rev. 1.0 rev. 1.1 remark advance preliminary preliminary preliminary final final history initial document. change jtag dc operating conditons/ac test conditions -to support 1.8~2.5v v dd , change some items. change dc characteristics (stop clock standby current) -i sb1 : 100 -> 150 change jtag instruction cording - for reserved change dc characteristics (increase operating current) - x36 : add 40ma, x18 : add 60ma add dc characteristics - v in-clk, v dif-clk, v cm-clk add ac input characteristics add input definition draft data oct. 2003 nov. 2003 feb. 2004 feb. 2004 mar. 2004 jan. 2004
rev 1.1 512kx36 & 1mx18 sram - 2 - jan. 2005 k7d161874b k7d163674b ordering information part number organization maximum frequency k7d163674b-hc37 512kx36 375mhz k7d163674b-hc33 333mhz K7D163674B-HC30 300mhz k7d163674b-hc27 275mhz k7d161874b-hc37 1mx18 375mhz k7d161874b-hc33 333mhz k7d161874b-hc30 300mhz k7d161874b-hc27 275mhz general description the k7d163674b and k7d161874b are 18,874,368 bit synchronous pipeline burst mode sram dev ices. they are organized as 524,288 words by 36 bits for k7d163674b and 1,048,576 words by 18 bits for k7d161874b, fabricated using samsung's advanced cmos technology. single differential hstl level clock, k and k are used to initiate the read/write operation and all internal operations are self-timed. at the rising edge of k clock, all addresses and burst control inputs are registered internally. data inputs are registered one c ycle after write addresses are asserted(late write), at the rising edge of k clock for single data rate (sdr) write operations and at risi ng and falling edge of k clock for a double data rate (ddr) write operations. data outputs are updated from output registers off the rising edge s of k clock for sdr read operations and off the rising and f alling edges of k clock for ddr read operations. fr ee running echo clocks are supported which are representive of data output access time for all sdr and ddr operations. the chip is operated with a single +2.5v power supply and is co mpatible with extended hstl input and output. the package is 9x17(153) ball grid array balls on a 1.27mm pitch. features ? 512kx36 or 1mx18 organizations. ? 1.8~2.5v v dd /1.5v v ddq .(1.9v max v ddq ) ? hstl input and outputs. ? single differential hstl clock. ? synchronous pipeline mode of operation with self-timed late write. ? free running active high and active low echo clock output pin. ? asynchronous output enable. ? registered addresses, burst control and data inputs. ? registered outputs. ? double and single data rate burst read and write. ? burst count controllable with max burst length of 4 ? interleved and linear burst mode support ? bypass operation support ? programmable impedance output drivers. ? jtag boundary scan (subset of ieee std. 1149.1) ? 153(9x17) pin ball grid array package(14mmx22mm)
rev 1.1 512kx36 & 1mx18 sram - 3 - jan. 2005 k7d161874b k7d163674b functional block diagram k,k b 1 b 3 b 2 g register ce memory array 512kx36 data out data in advance control sd/dd co clock synchronous buffer internal clock generator ce r/w ld data output strobe data output enable state machine strobe_out s/a array 2 : 1 mux data in register write buffer w/d array echo clock output 36(or 18)x2 36(or 18)x2 36(or18)x2 36(or18)x2 xdin cq,cq dq 36(or 18) select & r/w control output buffer write ce burst counter register address address comparator 2:1 mux dec. 19(or 20) 17(or 18) 17(or 18) 19(or 20) (burst write sa[0:18]( or sa[0:19]) or (1mx18) (2 stage) (2 stage) (burst address) address) pin description pin name pin description pin name pin description k, k differential clocks zq output driver impedance control input sa synchronous address input tck jtag test clock sa 0 , sa 1 synchronous burst address input (sa 0 = lsb) tms jtag test mode select dq synchronous data i/o tdi jtag test data input cq, cq differential output echo clocks tdo jtag test data output b 1 load external address v ref hstl input reference voltage b 2 burst r/w enable v dd power supply b 3 single/double data selection v ddq output power supply g asynchronous output enable v ss gnd lbo linear burst order nc no connection
rev 1.1 512kx36 & 1mx18 sram - 4 - jan. 2005 k7d161874b k7d163674b package pin configurations (top view) k7d163674b(512kx36) * mode pin(6l) is a internally nc. 1 2 3 4 5 6 7 8 9 a v ss v ddq sa sa zq sa sa v ddq v ss b dq dq sa v ss b 1 v ss sa dq dq c v ss v ddq sa sa g sa sa v ddq v ss d dq dq sa v ss v dd v ss sa dq dq e v ss v ddq v ss v dd v ref v dd v ss v ddq v ss f dq cq 1 dq v dd v dd v dd dq cq 2 dq g v ss v ddq v ss v ss kv ss v ss v ddq v ss h dq dq dq v dd k v dd dq dq dq j v ss v ddq v ss v dd v dd v dd v ss v ddq v ss k dq dq dq v ss b 2 v ss dq dq dq l v ss v ddq v ss lbo b 3 mode v ss v ddq v ss m dq cq 1 dq v dd v dd v dd dq cq 2 dq n v ss v ddq v ss v dd v ref v dd v ss v ddq v ss p dq dq nc v ss v dd v ss sa dq dq r v ss v ddq v dd sa sa 1 sa v dd v ddq v ss t dq dq sa v ss sa 0 v ss sa dq dq u v ss v ddq tms tdi tck tdo nc v ddq v ss k7d161874b(1mx18) * mode pin(6l)is a internally nc. 1 2 3 4 5 6 7 8 9 a v ss v ddq sa sa zq sa sa v ddq v ss b nc dq sa v ss b 1 v ss sa nc dq c v ss v ddq sa sa g sa sa v ddq v ss d dq nc sa v ss v dd v ss sa dq nc e v ss v ddq v ss v dd v ref v dd v ss v ddq v ss f nc cq 1 nc v dd v dd v dd dq nc dq g v ss v ddq v ss v ss kv ss v ss v ddq v ss h dq nc dq v dd k v dd nc dq nc j v ss v ddq v ss v dd v dd v dd v ss v ddq v ss k nc dq nc v ss b 2 v ss dq nc dq l v ss v ddq v ss lbo b 3 mode v ss v ddq v ss m dq nc dq v dd v dd v dd nc cq 1 nc n v ss v ddq v ss v dd v ref v dd v ss v ddq v ss p nc dq sa v ss v dd v ss sa nc dq r v ss v ddq v dd sa sa 1 sa v dd v ddq v ss t dq nc sa v ss sa 0 v ss sa dq nc u v ss v ddq tms tdi tck tdo nc v ddq v ss
rev 1.1 512kx36 & 1mx18 sram - 5 - jan. 2005 k7d161874b k7d163674b read operation(single and double) during sdr read operations, addresses and controls are registered at the first rising edge of k clock and then the internal arr ay is read between first and second rising edges of k clock. data outputs are updated from output registers off the second rising edg e of k clock. during ddr read operations, addresses and controls are registered at the first rising edge of k clock, and then the in ternal array is read twice between first and second rising edges of k cl ock. data outputs are updated from output registers sequentia lly by burst order off the second rising and falling edge of k clock. interleave and linear burst opera tion is controlled by lbo pin and the burst count is controllable with the maximum burst length of 4. to avoid data contention,at least one no p operations are required between the last read and the first write operation. write operation(late write) during sdr write operations, addresses and cont rols are registered at the first rising edge of k clock and data inputs are regi stered at the following rising edge of k clock. during ddr write operati ons, addresses and controls are registered at the first rising edge of k clock and data inputs are registered twic e at the following rising and falling edge of k clock. write addresses and data inpu ts are stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully writt en into sram array. echo clock operation free running type of echo clocks are generated from k clock regardless of read, write and nop operations. they will stop operat ion only when k clock is in the stop mode. echo clocks are designed to repres ent data output access time and this allows t he echo clocks to be used as reference to captur e data outputs outputs. bypass read operation bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are identical. for this case, data outputs are from the data in registers instead of sram array. programmable impedance output driver the data output and echo clock driver im pedance are adjusted by an external resi stor, rq, connected between zq pin and v ss , and are equal to rq/5. for example, 250 ? resistor will give an output impedance of 50 ? . output driver impedance tolerance is 15% by test(10% by design) and is periodicall y readjusted to reflect the changes in s upply voltage and temperature. impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. t hey may also occur in cycles initiated with g high. in all cases impedance updates are transparent to the user and do not produce access time "push-out s" or other anomalous behavior in the sram. impedance updates occur no more often than every 32 clock cycles. clock cycles are counted whether the sram is selected or not and proceed regardless of the type of cycle being ex ecuted. therefore, the user can be assured that after 33 co ntin- uous read cycles have occurred, an im pedance update will occur the next time g are high at a rising edge of the k clock. there are no power up requirements for the sram. however, to guarantee optimum output driver impedance after power up, the sram needs 1024 non-read cycles. power-up/power-down supply voltage sequencing the following power-up supply vo ltage application is recommended: v ss , v dd , v ddq , v ref , then v in . v dd and v ddq can be applied simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-up. the following power-down supply voltage removal sequence is recommended: v in , v ref , v ddq , v dd , v ss . v dd and v ddq can be removed simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-down.
rev 1.1 512kx36 & 1mx18 sram - 6 - jan. 2005 k7d161874b k7d163674b truth table note : - b(both) is din in write cycle and dout in read cycle. byte write function is not suppo rted. x means "don't care". - k & k are complementary. k g b1 b2 b3 dq operation lxxxxhi-z clock stop x h l x hi-z no operation, pipeline high-z l l h h dout load address, single read l l h l dout load address, double read x l l h din load address, single write x l l l din load address, double write x h h x b increment address, continue 4 burst operation for interleaved burst (lbo = v ddq ) note : - for interleave burst lbo = v ddq is recommended. if lbo = v dd , it must not exceed 2.63v. interleaved burst case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 burst sequence table 4 burst operation fo r linear burst (lbo = v ss ) linear burst mode case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0
rev 1.1 512kx36 & 1mx18 sram - 7 - jan. 2005 k7d161874b k7d163674b note : 1. state transitions ; b 1 =(load address), b 1 =(increment address, continue) b 2 =(read), b 2 =(write) b 3 =(single data rate), b 3 =(double data rate) bus cycle state diagram load new address increment address increment address increment address increment address read sdr write sdr read ddr write ddr b 2 , b 3 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 no op power up b 2 , b 3 b 1 b 2 , b 3 b 1 b 2 , b 3 b 1 b 1 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2
rev 1.1 512kx36 & 1mx18 sram - 8 - jan. 2005 k7d161874b k7d163674b recommended dc operating conditions note :1. these are dc test criteria. dc design criteria is v ref 50mv. the ac v ih /v il levels are defined separately for measuring timing parameters. 2. v ih (max)dc= v ddq +0.3, v ih (max)ac= 2.6 v (2.1v for dqs) (pulse width 20% of cycle time). 3. v il (min)dc= - 0.3v, v il (min)ac=-1.0v (-0.5v for dqs) (pulse width 20% of cycle time). 4. v in-clk specifies the maximum allowable dc level for the differential clock. i.e v il-clk and v ih-clk . 5. v dif-clk specifies the minimum clock differential voltage requi red for switching. i.e dc voltage difference between v il-clk and v ih-clk . 6. v cm-clk specifies the clock crossing point for the differential clock or the allowable common clock level for a single ended clock. parameter symbol min typ max unit note core power supply voltage v dd 1.7 2.5 2.63 v output power supply voltage v ddq 1.4 1.5 1.9 v input high level voltage v ih v ref +0.1 - v ddq +0.3 v 1, 2 input low level voltage v il -0.3 - v ref -0.1 v 1, 3 input reference voltage v ref 0.68 0.75 0.95 v clock input signal voltage v in-clk -0.3 - v ddq +0.3 v 1, 4 clock input differential voltage v dif-clk 0.1 - v ddq +0.6 v 1, 5 clock input common mode voltage v cm-clk 0.68 0.75 0.9 v 1, 6 absolute maximum ratings note : power dissipation capability will be dependent upon package characteristics and use envi ronment. see enclosed thermal impeda nce data. stresses greater than those listed under " absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other c onditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reliability. parameter symbol value unit core supply voltage relative to v ss v dd -0.5 to 3.13 v output supply voltage relative to v ss v ddq -0.5 to 2.3 v voltage on any pin relative to v ss v in -0.5 to v ddq +0.5 (2.3v max )v output short-circuit current(per i/o) i out 25 ma storage temperature t str -55 to 125 c dc characteristics note :1. minimum cycle. i out =0ma. 2. 50% read cycles. 3. |i oh |=(v ddq /2)/(rq/5) 15% @v oh =v ddq /2 for 175 ? rq 350 ? . 4. |i ol |=(v ddq /2)/(rq/5) 15% @v ol =v ddq /2 for 175 ? rq 350 ? . 5. minimum impedance mode when zq pin is connected to v ss . parameter symbol min max unit note average power supply operating current(x36) (cycle time = t khkh min) i dd37 i dd33 i dd30 i dd27 - 540 490 440 420 ma 1,2 average power supply operating current(x18) (cycle time = t khkh min) i dd37 i dd33 i dd30 i dd27 - 510 460 410 390 ma 1,2 stop clock standby current (v in =v dd -0.2v or 0.2v fixed, k=low, k =high) i sb1 - 150 ma 1 input leakage current (v in =v ss or v ddq ) i li -1 1 a output leakage current (v out =v ss or v ddq ) i lo -1 1 a output high voltage(programmable impedance mode) v oh1 v ddq /2 v ddq v3 output low voltage(programmable impedance mode) v ol1 v ss v ddq /2 v 4 output high voltage(i oh =-0.1ma) v oh2 v ddq -0.2 v ddq v5 output low voltage(i ol =0.1ma) v ol2 v ss 0.2 v 5
rev 1.1 512kx36 & 1mx18 sram - 9 - jan. 2005 k7d161874b k7d163674b pin capacitance note : periodically sampled and not 100% tested.(t a =25 c, f=1mhz) parameter symbol test condition typ max unit input capacitance c in v in =0v - 4 pf data output capacitance c out v out =0v - 5 pf ac test conditions (t a =0 to 70 c, v dd =1.7 -2.63v, v ddq =1.5v) parameter symbol value unit note input high/low level v ih /v il 1.25/0.25 v - input reference level v ref 0.75 v - input rise/fall time t r /t f 0.5/0.5 ns - output timing reference level 0.75 v - clock input timing reference level cross point v - output load see below - ac input characteristics parameter symbol min max unit note ac input logic high v ih (ac) v ref + 0.4 v - ac input logic low v il (ac) v ref - 0.4 v - clock input differential voltage v dif (ac) 0.8 v - v ref peak-to-peak ac voltage v ref (ac) 5% v ref (dc) v - ck ck v ih (ac) v ref v il (ac) ac input definition setup time hold time v dif (ac)
rev 1.1 512kx36 & 1mx18 sram - 10 jan. 2005 k7d161874b k7d163674b ac timing characteristics notes : 1. the maximum cycle time must be limited to guarantee ac timing specification. 2. this parameter is guaranteed by design, and may not be tested at values shown in the table. 3. this parameter refers to cq and cq rising and falling edges. 4. this parameter is only for 16mb density 5. k and k clocks must be used differencitally to meet ac timing specifications. parameter symbol -37 -33 -30 -27 units notes min max min max min max min max clock clock cycle time t khkh 2.66 - 3.0 - 3.3 - 3.63 - ns 1 clock high pulse width t khkl 1.3 - 1.3 - 1.5 - 1.7 - ns clock low pulse width t klkh 1.3 - 1.3 - 1.5 - 1.7 - ns setup times address setup time t avkh 0.4 - 0.4 - 0.4 - 0.5 - ns control(b1,b2,b3) setup time t bvkh 0.4 - 0.4 - 0.4 - 0.5 - ns data setup time t dvkx 0.25 - 0.3 - 0.3 - 0.4 - ns 2 hold times address hold time t khax 0.4 - 0.4 - 0.4 - 0.5 - ns control(b1,b2,b3) hold time t khbx 0.4 - 0.4 - 0.4 - 0.5 - ns data hold time t kxdx 0.25 - 0.3 - 0.3 - 0.4 - ns 2 output times echo clock high pulse width t chcl t khkl -0.1 t khkl +0.1 t khkl -0.1 t khkl +0.1 t khkl -0.1 t khkl +0.1 t khkl -0.1 t khkl +0.1 ns 2 echo clock low pulse width t clch t klkh -0.1 t klkh +0.1 t klkh -0.1 t klkh +0.1 t klkh -0.1 t klkh +0.1 t klkh -0.1 t klkh +0.1 ns 2 clock crossing to echo clock t cxch 0.5 2.3 0.5 2.3 0.5 2.3 0.5 2.3 ns 3 clock crossing to echo clock t cxcl 0.5 2.3 0.5 2.3 0.5 2.3 0.5 2.3 ns 3 echo clock high to output vaild t chqv -0.20 0.20 -0.20 0.20 -0.20 0.20 -0.20 0.20 ns echo clock low to output valid t clqv -0.20 0.20 -0.20 0.20 -0.20 0.20 -0.20 0.20 ns echo clock high to output hold t chqx -0.20 -0.20 -0.20 -0.20 ns echo clock low to output hold t clqx -0.20 -0.20 -0.20 -0.20 ns echo clock high to output high-z t chqz 0.20 0.20 0.20 0.20 ns echo clock high to output low-z t chlz -0.20 -0.20 -0.20 -0.20 ns g low to output valid t glqv - 1.7 - 1.7 - 1.9 - 2.0 ns 4 g high to output low-z t ghqx 0.5 0.5 0.5 0.5 ns 4 g high to output high-z t ghqz - 1.7 - 1.7 - 1.9 - 2.0 ns 4 50 ? 50 ? ac test output load 25 ? 5pf dq 0.75v 5pf 0.75v 50 ? 50 ? 0.75v
rev 1.1 512kx36 & 1mx18 sram - 11 jan. 2005 k7d161874b k7d163674b nop continue k k b1 g sa t avkh t khax cq nop 12 3 4 5 6 7 81012 11 b2 b3 cq dq read (burst of 4) read (burst of 2) read (burst of 4) nop write continue write (burst of 4) read 9 continue read read (burst of 4) continue read a 0 a 1 a 2 a 3 q x2 q 01 q 02 q 03 q 04 q 51 q 52 q 53 q 54 q 11 q 12 d 21 d 23 d 24 d 22 q 31 t bvkh t khbx t chqz t kxcv t ghqz t dvkh t khdx t glqx t glqv t khkh t ghqx undefined don?t care a 5 note 1. q 01 refers to output from address a. q 02 refers to output from the next internal burst address following a, etc. 2. outputs are disabled(high-z) one clock cycle after no p detected or after no pending data requests are present. 3. doing more than one read continue or write continue will cause the address to wrap around. timing waveforms for do uble data rate cycles (burst length=4, 2) t khkl t klkh t chcl t clch t chlz t chqv t chqx t clqv t kxcl
rev 1.1 512kx36 & 1mx18 sram - 12 jan. 2005 k7d161874b k7d163674b timing waveforms for si ngle data rate cycles note : 1. q 01 refers to output from address a 0 . q 02 refers to output from the next internal burst address following a 0 , etc. 2. outputs are disabled(high-z) one clock cycle after no p detected or after no pending data requests are present. 3. this devices supports cycle l engths of 1, 2, 4. continue(b1=high, b2=high, b3=x) up to three times following a b1 operation. any further continue assertions constitute invalid operations. 4. this device will have an address wraparound if further continues are applied. nop continue t khkh t avkh t khax nop 1 2 3 4 5 6 7 8 10 12 11 read (burst of 2) read read (burst of 4) nop write continue write (burst of 2) read 9 continue read continue read continue read a 0 a 1 a 2 a 3 q x1 d 22 d 21 t bvkh t khbx t chqz t kxcv t ghqz t ghqx t dvkh t khdx t glqx t glqv t klkh q 31 q 01 q 02 q 03 q 04 q 11 undefined don?t care t khkl k k b1 g sa b2 b3 dq cq cq (burst length=4, 2, 1) (burst of 1) t chcl t clch t kxcl t chlz t chqv t chqx
rev 1.1 512kx36 & 1mx18 sram - 13 jan. 2005 k7d161874b k7d163674b ieee 1149.1 test access po rt and boundary scan-jtag tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo sa sa tdi tms tck test logic reset run test idle 0 11 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 the sram provides a limited set of ieee standard 1149.1 jtag fu nctions. this is to test the connectivity during manufacturing between sram, printed circuit board and other components. internal data is not driven out of sram under jtag control. in confor m- ance with ieee 1149.1, the sram contains a tap controller, instru ction register, bypass register and id register. the tap contr ol- ler has a standard 16-state machine that resets internally upon pow er-up, therefore, trst signal is not required. it is possibl e to use this device without utilizing the tap. to disable the tap contro ller without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and therefore can be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected. jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. this instruction is not ieee 1149.1 compliant. 2. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 3. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 4. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 5. sample instruction dose not places dqs in hi-z. 6. this instruction is reserved for future use. ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 1 0 0 1 idcode identification register 3 0 1 0 sample-z boundary scan register 2 0 1 1 reserved do not use 6 1 0 0 sample boundary scan register 5 1 0 1 reserved do not use 6 1 1 0 reserved do not use 6 1 1 1 bypass bypass register 4
rev 1.1 512kx36 & 1mx18 sram - 14 jan. 2005 k7d161874b k7d163674b boundary scan exit order(x36) * reserved for mode pin 36 4a sa sa 6a 35 37 4c sa sa 6c 34 38 3a sa sa 7a 33 39 3b sa sa 7b 32 40 3c sa sa 7c 31 41 3d sa sa 7d 30 42 2b dq dq 8b 29 43 1b dq dq 9b 28 44 2d dq dq 8d 27 45 3f dq dq 7f 26 46 1d dq dq 9d 25 47 2f cq cq 8f 24 48 1f dq dq 9f 23 49 3h dq dq 7h 22 50 2h dq dq 8h 21 51 1h dq dq 9h 20 52 5a zq g 5c 19 53 5b b 1 k5g18 54 5k b 2 k 5h 17 55 5l b 3 mode 6l 16 56 4l lbo dq 9k 15 57 1k dq dq 8k 14 58 2k dq dq 7k 13 59 3k dq dq 9m 12 60 1m dq cq 8m 11 61 2m cq dq 9p 10 62 1p dq dq 7m 9 63 3m dq dq 8p 8 64 2p dq dq 9t 7 65 1t dq dq 8t 6 66 2t dq sa 7p 5 67 3t sa sa 7t 4 68 4r sa sa 6r 3 sa 5t 2 sa 5r 1 boundary scan exit order(x18) * reserved for mode pin 26 4a sa sa 6a 25 27 4c sa sa 6c 24 28 3a sa sa 7a 23 29 3b sa sa 7b 22 30 3c sa sa 7c 21 31 3d sa sa 7d 20 32 2b dq dq 9b 19 dq 8d 18 dq 7f 17 33 1d dq 34 2f cq dq 9f 16 35 3h dq dq 8h 15 36 1h dq 37 5a zq g 5c 14 38 5b b 1 k5g13 39 5k b 2 k 5h 12 40 5l b 3 mode 6l 11 41 4l lbo dq 9k 10 42 2k dq dq 7k 9 43 1m dq cq 8m 8 dq 9p 7 44 3m dq 45 2p dq 46 1t dq dq 8t 6 sa 7p 5 47 3p sa sa 7t 4 48 3t sa sa 6r 3 49 4r sa sa 5t 2 sa 5r 1 id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit (0) 512kx36 0000 00111 00100 xxxxxx 00001001110 1 1m x 18 0000 01000 00011 xxxxxx 00001001110 1 scan register definition part instruction register bypass register id register boundary scan 512kx36 3 bits 1 bits 32 bits 68 bits 1m x 18 3 bits 1 bits 32 bits 49 bits
rev 1.1 512kx36 & 1mx18 sram - 15 jan. 2005 k7d161874b k7d163674b jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification. parameter symbol min typ max unit note power supply voltage v dd 1.7 2.5 2.6 v input high level v ih 0.7*v dd -v dd +0.3 v input low level v il -0.3 - 0.3*v dd v output high voltage(i oh =-2ma) v oh 0.75*v dd -v dd v output low voltage(i ol =2ma) v ol v ss - 0.25*v dd v jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5-ns tms input hold time t chmx 5-ns tdi input setup time t dvch 5-ns tdi input hold time t chdx 5-ns clock low to output valid t clqv 010ns jtag ac test conditions note : 1. see sram ac test output load on page 5. parameter symbol min unit note input high/low level v ih /v il v dd /0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level v dd /2 v 1 jtag timing diagram tck tms tdi tdo t chch t chcl t clch t mvch t chmx t dvch t chdx t clqv
rev 1.1 512kx36 & 1mx18 sram - 16 jan. 2005 k7d161874b k7d163674b 153 bga package thermal characteristics note : 1. junction temperature can be calculated by : t j = t a + p d x theta_ja. parameter symbol thermal resistance unit note junction to ambient(at still air) theta_ja tbd c/w junction to case theta_jc tbd c/w junction to board theta_jb tbd c/w note : 1. all dimensions are in millimeters. 2. solder ball to pcs offset : 0.10 max. 3. pcb to cavity offset : 0.10 max. 153 bga package dimensions 1.27 7654321 0.050 b c d e f g h j k l m n p r t ua 1.27 0.050 ? bottom view 0.3/0.012max 153- ? 0.030 0.006 14.00 0.10 0.551 0.004 22.00 0.10 0.866 0.004 12.50 0.10 0.492 0.004 0.60 0.10 0.024 0.004 20.50 0.10 0.807 0.004 0.56 0.04 0.022 0.002 0.90 0.10 0.035 0.004 2.21 0.087 top view 0.006 0.15 max 0.75 0.15 max 98

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