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PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use PM4314 qdsx quad t1/e1 line interface device data sheet issue 5: june 1998
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use public revision history issue no. issue date details of change 5 june, 1998 data sheet reformatted no change in technical content generated r5 data sheet from pmc-950739, r4 4 january, 1997 eng doc issue r3 released 3 march, 1996 public release of document: removal of confidential notices 2 january, 1996 upgrade to eng doc issue p2 1 august, 1995 creation of document
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use i contents 1 features ...............................................................................................1 2 applications ........................................................................................ 5 3 references ......................................................................................... 6 4 application examples ...................................................................... 8 5 block diagram.................................................................................. 13 6 description ....................................................................................... 15 7 pin diagram ........................................................................................ 18 8 pin description ................................................................................ 19 9 functional description ...............................................................32 9.1 analog pulse slicer (rslc) .............................................. 32 9.2 clock and data recovery (cdrc) .................................... 35 9.3 line code violation performance monitor (lcv_pmon)............................................................................... 39 9.4 inband loopback code detector (ibcd) ....................... 40 9.5 pseudo-random bit sequence monitor (prsm).......... 40 9.6 timing options (tops) .......................................................... 42 9.7 pseudo-random bit sequence generator (prsg)..... 42 9.8 inband loopback code generator (xibc)..................... 43 9.9 b8zs/hdb3/ami line encoder (lcode) .............................. 43 9.10 digital jitter attenuator (djat)....................................... 43 9.11 analog pulse generator (xpls)...................................... 49
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use ii 9.12 ieee p1149.1 jtag test access port................................52 9.13 microprocessor interface ............................................. 52 9.14 register memory map ......................................................... 53 10 normal mode register description........................................ 56 11 test features description ....................................................... 113 11.1 test mode 0 details ........................................................... 114 11.2 jtag test port...................................................................... 116 12 operations....................................................................................... 119 12.1 programming the xpls waveform template ............ 122 12.2 using the digital jitter attenuator............................ 127 12.3 using xpls without djat .................................................. 128 12.3.1 fifo not in tx path, xsel[1] = 0 ...............................129 12.3.2 fifo not in tx path, xsel[1] = 1, xsel[0] = 0.......... 129 12.3.3 fifo is in tx path, xsel[1] = 1, xsel[0] = 0. ............ 129 12.3.4 fifo not in tx path, xsel[1] = 1, xsel[0] = 1.......... 129 12.3.5 fifo is in tx path, xsel[1] = 1, xsel[0] = 1.............. 130 12.4 jtag support ........................................................................ 130 13 functional timing ......................................................................... 141 13.1 line code violation insertion ....................................... 141 14 absolute maximum ratings........................................................ 144 15 capacitance ..................................................................................... 145 16 d.c. characteristics .................................................................... 146 17 microprocessor interface timing characteristics ...... 149
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use iii 18 a.c. timing characteristics ....................................................... 153 19 ordering and thermal information ...................................... 163 20 mechanical information............................................................. 164
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use iv list of registers register 000h, 040h, 080h, and 0c0h: receive configuration...... 57 register 001h, 041h, 081h, and 0c1h: transmit configuration ...60 register 002h, 042h, 082h, and 0c2h: tx/rx block placement...... 62 register 003h, 043h, 083h, and 0c3h: interrupt source ............... 64 register 005h, 045h, 085h, and 0c5h: diagnostics ........................... 65 register 006h or 106h: master test.................................................... 67 register 007h: revision/chip id/global monitoring update ....... 70 register 008h: interrupt quadrant id ............................................... 71 register 009h: tops master clock configuration/clock activity monitor.............................................................................. 72 register 00ah, 04ah, 08ah, and 0cah: tops clock timing options ................................................................................................................ 74 register 00bh, 04bh, 08bh, and 0cbh: lcode transmit line code configuration .................................................................................. 76 register 010h, 050h, 090h, and 0d0h: cdrc configuration ........... 77 registers 011h, 051h, 091h and 0d1h: cdrc interrupt enable.... 79 registers 012h, 052h, 092h and 0d2h: cdrc interrupt status..... 80 register 014h, 054h, 094h, and 0d4h: lcv_pmon interrupt enable/status ................................................................................... 81 registers 01ah-01bh, 05ah-05bh, 09ah-09bh, 0dah-0dbh: latching lcv performance data .................................................................. 82 registers 01ah, 05ah, 09ah and 0dah: lcv_pmon line code violation count lsb ....................................................................... 83
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use v registers 01bh, 05bh, 09bh and 0dbh: lcv_pmon line code violation count msb ...................................................................... 84 registers 01ch, 05ch, 09ch and 0dch: djat interrupt status .... 85 register 01dh, 05dh, 09dh and 0ddh: djat reference clock divisor (n1) control ...................................................................... 86 registers 01eh, 05eh, 09eh and 0deh: djat output clock divisor (n2) control ...................................................................................... 87 registers 01fh, 05fh, 09fh and 0dfh: djat configuration........... 88 registers 020h, 060h, 0a0h and 0e0h: ibcd configuration ........... 90 registers 021h, 061h, 0a1h and 0e1h: ibcd interrupt enable/status ................................................................................... 91 registers 022h, 062h, 0a2h and 0e2h: ibcd activate code............. 93 registers 023h, 063h, 0a3h and 0e3h: ibcd deactivate code........ 94 registers 024h, 064h, 0a4h and 0e4h: xibc control ....................... 95 registers 025h, 065h, 0a5h and 0e5h: xibc loopback code.......... 97 register 027h, 067h, 0a7h, 0e7h: prsg configuration ................... 98 register 029h, 069h, 0a9h, 0e9h: prsm control/status ................. 99 register 02ah, 06ah, 0aah, 0eah: prsm bit error event count lsb....................................................................................................... 102 register 02bh, 06bh, 0abh, 0ebh: prsm bit error event count msb...................................................................................................... 103 register 02ch, 06ch, 0ach, 0ech: xpls line length configuration .............................................................................................................. 104 register 02dh, 06dh, 0adh, 0edh: xpls control/status .............. 106 register 02eh, 06eh, 0aeh, 0eeh: xpls code indirect address 108 register 02fh, 06fh, 0afh, 0efh: xpls code indirect data.......... 110
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use vi register 030h, 070h, 0b0h, 0f0h: rslc configuration .................. 111 register 031h, 071h, 0b1h, 0f1h: rslc interrupt enable/status112
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use vii list of figures figure 1 - example 1. t1 or e1 atm interfaces.................................. 8 figure 2 - example 2. dsx-1 digital access cross connects (dacs).................................................................................................... 10 figure 3 - example 3. multiplexers (m13).......................................... 12 figure 4 - normal operating mode..................................................... 13 figure 5 - loopback modes.................................................................... 14 figure 6 - external analog receive interface circuit ............. 34 figure 7 - dsx-1 jitter tolerance ....................................................... 37 figure 8 - e1 jitter tolerance with algsel = 1 .............................. 38 figure 9 - e1 jitter tolerance with algsel = 0 .............................. 39 figure 10- dsx-1 jitter tolerance ....................................................... 45 figure 11- e1 jitter tolerance ............................................................. 46 figure 12- djat minimum jitter tolerance vs. xclk accuracy (dsx-1 case)........................................................................................ 47 figure 13- djat minimum jitter tolerance vs. xclk accuracy (e1 case)..................................................................................................... 47 figure 14- dsx-1 jitter transfer.......................................................... 48 figure 15- e1 jitter transfer................................................................49 figure 16- external analog transmit interface circuit ........... 51 figure 17- timing options ........................................................................ 75 figure 18- code register sequence during pulse generation ..................................................................................................... 125 figure 19- code register sequence for 0-110 feet build-out 126
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use viii figure 20- boundary scan architecture........................................ 131 figure 21- tap controller finite state machine .......................... 133 figure 22- input observation cell (in_cell) ................................... 138 figure 23- output cell (out_cell)..................................................... 139 figure 24- bidirectional cell (io_cell)............................................ 140 figure 25- layout of output enable and bidirectional cells 140 figure 26- b8zs line code violation insertion .............................. 141 figure 27- hdb3 line code violation insertion.............................. 142 figure 28- ami line code violation insertion ................................. 143 figure 29- microprocessor interface read timing.................... 150 figure 30- microprocessor interface write timing .................. 152 figure 31- xclk input timing for jitter attenuation .................. 153 figure 32- tclki input timing ................................................................154 figure 33- clko8x input timing diagram (fifo not in tx path) ... 156 figure 34- xclk input timing diagram (fifo not in tx path) ........ 157 figure 35- rclko output timing diagram......................................... 158 figure 36- jtag port interface timing.............................................. 160 figure 37- analog receive data input timing diagram................ 161
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use ix list of tables table 1 - ...................................................................................................... 33 table 2 - ...................................................................................................... 35 table 3 - ...................................................................................................... 51 table 4 - ...................................................................................................... 90 table 5 - test mode register memory map.................................. 113 table 6 - .................................................................................................... 115 table 7 - .................................................................................................... 115 table 8 - instruction register........................................................ 116 table 9 - boundary scan register ................................................. 117 table 10 - .................................................................................................... 122 table 11 - .................................................................................................... 123 table 12 - .................................................................................................... 124 table 13 - .................................................................................................... 136 table 14 -.qdsx absolute maximum ratings .................................. 144 table 15 - qdsx capacitance................................................................145 table 16 - qdsx d.c. characteristics............................................... 146 table 17 - microprocessor interface read access (figure 29) ..................................................................................................... 149 table 18 - microprocessor interface write access (figure 30) ..................................................................................................... 151 table 19 - xclk input for jitter attenuation (figure 31).......... 153 table 20 - tclki input timing (figure 32)........................................... 154
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use x table 21 - clko8x input timing (fifo not in tx path) (figure 33)156 table 22 - xclk input timing (fifo not in tx path) (figure 34).... 157 table 23 - rclko output timing (figure 35) .................................... 158 table 24 - jtag port interface timing (figure 36) ........................ 159 table 25 - analog receive data input timing (figure 37) ........... 161 table 26 - qdsx ordering information ........................................... 163 table 27 - qdsx thermal information.............................................. 163
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 1 1 features integrates four duplex dsx-1 or cept e1 compatible line interface circuits in a single monolithic device. line format is selected on a per-device basis. provides clock recovery and line performance monitoring in the receivers. provides jitter attenuation and programmable line build out in the transmitters. utilizes digital phase-locked loops for receive and transmit clock derivation without the use of tuned circuits. provides an integrated 8x clock multiplier for generation of required high- speed clocks in applications not requiring jitter attenuation. optionally inserts alarm indication signal (ais) when loopback modes are enabled. ais insertion may also be directly controlled via the microprocessor interface. provides a generic microprocessor interface for initial configuration, ongoing control, and status monitoring. generates an interrupt upon detection of any of various alarms, events, or changes in status. identification of interrupt sources, masking of interrupt sources, and acknowledgment of interrupts is provided via internal registers. provides optional hardware programmed mode which provides external configuration pins when microprocessor access is not available to the device. provides a standard 5 signal p1149.1 jtag test port for boundary scan board test purposes. provides seamless interface to pm4344 tquad, pm6344 equad, pm8313 d3mx, and pm7344 s/uni-mph. low power cmos technology, 1500 mw power dissipation processing all ones signals on all four quadrants. 128-pin (14mm x 20mm) pqfp package. each receiver section slices incoming g.703 dsx-1 and cept e1 bipolar line signals into digital return-to-zero (rz) pulses. selectable slicer levels (dsx-1/cept e1) to provide improved snr.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 2 squelches rz signals with pulse amplitudes below 140mv and 105mv for cept and t1, respectively. typical minimum sensitivity of 50 mv at transformer primary with a 1:2 turns ratio transformer allows for terminating or bridged performance monitoring applications. recovers a 1.544 mhz clock and ds-1 data or a 2.048 mhz clock and e1 data using a digital phase-locked loop to achieve high jitter accommodation. accommodates up to 0.4 ui peak-to-peak, high frequency jitter to satisfy at&t tr 62411 and itu-t g.823. optionally outputs either dual rail recovered line pulses or a single rail ds- 1/e1 signal. performs b8zs or ami decoding when processing a bipolar ds-1 signal and hdb3 or ami decoding when processing a bipolar e1 signal. detects line code violations (lcvs), b8zs/hdb3 line code signatures, and 16, 8, or 4 successive zeros. accumulates up to 4095 line code violations (lcvs), for performance monitoring purposes, over accumulation intervals defined by the period between software write accesses to the lcv register. detects loss of signal (los), which is defined as 10, 15, 31, 63, or 175 successive zeros. detects both programmable inband loopback activate and deactivate code sequences received in the ds-1 data stream when they are present for 5 seconds. optionally, enters loopback mode automatically on detection of an inband loopback code. detects any pair of arbitrary inband codes from three to eight bits in length. the inband code detection algorithm operates in the presence of a 10 -2 bit error rate. programmable to detect csu (channel service unit), network, and far-end loopback codes. optionally allows jitter attenuation of recovered clock and data, using a 2 x 48 bit fifo. optionally inserts unframed inband code sequences in place of recovered data.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 3 detects unframed 2 15 -1 test sequences as defined in itu-t o.151 and accumulates bit errors detected using this pseudo-random pattern. optionally inserts unframed 2 15 -1 test sequences in place of recovered data. each transmitter section generates dsx-1 and cept e1 compatible pulses with programmable pulse shape using an external 1:1.36 turns ratio transformer. accommodates standard cable types such as abam, pic, and coaxial. provides an integrated analog pulse driver performance monitor which can provide an interrupt upon detection of failure. allows bipolar violation (bpv) transparent operation for error restoring regenerator applications. allows bipolar violation (bpv) insertion for diagnostic testing purposes. supports all ones transmission for alarm indication signal (ais) generation. provides a digital phase-locked loop for generation of jitter reduced transmit output timing. the dpll utilizes a 37.056 mhz master clock for dsx-1 or a 49.152 mhz master clock for cept e1 applications. digital phase-locked loop locks 1.544 mhz or 2.048 mhz output timing to the average frequency of the 1.544 mhz or 2.048 mhz jittered transmit input clock. provides a 2 x 48 bit fifo for jitter attenuation in the transmit path. provides up to 55 db of jitter attenuation to satisfy at&t tr 62411, itu-t g.737, g.738, g.739, and g.742. provides fifo overrun and underrun indicators. inhibits fifo overrun and underrun for excessive jitter amplitudes. supports transmission of a programmable unframed inband loopback code sequence. programmable to transmit repetitions of any arbitrary code from three to eight bits in length. accepts either dual rail or single rail ds-1/e1 signals. performs b8zs or ami encoding when processing a single rail ds-1 signal and hdb3 or ami encoding when processing a single rail e1 signal.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 4 optionally detects inband code sequences in ds-1 transmit streams. optionally inserts unframed 2 15 -1 test sequences in place of input transmit data. optionally detects unframed 2 15 -1 test sequences in the input transmit data.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 5 2 applications t1 or e1 atm interfaces electronic dsx-1/cept e1 cross-connects digital access and cross-connect systems (dacs) multiplexers channel service units (csus) dsx-1/cept e1 repeaters test equipment
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 6 3 references 1. american national standard for telecommunications, ansi t1.102-1992 - "digital hierarchy - electrical interfaces". 2. american national standard for telecommunications, ansi t1.107-1991 - digital hierarchy - formats specifications. 3. american national standard for telecommunications, ansi t1.403-1989 - "carrier to customer installation - ds1 metallic interface specification". 4. american national standard for telecommunications, ansi t1.408-1990 - "integrated services digital network (isdn) primary rate - customer installation metallic interfaces layer 1 specification". 5. bell communications research, tr-tsy-000009 - "asynchronous digital multiplexes requirements and objectives", issue 1, may, 1986. 6. bell communications research, ta-tsy-000147 - "ds1 rate digital service monitoring unit functional specification", issue 1, october, 1987. 7. bell communications research, tr-tsy-000170 - "digital cross-connect system (dcs) - requirements and objectives", issue 1, november, 1985. 8. bell communications research, tr-tsy-000191 - "alarm indication signal requirements and objectives" issue 1, may 1986. 9. bell communications research, tr-tsy-000303 - "integrated digital loop carrier system generic requirements, objectives, and interface", issue 1, rev. 1, december, 1987. 10. bell communications research, tr-tsy-000312 - "functional criteria for the ds1 interface connector", issue 1, march, 1988. 11. bell communications research, tr-tsy-000499 - "transport systems generic requirements (tsgr): common requirement", issue 3, december, 1989. 12. at&t, tr 43801 - "digital channel bank - requirements and objectives", november, 1982.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 7 13. at&t, tr 43802 - "digital multiplexers - requirements and objectives", july, 1982. 14. at&t, tr 62411 - accunet t1.5 - "service description and interface specification", december, 1990. 15. ccitt red book, recommendation q.516, - "operations and maintenance functions", vol. vi, fasc. vi.5, 1984. 16. itu-t recommendation o.150, - "digital test patterns for performance measurements on digital transmission equipment", oct. 1992. 17. itu-t recommendation o.151, - "error performance measuring equipment operating at the primary rate and above", rev.1, 1992. 18. itu-t recommendation g.703, - "physical/electrical characteristics of hierarchical digital interfaces", rev.1, 1991. 19. itu-t recommendation g.704, - "synchronous frame structures used at primary and secondary hierarchical levels", rev.1, 1991. 20. itu-t recommendation g.821, - "error performance of an international digital connection forming part of an integrated services digital network", blue book fasc. iii.5, 1988. 21. itu-t recommendation g.823, - "the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy", 1993. 22. itu-t recommendation o.151, - "error performance measuring equipment operating at the primary rate and above", rev. 1, oct. 1992. 23. itu-t recommendation o.162, - "equipment to perform in service monitoring on 2048, 8448, 34368, and 139264 kbit/s signals", rev.1, oct. 1992. 24. itu-t, recommendation i.432 - b-isdn user-network interface - physical layer specification, august 1992.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 8 4 application examples figure 1 - example 1. t1 or e1 atm interfaces pm7344 s/uni-mph PM4314 qdsx sci-phy tm multi-phy atm cell bus generic microprocessor bus dsx-1 or e1 analog interfaces 1x transmit reference clock q uad t1/e1 multi-phy user network interface quad t1/e1 line interface device crystal oscillator 24x clock (37.056 mhz for t1 or 49.152 mhz for e1) if using jitter attenuator or xpls w iden function. 8x clock otherwise. example 1 shows the PM4314 qdsx used with the pm7344 s/uni-mph to implement a quad t1/e1 uni where the ds1 or e1 signals are presented on dsx-1 or e1 electrical interfaces. in this example, the dsx-1 or e1 line interface functions are provided by the qdsx and the ds-1 or e1 framing functions are provided by the s/uni-mph. the s/uni-mph also provides the atm cell processing functions associated with the phy layer, including the implementation of a sci-phy multi-phy interface to the atm layer device(s). the combination of the qdsx device with the s/uni- mph allows both ansi/itu compliant dsx-1/e1 analog signals and atm forum uni 3.1 and itu g.804 compliant ds1/e1 digital signals to be processed. jitter attenuation by both the qdsx and the s/uni-mph can be performed by supplying a 24x reference clock to the devices. if jitter attenuation is to be executed by the s/uni-mph only, then an 8x reference clock is required by the qdsx and a 24x reference clock is required by the s/uni-mph. if jitter attenuation is to be executed by the qdsx, then a 24x reference clock must be
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 9 supplied to it and an 8x reference clock may be supplied to the s/uni-mph. if jitter attenuation is not required by either device, then an 8x reference clock may be supplied to both devices.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 10 figure 2 - example 2. dsx-1 digital access cross connects (dacs) glue logic can be implemented using one 74hct00 and one 74hct175 pack. time /sp ace swi tch 4.096mhz d q qb syste m fr ame p ulse d q qb d q qb 2.048mhz pm4344 tquad rdp/rdd[1] rdn/rlcv[1] rclki[1] PM4314 qdsx rclko[3] rlcv/rdn/sdn[3] rdd/rdp/sd p[3] tdd/t dp[1 ] tclki[1 ] xclk 37.056 mhz clock xclk clko8x *note: rc atten uation networks not shown in[0] in[1] in[2] in[3] in[4] in[5] in[6] in[7] fp clk2x out[1] out[2] out[3] out[4] out[5] out[6] out[0] out[7] rxtip[ 1] rxring[1] rxtip[ 2] rxring[2] rxring[3] rxtip[ 3] rxring[4] rxtip[ 4] txring[4] txti p[4 ] txti p[3 ] txring[3] txti p[2 ] txring[2] txti p[1 ] txring[1] rclko[4] rlcv/rdn/sdn[4] rdd/rdp/sd p[4] rclko[2] rlcv/rdn/sdn[2] rdd/rdp/sd p[2] rclko[1] rlcv/rdn/sdn[1] rdd/rdp/sd p[1] tdd/t dp[2 ] tclki[2 ] tdd/t dp[3 ] tclki[3 ] tdd/t dp[4 ] tclki[4 ] brclk brfpi rdp/rdd[2] rdn/rlcv[2] rclki[2] rdp/rdd[3] rdn/rlcv[3] rclki[3] rdp/rdd[4] rdn/rlcv[4] rclki[4] tdd/t dp[1 ] tclko[1 ] tdd/t dp[2 ] tclko[2 ] tdd/t dp[3 ] tclko[3 ] tdd/t dp[4 ] tclko[4 ] brpcm[1] brsig[1] brfpo[1] brpcm[2] brsig[2] brfpo[2] brpcm[3] brsig[3] brfpo[3] brpcm[4] brsig[4] brfpo[4] tdn[1] tdn[2] tdn[3] tdn[4] tclki[1 ] btpcm[1 ] btsig [1] btfp[1 ] btclk [1] tclki[2 ] btpcm[2 ] btsig [2] btfp[2 ] btclk [2] tclki[3 ] btpcm[1 ] btsig [3] btfp[3 ] btclk [3] tclki[4 ] btpcm[4 ] btsig [4] btfp[4 ] btclk [4]
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 11 example 2 shows a dsx 1/0 cross-connect using a PM4314 qdsx, a pm4344 tquad, and a digital time/space switch to implement a simple 1/0 cross- connect. an alternate architecture could use two digital time/space switches, one as a voice switch and the other as a signaling switch, and 2 tquads to cross-connect eight t1s. (note: a true implementation would require redundancy in the switch core.) in this example, the tquad is programmed to receive and generate the same framing format, using the 2.048 mhz backplane data rate. the "system frame pulse" signal is stretched through the two d-ff into a pulse of 488ns duration, which is used to frame align the data out of each framer through the elastic store and to provide frame alignment indication to the transmitters. the raw system frame pulse signal is used to indicate frame alignment synchronization to the digital time/space switch. another d-ff is configured as a toggle to generate a 2.048mhz clock from the system 4.096mhz clock source, synchronized to the system frame pulse. the tquad is configured to accept and source unipolar signal from and to the qdsx. as shown, the jitter attenuation is performed in the qdsx and is disabled in the tquad.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 12 figure 3 - example 3. multiplexers (m13) p lin+ nc-r lin- rgnd rfo tgnd lout+ nc-t lout- rpos rneg rclk lf1 lf2 tpos tneg tclk ss i 7 8p 7 2 0 0 ds-3 line interface rpos rneg rclk tpos tn eg tclk ticlk to h tohen timfp tohclk to hfp a[8:0 ] d[7:0] ale rdb wrb csb rstb r d 1 d at1 rd1clk1 td1dat1 td1clk1 r d 1 d at2 rd1clk2 td1dat2 td1clk2 r d 1 d at3 rd1clk3 td1dat3 td1clk3 r d 1 d at4 rd1clk4 td1dat4 td1clk4 ? ? ? ? ? rd1dat28 rd1clk28 td1dat28 td1clk28 in tb pm8313 d3 mx m1 3 m ul tip lex e r ad [1 5 :0 ] al e rdb wr b resb in t from mas ter reset circuitry from chip s elect decode circuitry +5v tdd[1] tclki[1] rdd[1] rclko[1] tdd[2] tclki[2] rdd[2] rclko[2] tdd[3] tclki[3] rdd[3] rclko[3] tdd[4] tclki[4] rdd[4] rclko[4] a[8 :0 ] d[7:0] al e rdb wrb csb rstb PM4314 qd sx txtip[1] txrin g[1] rxtip[1] rxr ing[1] txtip[2] txrin g[2] rxtip[2] rxr ing[2] txtip[3] txrin g[3] rxtip[3] rxr ing[3] txtip[4] txrin g[4] rxtip[4] rxr ing[4] in tb fro m /t o p 1:1.36 1:1.36 ? ? ? ? ? ? ? ? ? 1:2 1:2 (7 quad dsx-1/e1 line interfaces) example 3 shows the use of the PM4314 qdsx with the pm8313 d3mx in an m13 multiplexer/demultiplexer application. use of the ssi liu as illustrated requires that ticlk of the d3mx has a duty cycle of 45% min., 55% max. or better (e.g.. using a connor winfield s65t3 reference oscillator).
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 13 5 block diagram figure 4 - normal operating mode rslc analog pu l se slic er xib c in- band loop- back c ode generato r djat digital jitter attenu ator lcv_pm on line code vi olat ion counter pr sm pr bs detector and error counter ibc d in- band loop- back c ode detector r c l ko [4:1 ] rdd/rdp/sdp[4:1] rlcv/rdn/sdn[4:1] rxtip[4:1] rxring[4:1] rc[4:1] pr s g pr bs genera tor cdrc c lo c k an d data recovery xp ls ana log pulse genera tor pr sm prbs detector and error counter pr s g pr bs generator xib c in- band loop- back c ode generator lcode am i/b8z s/h d b3 lin e en c od er tops tim ing options djat digital jitter attenu ator transmitter receiver control signals microprocessor interface or hardware control signals r db d[7:0] wrb a [8 :0 ] rstb a l e in tb cs b rdua l tdu al d c r clko8x/c lko1x tc [4 :1 ] txr in g[4 :1 ] txtip [4:1 ] tdd/tdp[4:1] tdn[4:1] tc l k i[4:1 ] boundary scan td o td i t m s tck tr st b ibc d in- band loop- back c ode detector xc l k/vc l k ieee p1149.1 jtag te s t acces s port note: dashed boxes show optional placement of blocks. default placement of the block is shown in solid boxes.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 14 figure 5 - loopback modes rslc ana log puls e slicer xibc in-band loop- back code generator djat digital jitter atten uator lcv_pmon line code vio lation counter prsm pr bs detector and error counter ibc d in-band loop- back code detector rclko[4:1] rdd/rdp/sdp[4:1] rlcv/rdn/sdn[4:1] rxtip[4:1] rxring[4:1] r c [4:1] prsg pr bs generator cdrc clock and data recovery xp ls ana log puls e genera tor prsm pr bs detector and error counter prs g prb s generator xibc in-ban d loop- back c ode generato r lcode ami/b 8zs/h db3 li n e encoder to ps timing options djat digital jit ter attenuator tr an smitte r receiver control signals microprocessor interface or hardw are control si g nals r d b d[7: 0] wrb a[ 8 :0 ] rst b al e in tb c sb rd ua l tdual d c r clko8x/clko1x tc[4:1] txring[4:1] txtip[4:1 ] tdd/tdp[4:1] tdn[4:1] tclki[4:1] boundary scan tdo tdi t m s tc k trstb ibc d in-ban d loop- back c ode detector xc l k/vc l k ieee p1149.1 jtag tes t acce s s po rt linelb dialb dmlb note: dashed boxes show optional placement of blocks. default placement of the block is shown in solid boxes.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 15 6 description the PM4314 qdsx quad t1/e1 line interface device is a monolithic integrated circuit that supports dsx-1 and cept e1 compatible transmit and receive interfaces for four 1.544 mbit/s or 2.048 mbit/s data streams. in the incoming direction, the dsx-1/e1 signals for each quadrant of the qdsx are first processed by a receive data slicer. the receive data slicer converts the line signal received via a coupling transformer to dual rail rz digital pulses. adaptation for attenuation is achieved using an integral peak detector that sets the slicing levels. through use of passive external attenuation circuitry, either terminated or bridge monitored dsx-1/e1 signal levels can be accommodated. the low signal level condition or signal squelch may be enabled to generate interrupts. clock and data are recovered from the dual rail rz digital pulses using a digital phase-locked loop that provides excellent high frequency jitter accommodation. the recovered data is decoded using b8zs, hdb3, or ami line code rules and is presented either as a ds-1/e1 stream or presented in an undecoded dual rail nrz format. loss of signal and line code violations are detected as well as 8 successive zeros/4 successive zeros, and the b8zs/hdb3 signature. the presence of programmable inband loopback codes is also detected. these various events or changes in status may be enabled to generate interrupts. additionally, line code violations are indicated on outputs. in the outgoing direction, each quadrant of the qdsx may accept either a ds- 1/e1 stream to be encoded using b8zs, hdb3, or ami line code rules, or it may accept pre-encoded data in dual rail nrz format. jitter attenuation is provided by passing outgoing data through a fifo. a low jitter clock is generated by an integral digital phase-locked loop and is used to read data from the fifo. fifo overrun or underrun may be enabled to generate interrupts. alarm indication signal (all ones) may be substituted for the fifo data. the digital data is converted to high drive, dual rail rz pulses that drive the dsx-1/e1 interface through a coupling transformer. the shape of the pulses is user programmable to ensure that the dsx-1/e1 pulse template is met after the signal is passed through different cable lengths or types. driver performance monitoring is provided and may be enabled to generate interrupts upon driver failure. the jitter attenuation function can optionally be moved to the receive side. the recovered clock and data is passed through the jitter attenuator before being presented at the digital receive outputs.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 16 internal high speed timing for all quadrants of the qdsx is provided by a common 37.056 mhz or 49.152 mhz master clock. this master clock rate is required for applications where qdsx provides jitter attenuation. for applications where qdsx is not required to attenuate jitter, a 12.352 mhz or 16.384 mhz clock may be used as the master clock and used directly as the internal 8x high speed clock. diagnostic loopback is provided and the loopback may be invoked past the analog transmit outputs using the driver performance monitors or invoked prior to the conversion to analog. line loopback with jitter attenuation is provided and may be enabled for automatic operation based on detected inband loopback codes. the qdsx detects framed or unframed inband loopback code sequences from the received input pulses. any arbitrary code from three to eight bits in length can be declared to be the activate and deactivate codes by writing to configuration registers. the inband loopback code detector can optionally be moved to the transmit side where it detects inband loopback codes in the unipolar input transmit data stream. for framed inband loopback code sequences, it is expected that the framing bit overwrites the inband loopback code bit. the qdsx may insert unframed inband loopback code sequences into the transmitted pcm data stream. these codes consist of continuous repetitions of specific bit sequences. any arbitrary code from three to eight bits in length is programmable by writing to configuration registers. this unframed inband loopback code insertion may optionally be switched to the receive side where it overwrites the data from the slicer. the qdsx may insert an unframed 2 15 -1 o.151 compatible pseudo-random bit sequence into the transmitted pcm data stream. optionally, the prbs insertion may be switched to the receive side where it overwrites the data from the slicer. the qdsx detects an unframed 2 15 -1 o.151 compatible pseudo-random bit sequence input to the receive slicer. this prbs detector can operate in the presence of a 10 -2 bit error rate. bit errors are detected and recorded. the prbs detector can optionally be switched to the transmit side where it can detect unframed prbs data from the unipolar input transmit data stream. the qdsx operates in conjunction with external line coupling transformers, resistors, and capacitors. an external crystal may be used for high speed timing
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 17 generation. the qdsx is configured, controlled, and monitored using registers that are accessed via a generic microprocessor interface.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 18 7 pin diagram the qdsx is packaged in a 128-pin plastic qfp package having a body size of 1mm by 20mm and a pin pitch of 0.5 mm. rlcv[4]/rdn[4]/sdn[4] rdd[4]/rdp[4]/sdp[4] rlcv[3]/rdn[3]/sdn[3] rdd[3]/rdp[3]/sdp[3] rlcv[2]/rdn[2]/sdn[2] rdd[2]/rdp[2]/sdp[2] rlcv[1]/rdn[1]/sdn[1] rdd[1]/rdp[1]/sdp[1] index pin PM4314 qdsx top view pin 1 pin 128 pin 103 pin 102 pin 65 pin 64 pin 39 pin 38 tdual tdn[4] tdd[4]/tdp[4] tclki[4] tdn[3] tdd[3]/tdp[3] tclki[3] tdn[2] tdd[2]/tdp[2] tclki[2] tdn[1] tdd[1]/tdp[1] tclki[1] xclk/vclk vssi[9] vssi[10] vssi[11] vssi[12] vddi[2] reserved clko8x/clk01x rclko[4] rclko[3] vsso[4] vddo[4] rclko[2] rclko[1] rdual vssi[13] vssi[5] dcr vddi[3] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] d[7] d[6] d[5] vssi[4] vssi[3] vssi[2] vddi[1] vsso[1] vdd0[1] d[4] d[3] d[2] d[1] d[0] intb rdb wrb csb ale rstb tdo trstb tms tck tdi vssi[1] vssi[8]
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 19 8 pin description pin name type pin no. function txtip[4] txtip[3] txtip[2] txtip[1] output 54 49 113 118 transmit bipolar tip (txtip[4:1]). the txtip[4:1] outputs are the transmit analog positive pulses. these analog outputs drive an ac signal through an external matching transformer. they must be connected to the positive lead of the transformer primary. an analog transmit monitor positive point is internally bonded to each of these outputs and is used to monitor the positive pulses on each transmit line. txring[4] txring[3] txring[2] txring[1] output 57 46 110 121 transmit bipolar ring (txring[4:1]). the txring[4:1] outputs are the transmit analog negative pulses. these analog outputs drive an ac signal through an external matching transformer. they must be connected to the negative lead of the transformer primary. an analog transmit monitor negative point is internally bonded to each of these outputs and is used to monitor the negative pulses on each transmit line. tc[4] tc[3] tc[2] tc[1] i/o 59 44 108 123 transmit reference decoupling capacitor (tc[4:1]). these analog bidirectionals provide decoupling for an internal reference generator. they must be connected to an external decoupling capacitor to the corresponding tavd[4:1].
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 20 pin name type pin no. function tdd[4] tdd[3] tdd[2] tdd[1] input 68 71 74 77 transmit data (tdd[4:1]). when in single-rail mode, these inputs are the nrz data signals to be transmitted. these inputs can be configured to be active high or active low. these inputs can be sampled on either the rising or falling edges of the corresponding tclki[4:1]. tdp[4] tdp[3] tdp[2] tdp[1] input transmit positive data (tdp[4:1]). when in dual- rail mode, these inputs are the nrz positive data signals to be transmitted. these inputs can be sampled on either the rising or falling edges of the corresponding tclki[4:1]. tdn[4] tdn[3] tdn[2] tdn[1] input 67 70 73 76 transmit negative data (tdn[4:1]). when in dual-rail mode, these inputs are the nrz negative data signals to be transmitted. these inputs can be sampled on either the rising or falling edges of the corresponding tclki[4:1]. these input pins are ignored if the device is configured for single-rail (unipolar) transmit mode. tclki[4] tclki[3] tclki[2] tclki[1] input 69 72 75 78 transmit clock (tclki[4:1]). this clock should be 1.544 mhz for ds1 or 2.048 mhz for e1 data streams and is used to sample the corresponding tdp/tdd[4:1] and tdn[4:1] signals. rxtip[4] rxtip[3] rxtip[2] rxtip[1] input 64 39 103 128 receive bipolar tip (rxtip[4:1]). the rxtip[4:1] inputs are the receive analog positive pulses. they must be connected to the positive lead of the transformer secondary through a passive attenuation network. rxring[4] rxring[3] rxring[2] rxring[1] i/o 63 40 104 127 receive bipolar ring (rxring[4:1]). the rxring[4:1] bidirectional pins provide dc bias to an external isolation transformer. they must be connected to the negative lead of the transformer secondary and to a decoupling capacitor to ravs[4:1].
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 21 pin name type pin no. function rc[4] rc[3] rc[2] rc[1] i/o 61 42 106 125 receive peak hold r-c network (rc[4:1]). the rc[4:1] analog bidirectional pins must be connected to an external parallel resistor/capacitor network to ravs[4:1]. this network is necessary to the operation of the internal peak detector that tracks the incoming signal level. rdd[4] rdd[3] rdd[2] rdd[1] output 89 92 97 100 receive digital data (rdd[4:1]). when configured for unipolar outputs, the rdd[4:1] nrz outputs contain the sampled ds-1 or e1 data which has been decoded by ami, b8zs, or hdb3 line code rules. rdd[4:1] outputs can be updated on either the falling or rising rclko[4:1] edge. rdp[4] rdp[3] rdp[2] rdp[1] output receive digital positive pulse (rdp[4:1]). when configured for bipolar outputs, the rdp[4:1] nrz outputs contain sampled bipolar positive pulses. rdp[4:1] outputs can be updated on either the falling or rising rclko[4:1] edge. sdp[4] sdp[3] sdp[2] sdp[1] output sliced positive line pulse (sdp[4:1]). a positive pulse on the sdp[4:1] outputs corresponds to the sampled positive pulse excursion on the rxtip[4:1] input.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 22 pin name type pin no. function rlcv[4] rlcv[3] rlcv[2] rlcv[1] output 88 91 96 99 receive line code violation indication (rlcv[4:1]). when configured for unipolar outputs, the rlcv[4:1] nrz outputs pulse whenever a line code violation or excess zeroes condition is detected. rdp[4:1] outputs can be updated on either the falling or rising rclko[4:1] edge. rdn[4] rdn[3] rdn[2] rdn[1] output receive digital positive pulse (rdn[4:1]). when configured for bipolar outputs, the rdn[4:1] nrz outputs contain sampled bipolar negative pulses. rdn[4:1] outputs can be updated on either the falling or rising rclko[4:1] edge. sdn[4] sdn[3] sdn[2] sdn[1] output sliced negative line pulse (sdn[4:1]). a positive pulse on the sdn[4:1] outputs corresponds to the sampled negative pulse excursion on the rxtip[4:1] input. rclko[4] rclko[3] rclko[2] rclko[1] output 87 90 95 98 recovered clock output (rclko[4:1]). rclko[4:1] is the clock recovered from the rxtip[4:1] and rxring[4:1] input signals. rclko[4:1] are 2ma output pads. care must be taken in board layouts to guarantee the integrity of the clock signals. xclk/ input 79 crystal clock input (xclk). this signal supplies the timing reference for the high-speed clocks required by many portions of the qdsx. when jitter attenuation is required, xclk is nominally a 24x clock (37.056 mhz for t1, 49.152 mhz for e1). when jitter attenuation is not required, xclk can be driven by an 8x clock (12.352 mhz for t1, 16.384 mhz for e1). vclk vector clock (vclk). the vclk signal is used during qdsx production test to verify internal functionality.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 23 pin name type pin no. function clko8x/ output 86 8x clock output (clko8x). this output is the internal 8x high-speed clock derived from the digital jitter attenuator, or derived by dividing down the 24x xclk input. it is used as the reference clock to generate the transmit analog pulse template. the clko8x signal is generated from quadrant 1. 1x clock output (clko1x). clko1x output when an 8x clock is provided on xclk, this is the internal 8x clock divided by 8. this output can be used to synchronously clock in data on tdp[4:1]/tdd[4:1] and tdn[4:1] by connecting it to tclki[4:1]. dcr input 37 disable clock recovery input (dcr). when set high, the dcr input will disable clock recovery in the qdsx and enable the sdp[4:1] and sdn[4:1] sliced line pulse outputs. this input is logically "ored" with the dcr register bits. tdual input 66 transmit dual-rail input select (tdual). this input selects whether the qdsx expects single- rail or dual-rail input transmit data. the tdual input is logically "ored" with the tdual register bits. when tdual is set high, the tdp[4:1] and tdn[4:1] inputs are enabled. when both the tdual input pin and register bits are set low, then the tdd[4:1] inputs are enabled and the tdn[4:1] inputs are ignored.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 24 pin name type pin no. function rdual input 101 receive dual-rail output select (rdual). this input selects whether the qdsx generates single-rail or dual-rail outputs from its receiver section. the rdual input is logically "ored" with the rdual register bits. when rdual is set high, the rdp[4:1] and rdn[4:1] outputs are enabled. when both the rdual input pin and register bits are set low, then line decoding is performed on the receive slicer outputs and the rdd[4:1] and rlcv[4:1] outputs are enabled. the state of the dcr input pin or the dcr register bits takes precedence over the rdual state. csb input 9 active low chip select (csb). this signal must be low to enable qdsx register accesses. csb must go high at least once after a powerup to clear internal test modes. if csb is not used, then it should be tied to an inverted version of rstb, in which case rdb and wrb determine register access. wrb input 10 active low write strobe (wrb). this signal is pulsed low to enable a qdsx register write access. the d[7:0] bus is clocked into the addressed register on the rising edge of wrb while csb is low. rdb input active low read enable (rdb). this signal is pulsed low to enable a qdsx register read access. the qdsx drives the d[7:0] bus with the contents of the addressed register while rdb and csb are both low.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 25 pin name type pin no. function a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] input 35 34 33 32 31 30 29 28 27 address bus (a[8:0]). this bus selects specific registers during qdsx register accesses. ale input 8 address latch enable (ale). this signal latches the address bus contents, a[8:0], when low, allowing the qdsx to be interfaced to a multiplexed address/data bus. when ale is high, the address latches are transparent. ale has an integral pull-up resistor. intb output 12 active low open-drain interrupt (intb). this signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources. note that intb will remain low until all active unmasked interrupt sources are acknowledged at their source.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 26 pin name type pin no. function d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] i/o 26 25 24 17 16 15 14 13 bidirectional data bus (d[7:0]). this bus is used during qdsx read and write accesses. rstb input 7 active low reset (rstb). this signal is set low to asynchronously reset the qdsx. rstb is a schmitt-trigger input with an integral pull-up resistor. tck input 3 test clock (tck). this signal provides timing for test operations that can be carried out using the ieee p1149.1 test access port. tms input 4 test mode select (tms). this signal controls the test operations that can be carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an integral pull up resistor. tdi input 2 test data input (tdi). this signal carries test data into the qdsx via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an integral pull up resistor. tdo tristate output 6 test data output (tdo). this signal carries test data out of the qdsx via the ieee p1149.1 test access port. tdo is updated on the falling edge of tck. tdo is a tristate output which is inactive except when scanning of data is in progress.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 27 pin name type pin no. function trstb input 5 active low test reset (trstb). this signal provides an asynchronous qdsx test access port reset via the ieee p1149.1 test access port. trstb is a schmitt triggered input with an integral pull up resistor. when not being used, trstb should be tied to rstb. vddo[6] vddo[5] vddo[4] vddo[3] vddo[2] vddo[1] power 119 112 94 55 48 18 pad ring power pins (vddo[6:1]). these pins must be connected to a common well decoupled +5v dc power supply together with the vddi[3:1], tavd[4:1], and ravd[4:1] pins. care must be taken to avoid coupling noise between these pins. vddi[3] vddi[2] vddi[1] power 36 84 20 core power pins (vddi[3:1]). these pins must be connected to a common well decoupled +5v dc power supply together with the vddo[6:1], tavd[4:1], and ravd[4:1] pins. care must be taken to avoid coupling noise between these pins. vsso[6] vsso[5] vsso[4] vsso[3] vsso[2] vsso[1] ground 120 111 93 56 47 19 pad ring ground pins (vsso[6:1]). these pins must be connected to a common ground together with the vssi[15:1], tavs[4:1], and ravs[4:1] pins. care must be taken to avoid coupling noise between these pins.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 28 pin name type pin no. function vssi[15] vssi[14] vssi[13] vssi[12] vssi[11] vssi[10] vssi[9] vssi[8] vssi[7] vssi[6] vssi[5] vssi[4] vssi[3] vssi[2] vssi[1] ground 116 115 102 83 82 81 80 65 52 51 38 23 22 21 1 core ground pins (vssi[15:1]). these pins must be connected to a common ground together with the vsso[6:1], tavs[4:1], and ravs[4:1]pins. care must be taken to avoid coupling noise between these pins. these pins also act as thermal-dissipation grounds, and as such should be thermally well-connected to a ground plane. tav d [ 4 ] tav d [ 3 ] tav d [ 2 ] tav d [ 1 ] tx analog power 58 45 109 122 transmit analog power pins (tavd[4:1]). these pins provide the +5 v supply to the transmit analog line interfaces. the transmit analog line interface remains in a low power consumption state after reset until enabled. tavd[4:1] must be connected to a common well decoupled +5 v dc power supply together with the vddo[6:1], vddi[3:1], and ravd[4:1] pins. care must be taken to avoid coupling noise between these pins. tavs[4] tavs[3] tavs[2] tavs[1] tx analog ground 53 50 114 117 transmit analog ground pins (tavs[4:1]). these pins provide the ground supply to the transmit analog line interface. tavs[4:1] must be connected to a common ground together with the vsso[6:1], vssi[15:1], and ravs[4:1] pins. care must be taken to avoid coupling noise between these pins.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 29 pin name type pin no. function ravd[4] ravd[3] ravd[2] ravd[1] rx analog power 62 41 105 126 receive analog power pins (ravd[4:1]). these pins provide the +5 v dc power supply to the receive analog line interface. ravd[4:1] must be connected to a common well decoupled +5 v dc power supply together with the vddo[6:1], vddi[3:1], and tavd[4:1] pins. care must be taken to avoid coupling noise between these pins. ravs[4] ravs[3] ravs[2] ravs[1] rx analog ground 60 43 107 124 receive analog ground pins (ravs[4:1]). these pins provide the ground supply to the receive analog line interface. ravs[4:1] must be connected to a common ground together with the vsso[6:1], vssi[15:1], and tavs[4:1] pins. care must be taken to avoid coupling noise between these pins. notes on pin description: 1. vddi[3:1] and vssi[15:1] are the +5 v and ground connections, respectively, for the core circuitry of the device. vddo[6:1] and vsso[6:1] are the +5 v and ground connections, respectively, for the pad ring circuitry of the device. tavd[4:1] and tavs[4:1] are the +5 v and ground connections, respectively, for the transmit analog circuitry of the device. ravd[4:1] and ravs[4:1] are the +5 v and ground connections, respectively, for the receive analog circuitry of the device. these power supply connections must all be utilized and must all connect to a common +5 v or ground rail, as appropriate. there is no low impedance connection within the PM4314 qdsx between the core, pad ring, transmit analog, and receive analog supply rails. failure to properly make these connections may result in improper operation or damage to the device. care must be taken to avoid coupling of noise into the transmit and receive analog supply rails. 2. inputs rstb, ale, tms, tdi, and trstb have integral pull-up resistors. 3. all qdsx inputs and bidirectionals present minimum capacitive loading and operate at ttl logic levels.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 30 4. all qdsx digital outputs and bidirectionals have 2 ma drive capability. the data bus outputs, d[7:0], and clko8x have 4 ma drive capability. for board layouts, care should be maken with the 2ma drive rclko[4:1] signals to guarantee clock signal integrity. 5. the recommended power supply sequencing is as follows: 5.1 vddi[3:1] power must be supplied either before vddo[6:1] or simultaneously with vddo[6:1]. connection of vddi[3:1] and vddo[6:1] to a common vdd power plane is recommended. 5.2 the vddi[3:1] and vddo[6:1] power must be applied before input pins are driven or the input current per pin must be limited to less than 20 ma. 5.3 analog power supplies must be applied after both vddi[3:1] and vddo[6:1] have been applied or the they must be current limited to the maximum latchup current specification. (100 ma). in operation the differential voltage measured between tavd[4:1] and ravd[4:1] supplies and vddi[3:1] and vddo[6:1] must be less than 0.5 volt. the relative power sequencing of tavd[4:1] and ravd[4:1] power supplies is not important. 5.4 power down the device in the reverse sequence.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 31 9 functional description 9.1 analog pulse slicer (rslc) the analog t1/e1 pulse slicer function is provided by the rslc block. the receive data slicer (rslc) block provides the first stage of signal conditioning for a g.703 1544kbit/s (dsx-1) or 2048 kbit/s (e1) serial data stream by converting bipolar line signals to dual rail rz pulses. before an rz output pulse is generated by the rslc block, bipolar input signals must rise to 50% (for e1) or 67% (for dsx-1) of their peak amplitude. this level is referred to as the slicing level. the threshold criteria insures accurate pulse or mark recognition in the presence of noise. the rslc block relies on an external network for compliance to the dsx-1 and e1 input port specifications. the rslc block is configured via an off-chip attenuator pad to operate in one of four modes: dsx-1 normal mode, dsx-1 bridging mode, g.703 120 w twisted pair, or g.703 75 w coax. according to g.703, the amplitude of a dsx-1 normal mode received pulse at the 1:2 line-coupling transformer's primary should be in the range from 3.6v to 1.2v (depending on the length of the cable from the signal source). in this mode, the qdsx can receive signal levels down to a typical squelching level of 227mv, leaving a 14.5db margin between the minimum expected signal level and the typical minimum receivable signal level. in dsx-1 bridging mode, the qdsx is connected to a monitor jack which bridges across the line and attenuates the signal levels by 20 db, so the expected pulse amplitude at the 1:2 line-coupling transformer's primary should be in the range from 360mv to 120mv (depending on the length of the cable from the signal source). in this mode, the qdsx can receive signal levels down to a squelching level of 50mv, leaving 7.6 db margin between the minimum expected signal level and the typical minimum receivable signal level. in 120 w e1 mode, the amplitude of a received pulse at the 1:2 line-coupling transformer's primary can be in the range from 3.3v to 1.4v (depending on the length of the cable from the signal source). in this mode, the qdsx can receive signal levels down to a squelching level of 276mv, which means that there is 14.1 db margin between the minimum expected signal level and the typcial minimum receivable signal level.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 32 in 75 w e1 mode, the amplitude of a received pulse at the 1:2 line-coupling transformer's primary can be in the range from 2.6v to 1.1v (depending on the length of the cable from the signal source). in this mode, the qdsx can receive signal levels down to a squelching level of 220mv which means that there is 14.0 db margin between the minimum expected signal level and the minimum receivable signal level in the worst case. the rslc block provides a squelching circuit, which indicates an alarm when input pulses are below the squelching level threshold. in this state, data is not sliced, which prevents the detection of noise on an idle transmission line. the sq status bit in the rslc interrupt enable/status registers (031h, 071h, 0b1h, and 0f1h) goes high whenever the rslc block is squelching the input signal. the rslc can be configured to generate an interrupt whenever the sq status bit changes state. the off-chip attenuator pad network is shown in figure 6 and the network values below are recommended for the specified applications: ta bl e 1 - signal type turns ratio (n 5%) r1 ( w 1%) r2 ( w 1%) squelch level at primary (mv typical) zo=120 w 2 357 121 276 cept e1 zo=75 w 2 205 95.3 220 normal 2 309 93 227 dsx-1 bridging 2 0 402 50 tight tolerances are required on the resistors and turns ratio to meet the return loss specification.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 33 figure 6 - external analog receive interface circuit t r 1:n 316 k w 1% 47 nf 10% rxtip rxring v ravs ravd rc 0.1 f 10% r2 r1 dd 2. some transformer manufacturers produce a dual part containing both the 1:2 & 1:1.36 transformers required for the receive and transmit interfaces, respectively. 1. all capacitors ceramic notes: the transformer used should be designed for use in t1/cept/isdn-pri applications. many manufacturers have standard products for these applications. typical characteristics of a suitable transformer are given in the following table.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 34 ta bl e 2 - tu r n s ratio (pri:sec) ocl (mh min.) c w/w (pf max.) l l (h max.) dcr pri. ( w max.) dcr sec. ( w max.) 1:2 1.20 35 0.80 0.80 1.2 where ocl is the open-circuit inductance, c w/w is the inter-winding capacitance, l l is the leakage inductance, and dcr is the dc resistance. pmc-sierra has verified the operation of the rslc functional block with the following transformers: pulse engineering pe64931 (1:1:1) and pe64952 (1:2ct) bh electronics 500-1775 (1:1:1) and 500-1777 (1:2ct) many manufacturers produce dual transformers containing the 1:2 ct and 1:1.36 transformers necessary for the receiver and transmitter circuits. pmc-sierra has verified the operation of xpls and rslc with the following dual parts: pulse engineering pe64952 pulse engineering pe65774 (for extended temperature range) bh electronics500-1777 9.2 clock and data recovery (cdrc) the clock and data recovery function is contained in the cdrc block and is active when clock recovery is not disabled. the cdrc provides clock and data recovery, b8zs/hdb3 decoding, bipolar violation detection, and loss of signal detection. it recovers the clock from the incoming rz data pulses using a digital phase-locked-loop and recovers the nrz data. loss of signal is declared after exceeding a programmed threshold of 10, 31, 63, or 175 consecutive bit periods of the absence of pulses on both the positive and negative line pulse inputs and is removed after the occurrence of a single line pulse. if enabled, a microprocessor interrupt is generated when a loss of signal is detected and when the signal returns. when the cdrc is disabled, the positive and negative sliced
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 35 pulses from rslc are passed directly to the sdp[x] and sdn[x] outputs respectively. the input jitter tolerance for dsx-1 interfaces complies with the bellcore document ta-tsy-000170 and with the at&t specification tr 62411. the tolerance is measured with a qrss sequence (2 20 -1 with 14 zero restriction). the cdrc block provides two algorithms for clock recovery that result in differing jitter tolerance characteristics. the first algorithm (when the algsel register bit in the cdrc configuration register (010h, 050h, 090h, 0d0h) is logic 0) provides good low frequency jitter tolerance, but the high frequency tolerance is close to the tr 62411 limit. the second algorithm (when algsel is logic 1) provides much better high frequency jitter tolerance, approaching 0.5uipp (unit intervals peak-to-peak), at the expense of the low frequency tolerance; the low frequency tolerance of the second algorithm is approximately 80% of that of the first algorithm. the dsx-1 jitter tolerance with algsel set to 1 and to 0 is shown in figure 7.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 36 figure 7 - dsx-1 jitter tolerance 10 0.3 0.31 10 100 0.4 at&t spec. bellcore spec. in spec. region cdrc max. tolerance (algsel=0) sinewave jitter frequency, khz - log scale sinewave jitter amplitude p. to p. (ui) log scale cdrc max. tolerance (algsel=1) 0.70 the input jitter tolerance for e1 interfaces complies with itu-t recommendation g.823. the tolerance is measured with a 2 15 -1 sequence. the e1 jitter tolerance with algsel set to 1 and to 0 is shown in figure 8 and figure 9.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 37 figure 8 - e1 jitter tolerance with algsel = 1 jitter frequency (hz) . 0.01 0.1 jitter amplitude (uip-p) 1.0 10 measured cdrc jitter tolerance (algsel = 1) g823 jitter tolerance specification measurement limit 100 1k 10k 100k . 10
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 38 figure 9 - e1 jitter tolerance with algsel = 0 . measurement limit measured cdrc jitter tolerance (algsel = 0) g823 jitter tolerance specification 0.01 0.1 jitter amplitude (uip-p) 1.0 10 jitter frequence (hz) 100 1k 10k 100k . 10 9.3 line code violation performance monitor (lcv_pmon) the line code violation performance monitor function is provided by the (lcv_pmon) block. this block accumulates line code violation events with saturating counters over consecutive intervals as defined by the period of the supplied transfer clock signal. when the transfer clock signal is applied, the lcv_pmon block transfers the counter values into holding registers and resets the counters to begin accumulating events for the interval. the counters are reset in such a manner that error events occurring during the reset are not missed. if enabled, an interrupt is generated whenever counter data is transferred into the holding registers. if the holding registers are not read between successive transfer clocks, the ovr register bit in the lcv_pmon interrupt enable/status register (014h, 054h, 094h, and 0d4h) is asserted.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 39 generation of the individual lcv_pmon transfer clocks for specific quadrants of the qdsx is performed by writing to any of the lcv_pmon counter register locations of the particular quadrant. a global performance monitor transfer clock signal is generated by writing to register 007h. this will latch the counter values in all the lcv_pmons and prsms of the qdsx. the holding register addresses are contiguous to facilitate polling operations. 9.4 inband loopback code detector (ibcd) the inband loopback code detection function is provided by the ibcd block. this block detects the presence of either of two programmable loopback code sequences, activate and deactivate, in framed or unframed ds-1 data streams. the inband code sequences are expected to be overwritten by the framing bit in framed data streams. each code sequence is defined as the repetition of the programmed code in the pcm stream for at least 5.1 seconds. the code sequence detection and timing is compatible with the specifications defined in t1.403, ta-tsy-000312, and tr-tsy-000303. activate and deactivate code indication is provided through internal register bits. an interrupt is generated to indicate when either code status has changed. the ibcd can detect inband loopback codes in the recovered unipolar receive data when configured to be in the receive data stream or in the unipolar input transmit data when configured to be in the transmit data stream. when enabled in the receive stream, the ibcd can be configured to enable and disable line loopback on detection of inband loopback activate and deactivate sequences. 9.5 pseudo-random bit sequence monitor (prsm) the pseudo-random sequence monitor (prsm) block monitors the recovered pcm data for the presence of an unframed 2 15 -1 test sequence as defined in recommendation o.151 and accumulates bit errors detected using this pseudo- random pattern. the test sequence may optionally be inverted before being checked against the generated pattern. the sequence monitor does not synchronize to an all zeroes pattern. the prsm declares synchronization when less than 15 sequence errors are detected in 256 bit periods. using this threshold, synchronization is achieved within 663 sec (for dsx-1 applications) or 500 sec (for e1 applications), 99.7% of the time, in the presence of a 10 -2 bit error rate. once synchronized, the mean time between loss of synchronization events is greater than 136 minutes (for dsx-1) or 103 minutes (for e1), in the presence of a 10 -2 bit error rate. when the test sequence is no longer present (as indicated by a bit error rate of 0.5) the prsm will lose synchronization in 48 sec (for dsx-1) or 36 sec (for e1), more than 99% of the time. in the
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 40 presence of random data (a bit error rate of 0.5) the mean time between false synchronization events is greater than 184 years. the prsm can be configured to detect either an inverted or a noninverted 2 15 -1 pseudorandom bit sequence (prbs). an inverted 2 15 -1 prbs will contain at most 15 consecutive zeroes, while a non-inverted 2 15 -1 prbs will contain at most 14 consecutive zeroes. the prsm block accumulates bit error events with a saturating counter over consecutive intervals as defined by the period of a latch clock signal. an internal latch clock signal, unique to each prsm in the qdsx, can be generated by writing to any of the particular prsm holding registers. a write to any prsm holding register in quadrant 1 of the qdsx generates an internal latch clock pulse for the prsm in quadrant 1. similarly a write to any prsm holding register in any other quadrant generates an internal latch clock pulse for the prsm in that same quadrant. a write to register 007h will generate a global performance monitor latch clock signal. a write to this register will toggle the internal latch clock pulses to all four prsms as well as all four lcv_pmons (which operate in a similar fashion). if enabled, an interrupt is generated whenever counter data is transferred into the prsm holding registers. if the holding registers are not read between successive transfer clocks, the overrun (ovr) bit in the prsm control/status register is set. an indication of whether or not the pseudorandom sequence monitor is synchronized is provided via the prsm control/status register and, if enabled, an interrupt is generated whenever a loss of synchronization or resynchronization occurs. the prsm can detect pseudorandom sequences in the receive stream, or in the transmit stream if tdual is set to logic 0. prsm functions are available only when microprocessor access is available (microen is high). 9.6 timing options (tops) if jitter attenuation is required, then xclk must be a 24x clock, and tops will generate the 8x clock either from the djat pll smoothed 8x clock from quadrant 1, or by dividing xclk by 3. this 8x clock will be presented on clko8x. otherwise, xclk is expected to be an 8x high speed clock and tops will simply buffer it before passing it off as the internal high speed
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 41 reference clock. when an 8x reference is provided, the clko1x output is active, and carries the internal 8x reference clock divided by 8. 9.7 pseudo-random bit sequence generator (prsg) the pseudo-random bit sequence generator (prsg) generates an unframed 2 15 -1 test sequence as defined in recommendation o.151. the prsg can be enabled to overwrite the unipolar input transmit data when configured to be in the transmit data stream or the recovered unipolar receive data when configured to be in the receive data stream. the microprocessor can force the prsg to insert single bit errors in the pseudorandom data for diagnostic purposes. the prsg can be configured to generate either an inverted or a noninverted 2 15 -1 pseudorandom bit sequence (prbs). an inverted 2 15 -1 prbs will contain at most 15 consecutive zeroes, while a non-inverted 2 15 -1 prbs will contain at most 14 consecutive zeroes. 9.8 inband loopback code generator (xibc) the inband loopback code generator function is provided by the xibc block. this block generates a stream of inband loopback codes to be inserted into a ds-1 data stream. the stream consists of continuous repetitions of a specific code. the contents of the code and its length are programmable from 3 to 8 bits. the xibc can be enabled to overwrite the unipolar input transmit data when configured to be in the transmit data stream or the recovered unipolar receive data when configured to be in the receive data stream. 9.9 b8zs/hdb3/ami line encoder (lcode) the b8zs/hdb3/ami line encoding function is provided by the lcode block. this block will encode single-rail data inputs into bipolar b8zs, hdb3, or ami format. for dsx-1 applications, b8zs line encoding is selected by default. for e1 applications, hdb3 line encoding is selected by default. the microprocessor may instruct the lcode block to insert line code violations for diagnostic purposes. 9.10 digital jitter attenuator (djat) the digital jitter attenuator (djat) function is used to attenuate jitter in the transmit clock when required. the djat block receives jittered data and stores
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 42 this data in a fifo. the data emerges from the djat timed to the jitter attenuated clock and is transferred to the xpls block for transmission. the djat generates a "jitter-free" 1.544/2.048 mhz clock by adaptively dividing the 24x xclk input according to the phase difference between the generated "jitter-free" clock and the input data clock to djat (tclki[x] when djat is in the default transmit path, or the recovered clock rclko[x] if in line loopback mode or when djat is configured to be on the receive path). phase variations in the input clock with a jitter frequency above 8.8 hz (for the e1 format) or 6.6 hz (for the t1 formats) are attenuated by 6 db per octave of jitter frequency. phase variations below these jitter frequencies are tracked by the "jitter-free" clock. jitter characteristics the djat provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. it can accommodate up to 28 uipp of input jitter at jitter frequencies above 6 hz for dsx-1 interfaces or 9 hz for e1 interfaces. for jitter frequencies below 6/9 hz, more correctly called wander, the tolerance increases 20 db per decade. in most applications djat will limit jitter tolerance at lower jitter frequencies only. the djat block meets the low frequency jitter tolerance requirements of at&t tr 62411 for dsx-1 interfaces, and itu-t g.823 for e1 interfaces. outgoing jitter may be dominated by the generated residual jitter in cases where the incoming jitter is insignificant. this residual jitter is directly related to the use of the 24x clock for the digital phase locked loop. for dsx-1 interfaces, djat meets the jitter attenuation requirements of at&t tr 62411. djat meets the implied jitter attenuation requirements for a te or an nt1 specified in ansi t1.408, and for a type ii customer interface specified in ansi t1.403. for e1 interfaces, djat meets the jitter attenuation requirements of itu-t recommendations g.737, g.738, g.739, and g.742. jitter tolerance jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. for djat, the input jitter tolerance is 29 unit intervals peak-to-peak (uipp) for a dsx-1 interface with a worst case frequency offset of 354 hz. the input jitter tolerance is 35 uipp for an e1 interface with a worst case frequency offset
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 43 of 308 hz. it is 48 uipp with no frequency offset. the frequency offset is the difference between the frequency of xclk divided by 24 and that of the input data clock. these tolerances are shown in figure 10 and figure 11. figure 10 - dsx-1 jitter tolerance 100 10 1.0 0.1 110 100 1k 10k jitter frequency, hz jitter amplitude, uipp 0.01 100k 28 29 acceptable unacceptable 0.2 4.9 0.3k djat minimum tolerance
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 44 figure 11 - e1 jitter tolerance 100 10 1.0 0.1 1 10 100 1k 10k jitter frequency, hz jitter amplitude, ui pp 0.01 100k 35 acceptable itu -t g.82 3 unacceptable region 0.2 djat minimum tolerance 1.5 20 2.4k 18k 40 the accuracy of the xclk frequency and that of the djat pll reference input clock used to generate the "jitter-free" clock have an effect on the minimum jitter tolerance. for dsx-1 interfaces, the djat pll reference clock accuracy can be 130 hz from 1.544 mhz, and the xclk input accuracy can be 100 ppm from 37.056 mhz. for e1 interfaces, the pll reference clock accuracy can be 50 hz from 2.048 mhz, and the xclk input accuracy can be 50 ppm from 49.152 mhz. the minimum jitter tolerance for various differences between the frequency of pll reference clock and xclk 24 are shown in figure 12 and figure 13.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 45 figure 12 - djat minimum jitter tolerance vs. xclk accuracy (dsx-1 case) 100 200 300 354 djat minimum jitter tolerance ui pp 40 35 30 25 0 100 32 max frequency offset (pll ref to xclk) xclk accuracy hz ppm 250 29 34 36 figure 13 - djat minimum jitter tolerance vs. xclk accuracy (e1 case) 100 200 300 308 djat minimum jitter tolerance ui pp 45 40 35 30 0 100 49 max frequency offset (pll ref to xclk) xclk accuracy hz ppm 34.9 39 42.4
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 46 jitter transfer the output jitter for jitter frequencies from 0 to 6.6 hz (for dsx-1 interfaces) or from 0 to 8.8 hz (for e1 interfaces) is no more than 0.1 db greater than the input jitter, excluding the residual jitter. jitter frequencies above 6.6/8.8 hz are attenuated at a level of 6 db per octave, as shown in figure 14 and figure 15. figure 14 - dsx-1 jitter transfer 0 -10 -20 -30 -40 -50 1 10 100 1k 10k jitter frequency, hz jitter gain (db) 6.6 62411 max 62411 min djat response 43802 max
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 47 figure 15 - e1 jitter transfer 0 -10 -20 -30 -40 -50 1 10 100 1k 10k jitter frequency, hz jitter gain (db) 8.8 g.737, g738, g.739, g.742 max djat response 40 -19 .5 u nacc eptable region 9.11 analog pulse generator (xpls) the analog pulse generator function is provided by the transmit pulse generator (xpls) block that converts non-return-to-zero (nrz) pulses into line signals suitable for use in a g.703 1544 kbit/s and 2048 kbit/s intra-office environment. a logical "1" on the positive nrz input to xpls causes a positive pulse to be transmitted; a similar signal on the negative nrz input to xpls causes a negative pulse to be transmitted. if both positive and negative nrz inputs to xpls are logical "0" or "1," no output pulse is transmitted. the output pulse shape is synthesized digitally from user-programmed template settings with an internal digital to analog (d/a) converter. the converter is updated eight times per period with these programmed words. these words define the output pulse shape. recommended codes for dsx-1 and cept e1 120 w symmetrical lines and 75 w coaxial lines are given in the operations section. if an external circuit different from that recommended in the following diagram is used, the pulse generator permits creation of custom pulse shapes. refer to the operations section for details. ami signaling is created by exciting either the internal tip or ring drivers that drive a line-coupling transformer differentially via the txtip[4:1] and
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 48 txring[4:1] outputs. this differential driving scheme insures a small positive to negative pulse imbalance. the drivers, with the step-up transformer, amplify the output pulses to their final levels. the tip and ring drivers also supply the high current capability required to drive the low impedance output load. a small, high-frequency negative-going spike may be observed on the falling edge of the transmit pulse. this spike can be filtered out by using the optional "snubbing" network shown in the following diagram. this snubbing network should not be required when driving longer dsx-1 lines. the xpls includes a driver performance monitor to detect nonfunctional links. two monitor inputs, pm_tip and pm_ring, are internally bonded to the xpls's own txtip and txring outputs. if no pulses are detected alternately across the tip or ring monitor points for 62 or 63 consecutive clock periods (the exact number of clock periods, 62 or 63, depends upon the pattern of bipolar violations and the line-build out), the monitored link is declared failed. the xpls can be programmed to produce an interrupt whenever the link monitor state changes. the xpls block provides alarm indication signaling (ais) generation capability by generating alternating mark signals on the link when the tais bit is set high in the xpls control/status register (02dh, 06dh, 0adh, and 0edh). this ais generation may optionally be enabled when internal loopback modes are enabled.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 49 figure 16 - external analog transmit interface circuit 1:1.36 vdd c2 tavs tavd tc txtip txring t r c3 optional "snubbin g " network r1 c1 0 to 655 foot cable for dsx-1 r3 dsx-1/e1 interface r2 r1 47 w 10% 22 w 10% 47 w 10% c1 1nf10% 1nf10% 1nf10% c2 470nf10% 470nf10% 470nf10% c3 0.68f10%,50v 0.68f20%,50v 0.68f20%,50v r2 2.7 w 5%,1/8w 6.2 w 5%,1/8w 0 w r3 100 w 120 w 75 w format dsx-1zo=100 w e1 zo=120 w e1 zo=75 w the transformer used should be designed for use in t1/cept/isdn-pri applications. many manufacturers have standard products for these applications. typical characteristics of a suitable transformer are given in the following table. ta bl e 3 - tu r n s ratio (pri:sec) ocl (mh min.) c w/w (pf max.) l l (h max.) dcr pri. ( w max.) dcr sec. ( w max.) 1:1.36 1.20 35 0.80 0.80 1.2 where ocl is the open-circuit inductance, c w/w is the inter-winding capacitance, l l is the leakage inductance, and dcr is the dc resistance.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 50 pmc-sierra has verified the operation of the xpls functional block with the following 1:1.36 transformers: pulse engineering pe64937 (1:1.36) pulse engineering pe65340 (1:1.36) (for extended temperature range) bh electronics 500-1776 (1:1.36) many manufacturers produce dual transformers containing the1:2 ct and 1:1.36 transformers necessary for the receiver and transmitter circuits. pmc-sierra has verified the operation of xpls and rslc with the following dual parts: pulse engineering pe64952 pulse engineering pe65774 (for extended temperature range) bh electronics500-1777 9.12 ieee p1149.1 jtag test access port the ieee p1149.1 jtag test access port block provides jtag support for boundary scan. the standard jtag extest, sample, bypass, idcode and stctest instructions are supported. the qdsx identification code is 043140cd in hexadecimal format, shifted least significant bit first. 9.13 microprocessor interface the microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. the normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the qdsx. the register set is accessed as follows:
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 51 9.14 register memory map address register #1 # 2 # 3 # 4 000h 040h 080h 0c0h receive configuration 001h 041h 081h 0c1h transmit configuration 002h 042h 082h 0c2h tx/rx block placement 003h 043h 083h 0c3h interrupt source 004h 044h 084h 0c4h reserved 005h 045h 085h 0c5h diagnostics 006h master test 007h revision/chip id/global monitoring update 008h interrupt quadrant id 009h tops master clock configuration/clock activity monitor 046h 086h 0c6h reserved 047h 087h 0c7h reserved 048h 088h 0c8h reserved 049h 089h 0c9h reserved 00ah 04ah 08ah 0cah tops clock timing options 00bh 04bh 08bh 0cbh lcode transmit line code configuration 00ch 04ch 08ch 0cch reserved 00dh 04dh 08dh 0cdh reserved 00eh 04eh 08eh 0ceh reserved 00fh 04fh 08fh 0cfh reserved 010h 050h 090h 0d0h cdrc configuration 011h 051h 091h 0d1h cdrc interrupt enable
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 52 address register #1 # 2 # 3 # 4 012h 052h 092h 0d2h cdrc interrupt status 013h 053h 093h 0d3h reserved 014h 054h 094h 0d4h lcv_pmon interrupt enable/status 015h - 019h 056h - 059h 096h - 099h 0d6h - 0d9h lcv_pmon reserved 01ah 05ah 09ah 0dah lcv_pmon lcv count (lsb) 01bh 05bh 09bh 0dbh lcv_pmon lcv count (msb) 01ch 05ch 09ch 0dch djat interrupt status 01dh 05dh 09dh 0ddh djat reference clock divisor (n1) control 01eh 05eh 09eh 0deh djat output clock divisor (n2) control 01fh 05fh 09fh 0dfh djat configuration 020h 060h 0a0h 0e0h ibcd configuration 021h 061h 0a1h 0e1h ibcd interrupt enable/status 022h 062h 0a2h 0e2h ibcd activate code 023h 063h 0a3h 0e3h ibcd deactivate code 024h 065h 0a4h 0e4h xibc control 025h 065h 0a5h 0e5h xibc loopback code 026h 066h 0a6h 0e6h reserved 027h 067h 0a7h 0e7h prsg configuration 028h 068h 0a8h 0e8h prsm reserved 029h 069h 0a9h 0e9h prsm control/status 02ah 06ah 0aah 0eah prsm bit error event count (lsb) 02bh 06bh 0abh 0ebh prsm bit error event count (msb) 02ch 06ch 0ach 0ech xpls line length configuration 02dh 06dh 0adh 0edh xpls control/status
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 53 address register #1 # 2 # 3 # 4 02eh 06eh 0aeh 0eeh xpls code indirect address 02fh 06fh 0afh 0efh xpls code indirect data 030h 070h 0b0h 0f0h rslc configuration 031h 071h 0b1h 0f1h rslc interrupt enable/status 100h-1ffh reserved for test
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 54 10 normal mode register description normal mode registers are used to configure and monitor the operation of the qdsx. normal mode registers (as opposed to test mode registers) are selected when a[8] is low. notes on normal mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits should be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. all configuration bits that can be written into can also be read back. this allows the processor controlling the qdsx to determine the programming state of the device. 3. writeable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect qdsx operation unless otherwise noted. 5. certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the qdsx operates as intended, reserved register bits must only be written with logic zero. similarly, writing to reserved registers should be avoided.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 55 register 000h, 040h, 080h, and 0c0h: receive configuration bit type function default bit 7 r/w rdpinv 0 bit 6 r/w rdninv 0 bit 5 r/w rdual 0 bit 4 r/w rrise 0 bit 3 r/w auto_llb_en 0 bit 2 r/w auto_ais_en 0 bit 1 r/w bpvcnt 0 bit 0 r/w cept 0 these registers enable the receive interface to handle the various input and output waveform formats. rdpinv,rdninv: the rdpinv and rdninv bits enable the receive interface to logically invert the signals output on multifunction pins rdd/rdp[x] and rlcv/rdn[x], respectively. when rdpinv is set to logic 1, the interface inverts the output on rdd/rdp[x]. when rdpinv is set to logic 0, the interface outputs rdd/rdp[x] normally. when rdninv is set to logic 1, the interface inverts the output on rlcv/rdn[x]. when rdninv is set to logic 0, the interface outputs rlcv/rdn[x] normally. rdual: rdual configures the rdd/rdp[x] and rlcv/rdn[x] outputs to unipolar or bipolar form. when the rdual bit is set to logic 1, the bipolar outputs rdp[x] and rdn[x] are enabled. when the rdual bit is set to logic 0, the unipolar outputs rdd[x] and rlcv[x] are enabled. the rdual bit is logically "ored" with the rdual input pin. if either are set to logic 1, then the bipolar outputs rdp and rdn will be enabled. if the xibc or prsg are in the receive path, they will be bypassed if rdual is set. also, though bipolar violations in the input data will appear on rdp and rdn, the ibcd and prsm blocks will operate on a hdb3/b8zs/ami decoded version of the data, depending on the configuration of cdrc. note that the dcr bit in the cdrc configuration register (010h, 050h, 090h, and 0d0h) takes precedence over the rdual bit.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 56 rrise: the rrise bit configures the interface to update the multifunction outputs rdd/rdp[x] and rlcv/rdn[x] on the rising edge of rclko[x]. when rrise is set to logic 1, the interface is enabled to update the rdd[x]/tdp[x] and rlcv/rdn[x] output pins on the rising rclko[x] edge. when rrise is set to logic 0, the interface is enabled to update the outputs on the falling rclko[x] edge. auto_llb_en: when the auto_llb_en bit is set to logic 1 and the ibcd is enabled in the receive path, then when the ibcd in a quadrant detects the inband loopback activate code, the quadrant is immediately placed in line loopback mode. the quadrant is taken out of line loopback when the inband loopback deactivate code is detected, or when auto_llb_en is written with a logic zero. whenever the quadrant is placed in line loopback mode due to the reception of an inband loopback code, the auto_llb bit will be set to logic 1 in the diagnostics register. auto_llb_en should not be set to logic 1 if the djat is bypassed (fifobyp=1), or if djattx =0. auto_llb_en has no effect when ibcdtx =1. auto_ais_en: when set to logic 1, the auto_ais_en bit enables the insertion of ais in the receive path whenever the quadrant is in line loopback mode due to the reception of an inband line loopback activate code. auto_ais_en has no effect when auto_llb_en is a logic zero. bpvcnt: the bpvcnt bit enables only bipolar violations to indicate line code violations and be accumulated in the lcv_pmon lcv count registers. when bpvcnt is set to logic 1, only bpvs not part of a valid ami, b8zs, or hdb3 signature (depending on the configuration of the receiver) generate an lcv indication and increment the lcv_pmon lcv counter. when bpvcnt is set to logic 0, both bpvs not part of a valid signature and excessive zeros generate an lcv indication and increment the lcv_pmon lcv counter. excessive zeros is defined for this operation to be a sequence of zeros greater than 15 bits long for an ami coded t1 signal, greater than 7 bits long for a b8zs coded signal, and greater than 3 bits long for an e1 signal. cept: the cept bit configures the receiver for e1 applications. when cept is set to logic 1, the receiver is configured for e1 applications. when cept is set to logic 0, the receiver is configured for t1 applications. all cept bits in all four
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 57 quadrants and in both the transmit configuration (registers 001h, 041h, 081h, and 0c1h) and receive configuration registers should be set to the same value.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 58 register 001h, 041h, 081h, and 0c1h: transmit configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w tdpinv 0 bit 3 r/w tdninv 0 bit 2 r/w tdual 0 bit 1 r/w tfall 0 bit 0 r/w cept 0 these registers enable the transmit interface to generate the required digital output waveform format. tdpinv,tdninv: the tdpinv and tdninv bits enable the transmit interface to logically invert the input signals on the tdd/tdp[x] and tdn[x] inputs, respectively. when tdpinv is set to logic 1, the tdd/tdp[x] input is inverted. when tdpinv is set to logic 0, the tdd/tdp[x] input is not inverted. when tdninv is set to logic 1, the tdn[x] input is inverted. when tdninv is set to logic 0, the tdn[x] input is not inverted. tdual: tdual configures the tdd/tdp[x] and tdn[x] inputs to unipolar or bipolar form. when the tdual bit is set to logic 1, the bipolar inputs tdp[x] and tdn[x] are enabled. when the tdual bit is set to logic 0, the unipolar input tdd[x] is enabled and tdn[x] is ignored. the tdual bit is logically "ored" with the tdual input pin. if either are set to logic 1, then the bipolar inputs will be enabled. tfall: the tfall bit enables the transmit interface to sample the tdd/tdp[x] and tdn[x] inputs on the falling tclki[x] edge. when tfall is set to logic 1, the interface is enabled to sample the inputs on the falling tclki[x] edge. when tfall is set to logic 0, the interface is enabled to sample the inputs on the rising tclki[x] edge.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 59 cept: the cept bit configures the transmitter for e1 applications. when cept is set to logic 1, the transmitter is configured for e1 applications. when cept is set to logic 0, the transmitter is configured for t1 applications. all cept bits in all four quadrants and in both the transmit configuration and receive configuration (registers 000h, 040h, 080h, and 0c0h) registers should be set to the same value.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 60 register 002h, 042h, 082h, and 0c2h: tx/rx block placement bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r/w prsmtx 0 bit 3 r/w prsgtx 1 bit 2 r/w ibcdtx 0 bit 1 r/w xibctx 1 bit 0 r/w djattx 1 this register is used to configure the prsm, prsg, ibcd, xibc, and djat blocks to be on the transmit or the receive data paths. prsmtx: the prsmtx bit determines whether the prsm block is placed on the transmit or receive data paths. when prsmtx is set to a logic 1, then the prsm block is moved to the transmit path and will be used to synchronize to 2 15 -1 prbs sequences on the tdd[x] input. when the prsm block is in the transmit path, the tdual bits (in registers 001h, 041h, 081h, and 0c1h) and the tdual input pin must be set to logic 0 for proper operation. when prsmtx is set to a logic 0, then the prsm block is moved to the receive path and will be used to synchronize to 2 15 -1 prbs sequences from the analog rxtip[x] and rxring[x] inputs. prsgtx: the prsgtx bit determines whether the prsg block is placed on the transmit or receive data paths. when prsgtx is set to a logic 1, then the prsg block is moved to the transmit path and can be used to insert the 2 15 -1 prbs sequence into the transmit data. when the tdual bit or the tdual pin are logic 1, then the prsg has no effect if placed in the transmit path. when prsgtx is set to a logic 0, then the prsg block is moved to the receive path and can be used to source an unframed 2 15 -1 prbs sequence to the rdd[x] output.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 61 ibcdtx: the ibcdtx bit determines whether the ibcd block is placed on the transmit or receive data paths. when ibcdtx is set to a logic 1, then the ibcd block is moved to the transmit path and can be used to detect inband loopback code sequences in the transmit data. when the ibcd block is in the transmit path, the tdual bits (in registers 001h, 041h, 081h, and 0c1h) and the tdual input pin must be set to logic 0 for proper operation. when ibcdtx is set to a logic 0, then the ibcd block is moved to the receive path will be used to detect inband loopback code sequences from the analog rxtip[x] and rxring[x] inputs. xibctx: the xibctx bit determines whether the xibc block is placed on the transmit or receive data paths. when xibctx is set to a logic 1, then the xibc block is moved to the transmit path and can be used to insert unframed inband loopback code sequences into the transmit data. when the tdual bit or the tdual pin are logic 1, then the xibc has no effect if placed the transmit path. when xibctx is set to a logic 0, then the xibc block is moved to the receive path and can be used to source an unframed inband loopback code sequence to the rdd[x] output. djattx: the djat bit determines whether the djat block is placed on the transmit or receive data paths. when djattx is set to a logic 1, then the djat block is moved to the transmit path to attenuate jitter in the transmit data stream. when djattx is set to a logic 0, then the djat block is moved to the receive path and will attenuate the jitter on the rdd/rdp[x], rlcv/rdn[x], and rclko[x] outputs. note that a 24x clock must be input on xclk for jitter attenuation to operate (see tops clock timing options register 00ah, 04ah, 08ah, and 0cah and tops master clock configuration/clock activity monitor register 009h). whenever the djat is not active in the transmit path, the system 8x clock (presented on clk08x) must be synchronous to tclki[x], and line loopback cannot be used. refer to the operations section for more details on using the qdsx without the djat enabled in the transmit path.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 62 register 003h, 043h, 083h, and 0c3h: interrupt source bit type function default bit 7 r rlsc 0 bit 6 r xpls 0 bit 5 r ibcd 0 bit 4 r prsm 0 bit 3 r lcv_pmon 0 bit 2 unused x bit 1 r cdrc 0 bit 0 r djat 0 these registers allow software to determine the block within the corresponding quadrant which produced the interrupt on the intb output pin. reading these registers does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 63 register 005h, 045h, 085h, and 0c5h: diagnostics bit type function default bit 7 r/w lcvins 0 bit 6 unused x bit 5 r auto_llb x bit 4 r/w rxaisen 0 bit 3 r/w txaisen 0 bit 2 r/w dialb 0 bit 1 r/w dmlb 0 bit 0 r/w linelb 0 these registers allow software to enable the diagnostic modes on each interface. lcvins: the lcvins bit introduces a single line code violation on the transmitted data stream. in b8zs, the violation is generated by masking the first violation pulse of a b8zs signature. in ami, one pulse is sent with the same polarity as the previous pulse. in hdb3, the violation is generated by causing the next hdb3-code generated bipolar violation pulse to be of the same polarity as the previous bipolar violation. see the operations section for details. to generate another violation, this bit must first be written to 0 and then to logic 1 again. at least one bit period should elapse between writing lcvins 0 and writing it 1 again, or vice versa, if an error is to be successfully inserted. lcvins has no effect when tdual is set to logic 1. auto_llb: when this bit is set, it indicates that the quadrant has been placed in line loopback mode due to the reception of an inband loopback code while auto_llb_en was set. auto_llb is cleared when the quadrant is taken out of line loopback mode by the reception of an inband loopback deactivate code, or when auto_llb_en for that quadrant is set to logic 0. line loopback should not be enabled in the qdsx unless djat is enabled in the transmit path.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 64 rxaisen: when rxaisen is set to logic 1, an ais is presented on the rdd/rdp[x] and rdn[x] outputs. when rdd[x] is enabled, rdd[x] will be held always high. if rdp[x] and rdn[x] are enabled, an alternating ones pattern (i.e. a sequence of ami coded ones) will be presented on rdp and rdn. note that the rdpinv and rdninv bits will invert the inserted ais signal in the same way as other data. when rxaisen is set to logic 0, rdd/rdp[x] and rdn[x] carry data normally. txaisen: when the txaisen bit is set to logic one, an ais signal is inserted on txtip[x] and txring. this ais signal consists of an ami-encoded all-ones sequence. when txais is set to logic zero, txtip[x] and txring[x] carry data as normal. dialb: the dialb bit selects the diagnostic digital loopback mode, where the transmit data stream is connected to the receive data stream. when dialb is set to logic 1, the diagnostic digital loopback mode is enabled. when dialb is set to logic 0, the diagnostic digital loopback mode is disabled. dmlb: the dmlb bit enables the diagnostic metallic loopback mode, where the digital, rz positive and negative sliced versions of the analog signals output on the txtip[x] and txring[x] pins from xpls are internally connected to the receive positive and negative pulse inputs of cdrc. when dmlb is set to logic 1, the diagnostic metallic loopback mode is enabled. when dmlb is set to logic 0, the diagnostic metallic loopback mode is disabled. because diagnostic metallic loopback is essentially a zero-line-length loopback, the 0- 110 line build out should be selected when using dmlb in t1 operation. linelb: the linelb bit selects the line loopback mode, where the data input on rxtip[x] and rxring[x] is passed through the cdrc and then through djat before being retransmitted on txtip[x] and txring[x] respectively. when linelb is set to logic 1, the line loopback mode is enabled. when linelb is set to logic 0, line loopback mode is disabled. line loopback should not be enabled in the qdsx unless djat is enabled in the transmit path.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 65 register 006h or 106h: master test bit type function default bit 7 r/w reserved 0 bit 6 r/w a_tm[7] x bit 5 r/w a_tm[6] x bit 4 w pmctst x bit 3 w dbctrl x bit 2 r/w iotst 0 bit 1 w hizdata x bit 0 r/w hizio 0 this register is used to enable qdsx test features. all bits, except pmctst and a_tm[7:6] are reset to zero by a hardware reset of the qdsx. register 006h and 106h access the same register. the "mirroring" of this register to the two register spaces is done to ensure access to this register is available if the a[8] address pin is tied to logic 1 or 0. reserved: this bit must be set to logic 0 for proper normal mode operation. eng: hwtst: a_tm[6]: the state of the a_tm[6] bit internally replaces the input address line a[6] when pmctst is set. this allows for more efficient use of the pmc manufacturing test vectors. pmctst: the pmctst bit is used to configure the qdsx for pmc's manufacturing tests. when pmctst is set to logic one, the qdsx microprocessor port becomes the test access port used to run the pmc manufacturing test vectors. the pmctst bit is logically "ored" with the iotst bit, and can be cleared by setting csb to logic one or by writing logic zero to the bit.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 66 dbctrl: the dbctrl bit is used to pass control of the data bus drivers to the csb pin. when the dbctrl bit is set to logic one and either iotst or pmctst are logic one, the csb pin controls the output enable for the data bus. while the dbctrl bit is set, holding the csb pin high (iotst must be set to logic 1 since csb high resets pmctst) causes the qdsx to drive the data bus and holding the csb pin low tristates the data bus. the dbctrl bit overrides the hizdata bit. the dbctrl bit is used to measure the drive capability of the data bus driver pads. iotst: the iotst bit is used to allow normal microprocessor access to the test registers and control the test mode in each tsb block in the qdsx for board level testing. when iotst is a logic one, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequentially the device outputs (refer to the "test mode 0 details" in the "test features" section). the iotst bit is also used in conjunction with the hwtst bit as described below. hizio, hizdata: the hizio and hizdata bits control the tristate modes of the qdsx. while the hizio bit is a logic one, all output pins of the qdsx except the data bus and output tdo are held tristate. the microprocessor interface is still active. while the hizdata bit is a logic one, the data bus is also held in a high- impedance state which inhibits microprocessor read cycles. the hizdata bit is overridden by the dbctrl bit.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 67 register 007h: revision/chip id/global monitoring update bit type function default bit 7 r/w reset 0 bit 6 r tip x bit 5 r type 0 bit 4 r id[4] 0 bit 3 r id[3] 0 bit 2 r id[2] 0 bit 1 r id[1] 0 bit 0 r id[0] 0 reset: the reset bit allows software to asynchronously reset the qdsx. the software reset is equivalent to setting the rstb input pin low. when a logic 1 is written to reset, the qdsx is reset. when a logic 0 is written to reset, the reset is removed. the reset bit must be explicitly set and cleared by writing the corresponding logic value to this register. tip: the tip bit is set to a logic one when any value with bit 7 set to logic 0 is written to this register. such a write initiates an accumulation interval transfer and loads all the performance meter registers in the lcv_pmon and prsm blocks. tip remains high while the transfer is in progress, and is set to a logic zero when the transfer is complete. tip can be polled by a microprocessor to determine when the accumulation interval transfer is complete. type: the chip identification type bit is set at a logic 0. id[4:0]: the id[4:0] bits allows software to identify the version level of the device.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 68 register 008h: interrupt quadrant id bit type function default bit 7 r int[4] 0 bit 6 r int[3] 0 bit 5 r int[2] 0 bit 4 r int[1] 0 bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x this register provides interrupt identification to show which quadrant of the qdsx asserted the intb output. int[4], int[3], int[2], int[1]: the int[x] bit will be high if the xth qdsx interface causes the intb pin to transition low.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 69 register 009h: tops master clock configuration/clock activity monitor bit type function default bit 7 r tclkia[4] x bit 6 r tclkia[3] x bit 5 r tclkia[2] x bit 4 r tclkia[1] x bit 3 r xclka x bit 2 r clko8xa x bit 1 r/w xsel[1] 0 bit 0 r/w xsel[0] 0 this register provides activity monitoring on qdsx clock inputs and configures the qdsx for the appropriate xclk input. figure 12 illustrates the different timing configurations. tclkia[4],tclkia[3],tclkia[2],tclkia[1]: the tclkia[4:1] bits monitors for low to high transitions on the tclki[4:1] inputs respectively. tclkia[x] is set high on a rising edge of tclki[x], and is set low when this register is read. xclka: the xclka bit monitors for low to high transitions on the xclk input. xclka is set high on a rising edge of xclk, and is set low when this register is read. clko8xa: the clko8xa bit monitors for low to high transitions on the clko8x output. clko8xa is set high on a rising edge of clko8x, and is set low when this register is read. xsel[1:0]: the xsel[1:0] bits configures the qdsx for the desired xclk input and for the clko8x/clk01x output according to the following table:
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 70 xsel[1] xsel[0] xclk requirements clko8x/clk01x output 0 0 24x input clock djat smoothed 8x output clock 0 1 24x input clock xclk 3 1 0 8x input clock xclk 8 (clko1x) 1 1 reserved reserved
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 71 register 00ah, 04ah, 08ah, and 0cah: tops clock timing options bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w fifobyp 0 bit 1 r/w pllref[1] 0 bit 0 r/w pllref[0] 0 this register is used to configure the timing options for the corresponding qdsx quadrant. figure 12 illustrates the different timing configurations. fifobyp: the fifobyp bit enables the transmit input signals to djat to be bypassed around the fifo to the outputs. when fifobyp is set to logic 1, the inputs to djat are routed around the fifo to the outputs. when fifobyp is set to logic 0, the transmit data passes through the djat fifo. when the djattx bit (registers 002h, 042h, 082h, and 0c2h) is set to logic 0, the fifo is automatically bypassed on the transmit path. whenever the fifo is not active in the transmit path, the system 8x clock (presented on clk08x) must be synchronous to tclki[x], and line loopback cannot be used. refer to the operations section for more details on using the qdsx without the djat enabled in the transmit path. pllref[1:0]: the pllref[1:0] bits select the source of the digital jitter attenuator phase locked loop reference signal as follows: pllref[1] pllref[0] transmit reference source 0 0 tclki[x] input. 0 1 clock recovered from the rxtip[x] and rxring[x] inputs.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 72 pllref[1] pllref[0] transmit reference source 1 0 xclk input divided by 24. xsel[1] must be set to 0 if this option is selected. (register 009h) 1 1 reserved. not to be used. figure 17 - timing options 10 djat fifo fifo input data clock 1 0 djat pll 01 rclko[x] pllref[1:0] 00 tclki[x] 8 0x 10 xsel[1:0] (24x, 8x) xclk 1x "jitter attenuated" clock 8x "high-speed" clock xpls data clock 3 *setting linelb automatically selects pllref[1:0] = 01b. 24x reference clock for jitter attenuation xpls cdrc smooth 8x clock clko8x 0 1 xpls reference 8x clock 1 0 djattx "and" not(linelb) 0 djattx "or" xsel[1] 1 1 0 djattx txtip[x], txring[x] fifobp "or" xsel[1] 0 1 1 xsel[1] 1 1 0 xsel[0] "or" xsel[1] clko1x fifobp note: the clko8x and clko1x outputs are generated from the first quadrant of the device.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 73 register 00bh, 04bh, 08bh, and 0cbh: lcode transmit line code configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r/w ami 0 ami: the ami bit enables ami line coding. if ami is set to a logic 1, the qdsx will perform ami line encoding on the tdd[x] single-rail input data stream. if ami is set to a logic 0, the qdsx will perform b8zs (if the cept bit in register 001h, 041h, 081h, and 0c1h is set to logic 0) or hdb3 (if the cept bit is set to logic 1) line encoding on the tdd[x] single-rail input data stream. the ami bit has no function if the tdual bit in the transmit configuration register (001h, 041h, 081h, and 0c1h) or if the tdual input pin is set to logic 1.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 74 register 010h, 050h, 090h, and 0d0h: cdrc configuration bit type function default bit 7 r/w ami 0 bit 6 r/w los[1] 0 bit 5 r/w los[0] 0 bit 4 r/w dcr 0 bit 3 r/w reserved 0 bit 2 r/w algsel 0 bit 1 r/w o162 0 bit 0 r/w reserved 0 reserved: the reserved bits must be programmed with a logic 0 ami: the alternate mark inversion (ami) bit selects the line code of the incoming e1 or ds1 signal. a logic 1 selects ami line code; a logic 0 selects hdb3 (e1 format) or b8zs (dsx-1 format). los[1:0]: the los[1:0] bits select the loss of signal declaration threshold. for example, if the threshold is set to 10, the 11th consecutive zero causes the declaration of los. los is removed when a single non-zero pulse is detected in the receive stream. the los declaration thresholds are shown in the table below: los[1] los[0] threshold (bit periods) 0 0 10 (e1 format selected) 15 (dsx-1 format or ami line code selected) 0131 1063 1 1 175
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 75 dcr: the disable clock recovery (dcr) bit is logically "ored" with the dcr input pin. dcr enables the sliced positive and negative pulses from the analog receive slicer to be visible on the sdp[x] and sdn[x] outputs. when dcr is set to logic 1, the sdp[x] and sdn[x] outputs are enabled. when dcr is set to logic 0, either the rdp[x] and rdn[x] or the rdd[x] and rlcv[x] outputs are enabled depending on the setting of the rdual bit in the receive configuration register (000h, 040h, 080h, and 0c0h). note that the dcr bit takes precedence over the rdual bit. algsel: the algorithm select (algsel) bit specifies the algorithm used by the dpll for clock and data recovery. the choice of algorithm determines the high frequency input jitter tolerance of the cdrc. when algsel is set to logic 1, the cdrc jitter tolerance is increased to approach 0.5uipp for jitter frequencies above 20khz. when algsel is set to logic 0, the jitter tolerance is increased for frequencies below 20khz (i.e. the tolerance is improved by 20% over that of algsel=1 at these frequencies), but the tolerance approaches 0.4uipp at the higher frequencies. o162: when the e1 format is selected and the ami bit is logic 0, the recommendation o.162 compatibility select bit (o162) allows selection between two line code definitions: 1. if o162 is a logic 0, a line code violation is indicated if the serial stream does not match the verbatim hdb3 definition given in recommendation g.703. a bipolar violation that is not part of an hdb3 signature or a bipolar violation in an hdb3 signature that is the same polarity as the last bipolar violation results in a line code violation indication. 2. if o162 is a logic 1, a line code violation is indicated by a lcv output pulse if a bipolar violation is of the same polarity as the last bipolar violation, as per recommendation o.162.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 76 registers 011h, 051h, 091h and 0d1h: cdrc interrupt enable bit type function default bit 7 r/w lcve 0 bit 6 r/w lose 0 bit 5 r/w lcsde 0 bit 4 r/w exze 0 bit 3 unused x bit 2 unused x bit 1 unused x bit 0 unused x the bit positions lcve, lose, lcsde and exze of this register are interrupt enables to select which of the status events (line code violation , loss of signal, b8zs/hdb3 signature detection, or excessive zeros detection), either individually or in combination, are enabled to generate an interrupt on the intb pin when they are detected. a logic 1 bit in the corresponding bit position enables the detection of these signals to generate an interrupt; a logic 0 bit in the corresponding bit position disables that signal from generating an interrupt.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 77 registers 012h, 052h, 092h and 0d2h: cdrc interrupt status bit type function default bit 7 r lcvi x bit 6 r losi x bit 5 r lcsdi x bit 4 r exzi x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r los x the bit positions lcvi, losi, lcsdi and exzi of this register indicate which of the status events generated an interrupt. a logic 1 in these bit positions indicate that the corresponding event was detected; a logic 0 in these bit positions indicate that no corresponding event has been detected. the bit positions lcvi, lcsdi and exzi are set on the assertion of a line code violation, a line code signature detection, and excessive zeros detection, respectively. losi is set on a change of state of the los alarm. bits lcvi, losi, lcsdi and exzi are cleared by reading this register. the current state of the los alarm can be determined by reading bit 0 of this register. note: in the cdrc, excess zeros is defined as a string greater than: 3 consecutive zeros for e1 data, or 7 consecutive zeros for t1 data.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 78 register 014h, 054h, 094h, and 0d4h: lcv_pmon interrupt enable/status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w inte 0 bit 1 r int x bit 0 r ovr x inte: the inte bit controls the generation of a microprocessor interrupt when the transfer clock has caused the counter values to be stored in the holding registers. a logic 1 bit in the inte position enables the generation of an interrupt. a logic 0 bit in the inte position disables the generation of an interrupt. int: the int bit is the current status of the interrupt signal. a logic 1 in this bit position indicates that a transfer has occurred. a logic 0 indicates that no transfer has occurred. the interrupt is cleared (acknowledged) by reading this register. ovr: the ovr bit is the overrun status of the holding registers. a logic 1 in this bit position indicates that a previous interrupt has not been acknowledged before the next transfer clock has been issued and that the contents of the holding registers have been overwritten. a logic 0 indicates that no overrun has occurred. the ovr bit is cleared by reading this register.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 79 registers 01ah-01bh, 05ah-05bh, 09ah-09bh, 0dah-0dbh: latching lcv performance data the lcv performance data registers for one of the four interfaces on the qdsx are updated as a group by writing to any of the lcv_pmon count registers (addresses 01ah-01bh, 05ah-05bh, 09ah-09bh, 0dah-0dbh). a write to any of these locations loads performance data located in the lcv_pmon block of that quadrant into the internal holding registers. the data contained in the holding registers can then be subsequently read by microprocessor accesses of the lcv_pmon lcv count registers. the latching of count data, and subsequent resetting of the counters, is synchronized to the internal event timing so that no events are missed. note: it is necessary to write to one, and only one, count register address to latch all the count data register values into the holding registers and to reset all the counters of the particular quadrant for each polling cycle. alternately, one may write to the global monitoring update register (009h) to transfer the contents of all four lcv_pmon counters and the prsm counters. the transfer in progress (tip) bit in register 007h is polled to determine when the transfer is complete.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 80 registers 01ah, 05ah, 09ah and 0dah: lcv_pmon line code violation count lsb bit type function default bit 7 r lcv[7] x bit 6 r lcv[6] x bit 5 r lcv[5] x bit 4 r lcv[4] x bit 3 r lcv[3] x bit 2 r lcv[2] x bit 1 r lcv[1] x bit 0 r lcv[0] x
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 81 registers 01bh, 05bh, 09bh and 0dbh: lcv_pmon line code violation count msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r lcv[12] x bit 3 r lcv[11] x bit 2 r lcv[10] x bit 1 r lcv[9] x bit 0 r lcv[8] x these registers indicate the number of lcv error events that occurred during the previous accumulation interval. an lcv event is defined as the occurrence of a bipolar violation or excessive zeros. the counting of excessive zeros (a string of greater than: 3 consecutive zeros for e1 data, 7 consecutive zeros for b8zs, or 15 consecutive zeros for t1 ami) can be disabled by the bpvcnt bit of the receive configuration register (000h, 040h, 080h, and 0c0h).
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 82 registers 01ch, 05ch, 09ch and 0dch: djat interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r ovri x bit 0 r undi x these registers contain the indication of the djat fifo status. ovri: the ovri bit is asserted when an attempt is made to write data into the fifo when the fifo is already full. when undi is a logic 1, an overrun event has occurred. undi: the undi bit is asserted when an attempt is made to read data from the fifo when the fifo is already empty. when undi is a logic 1, an underrun event has occurred.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 83 register 01dh, 05dh, 09dh and 0ddh: djat reference clock divisor (n1) control bit type function default bit 7 r/w n1[7] 0 bit 6 r/w n1[6] 0 bit 5 r/w n1[5] 1 bit 4 r/w n1[4] 0 bit 3 r/w n1[3] 1 bit 2 r/w n1[2] 1 bit 1 r/w n1[1] 1 bit 0 r/w n1[0] 1 these registers define an 8-bit binary number, n1, which is one less than the magnitude of the divisor used to scale down the djat pll reference clock input. the ref divisor magnitude, (n1+1), is the ratio between the frequency of ref input and the frequency applied to the phase discriminator input. writing to this register will reset the pll and, if the sync bit in the djat configuration register is high, will also reset the fifo.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 84 registers 01eh, 05eh, 09eh and 0deh: djat output clock divisor (n2) control bit type function default bit 7 r/w n2[7] 0 bit 6 r/w n2[6] 0 bit 5 r/w n2[5] 1 bit 4 r/w n2[4] 0 bit 3 r/w n2[3] 1 bit 2 r/w n2[2] 1 bit 1 r/w n2[1] 1 bit 0 r/w n2[0] 1 these registers define an 8-bit binary number, n2, which is one less than the magnitude of the divisor used to scale down the djat smooth output clock signal. the output clock divisor magnitude, (n2+1), is the ratio between the frequency of the smooth output clock and the frequency applied to the phase discriminator input. writing to this register will reset the pll and, if the sync bit is high, will also reset the fifo.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 85 registers 01fh, 05fh, 09fh and 0dfh: djat configuration bit type function default bit 7 unused x bit 6 unused x bit 5 r/w widen 1 bit 4 r/w cent 0 bit 3 r/w unde 0 bit 2 r/w ovre 0 bit 1 r/w sync 1 bit 0 r/w limit 1 these registers control the operation of the djat fifo read and write pointers and controls the generation of interrupt by the fifo status. widen: the widen bit controls the width of the generated pulse from the xpls block. when widen is set to logic 1, the high phase of one cycle of the 8x clock generated by the djat pll is modified to be nominally one 24x clock period wider. this results in the xpls producing a greater pulse width. when widen is set to logic 0, the smooth 8x clock from djat is not modified, resulting in pulses of minimum allowable width (approx. 50% duty cycle). these narrow pulses reduce the amount of energy sourced by the qdsx into the line. the widen bit has no effect when the djat pll is not used. cent: the cent bit allows the fifo to self-center its read pointer, maintaining the pointer at least 4 ui away from the fifo being empty or full. when cent is set to logic 1, the fifo is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. if an empty or full alarm occurs during this 384 ui period, then the period will be extended by the number of ui that the empty or full alarm persists. during the empty or full alarm conditions, data is lost. when cent is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during empty or full alarm conditions. cent can only be set to logic 1 if sync is set to logic 0.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 86 ovre,unde: the ovre and unde bits control the generation of an interrupt on the microprocessor intb pin when a fifo error event occurs. when ovre or unde is set to logic 1, an overrun event or underrun event, respectively, is allowed to generate an interrupt on the intb pin. when ovre or unde is set to logic 0, the fifo error events are disabled from generating an interrupt. sync: the sync bit enables the pll to synchronize the phase delay between the fifo input and output data to the phase delay between reference clock input and smooth output clock at the pll. for example, if the pll is operating so that the smooth output clock lags the reference clock by 24 ui, then the synchronization pulses that the pll sends to the fifo will force its output data to lag its input data by 24 ui. limit: the limit bit enables the pll to limit the jitter attenuation by enabling the fifo to increase or decrease the frequency of the smooth output clock whenever the fifo is within one unit interval (ui) of overflowing or underflowing. this limiting of jitter ensures that no data is lost during high phase shift conditions. when limit is set to logic 1, the pll jitter attenuation is limited. when limit is set to logic 0, the pll is allowed to operate normally.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 87 registers 020h, 060h, 0a0h and 0e0h: ibcd configuration bit type function default bit 7 r/w reserved 0 bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w dsel1 0 bit 2 r/w dsel0 0 bit 1 r/w asel1 0 bit 0 r/w asel0 0 these registers provide the selection of the activate and de-activate t1 loopback code lengths (from 3 bits to 8 bits) as follows: ta bl e 4 - deactivate code activate code dsel1 dsel0 asel1 asel0 code length 00005 bits 01016 (or 3*) bits 10107 bits 11118 (or 4*) bits *note: 3 and 4 bit code sequences can be accommodated by configuring the ibcd for 6 or 8 bits and by programming two repetitions of the code sequence. reserved: the reserved bit must be programmed to logic 0 for correct operation.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 88 registers 021h, 061h, 0a1h and 0e1h: ibcd interrupt enable/status bit type function default bit 7 r lbacp x bit 6 r lbdcp x bit 5 r/w lbae 0 bit 4 r/w lbde 0 bit 3 r lbai x bit 2 r lbdi x bit 1 r lba x bit 0 r lbd x lbacp,lbdcp: the lbacp and lbdcp bits indicate when the corresponding loopback code is present during a 39.8 ms interval (dsx-1 applications). lbae: the lbae bit enables the assertion or deassertion of the inband loopback activate (lba) detect indication to generate an interrupt on the intb pin. when lbae is set to logic 1, any change in the state of the lba detect indication generates an interrupt. when lbae is set to logic 0, no interrupt is generated by changes in the lba detect state. lbde: the lbde bit enables the assertion or deassertion of the inband loopback deactivate (lbd) detect indication to generate an interrupt on the intb pin. when lbde is set to logic 1, any change in the state of the lbd detect indication generates an interrupt. when lbde is set to logic 0, no interrupt is generated by changes in the lbd detect state. lbai,lbdi: the lbai and lbdi bits indicate which of the two expected loopback codes has changed state. a logic 1 in these bit positions indicate that a state change in that code has occurred; a logic 0 in these bit positions indicate that no state change has occurred.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 89 lba,lbd: the lba and lbd bits indicate the current state of the corresponding loopback code detect indication. a logic 1 in these bit positions indicate the presence of that code has been detected; a logic 0 in these bit positions indicate the absence of that code.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 90 registers 022h, 062h, 0a2h and 0e2h: ibcd activate code bit type function default bit 7 r/w act7 0 bit 6 r/w act6 0 bit 5 r/w act5 0 bit 4 r/w act4 0 bit 3 r/w act3 0 bit 2 r/w act2 0 bit 1 r/w act1 0 bit 0 r/w act0 0 this 8 bit register selects the activate code sequence that is to be detected. if the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8 bit register. for example, if code sequence is a repeating 00001, then the first 8 bits of two repetitions (0000100001) is programmed into the register (i.e. 00001000). note that bit act7 corresponds to the first code bit received.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 91 registers 023h, 063h, 0a3h and 0e3h: ibcd deactivate code bit type function default bit 7 r/w dact7 0 bit 6 r/w dact6 0 bit 5 r/w dact5 0 bit 4 r/w dact4 0 bit 3 r/w dact3 0 bit 2 r/w dact2 0 bit 1 r/w dact1 0 bit 0 r/w dact0 0 this 8 bit register selects the deactivate code sequence that is to be detected. if the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8 bit register. for example, if code sequence is a repeating 001, then the first 8 bits of three repetitions (001001001) is programmed into the register (i.e. 00100100). note that bit dact7 corresponds to the first code bit received.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 92 registers 024h, 064h, 0a4h and 0e4h: xibc control bit type function default bit 7 r/w en 0 bit 6 r/w reserved 0 bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w cl1 0 bit 0 r/w cl0 0 these registers control the transmission of t1 inband loopback activate and deactivate codes. en: the en bit controls whether the inband code is transmitted or not. a logic 1 in the en bit position enables transmission of inband codes; a logic 0 in the en bit position disables inband code transmission. reserved: this bit is reserved and should be set to logic 0 for proper operation. cl1, cl0: the bit positions cl[1:0] (bits 1 & 0) of this register indicate the length of the inband loopback code sequence, as follows: cl1 cl0 code length 005 016 107 118
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 93 codes of 3 or 4 bits in length may be accommodated by treating them as half of a double-sized code (i.e. a 3-bit code would use the 6-bit code length setting).
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 94 registers 025h, 065h, 0a5h and 0e5h: xibc loopback code bit type function default bit 7 r/w ibc7 x bit 6 r/w ibc6 x bit 5 r/w ibc5 x bit 4 r/w ibc4 x bit 3 r/w ibc3 x bit 2 r/w ibc2 x bit 1 r/w ibc1 x bit 0 r/w ibc0 x these registers contain the inband loopback code pattern to be transmitted. the code is transmitted most significant bit ( ibc7) first, followed by ibc6 and so on. the code, regardless of the length, must be aligned with the msb always in the ibc7 position (a 5-bit code would occupy the ibc7 through ibc2 bit positions). to transmit a 3-bit or a 4-bit code pattern, the pattern must be paired to form a double-sized code (the 3-bit code '011' would be written as the 6-bit code '011011').
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 95 register 027h, 067h, 0a7h, 0e7h: prsg configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w prbsinv 0 bit 1 r/w prbserr 0 bit 0 r/w prbsgen 0 this register enables the prsg pseudo-random bit sequence generation. prbsinv: when the prbsinv bit is set, the prsg block inverts the 2 15 -1 prbs data before transmission. an inverted 2 15 -1 prbs will contain at most 15 consecutive zeroes, while a non-inverted 2 15 -1 prbs will contain at most 14 consecutive zeroes. some testers may only support the inverted sequence. prbsgen: the prbsgen bit enables the prsg block to insert the 2 15 -1 prbs data stream into the transmit data stream. when prbsgen is set to logic 1, the prsg block will overwrite the data stream with the prbs data stream. when prbsgen is set to logic 0, the prbs generation is disabled. prbserr: when the prbserr bit is written with a logic 1, a single error is inserted in the pseudo-random bit stream by inverting a single bit. to insert another bit error, the prbserr bit must be written with a logic 0, and then re-written with another logic 1. at least one bit period should elapse between writing prbserr 0 and writing it 1 again, or vice versa, if an error is to be successfully inserted. prbserr has no effect when prbsgen is set to 0.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 96 register 029h, 069h, 0a9h, 0e9h: prsm control/status bit type function default bit 7 r/w prbsinv 0 bit 6 r/w reserved 0 bit 5 r/w oose 0 bit 4 r oosi x bit 3 r oos x bit 2 r/w inte 0 bit 1 r int x bit 0 r ovr x this register shows the prbs monitor synchronization state and enables an interrupt to be generated whenever synchronization is lost or regained. this register also enables an interrupt to be generated whenever the prbs error counter data is transferred into the prsm holding registers. the configuration register also contains status information as to whether these holding registers have been overrun. prbsinv: when the prbsinv bit is set, the prsm inverts the incoming data. this will allow it to synchronize to an inverted pseudorandom bit sequence. in the default setting, the prsm synchronizes to a non-inverted sequence. an inverted 2 15 -1 prbs will contain at most 15 consecutive zeroes, while a non- inverted 2 15 -1 prbs will contain at most 14 consecutive zeroes. some testers may only support the inverted sequence. reserved: the reserved bit must be programmed to logic 0 for proper operation. oose: the oose bit controls the generation of a microprocessor interrupt when a change of prbs synchronization state occurs a logic 1 bit in the oose position enables the generation of an interrupt; a logic 0 bit in the oose position disables the generation of an interrupt. the interrupt is cleared by reading this register.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 97 oosi: the oosi bit shows the current status of the interrupt signal. a logic 1 in this bit position indicates that a change in prbs synchronization state has occurred. a logic 0 indicates that no change in prbs synchronization state has occurred. the oosi bit is cleared following a read of this register. oos: the oos bit indicates the current prbs synchronization status of the prsm block. a logic 1 in this bit position indicates that the prsm block is out of sync. when out of sync, bit error events are not accumulated. a logic 0 indicates that the prsm block is synchronized and accumulating bit error events. inte: the inte bit controls the generation of a microprocessor interrupt when the transfer clock has caused the counter values to be stored in the holding registers. a logic 1 bit in the inte position enables the generation of an interrupt; a logic 0 bit in the inte position disables the generation of an interrupt. the interrupt is cleared (acknowledged) by reading this register. int: the int bit is the current status of the interrupt signal. a logic 1 in this bit position indicates that a transfer has occurred. a logic 0 indicates that no transfer has occurred. the int bit is cleared following a read of this register. ovr: the ovr bit holds the overrun status of the holding registers. a logic 1 in this bit position indicates that a previous interrupt has not been acknowledged before the next transfer clock has been issued and that the contents of the holding registers have been overwritten. a logic 0 indicates that no overrun has occurred. the ovr bit is cleared by reading this register. latching performance data the pseudo-random sequence monitor (prsm) holding registers (02ah-02bh, 06ah-06bh, 0aah-0abh, and 0eah-0ebh) are updated by a microprocessor write to either of the particular prsm's holding registers. the prsm block is loaded with new performance data within 4 clock periods (rclko[x] if in the receive path, tclki[x] if in the transmit path) after the write. thus, the prsm holding registers should not be read until after 2 s (e1 case) or 2.6 s (dsx-1 case) has elapsed since the write was completed. alternatively, the prsm control/status register may be polled until the int bit goes to logic 1, indicating
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 98 that the transfer is complete and the data is ready to be read. the data contained in the holding registers can subsequently be read by the microprocessor. the loading is synchronized to the internal event timing so that no events are missed. alternately, one may write to the global monitoring update register (009h) to transfer the contents of the prsm counters as well as the lcv_pmon registers of all four quadrants. the transfer in progress (tip) bit in register 007h is polled to determine when the transfer is complete.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 99 register 02ah, 06ah, 0aah, 0eah: prsm bit error event count lsb bit type function default bit 7 r ber[7] x bit 6 r ber[6] x bit 5 r ber[5] x bit 4 r ber[4] x bit 3 r ber[3] x bit 2 r ber[2] x bit 1 r ber[1] x bit 0 r ber[0] x
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 100 register 02bh, 06bh, 0abh, 0ebh: prsm bit error event count msb bit type function default bit 7 r ber[15] x bit 6 r ber[14] x bit 5 r ber[13] x bit 4 r ber[12] x bit 3 r ber[11] x bit 2 r ber[10] x bit 1 r ber[9] x bit 0 r ber[8] x these holding registers indicate the number of bit error events that occurred during the previous accumulation interval. the contents of these registers are valid 2 s after a transfer is triggered by a write to any one of the pmons holding register addresses, or to register 007h.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 101 register 02ch, 06ch, 0ach, 0ech: xpls line length configuration bit type function default bit 7 r/w rpt 0 bit 6 r/w reserved 0 bit 5 r reserved x bit 4 r reserved x bit 3 r reserved x bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 this register allows software to select the length of cable that xpls is required to drive and to enable generation of user-programmable output templates. rpt: the rpt bit enables the 4-bit dac codes contained in the programmable template code registers to generate the output waveform. when rpt is set to a logic 1, the internal user-programmable xpls code registers supply the dac codes used to generate the waveform. rpt must be set to logic 1 and the desired template codes programmed for correct output pulse generation. the operations section contains the required details for programming the templates. sm: reserved the reserved bits must be programmed to logic 0 for correct operation. ils[2:0]:
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 102 register 02dh, 06dh, 0adh, 0edh: xpls control/status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w tais 0 bit 2 r dpmv x bit 1 r dpmi x bit 0 r/w dpme 0 ta i s : the tais bit enables the xpls to generate an unframed all-ones ais alarm on the txtip[x] and txring[x] output pins. when tais is set to logic 1, the outputs are forced to pulse alternately, creating an all-ones signal. when tais is set to logic 0, the outputs operate normally. the transition to transmitting ais is done in such a way as to not introduce any bipolar violations. dpmv: the dpmv bit reflects the current state of the dpm alarm signal. dpmi: the dpmi bit is set to logic 1 when any change of state occurs on the driver performance monitor (dpm) alarm signal. this bit is cleared when the register is read.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 103 dpme: the dpme bit controls the generation of an interrupt on the microprocessor intb pin by the driver performance monitor portion of xpls. when dpme is set to logic 1, an interrupt is generated on intb whenever an alarm condition occurs on the driver performance monitor points. a driver performance monitor alarm is declared whenever a period of 62 or 63 consecutive bit periods with no pulses on either the txtip[x] or txring[x] output pins occurs. the exact threshold (62 or 63 bit periods) depends on the line build- out and the pattern of bipolar violations. when dpme is set to logic 0, detection of a driver performance monitor alarm condition is disabled from generating an interrupt.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 104 register 02eh, 06eh, 0aeh, 0eeh: xpls code indirect address bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w cra2 0 bit 1 r/w cra1 0 bit 0 r/w cra0 0 this register allows software to select any one of the eight internal waveform code registers, addressed by the cra[2:0] bits, for subsequent access through the code indirect data register. when accessing the internal code registers, the address of the desired register must first be written to this register. then, by reading or writing the indirect data register (registers 2fh, 06fh, 0afh, 0efh), the microprocessor can either read from or write to the internal register identified by the cra[2:0] bits. the cra[2:0] bits address the internal registers as follows: cra2 cra1 cra0 internal code register 0 0 0 code register #0 - first code applied 0 0 1 code register #1 0 1 0 code register #2 0 1 1 code register #3 1 0 0 code register #4 1 0 1 code register #5 1 1 0 code register #6 1 1 1 code register #7 - last code applied
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 105 see the operations section for more details on setting up custom waveform templates.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 106 register 02fh, 06fh, 0afh, 0efh: xpls code indirect data bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w crd3 0 bit 2 r/w crd2 0 bit 1 r/w crd1 0 bit 0 r/w crd0 0 this register allows software to access the contents of any one of the eight internal waveform code registers, addressed by the cra[2:0] bits in the code indirect address register. when accessing the internal code registers, the address of the desired register must first be written to the indirect address register (registers 2eh, 06eh, 0aeh, 0eeh). then, by reading or writing the indirect data register, the microprocessor can either read from or write to the internal register identified by the cra[2:0] bits. the value read from or written to the internal code registers is contained in the crd[3:0] bits. crd3 is the most significant bit. see the operations section for more details on setting up custom waveform templates.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 107 register 030h, 070h, 0b0h, 0f0h: rslc configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r/w ths 0 ths: the bit ths controls the selection of slicing threshold. the analog pulse slicer generates a logic one on either the sdp or sdn output if the amplitude (positive or negative) of the line voltage exceeds the adaptive slicing threshold. the ths bit selects between two fractions of the pulse amplitude for the slicing threshold. when ths is set to logic 0, the slicing threshold is 67% of the peak amplitude and is intended for dsx-1 applications. when ths is set to logic 1, the slicing threshold is 50% of the peak amplitude and is intended for g.703 2048 kbit/s applications. the ths bit is internally ored with the cept bit in the receive configuration register (registers 000h, 040h, 080h, 0c0h).
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 108 register 031h, 071h, 0b1h, 0f1h: rslc interrupt enable/status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r sq x bit 1 r sqi x bit 0 r/w sqe 0 sq: the sq bit reflects the current state of the squelch alarm. sqi: the sqi bit is set to logic 1 when a change in the state of the squelch alarm occurs. the bit is cleared to logic 0 when the register is read. sqe: the sqe bit enables the generation of an interrupt when the squelch alarm changes state. when sqe is set to logic 1, the squelch alarm event is enabled to generate an interrupt on the microprocessor intb pin. when the qdsx is reset, the sqe bit is set to logic 0, disabling a squelch event from generating an interrupt.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 109 11 test features description simultaneously asserting (low) the csb, rdb and wrb inputs causes all digital output pins and the data bus to be held in a high-impedance state. this test feature may be used for board testing. test mode registers are used to apply test vectors during production testing of the qdsx. test mode registers (as opposed to normal mode registers) are selected when a[8] is high. test mode registers may also be used for board testing. when all of the tsbs within the qdsx are placed in test mode 0, device digital inputs may be read and outputs may be forced via the microprocessor interface (refer to the section "test mode 0" for details). in addition, the qdsx also supports a standard ieee 1149.1 five-signal jtag boundary scan test port for use in board testing. all digital device inputs may be read and all digital device outputs may be forced via the jtag test port. table 5 - test mode register memory map address register 000h-0ffh normal mode registers 006h or 106h master test register 100h-10fh qdsx test reserved 110h, 150h, 190h, 1d0h cdrc test register 0 111h, 151h, 191h, 1d1h cdrc test register 1 112h, 152h, 192h, 1d2h cdrc test register 2 113h, 153h, 193h, 1d3h qdsx test reserved 114h, 154h, 194h, 1d4h lcv_pmon test register 0 115h, 155h, 195h, 1d5h lcv_pmon test register 1 116h-11bh, 156h-15bh, 196h-19bh, 1d6h-1dbh lcv_pmon test reserved 11ch, 15ch, 19ch, 1dch djat test register 0 11dh, 15dh, 19dh, 1ddh djat test register 1
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 110 address register 11eh, 15eh, 19eh, 1deh djat test register 2 11fh, 15fh, 19fh, 1dfh djat test reserved 120h, 160h, 1a0h, 1e0h ibcd test register 0 121h, 161h, 1a1h, 1e1h ibcd test register 1 122h-123h, 162h-163h, 1a2h-1a3h, 1e2h-1e3h ibcd test reserved 124h, 164h, 1a4h, 1e4h xibc test register 0 125h, 165h, 1a5h, 1e5h xibc test register 1 126h-12bh, 166h-16bh, 1a6h-1abh, 1e6h-1ebh qdsx test reserved 12ch, 16ch, 1ach, 1ech xpls test register 0 12dh, 16dh, 1adh, 1edh xpls test register 1 12eh, 16eh, 1aeh, 1eeh xpls test register 2 12fh, 16fh, 1afh, 1efh xpls test register 3 130h, 170h, 1b0h, 1f0h rslc test register 0 131h, 171h, 1b1h, 1f1h rslc test register 1 notes on test mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. writeable test mode register bits are not initialized upon reset unless otherwise noted. 11.1 test mode 0 details in test mode 0, the qdsx allows the logic levels on the digital device inputs to be read through the microprocessor interface and allows the digital device outputs to be forced to either logic level through the microprocessor interface. the iotst bit in the master test register must be set to logic one to access the device i/o. to enable test mode 0, the iotst bit in the master test register is set to logic one, all normal mode registers should be set to their default state, and the
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 111 following addresses must be written with 00h: 111h, 115h, 11dh, 121h, 125h, 129h, 12dh, 131h, 151h, 155h, 15dh, 161h, 165h, 169h, 16dh, 171h, 191h, 195h, 19dh, 1a1h, 1a5h, 1a9h, 1adh, 1b1h, 1d1h, 1d5h, 1ddh, 1e1h, 1e5h, 1e9h, 1edh, and 1f1h. reading the following address locations returns the values on the indicated inputs: ta bl e 6 - addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 110h dcr 11ch tclki[1] xclk tdn[1] tdp[1] 120h rdual 124h tdual 15ch tclki[2] xclk tdn[2] tdp[2] 19ch tclki[3] xclk tdn[3] tdp[3] 1dch tclki[4] xclk tdn[4] tdp[4] writing the following address locations forces the outputs to the value in the corresponding bit position (zeros should be written to all unused test register locations): ta bl e 7 - addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 110h int 1 rclko[1] 114h int 1 11ch int 1 clko8x 120h int 1 12ch int 1 130h rdp[1] rdn[1] int 1 150h int 1 rclko[2] 154h int 1 15ch int 1 160h int 1 16ch int 1 170h rdp[2] rdn[2] int 1
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 112 addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 190h int 1 rclko[3] 194h int 1 19ch int 1 1a0h int 1 1ach int 1 1b0h rdp[3] rdn[3] int 1 1d0h int 1 rclko[4] 1d4h int 1 1dch int 1 1e0h int 1 1ech int 1 1f0h rdp[4] rdn[4] int 1 notes: 1. writing a logic 1 to any of the block interrupt signals asserts the intb output low. to deassert intb, all the int register bits should be set to logic 0. 11.2 jtag test port the qdsx jtag test access port (tap) allows access to the tap controller and the 4 tap registers: instruction, bypass, device identification and boundary scan. using the tap, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. for more details on the jtag port, please refer to the operations section. table 8 - instruction register length - 3 bits instructions selected register instruction codes, ir[2:0] extest boundary scan 000 idcode identification 001 sample boundary scan 010
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 113 instructions selected register instruction codes, ir[2:0] bypass bypass 011 bypass bypass 100 stctest boundary scan 101 bypass bypass 110 bypass bypass 111 identification register length - 32 bits version number - 0h part number - 4314h manufacturer's identification code - 0cdh device identification - 043140cdh table 9 - boundary scan register (length - 64 bits) pin/enable boundary scan register bit pin/enable boundary scan register bit rstb 4 63 rdp[3] 27 ale 62 rclko[2] 26 csb 61 rdn[2] 25 wrb 60 rdp[2] 24 rdb 59 rclko[1] 23 a[0:8] 58 - 50 rdn[1] 22 vddi[3] 49 rdp[1] 21 dcr 48 rdual 20 tdual 47 intb 19 tdn[4] 46 intb_oen 1 18 tdp[4] 45 d[0] 17
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 114 pin/enable boundary scan register bit pin/enable boundary scan register bit tclki[4] 44 d0_oen 1 16 tdn[3] 43 d[1] 15 tdp[3] 42 d1_oen 1 14 tclki[3] 41 d[2] 13 tdn[2] 40 d2_oen 1 12 tdp[2] 39 d[3] 11 tclki[2] 38 d3_oen 1 10 tdn[1] 37 d[4] 9 tdp[1] 36 d4_oen 1 8 tclki[1] 35 d[5] 7 xclk 34 d5_oen 1 6 clko8x 33 d[6] 5 rclko[4] 32 d6_oen 1 4 rdn[4] 31 d[7] 3 rdp[4] 30 d7_oen 1 2 rclko[3] 29 hiz[2] 2 1 rdn[3] 28 hiz[4] 3 0 note: 1. all oen signals will set the corresponding bidirectional signal to an output when set low. 2. when set high, rdp[4:1], rdn[4:1], and rclko[4:1] will be set to high impedance. 3. when set high, clko8x will be set to high impedance. 4. rstb is the first bit of the boundary scan chain.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 115 12 operations 12.1 programming the xpls waveform template the internal xpls code registers, at registers 02fh, 06fh, 0afh, 0efh, are used to create a custom waveform across the analog transmit outputs, txtip[x] and txring[x]. these eight code registers are accessed indirectly through register 2eh, 06eh, 0aeh, 0eeh and contain 4-bit binary values corresponding to one of 16 quantized levels for the amplitude of the output pulse during each of eight synchronous, "high-speed" clock periods within a data clock cycle. the full swing of the amplifier outputs txtip[x] and txring[x] ranges from 0 to 4.02 volts. the codes select the nominal voltage levels into 50 w as follows: table 10 - code typical output vo l t a g e code typical output vo l t a g e 0000 0.05 v 1000 2.16 v 0001 0.31 v 1001 2.43 v 0010 0.58 v 1010 2.70 v 0011 0.85 v 1011 2.97 v 0100 1.16 v 1100 3.23 v 0101 1.38 v 1101 3.49 v 0110 1.65 v 1110 3.76 v 0111 1.91 v 1111 4.02 v the contents of the code registers are used by xpls and internally applied to the output d/a converter in sequence, beginning with code reg. #0, on the first falling edge of the internal, synchronous high-speed clock once the data clock has gone low. the first four codes determine the shape of the bulk of the pulse, whereas the last four codes determine the shape of the tail end of the pulse. depending on the polarity of the input pulse (either on the positive pulse input or the negative pulse input to xpls), the bulk of the pulse is generated on either txtip[x] or txring[x], with the tail generated on txtip[x] or txring[x], respectively. the pulse is produced differentially across the transformer primary
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 116 so that, for example, while the first four codes are generating the pulse on txtip[x], txring[x] is grounded through the output amplifier. to generate the negative portion of the pulse, the last four codes generate the tail of the pulse on txtip[x] while txring[x] is grounded through the other output amplifier. the on-resistance of either txtip[x] or txring[x] output amplifier is nominally 2.5 w when acting as a ground for the transformer. the output impedance of the amplifier when driving the pulse is typically <0.5 w at half the bit rate. the recommended template waveforms codes are given below. the widen=1 and widen=0 function corresponds to the state of the widen bit in the djat configuration register (01fh, 05fh, 09fh, and 0dfh) if the 24x clock is input to xclk. note that if the transmit jitter attenuation function is not enabled (xsel[1] = 1, or fifobyp=1, or djattx=0), then the widen=0 configuration is enabled by default. table 11 - length setting (ft.) recommended code register values (widen=1) register # 0 1 2 3 4 5 6 7 0-110 a 9 9 9 3 2 1 0 110-220 c b a a 4 3 2 1 220-330 e c b b 5 4 2 1 330-440 e d b b 6 5 3 1 440-550 e b a a 7 4 2 1 550-660 f c b a 8 5 3 1 g.703 2048 kbit/s 75 w 8 8 8 8 0 0 0 0 g.703 2048 kbit/s 120 w 9 9 9 9 0 0 0 0
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 117 table 12 - length setting (ft.) recommended code register values (widen=1) register # 0 1 2 3 4 5 6 7 0-110 a 9 9 9 3 2 1 0 110-220 c a a a 3 2 1 0 220-440 d b a a 5 4 2 1 440-660 e b a 9 7 4 2 1 g.703 2048 kbit/s 75 w 8 8 8 8 0 0 0 0 g.703 2048 kbit/s 120 w 9 9 9 9 0 0 0 0 figure 18 shows the relationship between the data clock (tclko[x]), the internal synchronous, high-speed clock sclk timing, and the application of the code register contents for a positive pulse immediately followed by a negative pulse. the resultant waveform across txtip[x] and txring[x] is also shown.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 118 figure 18 - code register sequence during pulse generation positive pulse internal 8x clock (sclk) txtip txtip- txring negative pulse txring contents of xpls internal code reg # 0 tclko 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 the actual waveform produced at the transformer secondary depends upon the turns ratio of the transformer used, the series resistance on the primary side used to match the line, the output impedance of the amplifier, the on-resistance of the amplifier while providing the transformer ground, and the transformer winding resistance. to ensure that the amplifiers can drive the reflected load, it is recommended that a transformer have a turns ratio of no more than 1:2. it is also recommended that the codes presented here be used as a guideline and that the
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 119 actual code values be verified (and modified) on the bench with the device driving the actual transformer and termination expected in the application. figure 19 shows the d/a codes necessary for xpls to drive a dsx-1 pulse using a pulse engineering 1:1.36 5% turns ratio step-up transformer (pe # 64952, or pe 65774) and 0-110ft of 22 awg twisted pair cable. (these code values are the same as those contained in the internal xpls rom for the 0-110 ft. waveform template, i.e. sm=1, ils[2:0]=000.) figure 19 - code register sequence for 0-110 feet build-out txtip- txring 0 a 1 9 2 9 3 9 4 3 5 2 6 1 7 0 code reg# contents (hex) to program the xpls code registers for a custom waveform template, the following sequence should be used: 1. set the rpt bit in the xpls configuration register (02ch, 06ch, 0ach, 0ech) to logic 0. 2. write the code register address (0-7) in the xpls code indirect address register (register 02eh, 06eh, 0aeh, 0eeh). 3. write the desired code value to the xpls code indirect data register (register 02fh, 06fh, 0afh, 0efh). 4. repeat steps 2 and 3 until all the code registers are written. 5. enable xpls to generate the new waveform by setting rpt to logic 1. the contents of the xpls code registers can be reviewed at any time by using the following sequence: 1. write the code register address (0-7) in the xpls code indirect address register (register 02eh, 06eh, 0aeh, 0eeh).
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 120 2. read the xpls code indirect data register (register 02fh, 06fh, 0afh, 0efh). this returns the code contents of the desired code register. 12.2 using the digital jitter attenuator the key to using djat lies in selecting the appropriate divisors for the phase comparison between the selected reference clock and the generated "jitter-free" clock. default application upon reset, the qdsx default condition provides jitter attenuation with the "jitter- free" clock referenced to the transmit clock tclki[x]. the djat sync bit is also logic 1 by default. djat is configured to divide its input clock rate, tclki[x], and its output "jitter-free" clock rate, both by 48, which is the maximum length of the fifo. these divided down clock rates are then used by the phase comparator to update the djat dpll. the phase delay between tclki[x] and the "jitter-free" clock is synchronized to the physical data delay through the fifo. for example, if the phase delay between tclki[x] and the "jitter-free" clock is 12 ui (unit intervals), the fifo will be forced to lag its output data 12 bits from its input data. the default mode works well with tclki[x] at 1.544mhz for t1 operation format or at 2.048mhz for e1 operation format. data burst application in applications where tclki[x] works at a higher than nominal instantaneous rate (but with gapping to provide the same nominal rate over time), a few factors must be considered to adequately filter the resultant "jitter-free" clock into a smooth 1.544mhz or 2.048mhz clock. the magnitude of the phase shifts in the incoming bursty data are too large to be properly attenuated by the pll alone. however, the magnitudes, and the frequency components of these phase shifts are known, and are most often multiples of 8 khz. in this situation, the input clock to djat is a gapped bursty clock. the phase shifts of the input clock with respect to the generated "jitter-free" clock in this case are large, but when viewed over a longer period, such as a frame, there is little net phase shift. therefore, by choosing the divisors appropriately, the large phase shifts can be filtered out, leaving a stable reference for the dpll to lock onto. in this application, the n1 and n2 divisors should be changed to c0h (i.e. divisors of 193 for t1 applications) or ffh (i.e. divisors of 256 for e1
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 121 applications). consequently, the frequency of the clock inputs to the phase discriminator in the pll is 8 khz. the djat sync option must be disabled since the divisor magnitude of 193 or 256 is not an integer multiple of the fifo length 48. the djat phase lock loop has a single order low pass jitter transfer function. by default, the corner frequency is 8.8 hz. the corner may be moved by the appropriate selection of clock divisors: f c = () 1 2 n 1536 f t + p where f c = corner frequency f t= tclki[x] average frequency n2= value in the output clock divisor control register ensure the reference clock divisor control value (n1) is also modified to be equal to the output clock divisor control value(n2). the self-centering circuitry of the fifo should be enabled by setting the cent register bit. this sets up the fifo read pointer to be at least 4 ui away from the end of the fifo registers, and then disengages. should variations in the frequency of input clock or the output clock cause the read pointer to drift to within one unit interval of fifo overflow or underflow, the pointer will be incrementally pushed away by the limit control without any loss of data. with sync disabled, and cent and limit enabled, the maximum tolerable phase difference between the bursty input clock and the smooth "jitter-free" clock is 40ui. phase wander between the two clock signals is compensated for by the limit control. 12.3 using xpls without djat the xpls requires an 8x clock that is synchronous to its transmit clock, and which satisfies particular setup and hold requirements with respect to that transmit clock. when the djat pll is in the transmit stream, it provides the necessary clocks. should the djat be bypassed or in the receive stream, or should a 24x clock not be available to the pll, alternate arrangements must be made to supply xpls with its required clocks. the possible cases are: a)
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 122 fifobyp =1 or djattx =0 when xsel[1] = 0, b) fifobyp = 1 or djattx =0 when xsel[1:0] = 10, c) fifobyp=0 and djattx=1 but xsel[1] = 1, d) fifobyp = 1 or djattx =0 when xsel[1:0] = 11, and e) fifobyp = 0 and djattx =1 but xsel[1:0] = 11. 12.3.1 fifo not in tx path, xsel[1] = 0 when fifobyp =1 or djattx =0, but xsel[1] = 0, a 24x clock must be provided on xclk. an 8x clock will be internally generated, either by dividing xclk by 3 (if xsel[0] = 1) or synchronous to the pll reference. (xsel[0] = 0). all quadrants on the qdsx share a single 8x clock, which is presented on clko8x. tclki[4:1] must be synchronous to clko8x, and must satisfy the setup and hold conditions specified in the a.c. characteristics section. 12.3.2 fifo not in tx path, xsel[1] = 1, xsel[0] = 0. when fifobyp =1 or djattx =0, but xsel[1:0] = 10, a 8x clock must be provided on xclk. this 8x clock must be synchronous with tclki[4:1], and tclki[4:1] must satisfy the setup and hold relationships to xclk specified in the a.c. characteristics section. 12.3.3 fifo is in tx path, xsel[1] = 1, xsel[0] = 0. when fifobyp = 0 and djattx = 1, but xsel[1:0] = 10, then the djat fifo is used to buffer between tclki[4:1] and an xpls transmit clock generated by dividing down the system 8x clock. this arrangement guarantees the xpls will get the clocks it needs. in this case, the 8x clock (provided on xclk) need only be frequency locked to 8x the tclki[4:1] frequency. tclki[4:1] need not be phase locked to the 8x clock in this case. 12.3.4 fifo not in tx path, xsel[1] = 1, xsel[0] = 1. this setting is reserved. 12.3.5 fifo is in tx path, xsel[1] = 1, xsel[0] = 1. this setting is reserved.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 123 12.4 jtag support the qdsx supports the ieee boundary scan specification as described in the ieee 1149.1 standards. the test access port (tap) consists of the five standard pins, trstb, tck, tms, tdi and tdo used to control the tap controller and the boundary scan registers. the trstb input is the active-low reset signal used to reset the tap controller. tck is the test clock used to sample data on input, tdi and to output data on output, tdo. the tms input is used to direct the tap controller through its states. the basic boundary scan architecture is shown in figure 20. figure 20 - boundary scan architecture boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms tck test access port controller mux dff select tri-state enable
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 124 the boundary scan architecture consists of a tap controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. the tap controller interprets the tms input and generates control signals to load the instruction and data registers. the instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. the bypass register offers a single- bit delay from primary input tdi to primary output tdo. the device identification register contains the device identification code. the boundary scan register allows testing of board inter-connectivity. the boundary scan register consists of a shift register place in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output tdo. in addition, patterns can be shifted in on primary input tdi and forced onto all digital outputs. tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controlled using primary tms. the finite state machine is shown in figure 21.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 125 figure 21 - tap controller finite state machine test-logic-reset run-test-idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 all transitions dependent on input tms 0 0 0 0 0 1 test-logic-reset the test logic reset state is used to disable the tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input,
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 126 trstb. the state is entered synchronously regardless of the current tap controller state by forcing input, tms high for 5 tck clock cycles. while in this state, the instruction register is set to the idcode instruction. run-test-idle the run test/idle state is used to execute tests. capture-dr the capture data register state is used to load parallel data into the test data registers selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. loading occurs on the rising edge of tck. shift-dr the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-dr the update data register state is used to load a test register's parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. the parallel output latches are updated on the falling edge of tck. capture-ir the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck. shift-ir the shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 127 update-ir the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. boundary scan instructions the following is an description of the standard instructions. each instruction selects an serial test data register path between input tdi and output tdo. bypass the bypass instruction shifts data from input tdi to output tdo with one tck clock period delay. the instruction is used to bypass the device. extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is placed between tdi and tdo. primary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. primary device outputs can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. sample the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 128 idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identification code can then be shifted out using the shift-dr state. stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is connected between tdi and tdo. during the capture-dr state, the device identification code is loaded into the boundary scan register. the code can then be shifted out tdo using the shift-dr state. boundary scan register the boundary scan register is made up of 64 boundary scan cells, divided into input observation (in_cell), output (out_cell), and bidirectional (io_cell) cells. these cells are detailed in the pages which follow. the first 32 cells form the id code register, and carry the code 043140cd. the cells are arranged as follows: table 13 - pin/enable register bit cell type i.d. bit pin/ enable register bit cell type i.d. bit rstb 4 63 in_cell 0 rdp[3] 27 out_cell - ale 62 in_cell 0 rclko[2] 26 out_cell - csb 61 in_cell 0 rdn[2] 25 out_cell - wrb 60 in_cell 0 rdp[2] 24 out_cell - rdb 59 in_cell 0 rclko[1] 23 out_cell - a[0:8] 58 - 50 in_cell 100001100 rdn[1] 22 out_cell - ddi[3] 49 in_cell 0 rdp[1] 21 out_cell - dcr 48 in_cell 1 rdual 20 in_cell - tdual 47 in_cell 0 intb 19 io_cell - tdn[4] 46 in_cell 1 intb_oen 1 18 out_cell - tdp[4] 45 in_cell 0 d[0] 17 io_cell -
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 129 pin/enable register bit cell type i.d. bit pin/ enable register bit cell type i.d. bit tclki[4] 44 in_cell 0 d0_oen 1 16 out_cell - tdn[3] 43 in_cell 0 d[1] 15 io_cell tdp[3] 42 in_cell 0 d1_oen 1 14 out_cell - tclki[3] 41 in_cell 0 d[2] 13 io_cell - tdn[2] 40 in_cell 0 d2_oen 1 12 out_cell - tdp[2] 39 in_cell 1 d[3] 11 io_cell - tclki[2] 38 in_cell 1 d3_oen 1 10 out_cell - tdn[1] 37 in_cell 0 d[4] 9 io_cell - tdp[1] 36 in_cell 0 d4_oen 1 8out_cell- tclki[1] 35 in_cell 1 d[5] 7 io_cell - xclk 34 in_cell 1 d5_oen 1 6out_cell- clko8x 33 out_cell 0 d[6] 5 io_cell rclko[4] 32 out_cell 1 d6_oen 1 4out_cell- rdn[4] 31 out_cell - d[7] 3 io_cell - rdp[4] 30 out_cell - d7_oen 1 2out_cell rclko[3] 29 out_cell - hiz[2] 2 1out_cell- rdn[3] 28 out_cell - hiz[4] 3 0out_cell- notes: 1. all oen signals will set the corresponding bidirectional pin to an output when set low. 2. when set high, rdp[4:1], rdn[4:1], and rclko[4:1] will be set to high impedance. 3. when set high, clko8x will be set to high impedance. 4. rstb is the first bit of the boundary scan chain.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 130 figure 22 - input observation cell (in_cell) input pad d c clock-dr scan chain out input to internal logic shift-dr scan chain in 1 2 mux 1 2 1 2 1 2 i.d. code bit idcode g1 g2 in this diagram and those that follow, clock-dr is equal to tck when the current controller state is shift-dr or capture-dr, and unchanging otherwise. the multiplexer in the centre of the diagram selects one of four inputs, depending on the status of select lines g1 and g2. the id code bit is as listed in the table above.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 131 figure 23 - output cell (out_cell) d c d c g1 g2 1 2 mu x g1 1 1 mu x ou t p u t or e n abl e from system logic s can ch ai n i n scan chain out ext est ou t p u t o r enable shift -dr cl ock - d r updat e-dr 1 2 1 2 1 2 idcode i.d. code bit
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 132 figure 24 - bidirectional cell (io_cell) d c d c g1 1 1 mux output from internal logic scan chain in scan chain out extest output to pin shift-dr clock-dr update-dr input from pin input to internal logic g1 1 2 mux 1 2 1 2 1 2 g2 idcode i.d. code bit figure 25 - layout of output enable and bidirectional cells output enable from internal logic (0 = drive) input to internal logic output from internal logic scan chain in scan chain out i/o pad out_cell io_cell
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 133 13 functional timing 13.1 line code violation insertion figure 26 - b8zs line code violation insertion clk unidat txtip txring continuous zeros 000 0 vv bb b8zs signature pattern b b v v 000 0 lcvins = 1 causes omis s i on of f i r s t bi polar violation puls e. b b 0 v 000 0 clk unidat txtip txring continuous zeros 000 0 vv bb b8zs signature pattern the effect of setting the lcvins bit of the diagnostics register (005h, 045h, 085h, and 0c5h) is shown in the above diagrams. the signals clk and unidat are not actual signals but are used as reference guidelines and txtip[x] and txring[x] have been shown as square nrz pulses for illustrative purposes. clk shows the reference 1x clock used to generate the txtip[x] and txring[x] outputs. unidat is the unipolar data stream that is b8zs encoded to generate the txtip[x] and txring[x] bipolar output streams. setting lcvins
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 134 to a logic 1 generates one line code violation and 3 bit errors by causing the omission of the first line code violation pulse when a string of 8 consecutive zeros occurs in the unipolar data stream unidat. to generate another line code violation, the lcvins bit must be reset to logic 0 and then set to logic 1 again. figure 27 - hdb3 line code violation insertion clk unidat txtip txring continuous zeros 00 0v 10 0v 10 0v 1 clk unidat txtip txring continuous zeros 00 0 v 10 0v v 00 0 l cvins = 1 caus es omis s i on of bipol ar puls e and vi ol at i on of same polarity as previous violation. 1 the effect of setting the lcvins bit of the diagnostics register (005h, 045h, 085h, and 0c5h) is shown in the above diagrams. the signals clk and unidat are not actual signals but are used as reference guidelines and txtip[x] and txring[x] have been shown as square nrz pulses for illustrative purposes. clk shows the reference 1x clock used to generate the txtip[x] and txring[x] outputs. unidat is the unipolar data stream that is hdb3 encoded to generate the txtip[x] and txring[x] bipolar output streams. setting lcvins to a logic 1 generates one line code violation by causing the a bipolar violation pulse of the same polarity as the previous bipolar violation pulse when a string of 4 consecutive zeros occurs in the unipolar data stream unidat. to
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 135 generate another line code violation, the lcvins bit must be reset to logic 0 and then set to logic 1 again. figure 28 - ami line code violation insertion clk unidat txtip txring clk unidat txtip txring v lcvins = 1 causes a bi pol ar v iol at i on. the effect of setting the lcvins bit of the diagnostics register (005h, 045h, 085h, and 0c5h) is shown in the above diagrams. the signals clk and unidat are not actual signals but are used as reference guidelines and txtip[x] and txring[x] have been shown as square nrz pulses for illustrative purposes. clk shows the reference 1x clock used to generate the txtip[x] and txring[x] outputs. unidat is the unipolar data stream that is ami encoded to generate the txtip[x] and txring[x] bipolar output streams. setting lcvins to a logic 1 generates one line code violation by causing the next pulse to be of the same polarity as the previous pulse. subsequent pulses will be of alternate polarity. to generate another line code violation, the lcvins bit must be reset to logic 0 and then set to logic 1 again.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 136 14 absolute maximum ratings table 14 -.qdsx absolute maximum ratings ambient temperature under bias -55c to +125c storage temperature -65c to +150c voltage on vdd with respect to gnd -0.6v to +6.0v voltage on any pin -0.6v to vdd+0.6v static discharge voltage 1000 v latch-up current (t a = -40c to +85c) 100 ma package power dissipation 2.0 w
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 137 15 capacitance table 15 - qdsx capacitance symbol parameter typ units conditions c in input capacitance 10 pf t a = 25c, f = 1 mhz (sampled only) c out output capacitance 10 pf t a = 25c, f = 1 mhz (sampled only) c bidir bidirectional capacitance 10 pf t a = 25c, f = 1 mhz (sampled only)
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 138 16 d.c. characteristics (t a = -40c to +85c, v dd = 5 v 5%) (typical conditions: t a = 25c, v dd = 5 v) table 16 - qdsx d.c. characteristics symbol parameter min typ. max units conditions v dd ,ra vd , ta vd power supply 4.75 5.0 5.25 volts v il input low voltage -0.5 0.8 volts guaranteed input low voltage v ih input high voltage 2.0 v dd + 0.5 volts guaranteed input high voltage v rxtip analog input voltage a vs -0.6 a vd +0.6 volts v ol output or bidirectional low voltage 0.1 0.4 volts v dd = 5.0 v, i ol = -4 ma for data bus pins and -2 ma for others, note 3 v oh output or bidirectional high voltage vdd- 1.0v 4.7 volts v dd = 5.0 v, i oh = 4 ma for data bus pins and 2 ma for others, note 3 v t+ reset input high voltage 3.5 volts v t- reset input low voltage 1.0 volts
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 139 symbol parameter min typ. max units conditions v th reset input hysteresis voltage 1.0 volts i ilpu input low current +20 +83 +200 a v il = gnd, notes 1, 3 i ihpu input high current -10 0 +10 a v ih = v dd , notes 1, 3 i il input low current -10 0 +10 a v il = gnd, notes 2, 3 i ih input high current -10 0 +10 a v ih = v dd , notes 2, 3 i ddop1 operating current dsx-1 configuration 325 ma v dd = 5.25 v, outputs unloaded, xclk = 37.056 mhz, tclki[4:1] = 1.544 mhz, 1.544 mbit/s data rate on rxtip. note 4 i ddop2 operating current e1 configuration 330 ma v dd = 5.25 v, outputs unloaded, xclk = 49.152 mhz, tclki[4:1] = 2.048 mhz, 2.048 mbit/s data rate on rxtip. note 4 notes on d.c. characteristics: 1. input pin or bidirectional pin with internal pull-up resistors. 2. input pin or bidirectional pin without internal pull-up resistors
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 140 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. i ddop is the sum of all power supply currents when transmitting all ones from xpls. for dsx-1, xpls is using the 440-550 line buildout, which is the most energetic, and a 50 w resistor is connected across txtip and txring of each quadrant in order to mimic a 100 w line reflected back through a 1:1.36 transformer. for e1, xpls is using the 75 w template, and a 44 w resistor is connected across txtip and txring of each quadrant in order to mimic a 75 w line reflected back through a 1:1.36 transformer. 5. typical values are given as an aid to the system designer. product is not tested to the typical values given in the data sheet.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 141 17 microprocessor interface timing characteristics t a = -40c to +85c, v dd = 5 v 5% table 17 - microprocessor interface read access (figure 29) symbol parameter min max. units ts ar address to valid read set-up time 10 ns th ar address to valid read hold time 5 ns ts alr address to latch set-up time 10 ns th alr address to latch hold time 10 ns tv l valid latch pulse width 20 ns ts lr latch to read set-up 0 ns th lr latch to read hold 5 ns tp rd valid read to valid data propagation delay 80 ns tz rd valid read negated to output tristate 20 ns tz inth valid read negated to intb open 50 ns
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 142 figure 29 - microprocessor interface read timing intb tz inth (csb+rdb) valid data d[7:0] tp rd tz rd ts ar th ar valid address a[7:0] ale ts alr tv l ts lr th alr th lr notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[7:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 143 4. in non-multiplexed address/data bus architectures, ale should be held high and parameters tsalr, thalr, tvl, tslr, and thlr are not applicable. 5. parameter th ar is not applicable if address latching is used. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. table 18 - microprocessor interface write access (figure 30) symbol parameter min max. units ts aw address to valid write set-up time 10 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 10 ns th alw address to latch hold time 10 ns tv l valid latch pulse width 20 ns ts lw latch to write set-up 0 ns th lw latch to write hold 5 ns th dw data to valid write hold time 5 ns th aw address to valid write hold time 5 ns tv wr valid write pulse width 40 ns
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 144 figure 30 - microprocessor interface write timing th dw valid data d[7:0] tv wr ts aw th aw ts dw (csb+wrb) a[7:0] valid address ale tv l ts alw ts lw th alw th lw notes on microprocessor interface write timing: 1. a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. in non-multiplexed address/data bus architectures, ale should be held high and parameters tsalw, thalw, tvl, tslw, and thlw are not applicable. 3. parameter th aw is not applicable if address latching is used. 4. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 5. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 145 18 a.c. timing characteristics t a = -40 to +85c, v dd =5v 5% table 19 - xclk input for jitter attenuation (figure 31) symbol description min max. units txclk xclk frequency (nominally 37.056 mhz 100 ppm for t1 format or 49.152 mhz 50 ppm for e1 format) 50 mhz xclk duty cycle (at xclk = 37.056 mhz for t1, 49.152 mhz for e1) 40 60 % figure 31 - xclk input timing for jitter attenuation xclk xclk 1/t
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 146 table 20 - tclki input timing (figure 32) symbol description min max. units tt1tclki tclki frequency for t1 1 (nominally 1.544 mhz 130 ppm) 1.545 mhz te1tclki tclki frequency for e1 (note 1) 1 (nominally 2.048 mhz 50 ppm) 2.049 mhz thttclki tclki high duration (for t1 formats) 165 ns tlttclki tclki low duration (for t1 formats) 165 ns thetclki tclki high duration (for e1 formats) 125 ns tletclki tclki low duration (for e1 formats) 125 ns tstclki tclki to tdd/tdp or tdn input set-up time 20 ns thtclki tclki to tdd/tdp or tdn input hold-up time 20 ns figure 32 - tclki input timing tclki[x] th ttclki , th etclki , tl ttclki , tl etclki ,
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 147 tdd/tdp[x], tdn[x] tclki[x] valid t stclki t with tfall bit =1 tclki[x] valid t stclki t with tfall bit =0 tdd/tdp[x], tdn[x] htclki htclki
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 148 table 21 - clko8x input timing (fifo not in tx path) (figure 33) symbol description min max. units t s clko8x tclki[x] to clko8x setup time 25 ns t h clko8x tclki[x] to clko8x hold time 10 ns the above timing parameters apply when fifobyp=1 or djattx=0, but xsel[1:0] is not set to 10 binary. figure 33 - clko8x input timing diagram (fifo not in tx path) ts clko8x th clko8x tclki[x] clko8x
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 149 table 22 - xclk input timing (fifo not in tx path) (figure 34) symbol description min max. units t s xclk tclki[x] to xclk setup time 10 ns t h xclk tclki[x] to xclk hold time 25 ns the above timing parameters apply when fifobyp=1 or djattx=0, and xsel[1:0] is set to 10 binary. figure 34 - xclk input timing diagram (fifo not in tx path) ts xclk th xclk tclki[x] xclk
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 150 table 23 - rclko output timing (figure 35) symbol description min max. units tprclko rclko to output signals propagation delay 50 ns figure 35 - rclko output timing diagram rclko[x] valid t prclko rdd/rdp[x], rlcv/rdn[x] with rrise bit=0 rclko[x] valid t prclko rdd/rdp[x], rlcv/rdn[x], with rrise bit=1
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 151 table 24 - jtag port interface timing (figure 36) symbol description min max. units t tck tck frequency 1 mhz td tck tck duty cycle 40 60 % ts tms tms set-up time to tck 50 ns th tms tms hold time to tck 50 ns ts tdi tdi set-up time to tck 50 ns th tdi tdi hold time to tck 50 ns t p tdo tck low to tdo valid 2 50 ns
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 152 figure 36 - jtag port interface timing ts tms th tms tms tck ts tdi th tdi tdi tp tdo tdo tck
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 153 table 25 - analog receive data input timing (figure 37) symbol description min max. units twe1ain receive analog data signal pulse width in cept e1 mode 5 200 300 ns twt1ain receive analog data signal pulse width in t1 mode 5 250 400 ns figure 37 - analog receive data input timing diagram rxtip t ain w t ain w notes on input timing: 1. tclki can be a jittered clock signal subject to the minimum high and low durations th ttclki , tl ttclki , th etclki , and tl etclki . these durations correspond to the nominal xclk input frequency for the selected dsx-1 or cept e1 format. proper operation when tclki is a jittered clock is guaranteed by the design of the djat, and thus is not completely production tested. 2. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 3. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 154 4. when an input high clock time is specified, the clock high pulse width is measured between the 1.4 volt points of the rise and fall ramps. when an input low clock time is specified, the clock low pulse width is measured between the 1.4 volt points of the fall and rise ramps. 5. parameter guaranteed by design, not production tested. 6. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 7. maximum output propagation delays are measured with a 50 pf load on the outputs.
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 155 19 ordering and thermal information table 26 - qdsx ordering information part no. description PM4314-ri 128 plastic quad flat pack (pqfp) table 27 - qdsx thermal information part no. case temperature theta ja theta jc PM4314-ri -40c to 85c 31c/w 11c/w
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 156 20 mechanical information e 1 d e1 d1 e 128 8-12 deg a 8-12 deg a2 pin 1 designator nom. min. max. dim. aa1 a2 d d1 e e1 l e b ccc package type: body size: 14.10 14.00 13.90 0.73 0.88 1.03 0.10 14 x 20 x 2.7 mm 2.82 3.40 0.25 0.53 2.57 2.70 2.87 22.95 23.20 23.45 19.90 20.00 20.10 16.95 17.20 17.45 0.50 0.17 0.22 0.27 see detail a 128 pin metric rectangular plastic quad flatpack-mqfp gage plane, 0.25 above seating plane. detail a 0-7 deg plane seating 0.13-0.23 c l .25 a 0-10 deg. ccc c lead coplanarity notes: 1) all dimensions in millimeter. b standoff a1 3) foot length "l" is measured at c with tolerances as indicated. 2) dimensions shown are nominal
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device proprietary and confidential to pmc-sierra, inc., and for its customers internal use 157 notes
PM4314 qdsx data sheet pmc-950857 issue 5 quad t1/e1 line interface device none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchanta bility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not l imited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. ? 1998 pmc-sierra, inc. pmc-950857 (r5) ref pmc-950739 (r4) issue date: june 1998 proprietary and confidential to pmc-sierra, inc., and for its customers internal use contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com web site: http://www.pmc-sierra.com

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