View AD5764ASU-REEL7_2107692.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

complete, quad, 16-bit, high accuracy, serial input, bipolar voltage output dac preliminary technical data ad5764 rev. prc 21-oct-04 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features complete quad 16-bit d/a converter programmable output range: 10 v, 10.25 v, or 10.5 v 1 lsb max inl error, 1 lsb max dnl error low noise : 60 nv/ hz settling time: 10s max integrated reference buffers internal reference, 10 ppm/c on-chip temp sensor, 5c accuracy output control during power-up/brownout programmable short-circuit protection simultaneous updating via ldac asynchronous clr to zero code digital offset and gain adjust logic output control pins dsp/microcontroller compat ible serial interface temperature range:?40c to +85c i cmos? process technology applications industrial automation closed-loop servo control, process control data acquisition systems automatic test equipment automotive test and measurement high accuracy instrumentation general description the ad5764 is a quad, 16-bit serial input, voltage output digital-to analog converter that operates from supply voltages of 12 v up to 15 v. nominal full-scale output range is 10 v, provided are integrated output amplifiers, reference buffers, internal reference, and proprietary power-up/power-down control circuitry. it also features a digital i/o port that may be programmed via the serial interface, and an analog temperature sensor. the part incorporates digital offset and gain adjust registers per channel. the ad5764 is a high performance converter that offers guaranteed monotonicity, integral nonlinearity (inl) of 1 lsb, low noise and 10 s settling time and includes an on-chip 5 v reference with a reference tempco of 10 ppm/c max. during power-up (when the supply voltages are changing), vout is clamped to 0v via a low impedance path. the ad5764 uses a serial interface that operates at clock rates up to 30 mhz and is compatible with dsp and microcontroller interface standards. double buffering allows the simultaneous updating of all dacs. the input coding is programmable to either twos complement or straight binary formats. the asynchronous clear function clears all dac registers to either bipolar zero or zero-scale depending on the coding used. the ad5764 is ideal for both closed-loop servo control and open-loop control applications. the ad5764 is available in a 32-lead tqfp package, and offers guaranteed specifications over the ?40c to +85c industrial temperature range. see functional block diagram, figure 1. i cmos? process technology for analog systems designers within industrial/instrumentation eq uipment oems who need high performance ics at higher-voltage l evels, i cmos is a technology platform that enable s the development of analog ics capable of 30v an d operating at +/-15v supplies while allowing d ramatic reductions in power consumption and package size, and increased ac and dc performance.
ad5764 preliminary technical data rev. prc 21-oct-04| page 2 of 28 table of contents functional block diagram .............................................................. 3 specifications..................................................................................... 4 ac performance characteristics ................................................ 6 timing characteristics ................................................................ 7 absolute maximum ratings.......................................................... 10 esd caution................................................................................ 10 pin configuration and function descriptions........................... 11 terminology .................................................................................... 13 typical performance characteristics ........ error! bookmark not defined. general description ....................................................................... 15 dac architecture........................................................................... 16 reference buffers........................................................................ 16 serial interface ............................................................................ 16 simultaneous updating via ldac .......................................... 17 transfer function ......................................................................... 18 asynchronous clear ( clr )....................................................... 18 function register ....................................................................... 20 data register ............................................................................... 21 coarse gain register.................................................................... 21 fine gain register ........................................................................ 21 offset register............................................................................... 22 ad5764 features ............................................................................ 23 analog output control ............................................................. 23 digital offset and gain control............................................... 23 programmable short-circuit protection................................. 23 digital i/o port........................................................................... 23 temperature sensor ................................................................... 23 local ground offset adjust......................................................... 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 28 revision history revision prc 21-oct-04: preliminary version
preliminary technical data ad5764 rev. prc 21-oct-04| page 3 of 28 functional block diagram input reg c m reg c c reg c dac reg c 16 dac c input reg d m reg d reference buffers c reg d dac reg d 16 dac d g1 g2 input reg b m reg b c reg b dac reg b 16 dac b input reg a m reg a c reg a dac reg a 16 16 dac a ldac vref cd temp rstin rstout v ref ab refgnd agndd voutd agndc voutc agndb voutb agnda vouta iscc temp sensor reference buffers a v ss sdin sclk sync sdo d0 d1 bin/2scomp clr a v dd a v ss a v dd pgnd dv cc dgnd +5v reference voltage monitor and control input shift register and control logic g1 g2 g1 g2 g1 g2 04641-pra-001 refout figure 1. functional block diagram
ad5764 preliminary technical data rev. prc 21-oct-04| page 4 of 28 specifications av dd = +11.4 v to +15.75 v, av ss = ?11.4 v to ?15.75 v, agnd = dgnd = refgnd = pgnd=0 v; refab = refcd= 5 v ext; dv cc = 2.7 v to 5.5 v, r load = 10 k, c l = 200 pf. all specifications t min to t max , unless otherwise noted. table 1. parameter a grade 1 b grade 1 c grade 1 unit test conditions/comments accurac resolution 1 1 1 bits relative accuracy in 4 2 1 sb ma differential nonlinearity 1 1 1 sb ma guaranteed monotonic bipolar zero error 1 1 1 mv ma at 25c. error at other temperatures obtained using bipolar ero tc. bipolar zero tc 2 2 2 ppm fsr/c ma zero code error 1 1 1 mv ma at 25c. error at other temperatures obtained using ero code tc. zero code tc 2 2 2 ppm fsr/c ma gain error .2 .2 .2 fsr ma at 25c. error at other temperatures obtained using gain tc. gain tc 2 2 2 ppm fsr/c ma dc crosstalk 2 .5 .5 .5 sb ma referenceinput/output reference input 2 reference input voltage 5 5 5 v nom 1 for specified performance dc input impedance 1 1 1 m min typically 1 m input current 1 1 1 a ma typically 3 na reference range 1/5 1/5 1/5 v min/ma reference output output voltage 4./5.1 4./ 5.1 4./5.1 v min/ma at 25c reference tc 1 1 1 ppm/c ma 3 3 3 ppm/c typ output noise.1 to 1 tbd tbd tbd v p-p typ noise spectral density tbd tbd tbd nv/ typ output caracteristics 2 output voltage range 3 1 1 1 v min/ma av dd /av ss 11.4 v 13 13 13 v min/ma av dd /av ss 14.5 v output voltage tc 2 2 2 ppm fsr/c ma output voltage drift v s time tbd tbd tbd ppm fsr/1 ours typ short circuit current 1 1 1 ma ma ri scc ?
preliminary technical data ad5764 rev. prc 21-oct-04| page 5 of 28 parameter a grade 1 b grade 1 c grade 1 unit test conditions/comments digital inputs 2 dv cc = 2.7 v to 5.5 v, jedec compliant v ih , input high voltage 2 2 2 v min v il , input low voltage 0.8 0.8 0.8 v max input current 10 10 10 a max total for all pins. t a = t min to t max . pin capacitance 10 10 10 pf max digital outputs (d0,d1, sdo) 2 output low voltage 0.4 0.4 0.4 v max dv cc = 5 v 10%, sinking 200 a output high voltage dv cc ? 1 dv cc ? 1 dv cc ? 1 v min dv cc = 5 v 10%, sourcing 200 a output low voltage 0.4 0.4 0.4 v max dv cc = 2.7 v to 3.6 v, sinking 200 a output high voltage dv cc ? 0.5 dv cc ? 0.5 dv cc ? 0.5 v min dv cc = 2.7 v to 3.6 v, sourcing 200 a high impedance leakage current 1 1 1 a max sdo only high impedance output capacitance 5 5 5 pf typ sdo only temp sensor accuracy 1 1 1 c typ at 25c 5 5 5 c max ?40c < t <+85c output voltage @ 25c 1.5 1.5 1.5 v typ output voltage scale factor 5 5 5 mv/c typ output voltage range 0/3.0 0/3.0 0/3.0 v min/max output load current 200 200 200 a max current source only. power on time 10 10 10 ms typ to within 5c power requirements av dd /av ss 11.4/15.75 11.4/15.75 11.4/15.75 v min/max dv cc 2.7/5.5 2.7/5.5 2.7/5.5 v min/max power supply sensitivity 4 v out /v dd ?85 ?85 ?85 db typ ai dd 3.75 3.75 3.75 ma/channel max outputs unloaded ai ss 2.75 2.75 2.75 ma/channel max outputs unloaded di cc 1 1 1 ma max v ih = dv cc , v il = dgnd. tbd ma typ power dissipation 244 244 244 mw typ 12 v operation output unloaded 4 guaranteed by characterization. not production tested.
ad5764 preliminary technical data rev. prc 21-oct-04| page 6 of 28 ac performance characteristics av dd = +11.4 v to +15.75 v, av ss = ?11.4 v to ?15.75 v, agnd = dgnd = refgnd = pgnd=0 v; refab = refcd= 5 v ext; dv cc = 2.7 v to 5.5 v, r load = 10 k, c l = 200 pf. all specifications t min to t max , unless otherwise noted. guaranteed by design and characterization, not production tested. table 2. parameter a grade b grade c grade unit test conditions/comments dnamic performance output voltage settling time s typ full-scale step 1 1 1 s ma 1 1 1 s ma 512 sb step settling slew rate 5 5 5 v/s typ digital-to-analog glitch energy 5 5 5 nv-s typ glitch impulse peak amplitude 5 5 5 mv ma channel-to-channel isolation 1 1 1 db typ dac-to-dac crosstalk 5 5 5 nv-s typ digital crosstalk 5 5 nv-s typ digital feedthrough 1 1 nv-s typ effect of input bus activity on dac output under test output noise .1 to 1 .1 .1 sb p-p typ output noise .1 k to 1 k 5 45 45 v rms ma 1/f corner freuency 1 1 k typ output noise spectral density nv/ typ measured at 1 k complete system o utput noise spectral density nv/ typ measured at 1 k 5 guaranteed by design and characteriation. not production tested. includes noise contributions from integrated reference buffers 1-bit dac and output amplifier.
preliminary technical data ad5764 rev. prc 21-oct-04| page 7 of 28 timing characteristics av dd = +11.4 v to +15.75 v, av ss = ?11.4 v to ?15.75 v, agnd = dgnd = refgnd = pgnd = 0 v; refab = refcd= 5 v ext; dv cc = 2.7 v to 5.5 v, r load = 10 k, c l = 200 pf. all specifications t min to t max , unless otherwise noted. table 3. parameter imit at t min t ma unit description t 1 33 ns min sc cycle time t 2 13 ns min sc high time t 3 13 ns min sc low time t 4 13 ns min snc falling edge to sc falling edge setup time t 5 1 13 ns min 24 th sc falling edge to snc rising edge t 4 ns min minimum snc high time t 5 ns min data setup time t ns min data hold time t 2 ns min snc rising edge to dac falling edge t 1 2 ns min dac pulse width low t 11 5 ns min dac falling edge to dac output response time t 12 1 s ma dac output settling time t 13 2 ns min cr pulse width low t 14 12 s ma cr pulse activation time t 15 1112 2 ns ma sc rising edge to sdo valid t 1 12 ns min sc falling edge to snc rising edge t 1 12 2 ns min snc rising edge to dac falling edge guaranteed by design and characteriation. not production tested. all input signals are specified with t r t f 5 ns 1 to of dv cc and timed from a voltage level of 1.2 v. see figure 2 figure 3 and figure 4. 1 stand-alone mode only. 11 measured with the load circuit of figure 5. 12 daisy-chain mode only.
ad5764 preliminary technical data rev. prc 21-oct-04| page 8 of 28 db23 sclk sync sdin ldac v out ldac = 0 v out clr v out 12 24 db0 t 4 t 5 t 8 t 7 t 3 t 2 t 12 t 11 t 12 t 11 t 9 t 10 t 1 t 13 t 14 04641-pra-002 t 6 figure 2. serial interface timing diagram t 4 t 17 t 15 t 8 t 7 t 10 t 3 t 2 t 5 t 1 t 6 t 16 ldac sdo sdin sync sclk 24 48 db23 db0 db23 db0 db23 input word for dac n undefined input word for dac n+1 input word for dac n db0 0 4641-pra-003 figure 3. daisy chain timing diagram
preliminary technical data ad5764 rev. prc 21-oct-04| page 9 of 28 sdo sdin sync sclk 24 48 db23 db0 db23 db0 db23 selected register data clocked out undefined nop condition input word specifies register to be read db0 04641-pra-005 figure 4. readback timing diagram 200
ad5764 preliminary technical data rev. prc 21-oct-04| page 10 of 28 absolute maximum ratings t a = 25c unless otherwise noted. transient currents of up to 100 ma will not cause scr latch-up. table 4. parameter rating av dd to agnd dgnd .3 v to 1 v av ss to agnd dgnd .3 v to 1 v dv cc to dgnd .3 v to v digital inputs to dgnd .3 v to dv cc .3 v digital outputs to dgnd .3 v to dv cc .3 v ref in to agnd prgnd .3 v to 1 v ref out to agnd av ss to av dd v out abcd to agnd av ss to av dd agnd to dgnd .3 v to .3 v operating temperature range industrial 4c to 5c storage temperature range 5c to 15c unction temperature t ma 15c 32-ead tfp package a thermal impedance tbdc/ reflow soldering peak temperature 22c time at peak temperature 1 sec to 4 sec stresses above those listed under absolute maimum ratings may cause permanent damage to the device. this is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. eposure to absolute maimum rating conditions for etended periods may affect device reliability. esd caution esd electrostatic discharge sensitive device. electros tatic charges as high as 4 v readily accumulate on the human body and test euipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore proper esd precautions are recommended to avoid performance degradation or loss of functionality.
preliminary technical data ad5764 rev. prc 21-oct-04| page 11 of 28 pin configuration and fu nction descriptions ad5764 top view (not to scale) sync sclk sdin sdo clr ldac d1 d0 agnda vouta voutb agndb agndc voutc voutd agndd rstout rstin dgnd dv cc av dd pgnd iscc av ss bin/2scomp av dd av ss temp refgnd refout refcd refab 1 32 25 916 8 24 17 pin 1 indicator 04641-pra-007 figure 6. 32-lead tqfp pin configuration diagram table 5. pin function descriptions pin no. mnemonic function 1 snc active ow input. this is the frame synchron iation signal for the serial interface. hile snc is low data is transferred in on the falling edge of sc. 2 sc 13 serial clock input. data is cl ocked into the shift register on the falling edge of sc. this operates at clock speeds up to 3 m. 3 sdin 13 serial data input. data must be valid on the falling edge of sc. 4 sdo serial data output. used to clock data from the serial register in daisy-chain or readback mode. 5 cr 13 active ow input. asserting this pi n sets the dac registers to . dac oad dac. ogic input. this is used to update the da c registers and conseuently the analog output. hen tied permanentl y low the addressed dac register is updated on the 24 th clock of the serial register write. if dac is held high during the write cycle the dac input register is upda ted but the output is held off until the falling edge of dac . in this mode all analog outputs can be updated simultaneously on the falling edge of dac . d d1 d and d1 form a digital i/o port. the user can configure these pins as inputs or outputs that are configurable and readab le over the serial interface. hen configured as inputs these pins have weak internal pull-ups to dv cc . rstout reset ogic output. this is the output from the on-chip vo ltage monitor used in the reset circuit. if desired it may be us ed to control other system components. 1 rstin reset ogic input. this inp ut allows eternal access to the internal reset logic. applying a ogic to this in put resets the dac output to v. in normal operation rstin should be tied to ogic 1. 11 dgnd digital gnd pin. 12 dv cc digital supply pin. voltage ranges from 2. v to 5.5 v. hen programmed as outputs d and d1 are referenced to dv cc . 13 31 av dd positive analog supply pins. voltag e ranges from 11.4 v to 15.5 v. 14 pgnd ground reference point for analog circuitry. 15 3 av ss negative analog supply pins. voltage ranges from 11.4 v to 15.5 v. 1 iscc this pin us used in association with an eternal resistor to agnd to program the short-circuit current of the output amplifiers. 1 agndd ground reference pin for dac d output amplifier. 13 internal pull-up device on this logic input. therefore it can be left floating and will default to a logic high condition.
ad5764 preliminary technical data rev. prc 21-oct-04| page 12 of 28 pin no. mnemonic function 18 voutd analog output voltage of dac d. buffere d output with a nominal full-scale output range of 10 v. the output amplifier is ca pable of directly driving a 10 k, 200 pf load. 19 voutc analog output voltage of dac c. buffere d output with a nominal full-scale output range of 10 v. the output amplifier is ca pable of directly driving a 10 k, 200 pf load. 20 agndc ground reference pin for dac c output amplifier. 21 agndb ground reference pin for dac b output amplifier. 22 voutb analog output voltage of dac b. buffere d output with a nominal full-scale output range of 10 v. the output amplifier is ca pable of directly driving a 10 k, 200 pf load. 23 vouta analog output voltage of dac a. buffere d output with a nominal full-scale output range of 10 v. the output amplifier is ca pable of directly driving a 10 k, 200 pf load. 24 agnda ground reference pin for dac a output amplifier. 25 refab external reference voltage in put for channels a and b. reference input range is 1 v to 5 v; programs the full-scale output voltage. refin = 5 v for specified performance. 26 refcd external reference voltage in put for channels c and d. reference input range is 1 v to 5 v; programs the full-scale output voltage. refin = 5 v for specified performance. 27 refout reference output. this is the buffered re ference output from the internal voltage reference. the internal reference is 5 v 1 mv, with a reference tempco of 10 ppm/c. 28 refgnd reference ground return for the reference generator and buffers. 29 temp this pin provides an output voltage pr oportional to temp erature. the output voltage is 750 mv typical at 25c; vari ation with temperature is 10 mv/c. 32 bin/ 2scomp determines the dac coding. when set to a lo gic high, input coding is offset binary; 0x0000 outputs negative full-scale and 0xffff o utputs positive full-scale. invoking a clr in this mode sets the outp ut to negative full-scale. when set to a logic low, input coding is twos complement; 0x8000 outp uts negative full-scale, 0x0000 outputs 0v, and 0x7fff outputs positive full-scale. invoking a clr in this mode sets the output to 0 v.
preliminary technical data ad5764 rev. prc 21-oct-04| page 13 of 28 terminology relative accuracy for the dac relative accuracy or integral nonlinearity in is a measure of the maimum deviation in sbs from a straight line passing through the endpoints of the dac transfer function. a typical in vs. code plot can be seen in figure . differential nonlinearity differential nonlinearity dn is the difference between the measured change and the ideal 1 sb change between any two adjacent codes. a specified differential nonlinearity of 1 sb maimum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dn vs. code plot can be seen in figure . monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the ad54 is monotonic over its full operating temperature range bipolar zero error bipolar ero error is the deviation of the analog output from the ideal half-scale output of v when the dac register is loaded with straight binary coding or 2scomplement coding full-scale error full-scale error is a measure of the output error when full-scale code ffff e is loaded to the dac register. ideally the output should be programmed full scale value 1 sb. full- scale error is epressed in percent of full-scale range. a plot of full-scale error vs. temperature can be seen in figure . negative full-scale error / zero scale error negative full-scale error is the error in the dac output voltage when straight binary coding or 2scomplement coding is loaded to the dac register. ideally the output voltage should be programmed negative full scale value 1 sb. output voltage settling time output voltage settling time is the amount od time it takes for the output to settle to a specified level for a full-scale input change. slew rate the slew rate of a device is a limatation in the rate of change of the output voltage. the output slewing speed of a voltage- output d/a converter is usually limited by the slew rate of the amplifierused at its output. slew rate is measured from 1 to of the output signal and is given in vs. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal epressed as a percent of the full-scale range. total unadjusted error total unadjusted error tue is a measure of the output error taking all the various errors into account. a typical tue vs. code plot can be seen in figure . zero-code error drift this is a measure of the change in ero-code error with a change in temperature. it is epressed in v/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is epressed in ppm of full-scale range/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv secs and is measured when the digital input code is changed by 1 sb at the major carry transition fff e to e. see figure . digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv secs and measured with a full-scale code change on the data bus i.e. from all s to all 1s and vice versa. power supply sensitivity power supply sensitivity indicates how the output of the dac is affected by changes in the power supply voltage. dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac. it is epressed in v. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac
ad5764 preliminary technical data rev. prc 21-oct-04| page 14 of 28 due to a digital code changeand subsequent output change of another dac. this includes both digital and anlalog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with /ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. channel-to-channel isolation this is the ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference input of another dac. it is measured in db.
preliminary technical data ad5764 rev. prc 21-oct-04| page 15 of 28 typical performance characteristics
ad5764 preliminary technical data rev. prc 21-oct-04| page 16 of 28 general description the ad5764 is a quad 16-bit, serial input, bipolar voltage output dac. it operates from supply voltages of 11.4 v to 16.5 v and has a buffered output voltage of up to 10.25 v. data is written to the ad5764 in a 24-bit word format, via a 3- wire serial interface. the device also offers an sdo pin, which is available for daisy chaining or readback. the ad5764 incorporates a power-on reset circuit, which ensures that the dac outputs power up to 0v. the ad5764 also features a digital i/o port that may be programmed via the serial interface, an analog temperature sensor, on-chip 10 ppm/c voltage reference, on-chip reference buffers and per channel digital gain and offset registers. dac architecture the dac architecture of the ad5764 consists of a 16-bit current-mode segmented r-2r dac. the simplified circuit diagram for the dac section is shown in figure 13. the four msbs of the 16-bit data word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of the 15 matched resistors to either agnd or iout. the remaining 12 bits of the data word drive switches s0 to s11 of the 12-bit r- 2r ladder network. 2r e15 v ref 2r e14 e1 2r s11 rr r 2r s10 2r 12 bit r-2r ladder v out 2r s0 2r agnd r/8 4 msbs decoded into 15 equal segments figure 7. dac ladder structure reference buffers the ad5764 can operate with either an external or internal reference. the reference inputs (refab and refcd) have an input range up to 5 v. this input voltage is then used to provide a buffered positive and negative reference for the dac cores. the positive reference is given by + v ref = 2* v ref while the negative reference to the dac cores is given by -v ref = -2*v ref these positive and negative reference voltages (along with the gain register values) define the output ranges of the dacs. serial interface the ad5764 is controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 mhz and is compatible with spi, qspi, microwire and dsp standards. input shift register he input shift register is 24 bits ide data is loaded into the device ms first as a 24-bit ord under the control of a serial clock input sc he input register consists of a read/rite bit three register select bits three dac address bits and 16 data bits as shon in able 6 he timing diagram for this operation is shon in figure 2 upon poer-up the dac registers are loaded ith ero code 0x0000 he corresponding output voltage depends on the state of the in/2scomp pin if the in/2scomp pin is tied to dgnd then the data coding is 2scomplement and the outputs ill poer-up to 0v if the in/2scomp pin is tied high then the data coding is straight binary and the outputs ill poer-up to negative full-scale standalone operation he serial interface orks ith both a continuous and noncon- tinuous serial clock a continuous sc source can only be used if snc is held lo for the correct number of clock cycles in gated clock mode a burst clock containing the exact number of clock cycles must be used and snc must be taken high after the final clock to latch the data he first falling edge of snc starts the rite cycle xactly 24 falling clock edges must be applied to sc before snc is brought back high again if snc is brought high before the 24 th falling sc edge the rite is aborted if more than 24 falling sc edges are applied before snc is brought high the input data ill be corrupted he input register addressed is updated on the rising edge of snc in order for another serial transfer to take place snc must be brought lo again after the end of the serial data transfer data is automatically transferred from the input shift register to the input register of the addressed dac hen the data has been transferred into the input register of the addressed dac all dac registers and outputs can be updated by taking dac lo hile snc is high
preliminary technical data ad5764 rev. prc 21-oct-04| page 17 of 28 68hc11* miso sync sdin sclk mosi sck pc7 pc6 ldac sdo sync sclk ldac sdo sync sclk ldac sdo sdin sdin *additional pins omitted for clarity ad5764* ad5764* ad5764* r figure 8. daisy chaining the ad5764 daisy-chain operation for systems that contain several devices the sdo pin may be used to daisy-chain several devices together his daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines he first falling edge of snc starts the rite cycle he sc is continuously applied to the input shift register hen snc is lo if more than 24 clock pulses are applied the data ripples out of the shift register and appears on the sdo line his data is clocked out on the rising edge of sc and is valid on the falling edge y connecting the sdo of the first device to the din input of the next device in the chain a multidevice interface is constructed ach device in the system reuires 24 clock pulses herefore the total number of clock cycles must eual 24n here n is the total number of ad5764s in the chain hen the serial transfer to all devices is complete snc is taken high his latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register he serial clock may be a continuous or a gated clock a continuous sc source can only be used if snc is held lo for the correct number of clock cycles in gated clock mode a burst clock containing the exact number of clock cycles must be used and snc must be taken high after the final clock to latch the data readback operation readback mode is invoked by setting the r/ bit 1 in the serial input register rite ith r/ 1 its a2a0 in association ith its rg2 rg1 and rg0 select the register to be read he remaining data bits in the rite seuence are dont cares during the next spi rite the data appearing on the sdo output ill contain the data from the previously addressed register for a read of a single register the nop command can be used in clocking out the data from the selected register on sdo he readback diagram in figure 4 shos the readback seuence for example to read back the fine gain register of channel a on the ad5764 the folloing seuence should be implemented first rite 0xa0 to the ad5764 input register his configures the ad5764 for read mode ith the fine gain register of channel a selected note that all the data bits d15 to d0 are dont cares follo this ith a second rite a nop condition 0x00 during this rite the data from the fine gain register is clocked out on the sdo line ie data clocked out ill contain the data from the fine gain register in its d5 to d0 simuanous updaing via dac after data has been transferred into the input register of the dacs there are to ays in hich the dac registers and dac outputs can be updated depending on the status of both snc and dac one of to update modes is selected individual dac updating in this mode dac is held lo hile data is being clocked into the input shift register he addressed dac output is updated on the rising edge of snc simultaneous updating of all dacs in this mode dac is held high hile data is being clocked into the input shift register all dac outputs are updated by taking dac lo any time after snc has been taken high he update no occurs on the falling edge of dac
ad5764 preliminary technical data rev. prc 21-oct-04| page 18 of 28 v out dac register interface logic output i/v amplifier ldac sdo sdin 16-bit dac v refin sync input register sclk figure 9. simplified serial interface showing input loading circuitry for one dac channel transfer function table ? shows the ideal input code to output voltage relationship for the ad5764 for both straight binary and twos complement data coding. digital input analog output straight binary data coding msb lsb v out 1111 1111 1111 1111 +2 v ref x (32767/32768) 1000 0000 0000 0001 +2 v ref x (1/32768) 1000 0000 0000 0000 0 v 0111 1111 1111 1111 -2 v ref x (1/32768) 0000 0000 0000 0000 -2 v ref x (32767/32768) twos complement data coding msb lsb v out 0111 1111 1111 1111 +2 v ref x (32767/32768) 0000 0000 0000 0001 +2 v ref x (1/32768) 0000 0000 0000 0000 0 v 1111 1111 1111 1111 -2 v ref x (1/32768) 1000 0000 0000 0000 -2 v ref x (32767/32768) the output voltage expression is given by ? ? ? ? ? ? + ? = 65536 4 2 d v v v refin refin out where: d is the decimal equivalent of the code loaded to the dac. v refin is the reference voltage applied at the refin pin. asynchronous clear (clr ) clr is an active low, level sensitive clear that allows the outputs to be cleared to either 0 v (straight binary coding) or negative full scale (twos complement coding). it is necessary to maintain clr low for a minimum amount of time (refer to figure 3) for the operation to complete. when the clr signal is returned high, the output remains at the cleared value until a new value is programmed. the clr signal has priority over ldac and sync . a clear can also be initiated through software by writing the command 0x04xxxx to the ad 5764.
ad5764 preliminary technical data rev. prc 21-oct-04| page 20 of 28 table 6. input r eg ister for mat msb lsb r/ w 0 reg2 reg1 reg0 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 7. input register bit functions r/ w indicates a read from or a write to the addressed register. reg2, reg1, reg0 used in association with the address bits to determine if a read or write opera tion is to the data register, offset register, gain register, or function register. reg2 reg1 reg0 function 0 0 0 function register 0 1 0 data register 0 1 1 coarse gain register 1 0 0 fine gain register 1 0 1 offset register a2, a1, a0 these bits are used to decode the dac channels a2 a1 a0 channel address 0 0 0 dac a 0 0 1 dac b 0 1 0 dac c 0 1 1 dac d 1 0 0 all dacs d15 ? d0 data bits function register the function register is addressed by setting the three reg bits to 000. the values written to the address bits and the data bi ts determine the function addressed. the functions available through the function register are shown in table 8 and table 9. table 8. function register options reg2 reg1 reg0 a2 a1 a0 d15 ?. d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 nop, data = don?t care 0 0 0 0 0 1 don?t care local- ground- offset adjust d1 direction d1 value d0 direction d0 value sdo disable 0 0 0 1 0 0 clr, data = don?t care 0 0 0 1 0 1 load, data = don?t care table 9. explanation of function register options nop no operation instruction us ed in readback operations. local-ground- offset adjust set by the user to enable loca l-ground-offset adjust function. cleared by the user to disable local-gr ound-offset adjust function (default). d0 / d1 direction set by the user to enable d0/d1 as outputs. cleared by the user to enable d0/d1 as in puts (default). have weak internal pull-ups. d0 / d1 value i/o port status bits. logic values writte n to these locations determine the logic outputs on the d0 and d1 pins when configured as outputs. these bits indicate the status of the d0 and d1 pins when the i/o port is active as an input. when enabled as inputs, these bits are do n?t cares during a write operation. sdo disable set by the user to disable the sdo output. cleared by the user to enab le the sdo output (default). clr addressing this function resets the da c outputs to 0 v in twos complement mode and negative full scale in binary mode. load addressing this function updates the dac registers and consequently the analog outputs.
preliminary technical data ad5764 rev. prc 21-oct-04| page 21 of 28 data register the data register is addressed by setting the three reg bits to 010. the dac address bits select with which dac channel the dat a transfer is to take place (refer to table 7). the 16 data bits are in positions d15 to d0 as shown in table 10. table 10. programming the data register reg2 reg1 reg0 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 dac address 16 bit dac data coarse gain register the coarse gain register is addressed by setting the three reg bits to 011. the dac address bits select with which dac channel the data transfer is to take place (refer to table 7). the coarse gain register ia a 2-bit register and allows the user to select t he output range of each dac as shown in table 12. table 11. programming the coarse gain register reg2 reg1 reg0 a2 a1 a0 d15 ?. d2 d1 d0 0 1 1 dac address don?t care cg1 cg0 table 12. output range selection output range cg1 cg0 10 v 0 0 10.25 v 0 1 10.5 v 1 0 fine gain register the fine gain register is addressed by setting the three reg bi ts to 100. the dac address bits select with which dac channel th e data transfer is to take place (refer to table 7). the fine gain register is a 6-bit register and allows the user to adjust the gain of each dac channel by -32 lsbs to +31 lsbs in 1 lsb steps as shown in table 13 and table 14. table 13. programming the fine gain register reg2 reg1 reg0 a2 a1 a0 d15 ?. d6 d5 d4 d3 d2 d1 d0 1 0 0 dac address don?t care fg5 fg4 fg3 fg2 fg1 fg0 table 14. fine gain register options gain adjustment fg5 fg4 fg3 fg2 fg1 fg0 +31 lsbs 0 0 0 0 0 0 +30 lsbs 0 0 0 0 0 1 - - - - - - no adjustment 1 0 0 0 0 0 - - - - - - -31 lsbs 1 1 1 1 1 0 -32 lsbs 1 1 1 1 1 1
ad5764 preliminary technical data rev. prc 21-oct-04| page 22 of 28 offset register the offset register is addressed by setting the three reg bits to 101. the dac address bits select with which dac channel the d ata transfer is to take place (refer to table 7). the offset register is an 8-bit register and allows the user to adjust the offset of each channel by ? 15.875 lsbs to + 16 lsbs in steps of 1/8 lsb as shown in table 15 and table 16. table 15. programming the offset register reg2 reg1 reg0 a2 a1 a0 d15 ?. d8 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 dac address don?t care of7 of6 of5 of4 of3 of2 of1 of0 table 16. offset register options offset adjustment of7 of6 of5 of4 of3 of2 of1 of0 +15.875 lsbs 0 0 0 0 0 0 0 0 +15.75 lsbs 0 0 0 0 0 0 0 1 - - - - - - - - no adjustment 1 0 0 0 0 0 0 0 - - - - - - - - -15.875 lsbs 1 1 1 1 1 1 1 0 -16 lsbs 1 1 1 1 1 1 1 1
preliminary technical data ad5764 rev. prc 21-oct-04| page 23 of 28 ad5764 features analog output control in many industrial process control applications, it is vital that the output voltage be controlled during power up and during brownout conditions. when the supply voltages are changing, the vout pin is clamped to 0 v via a low impedance path. to prevent the output amp being shorted to 0 v during this time, transmission gate g1 is also opened. these conditions are maintained until the power supplies stabilize and a valid word is written to the dac register. at this time, g2 opens and g1 closes. both transmission gates are also externally controllable via the reset in ( rstin ) control input. for instance, if rstin is driven from a battery supervisor chip, the rstin input is driven low to open g1 and close g2 on power-off or during a brownout. conversely, the on-chip voltage detector output ( rstout ) is also available to the user to control other parts of the system. the basic transmission gate functionality is shown in figure 10. voltage monitor and control agnda vouta g1 rstout rstin g2 04641-pra-008 figure 10. analog output control circuitry digital offset and gain control the ad5764 incorporates a digital offset adjust function with a 16 lsb adjust range and 0.125 lsb resolution. the gain register allows the user to adjust the ad5764?s full-scale output range. the full-scale output can be programmed to achieve full- scale ranges of 10 v, 10.256 v, and 10.526 v. a fine gain trim is also available, allowing a trim range of 16 lsb in 1 lsb steps. programmable short-circuit protection the short-circuit current of the output amplifiers can be pro- grammed by inserting an external resistor between the iscc pin and agnd. the programmable range for the current is 500 a to 10 ma, corresponding to a resistor range of 120 k ? ?
ad5764 preliminary technical data rev. prc 21-oct-04| page 24 of 28 applications information typical operating circuit figure ?? shows the typical operating circuit for the ad5764. the only external components needed for this precision 16-bit dac are decoupling capacitors on the supply pins, r-c connection from refout to refab and refcd and a short circuit current setting resistor. because the device incorporates a voltage reference, and reference buffers, it eliminates the need for an external bipolar reference and associated buffers. this leads to an overall saving in both cost and board space. in the circuit below, vdd and vss are both conneted to 15 v, but vdd and vss can operate with supplies from 11.4 v to 16.5 v. in figure ??, agnda is connected to refgnd, but the option of force/sense is included on this device, if required by the user. 1 2 3 4 5 6 7 8 23 22 21 18 19 20 24 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ad5764 /sync sclk sdin sdo d0 /ldac clr d1 vouta voutb agndb voutd voutc agndc agnda agndd /rstout /rstin dgnd dvcc avdd pgnd avss iscc bin//2scomp avdd avss temp refgnd refout refcd refab /sync sclk sdin sdo /ldac d0 d1 /rstout /rstin bin//2scomp +5v +5v +15v -15v +15v -15v vouta v outb v outc v outd 6k ? ? force/sense of agnd ecause of the extremelyhigh accuracy of this device system design issues such as grounding and contact resistance are very important he ad5764 ith 10 v output has an s sie of 305 v herefore series iring and connector resistances of very small values could cause voltage drops of an s for this reason the ad5764 offers a force/sense output configuration figure shos ho to connect the ad5764 to the force/sense amplifier here accuracy of the output is important an amplifier such as the op177 is ideal he op177 is ultraprecise ith offset voltages of 10 v maximum at room temperature and offset drift 0f 01 v/c maximum alternative recommended amplifiers are the op1177 and the op77 for applications here optimiation of the circuit for settling time is needed the ad845 is recommended figure driving rfgnd and agnda using a force/sense amplifier precision voltage reference selection o achieve the optimum performance from the ad5764 over its full operating temperature range an external voltage reference must be used hought should be given to the selection of a precision voltage reference he ad5764 has to reference inputs rfa and rfcd he voltages applied to the reference inputs are used tomprovide a buffered positiver and negative reference for the dac cores herefore any error in the voltage reference is reflected in the outputs of the device here are four possible sources of error to consider hen choosing a voltage reference for high accuracy applications initial accuracy temperature coefficient of the output voltage long term drift and output voltage noise initial accuracy error on the output voltage of an external reference could lead to a full-scale error in the dac herefore to minimie these errors a reference ith lo initial accuracy error specification is preferred also choosing a reference ith an output trim adustment such as the adr425 allos a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal he trim adustment can also be used at temperature to trim out any error ong term drift is a measure of ho much the reference output voltage drifts over time a reference ith a tight lon-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime he temperature coefficient of a references output voltage affects in dn and u a reference ith a tight tempaerature coefficient specifiaction should be chosen to reduce the dependence of the dac output voltage on ambient conditions in high accuracy applications hich have a relatively lo noise budget reference output voltage noise needs to be considered choosing a reference aith as lo an output noise voltage as practical for the system resolution reuired is important precision voltage references such as the adr435 f design produce lo output noise in the 01 hx to 10 h region hoever as the circuit bandidth increases filtering the output of the reference may be reuired to minimise the output noise
preliminary technical data ad5764 rev. prc 21-oct-04| page 25 of 28 table ??. partial list of precision references recommended for use with the ad5764 part no. initial accuracy (mv max) long-term drift (ppm typ) temp drift (ppm/ c max) 0.1 hz to 10 hz noise (v p-p typ) adr435 6 30 3 3.4 adr425 6 50 3 3.4 adr02 5 50 3 15 adr395 6 50 25 5 ad586 2.5 15 10 4 aout guideines in any circuit where accura cy is important careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad54 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad54 is in a system where multiple devices reuire an agnd-to-dgnd connection the connection should be made at one point only. the star ground point should be established as close as possible to the device. the ad54 should have ample supply bypassing of 1 f in parallel with .1 f on each su pply located as close to the package as possible ideally right up against the device. the 1 f capacitors are the tantalum bead type. the .1 f capacitor should have low effective seri es resistance esr and low effective series inductance esi such as the common ceramic types which provide a low impedance path to ground at high freuencies to handle transient currents due to internal logic switching. the power supply lines of the ad54 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. a ground line routed between the sdin and sc lines helps reduce crosstalk between them not reuired on a multilayer board which has a separate ground plane but sepa rating the lines helps. it is essential to minimie noise on the refin line because it couples through to the dac output. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feed through the board. a microstrip techniue is by far the best but not always possible with a double-sided board. in this techniue the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. isoated interface in many process control applications it is necessary to provide an isolation barrier between the controller and the unit being controlled. opto-isolators can provide voltage isolation in ecess of 3 kv. the serial loading structure of the ad54 makes it ideal for opto-isolated interfaces because the number of interface lines is kept to a minimum. figure shows a 4- channel isolated interface to the ad54. to reduce the number of opto-isolators if the simultaneous updating of the dac is not reuired the dac pin may be tied permanently low. the dac can then be updated on the rising edge of snc. dv cc to sdin to sc to snc snc out seria coc out seria data out ad5764 to mc68hc11 interface figure shos an example of a serial interface beteen the ad5764 and the mc68hc11 microc ontroller he serial peripheral interface spi on the mc68hc11 is configured for master mode msr 1 clock polarity bit cpo 0 and the clock phase bit cpha 1 he spi is configured by
ad5764 preliminary technical data rev. prc 21-oct-04| page 26 of 28 w r i t i n g t o t h e s p i c o n t r o l r e g i s t e r ( s p c r ) ---- -see the 68hc11 user manual c o te 68hc11 ries te c o te 76 te mi outut ries t e serial ata line i o te 76 an te mi inut is rien ro e c is rien ro one o te ort lines in tis case pc7 en ata is ein transitte to te 76 te c line pc7 is taen lo an ata is transitte m irst ata aearin on te mi outut is ali on te allin ee o c it allin cloc ees occur in te transit ccle so in orer to loa te reuire it or pc7 is not rout i until te tir 8it or as een transerre to te cs inut sit reister 76 c i c mi c pc7 mc68hc11 ii pi mi ci mi iure 1 76 to mc68hc11 interace c is controlle te pc6 ort outut e c can e uate ater eac te transer rinin c lo is eale oes not so oter serial lines or te c i c ere use it coul e controlle ort outut pc or eale ad5764 to 8051 interface he ad5764 reuires a clock synchr onied to the serial data for this reason the 8051 must be operated in mode 0 in this mode serial data enters and exits through rxd and a shift clock is output on rxd p33 and p34 are bit programmable pins on the serial port and are used to drive snc and dac respectively he 8051 provides the s of its suf register as the first bit in the data stream he user must ensure that the data in the suf register is arranged correctly because the dac expects ms first hen data is to be transmitted to the dac p33 is taken lo data on rxd is clocked out of the microcontroller on the rising edge of xd and is valid on the falling edge as a result no glue logic is reuired beteen this dac and the microcontroller interface he 8051 transmits data in 8-bit bytes ith only eight falling clock edges occurring in the transmit cycle ecause the dac expects a 24-bit ord snc p33 must be left lo after the first eight bits are transferred after the third byte has been transferred the p33 line is taken high he dac may be updated using dac via p34 of the 8051 ad5764 to adsp2101/adsp2103 interface an interface beteen the ad5764 and the adsp2101/ adsp2103 is shon in figure he adsp2101/adsp2103 should be set up to operate in the spor transmit alternate framing mode he adsp2101 /adsp2103 are programmed through the spor control regist er and should be configured as follos internal clock operation active lo framing and 24-bit ord length ransmission is initiated by riting a ord to the x register after the spor has been enabled as the data is clocked out of the dsp on the rising edge of sc no glue logic is reuired to interface the dsp to the dac in the interface shon the dac output is updated using the dac pin via the dsp alternatively the dac input could be tied permanently lo and then the update takes place automatically hen fs is taken high ad5764 sc sdin snc d sc rfs adsp2101/ adsp2103 addiiona pins omid for cari sdo dr fs dac fo figure 14 ad5764 to adsp2101/adsp2103 interface ad5764 to pic16c6x/7x interface he pic16c6x/7x synchronous serial port ssp is configured as an spi master ith the clock polarity bit set to 0 his is done by riting to the synchronous serial port control register sspcon see the pic16/17 microcontroller user manual in tis eale i/ ort 1 is ein use to ulse c an enale te serial ort o t e 76 is icrocontroller transers onl eit its o ata urin eac serial transer oeration tereore tree co nsecutie rite oerations are neee iure sos te connection iara
preliminary technical data ad5764 rev. prc 21-oct-04| page 27 of 28 ad5764* sclk sdin sync sdo/rc5 sclk/rc3 ra1 pic16c6x/7x* *additional pins omitted for clarity sdo sdi/rc4 figure 15. ad5764 to pic16c6x/7x interface evaluation board the ad5764 comes with a full evaluation board to aid designers in evaluating the high performance of the part with a minimum of effort. all that is required with the evaluation board is a power supply, a pc, and an oscilloscope. the ad5764 evaluation kit includ es a populated, tested ad5764 printed circuit bo ard. the evaluation board interfaces to the usb interface of the pc. software is available with the evaluation board, which allows the user to easily program the ad5764. a schematic of the evaluation board is shown in figure ??. the software runs on any pc that has microsoft windows? 95/98/me/2000/nt /xp installed. an application note is available that gives full details on operating the evaluation board.
ad5764 preliminary technical data rev. prc 21-oct-04| page 28 of 28 outline dimensions top view (pins down) 1 24 17 25 32 8 9 16 0.45 0.37 0.30 0.80 bsc 7.00 sq 9.00 sq 1.05 1.00 0.95 seating plane 1.20 max 0.15 0.05 7 0 0.75 0.60 0.45 compliant to jedec standards ms-026aba figure 16. 32-lead thin quad flatpack [tqfp] (su-32) dimensions shown in millimeters ordering guide model function inl package description package option ad5764csu quad 16-bit dac 1 lsb max 32-lead tqfp su-32 ad5764bsu quad 16-bit dac 2 lsb max 32-lead tqfp su-32 ad5764asu quad 16-bit dac 4 lsb max 32-lead tqfp su-32 ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners.

▲Up To Search▲

Price & Availability of AD5764ASU-REEL7

	To Download AD5764ASU-REEL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .