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d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct4353 triple 2-channel analog multiplexer/demultiplexer with latch for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 features wide analog input voltage range: 5 v low on resistance: 80 w (typ.) at v cc - v ee = 4.5 v 70 w (typ.) at v cc - v ee = 6.0 v 60 w (typ.) at v cc - v ee = 9.0 v logic level translation: to enable 5 v logic to communicate with 5 v analog signals typical break before make built in address latches provided output capability: non-standard i cc category: msi general description the 74hc/hct4353 are high-speed si-gate cmos devices. they are specified in compliance with jedec standard no. 7a. the 74hc/hct4353 are triple 2-channel analog multiplexers/demultiplexers with two common enable inputs ( e 1 and e 2 ) and a latch enable input ( le). each multiplexer has two independent inputs/outputs (ny 0 and ny 1 ), a common input/output (nz) and select inputs (s 1 to s 3 ). each multiplexer/demultiplexer contains two bidirectional analog switches, each with one side connected to an independent input/output (ny 0 and ny 1 ) and the other side connected to a common input/output (nz). with e 1 low and e 2 high, one of the two switches is selected (low impedance on-state) by s 1 to s 3 . the data at the select inputs may be latched by using the active low latch enable input ( le). when le is high, the latch is transparent. when either of the two enable inputs, e 1 (active low) and e 2 (active high), is inactive, all analog switches are turned off. v cc and gnd are the supply voltage pins for the digital control inputs (s 1 to s 3 , le, e 1 and e 2 ). the v cc to gnd ranges are 2.0 to 10.0 v for hc and 4.5 to 5.5 v for hct. the analog inputs/outputs (ny 0 and ny 1 , and nz) can swing between v cc as a positive limit and v ee as a negative limit. v cc - v ee may not exceed 10.0 v. for operation as a digital multiplexer/demultiplexer, v ee is connected to gnd (typically ground). quick reference data v ee = gnd = 0 v; t amb = 25 c; t r = t f = 6 ns symbol parameter conditions typical unit hc hct t pzh / t pzl turn on time e 1 ,e 2 or s n to v os c l = 50 pf; r l =1 k w ; v cc = 5 v 29 21 ns t phz / t plz turn off time e 1 ,e 2 or s n to v os 20 22 ns c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per switch notes 1 and 2 23 23 pf c s max. switch capacitance independent (y) 5 5 pf common (z) 8 8 pf notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d = c pd v cc 2 f i + ? {(c l +c s ) v cc 2 f o } where: f i = input frequency in mhz c l = output load capacitance in pf f o = output frequency in mhz c s = max. switch capacitance in pf ? {(c l c s ) v cc 2 f o } = sum of outputs v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information .
december 1990 3 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 pin description pin no. symbol name and function 2, 1 2y 0 ,2y 1 independent inputs/outputs 5 3z common input/output 6, 4 3y 0 ,3y 1 independent inputs/outputs 3, 14 n.c. not connected 7 e 1 enable input (active low) 8e 2 enable input (active high) 9v ee negative supply voltage 10 gnd ground (0 v) 11 le latch enable input (active low) 15, 13, 12 s 1 to s 3 select inputs 16, 17 1y 0 ,1y 1 independent inputs/outputs 18 1z common input/output 19 2z common input/output 20 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 4 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 function table notes 1. last selected channel on. 2. selected channels latched. h = high voltage level l = low voltage level x = dont care = high-to-low le transition applications analog multiplexing and demultiplexing digital multiplexing and demultiplexing signal gating inputs channel on e 1 e 2 le s n h x h l x x x x none none l l h h h h l h ny0 - nz ny 1 - nz l x h x l x x (1) (2) fig.4 functional diagram. fig.5 schematic diagram (one switch).
december 1990 5 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 ratings limiting values in accordance with the absolute maximum system (iec 134) voltages are referenced to v ee = gnd (ground = 0 v) note to ratings 1. to avoid drawing v cc current out of terminals nz, when switch current flows in terminals ny n , the voltage drop across the bidirectional switch must not exceed 0.4 v. if the switch current flows into terminals nz, no v cc current will flow out of terminals ny n . in this case there is no limit for the voltage drop across the switch, but the voltages at ny n and nz may not exceed v cc or v ee . recommended operating conditions symbol parameter min. max. unit conditions v cc dc supply voltage - 0.5 +11.0 v i ik dc digital input diode current 20 ma for v i <- 0.5 v or v i > v cc + 0.5 v i sk dc switch diode current 20 ma for v s <- 0.5 v or v s > v cc + 0.5 v i s dc switch current 25 ma for - 0.5 v < v s < v cc + 0.5 v i ee dc v ee current 20 ma i cc ; i gnd dc v cc or gnd current 50 ma t stg storage temperature range - 65 +150 c p tot power dissipation per package for temperature range: - 40 to +125 c 74hc/hct plastic dil 750 mw above +70 c: derate linearly with 12 mw/k plastic mini-pack (so) 500 mw above +70 c: derate linearly with 8 mw/k p s power dissipation per switch 100 mw symbol parameter 74hc 74hct unit conditions min. typ. max. min. typ. max. v cc dc supply voltage v cc - gnd 2.0 5.0 10.0 4.5 5.0 5.5 v see figs 6 and 7 v cc dc supply voltage v cc - v ee 2.0 5.0 10.0 2.0 5.0 10.0 v see figs 6 and 7 v i dc input voltage range gnd v cc gnd v cc v v s dc switch voltage range v ee v cc v ee v cc v t amb operating ambient temperature range - 40 +85 - 40 +85 c see dc and ac character- istics t amb operating ambient temperature range - 40 +125 - 40 +125 c t r ,t f input rise and fall times 6.0 1000 500 400 250 6.0 500 ns v cc = 2.0 v v cc = 4.5 v v cc = 6.0 v v cc = 10.0 v
december 1990 6 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 fig.6 guaranteed operating area as a function of the supply voltages for 74hc4353. handbook, halfpage 10 8 6 4 2 0 0246810 v cc - v ee (v) v cc - gnd (v) mba334 operating area fig.7 guaranteed operating area as a function of the supply voltages for 74hct4353. dc characteristics for 74hc/hct for 74hc: v cc - gnd or v cc - v ee = 2.0, 4.5, 6.0 and 9.0 v for 74hct: v cc - gnd = 4.5 and 5.5 v; v cc - v ee = 2.0, 4.5, 6.0 and 9.0 v notes to dc characteristics 1. at supply voltages (v cc - v ee ) approaching 2.0 v the analog switch on-resistance becomes extremely non-linear. there it is recommended that these devices be used to transmit digital signals only, when using these supply voltages. 2. for test circuit measuring r on see fig.8. symbol parameter t amb ( c) unit test conditions 74hc/hct v cc (v) v ee (v) i s ( m a) v is v i +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. r on on resistance (peak) - 100 90 70 - 180 160 130 - 225 200 165 - 270 240 195 w w w w 2.0 4.5 6.0 4.5 0 0 0 - 4.5 100 1000 1000 1000 v cc to v ee v in or v il r on on resistance (rail) 150 80 70 60 - 140 120 105 - 175 150 130 - 210 180 160 w w w w 2.0 4.5 6.0 4.5 0 0 0 - 4.5 100 1000 1000 1000 v ee v ih or v il r on on resistance 150 90 80 65 - 160 140 120 - 200 175 150 - 240 210 180 w w w w 2.0 4.5 6.0 4.5 0 0 0 - 4.5 100 1000 1000 1000 v cc v ih or v il d r on maximum d on resistance between any two channels - 9 8 6 w w w w 2.0 4.5 6.0 4.5 0 0 0 - 4.5 v cc to v ee v ih or v il
december 1990 7 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 dc characteristics for 74hc voltages are referenced to gnd (ground = 0 v) symbol parameter t amb ( c) unit test conditions 74hc v cc (v) v ee (v) v i other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v ih high level input voltage 1.5 3.15 4.2 6.3 1.2 2.4 3.2 4.7 1.5 3.15 4.2 6.3 1.5 3.15 4.2 6.3 v 2.0 4.5 6.0 9.0 v il low level input voltage 0.8 2.1 2.8 4.3 0.5 1.35 1.8 2.7 0.5 1.35 1.8 2.7 0.5 1.35 1.8 2.7 v 2.0 4.5 6.0 9.0 i i input leakage current 0.1 0.2 1.0 2.0 1.0 2.0 m a 6.0 10.0 0 0 v cc or gnd i s analog switch off-state current per channel 0.1 1.0 1.0 m a 10.0 0v ih or v il v s ? = v cc - v ee (see fig.10) i s analog switch off-state current all channels 0.1 1.0 1.0 m a 10.0 0v ih or v il v s ? = v cc - v ee (see fig.10) i s analog switch on-state current 0.1 1.0 1.0 m a 10.0 0v ih or v il v s ? = v cc - v ee (see fig.11) i cc quiescent supply current 8.0 16.0 80.0 160.0 160.0 320.0 m a 6.0 10.0 0 0 v cc or gnd v is =v ee or v cc ;v os = v cc or v ee
december 1990 8 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) v ee (v) other + 25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay v is to v os 14 5 4 4 60 12 10 8 75 15 13 10 90 18 15 12 ns 2.0 4.5 6.0 4.5 0 0 0 - 4.5 r l = ; c l = 50 pf (see fig.18) t pzh / t pzl turn on time e 1 ;e 2 to v os 61 22 18 18 250 50 43 40 315 63 54 50 375 75 64 60 ns 2.0 4.5 6.0 4.5 0 0 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t pzh / t pzl turn on time le to v os 55 20 16 17 200 40 34 40 250 50 43 50 300 60 51 60 ns 2.0 4.5 6.0 4.5 0 0 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t pzh / t pzl turn on time s n to v os 61 22 18 17 225 45 38 40 280 56 48 50 340 68 58 60 ns 2.0 4.5 6.0 4.5 0 0 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t phz / t plz turn off time e 1 ;e 2 to v os 66 24 19 19 250 50 43 40 315 63 54 50 375 75 64 60 ns 2.0 4.5 6.0 4.5 0 0 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t phz / t plz turn off time s n to v os ; le to v os 55 20 16 19 200 40 34 40 250 50 43 50 300 60 51 60 ns 2.0 4.5 6.0 4.5 0 0 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t su set-up time s n to le 60 12 10 18 17 6 5 8 75 15 13 23 90 18 15 27 ns 2.0 4.5 6.0 4.5 0 0 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.20) t h hold time s n to le 5 5 5 5 - 6 - 2 - 2 - 3 5 5 5 5 5 5 5 5 ns 2.0 4.5 6.0 4.5 0 0 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.20) t w le minimum pulse width high 80 16 14 16 11 4 3 6 100 20 17 20 120 24 20 24 ns 2.0 4.5 6.0 4.5 0 0 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.20)
december 1990 9 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 dc characteristics for 74hct voltages are referenced to gnd (ground = 0 v) note to hct types 1. the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given here. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. symbol parameter t amb ( c) unit test conditions 74hct v cc (v) v ee (v) v i other + 25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.6 2.0 2.0 v 4.5 to 5.5 v il low level input voltage 1.2 0.8 0.8 0.8 v 4.5 to 5.5 i i input leakage current 0.1 1.0 1.0 m a 5.5 0 v cc or gnd i s analog switch off-state current per channel 0.1 1.0 1.0 m a 10.0 0v ih or v il v s ? = v cc - v ee fig.10 i s analog switch off-state current all channels 0.1 1.0 1.0 m a 10.0 0v ih or v il v s ? = v cc - v ee fig.10 i s analog switch on-state current 0.1 1.0 1.0 m a 10.0 0v ih or v il v s ? = v cc - v ee fig.11 i cc quiescent supply current 8.0 16.0 80.0 160.0 160.0 320.0 m a 5.5 5.0 0 - 5.0 v cc or gnd v is =v ee or v cc ; v os = v cc or v ee d i cc additional quiescent supply current per input pin for unit load coef?cient is 1 (note 1) 100 360 450 490 m a 4.5 to 5.5 0 v cc - 2.1 v other inputs at v cc or gnd input unit load coefficient e 1 ,e 2 s n le 0.50 0.50 1.5
december 1990 10 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) v ee (v) other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay v is to v os 5 4 12 8 15 10 18 12 ns 4.5 4.5 0 - 4.5 r l = ; c l = 50 pf (see fig.18) t pzh / t pzl turn on time e 1 to v os 26 22 55 45 69 56 83 68 ns 4.5 4.5 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t pzh / t pzl turn on time e 2 to v os 22 18 50 40 63 50 75 60 ns 4.5 4.5 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t pzh / t pzl turn on time le to v os 21 17 45 40 56 50 68 60 ns 4.5 4.5 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t pzh / t pzl turn on time s n to v os 25 19 50 45 63 56 75 68 ns 4.5 4.5 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t phz / t plz turn off time e 1 to v os 23 19 50 40 63 50 75 60 ns 4.5 4.5 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t phz / t plz turn off time e 2 to v os 27 23 50 40 63 50 75 60 ns 4.5 4.5 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t phz / t plz turn off time le to v os 19 19 40 40 50 50 60 60 ns 4.5 4.5 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t phz / t plz turn off time s n to v os 22 22 45 45 56 56 68 68 ns 4.5 4.5 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.19) t su set-up time s n to le 12 15 7 9 15 19 18 22 ns 4.5 4.5 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.20) t h hold time s n to le 5 5 0 - 2 5 5 5 5 ns 4.5 4.5 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.20) t w le minimum pulse width high 16 16 3 5 20 20 24 24 ns 4.5 4.5 0 - 4.5 r l =1k w ; c l = 50 pf (see fig.20)
december 1990 11 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 fig.8 test circuit for measuring r on . fig.9 typical r on as a function of input voltage v is for v is = 0 to v cc - v ee . fig.10 test circuit for measuring off-state current. fig.11 test circuit for measuring on-state current.
december 1990 12 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 additional ac characteristics for 74hc/hct recommended conditions and typical values gnd = 0 v; t amb =25 c notes to the ac characteristics 1. adjust input voltage v is to 0 dbm level (0 dbm = 1 mw into 600 w ). 2. adjust input voltage v is to 0 dbm level at v os for 1 mhz (0 dbm = 1 mw into 50 w ). general note v is is the input voltage at an ny n or nz terminal, whichever is assigned as an input. v os is the output voltage at an ny n or nz terminal, whichever is assigned as an output. symbol parameter typ. unit v cc (v) v ee (v) v is(p-p) (v) conditions sine-wave distortion f = 1 khz 0.04 0.02 % % 2.25 4.5 - 2.25 - 4.5 4.0 8.0 r l = 10 k w ;c l = 50 pf (see fig.14) sine-wave distortion f = 10 khz 0.12 0.06 % % 2.25 4.5 - 2.25 - 4.5 4.0 8.0 r l = 10 k w ;c l = 50 pf (see fig.14) switch off signal feed-through - 50 - 50 db db 2.25 4.5 - 2.25 - 4.5 note 1 r l = 600 w ;c l = 50 pf f = 1 mhz (see figs 12 and 15) crosstalk between any two switches/ multiplexers - 60 - 60 db db 2.25 4.5 - 2.25 - 4.5 note 1 r l = 600 w ;c l = 50 pf; f = 1 mhz (see fig.16) v (p - p) crosstalk voltage between control and any switch (peak-to-peak value) 110 220 mv mv 4.5 4.5 0 - 4.5 r l = 600 w ;c l = 50 pf; f = 1 mhz ( e 1 ,e 2 or s n , square-wave between v cc and gnd, t r =t f = 6 ns) (see fig.17) f max minimum frequency response ( - 3db) 160 170 mhz mhz 2.25 4.5 - 2.25 - 4.5 note 2 r l =50 w ;c l = 10 pf (see figs 13 and 14) c s maximum switch capacitance independent (y) common (z) 5 12 pf pf fig.12 typical switch off signal feed-through as a function of frequency. test conditions: v cc = 4.5 v; gnd = 0 v; v ee = - 4.5 v; r l =50 w ;r source =1 k w .
december 1990 13 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 fig.13 typical frequency response. test conditions: v cc = 4.5 v; gnd = 0 v; v ee = - 4.5 v; r l =50 w ;r source =1 k w . fig.14 test circuit for measuring sine-wave distortion and minimum frequency response. fig.15 test circuit for measuring switch off signal feed-through. fig.16 test circuits for measuring crosstalk between any two switches/multiplexers. (a) = channel on condition (b) channel off condition. fig.17 test circuit for measuring crosstalk between control and any switch. the crosstalk is defined as follows (oscilloscope output):
december 1990 14 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 ac waveforms fig.18 waveforms showing the input (v is )to output (v os ) propagation delays. fig.19 waveforms showing the turn-on and turn-off times. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.20 waveforms showing the set-up and hold times from s n inputs to le input, and minimum pulse width of le. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v.
december 1990 15 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 test circuit and waveforms fig.21 test circuit for measuring ac performance. conditions test switch v is t pzh t pzl t phz t plz others v ee v cc v ee v cc open v cc v ee v cc v ee pulse family amplitude v m t r ;t f f max ; pulse width other 74hc v cc 50% < 2 ns 6 ns 74hct 3.0 v 1.3 v < 2 ns 6 ns c l = load capacitance including jig and probe capacitance (see ac characteristics for values). r t = termination resistance should be equal to the output impedance z o of the pulse generator. t r =t f = 6 ns; when measuring f max , there is no constraint on t r , t f with 50% duty factor. fig.22 input pulse definitions. conditions test switch v is t pzh t pzl t phz t plz others v ee v cc v ee v cc open v cc v ee v cc v ee pulse family amplitude v m t r ;t f f max ; pulse width other 74hc v cc 50% < 2 ns 6 ns 74hct 3.0 v 1.3 v < 2 ns 6 ns c l = load capacitance including jig and probe capacitance (see ac characteristics for values). r t = termination resistance should be equal to the output impedance z o of the pulse generator. t r =t f = 6 ns; when measuring f max , there is no constraint on t r , t f with 50% duty factor.
december 1990 16 philips semiconductors product speci?cation triple 2-channel analog multiplexer/demultiplexer with latch 74hc/hct4353 package outlines see 74hc/hct/hcu/hcmos logic package outlines .

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