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BTS4130QGA smart high-side power switch data sheet, rev. 1.0, march 2008 automotive power
datasheet 2 1.0, 2008-27-02 bts 4130qga 1overview 3 2block diagram 5 3 pin configuration 6 3.1 pin assignment 6 3.2 pin definitions and functions 6 3.3 voltage and current definition 7 4 general product characteristics 8 4.1 absolute maximum ratings 8 4.2 functional range 9 4.3 thermal resistance 9 5 power stage 10 5.1 output on-state resistance 10 5.2 turn on / off characteristics 10 5.3 inductive output clamp 11 5.3.1 maximum load inductance 12 5.4 electrical characteristics power stage 13 6 protection mechanisms 14 6.1 loss of ground protection 14 6.2 undervoltage protection 14 6.3 overvoltage protection 14 6.4 reverse polarity protection 15 6.5 overload protection 15 6.5.1 current limitation 16 6.6 electrical characteristics protection functions 17 7 diagnostic mechanism 18 7.1 st 0/1/2/3 pin 18 7.2 st0/1/2/3 signal in case of failures 18 7.2.1 diagnostic in open load, channel off 19 7.2.2 st 0/1 signal in case of over temperature 20 7.3 electrical characteristics diagnostic functions 21 8 input pins 22 8.1 input circuitry 22 8.2 electrical characteristics 22 9 application information 23 9.1 further application information 23 10 package outlines 24 11 revision history 25
pg-dso-20-32 type package marking BTS4130QGA pg-dso-20-32 BTS4130QGA data sheet 3 rev. 1.0, 2008-03-18 smart high-side power switch four channel device BTS4130QGA 1 overview basic features ? withstand low cranking voltage ? fit for 12v application ? four channel device ? very low stand-by current ? cmos compatible inputs ? electrostatic discharge protection (esd) ? optimized electromagnetic compatibility ? logic ground independent from load ground ? very low leakage current from out to the load in off state ? green product (rohs compliant) ?aec qualified description the BTS4130QGA is a quad channel smart high-side power switch. it is embedded in a pg-dso-20-32 package, providing protective functions and diagnostics. the power transistor is built by a n-channel power mosfet with charge pump. the device is monolithically integrated in smart technology. it is specially designed to drive relays as well as resistive loads in the harsh automotive environment. table 1 electrical parameters (short form) parameter symbol value operating voltage range v sop 5.5v .... 20v undervoltage switch off at t j = -40c v s (uso) 3.2v maximum load per channel p bulb 2 * r5w, relays or led over voltage protection v s (az) 43v max on state resistance at t j = 150c per channel r ds(on) 260m ? nominal load current (one channel active) i l (nom) 1.8a minimum current limitation i l_scr 5a standby current for the whole device with load i s(off) 16a maximum reverse battery voltage - v s(rev) 32v
data sheet 4 rev. 1.0, 2008-03-18 BTS4130QGA overview diagnostic feature ? open load detection in off state ? feedback of the thermal shutdown in on state ? diagnostic feedback with open drain output protection functions ? short circuit protection ? overload protection ? current limitation ? thermal shutdown ? overvoltage protection (including load dump) with external resistor ? reverse battery protection with external resistor ? loss of ground and loss of v s protection ? electrostatic discharge protection (esd) application ? all types of resistiv, inductive and capacitive loads
data sheet 5 rev. 1.0, 2008-03-18 BTS4130QGA block diagram 2 block diagram figure 1 block diagram for the BTS4130QGA block diagram . emf channel 0 v s out 0 in0 t driver logic gate control & charge pump open load detection over temperature clamp for inductive load over current switch o ff voltage sensor esd protection st 0/1 internal power supply channel 1 in1 control and protection circuit equivalent to channel 0 t v s out 1 channel 2 v s out 2 in2 t driver logic gate control & charge pump open load detection over temperature clamp for inductive load over current switch o ff voltage sensor gnd esd protection st 2/3 internal power supply channel 3 in3 control and protection circuit equivalent to channel 0 t v s out 3
data sheet 6 rev. 1.0, 2008-03-18 BTS4130QGA pin configuration 3 pin configuration 3.1 pin assignment figure 2 pin configuration 3.2 pin definitions and functions pin symbol function 1, 10, 11, 12, 15, 16, 19, 20 v s battery voltage; design the wiring for the simultaneous maximum short circuit currents from channel 0 and 1 and also for low thermal resistance 2 gnd0/1 ground ; ground connection for channel 0 and 1 3 in0 input channel 0; input signal for channel 0. activate the channel in case of logic high level 4 st 0/1 diagnostic feedback; of channel 0/1. open drain. 5 in1 input channel 1; input signal for channel 1. activate the channel in case of logic high level 6 gnd2/3 ground ; ground connection for channel 2 and 3 7 in2 input channel 2; input signal for channel 2. activate the channel in case of logic high level 8 st 2/3 diagnostic feedback; of channel 2/3. open drain. 9 in3 input channel 3; input signal for channel 3. activate the channel in case of logic high level 1 2 3 4 14 13 12 11 st 0/1 gnd0/1 in0 vs 5 6 7 in1 17 16 15 out0 out1 vs gnd2/3 pinout so20 shared diag.vsd 10 9 8 20 19 18 vs vs vs out3 out2 vs vs vs in2 st2/3 in3
data sheet 7 rev. 1.0, 2008-03-18 BTS4130QGA pin configuration 3.3 voltage and current definition figure 3 shows all terms used in this data sheet, with associated convention for positive values. figure 3 voltage and current definition 13 out3 output 3; protected high side power output channel 3 14 out2 output 2; protected high side power output channel 2 17 out1 output 1; protected high side power output channel 1 18 out0 output 0; protected high side power output channel 0 pin symbol function v s in0 in1 st 0/1 gnd out0 out1 i in 0 i in1 i st0 /1 v s v in0 v in1 v st0 /1 i s i gnd v ds0 v ds1 v out0 v out1 voltage and current convention quad shared diag.vsd in2 in3 st 2/3 i in 2 i in 3 i st2 /3 out2 out3 v out3 v ds2 v ds3 v out2 i out3 i out0 i out1 i out2
data sheet 8 rev. 1.0, 2008-03-18 BTS4130QGA general product characteristics 4 general product characteristics 4.1 absolute maximum ratings note: stresses above the ones listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings 1) t j = 25c; (unless otherwise specified) 1) not subject to production test, specified by design pos. parameter symbol limit values unit conditions min. max. voltages 4.1.1 supply voltage v s -0.3 43 v ? 4.1.2 reverse polarity voltage - v s(rev) ? 32 v ? 4.1.3 supply voltage for short circuit protection v bat(sc) 0 20 v r ecu = 20m ?, r cable = 16m ? /m, l cable = 1h/m, l = 0 or 5m 2) see chapter 6 2) set up in accordance to aec q100-012 and aec q101-006 input pins 4.1.4 voltage at input pins v in -10 16 v ? 4.1.5 current through input pins i in -0.3 0.3 ma ? 4.1.6 current through input pins pulsed i in -5 5 ma only for testing status pin 4.1.7 current through st 0/1 pin i st0/1 -5 5 ma ? 4.1.8 current through st 2/3 pin i st2/3 -5 5 ma ? power stage 4.1.9 load current | i l | ? i l(lim) a ? 4.1.10 power dissipation (dc), all channel active p tot ? 1.4 w t a = 85c, t j <150c 4.1.11 maximum switchable energy, single pulse e as ? 76 mj i l = 2.3a, v s = 12v temperatures 4.1.12 junction temperature t j -40 150 c ? 4.1.13 dynamic temperature increase while switching ? t j ? 60 k ? 4.1.14 storage temperature t stg -55 150 c ? esd susceptibility 4.1.15 esd resistivity in pin v esd -1 1 kv hbm 3) 3) esd susceptibility hbm according to eia/jesd 22-a 114b 4.1.16 esd resistivity st 0/1, 2/3 pins v esd -4 4 kv hbm 3) 4.1.17 esd resistivity out to all other pins shorted v esd -5 5 kv hbm 3)
data sheet 9 rev. 1.0, 2008-03-18 BTS4130QGA general product characteristics note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 4.2 functional range t j = -40 c to +150 c; (unless otherwise specified) note: within the functional range the ic operates as described in the circuit description. the electrical characteristics are specified within the conditions given in the related electrical characteristics table. 4.3 thermal resistance pos. parameter symbol limit values unit conditions min. max. 4.2.1 operating voltage v sop 5.5 20 v v in = 4.5v, r l = 12 ?, v ds < 0.5v 4.2.2 undervoltage switch off v suv ? 3.2 v - 1) , t j = -40c, v ds < 0.5v 1) battery voltage is decreasing 4.2.3 operating current one channel active four channels active i gnd ? ? 0.9 3.3 ma v in = 5v 4.2.4 standby current for whole device with load i s(off) ? ? ? 16 16 24 a t j = 25c t j = 85c 2) t j = 150c, v s = 12v, r l = 12 ?, v in = 0v 2) not subject to production test. specified by design pos. parameter symbol limit values unit conditions min. typ. max. 4.3.1 junction to soldering point each channel r thjsp ? ? 15 k/w ? 1) 1) not subject to production test, specified by design 4.3.2 junction to ambient r thja ? 45 ? k/w with 6cm2 cooling area 1)
data sheet 10 rev. 1.0, 2008-03-18 BTS4130QGA power stage 5 power stage the power stages are built by an n-channel vertical power mosfet (dmos) with charge pump. 5.1 output on-state resistance the on-state resistance r ds(on) depends on the supply voltage as well as the junction temperature t j . figure 4 shows the dependencies for the typical on-state resistance. the behavior in reverse polarity is described in chapter 6.4 . figure 4 typical on-state resistance a high signal (see chapter 8 ) at the input pin causes the power dmos to switch on with a dedicated slope, which is optimized in terms of emc emission. 5.2 turn on / off characteristics figure 5 shows the typical timing when switching a resistive load. figure 5 turn on/off (resistive) timing 0 50 100 150 200 250 300 5 7 9 11 13 15 17 19 vs (v) rdson (mohm) rdson (mohm) @ -40c rdson (mohm) @ +25c rdson (mohm) @ +150c ron.vsd in t v out t on t off 90% v s 10% v s v in_h_min v in_l_max t switching times.vs d 30% v s 70% v s dv/dt on dv/dt off
data sheet 11 rev. 1.0, 2008-03-18 BTS4130QGA power stage 5.3 inductive output clamp when switching off inductive loads with high side switches, the voltage v out drops below ground potential, because the inductance intends to continue driving the current. to prevent the destruction of the device due to high voltages, there is a voltage clamp mechanism implemented that keeps the negative output voltage at a certain level ( v s - v ds(az) ). please refers to figure 6 and figure 7 for details. nevertheless, the maximum allowed load inductance is limited. figure 6 output clamp (out0 and out1) figure 7 switching an inductance v bat v out i l l, r l v s out v ds logic in v in output clamp.vsd gnd in v out i l v s v s- v ds(az) t t t switching an inductance.vs d t peak
data sheet 12 rev. 1.0, 2008-03-18 BTS4130QGA power stage 5.3.1 maximum load inductance during demagnetization of inductive loads, energy has to be dissipated in the BTS4130QGA. this energy can be calculated with following equation: following equation simplifies under the assumption of r l = 0 ? . the energy, which is converted into heat, is limited by the thermal design of the component. see figure 8 for the maximum allowed inductivity. figure 8 maximum energy dissipation single pulse, t j,start = 150 c ev ds az () l r l ------ - v s v ds az () ? r l ---------------------------------- 1 r l i l v s v ds az () ? ---------------------------------- ? ?? ?? ln i l + = e 1 2 -- - li 2 1 v s v s v ds az () ? ---------------------------------- ? ?? ?? = max eas.vsd 1 10 100 1000 123456 il (a) zl (mh)
data sheet 13 rev. 1.0, 2008-03-18 BTS4130QGA power stage 5.4 electrical characteristics power stage electrical characteristics: power stage v s = 12 v, t j = -40 c to +150 c. typical values are given at t j = 25c pos. parameter symbol limit values unit conditions min. typ. max. 5.4.1 on-state resistance per channel r ds(on) ? 130 ? m ? t j = 25c, 1) i l = 2a, v in = 5v, see figure 4 1) not subject to production test, specified by design ? 210 260 t j = 150c 5.4.2 nominal load current per channel one channel active two channel active four channel active i l(nom) 2.1 1.5 1.1 ? ? ? ? ? ? a t a = 85c 1) , t j <150c 5.4.3 drain to source clamping voltage v ds(az) = v s - v out v ds(az) 41 47 52 v i ds = 40ma 2) 2) voltage is measured by forcing i ds. 5.4.4 output leakage current per channel i l(off) ? 1 5 a v in = 0v 5.4.5 slew rate on 10% to 30% v out d v/dt on 0.2 ? 1 v/s r l = 12 ?, v s =12v see figure 5 5.4.6 slew rate off 70% to 40% v out -d v/dt off 0.2 ? 1.1 v/s 5.4.7 turn-on time to 90% v s includes propagation delay t on ? 100 250 s 5.4.8 turn-off time to 10% v s includes propagation delay t off ? 100 270 s
data sheet 14 rev. 1.0, 2008-03-18 BTS4130QGA protection mechanisms 6 protection mechanisms the device provides embedded protective functions. integrated protection functions are designed to prevent the destruction of the ic from fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are designed for neither continuous nor repetitive operation. 6.1 loss of ground protection in case of loss of the module ground, where the load remains connected to ground, the device protects itself by automatically turning off (when it was previously on) or remains off, regardless of the voltage applied on in pins. in that case, a maximum i (outgnd) can flow out of the output. 6.2 undervoltage protection below v suv_max , the under voltage mechanism is met. if the supply voltage is below the under voltage mechanism, the device is off (turns off). as soon as the supply voltage is above the under voltage mechanism, then the device can be switched on and the protection functions are operational. 6.3 overvoltage protection there is a clamp mechanism for over voltage protection. to guarantee this mechanism operates properly in the application, the current in the zener diode zd az has to be limited by a ground resistor. figure 9 shows a typical application to withstand overvoltage issues. in case of supply greater than v s(az) , the power transistor switches on and the voltage across logic section is clamped. as a result, the internal ground potential rises to v s - v s(az) . due to the esd zener diodes, the potential at pins in and st 0/1/2/3 rises almost to that potential, depending on the impedance of the connected circuitry. integrated resistors are provided at the in pins to protect the input circuitry from excessive current flow during this condition but an external resistor must be provided at the st0/1/2/3 pins. figure 9 over voltage protection with external components in1 r in0 in0 r in1 zd esd gnd out v s v bat r gnd zd az overvoltage protection quad diag shared.vsd v ccc r l r st 0/1 st 0/1 r pu_st 0/1 in3 r in2 in2 r in3 zd esd v ccc r st 2/3 st 2/3 r pu_st 3 logic
data sheet 15 rev. 1.0, 2008-03-18 BTS4130QGA protection mechanisms in the case the supply voltage is in between of v s(sc) max and v ds(az) , the output transistor is still operational and follow the input. if at least one channel is in on state, parameters are no longer warranted and lifetime is reduced compared to normal mode. this specially impacts the short circuit robustness, as well as the maximum energy e as the device can handle. 6.4 reverse polarity protection in case of reverse polarity, the intrinsic body diode causes power dissipation. the current in this intrinsic body diode is limited by the load itself. additionally, the current into the ground path and the logical pins has to be limited to the maximum current described in chapter 4.1 , sometimes with an external resistor. figure 10 shows a typical application. the r gnd resistor is used to limit the current in the zener protection of the device. resistors r in and r st are used to limit the current in the logic of the device and in the esd protection stage. the recommended value for r gnd is 150 ? , for r st 0/1 = 15k ? . in case the over voltage is not considered in the application, r gnd can be replaced by a shottky diode. figure 10 reverse polarity protection with external components 6.5 overload protection in case of overload, or short circuit to ground, the BTS4130QGA offers several protections mechanisms. micro controller protection diodes gnd out0, 1, 2, 3 in1 v s v bat r in0 in0 st 0/1 r in 1 r st /1 r gnd zd body r everse polarity quad shared diag .vsd -v ds(rev) i l(nom) r l r pu st 0/1 vccc zd esd in1 r in0 in0 st 2/3 r in 1 r st 2/3 r pu st 2/3 vccc zd esd
data sheet 16 rev. 1.0, 2008-03-18 BTS4130QGA protection mechanisms 6.5.1 current limitation at first step, the instantaneous power in the switch is maintained to a safe level by limiting the current to the maximum current allowed in the switch i l(lim) . during this time, the dmos temperature is increasing, which affects the current flowing in the dmos. at thermal shutdown, the device turns off and cools down. a restart mechanism is used, after cooling down, the device restarts and limits the current to i l(scr) . figure 11 shows the behavior of the current limitation as a function of time. figure 11 current limitation function of the time t i l i l(lim) i l(scr) current limitation with diag shared.vs d t in st 0/1 t
data sheet 17 rev. 1.0, 2008-03-18 BTS4130QGA protection mechanisms 6.6 electrical characteristics protection functions electrical characteristics: protection v s = 12 v, t j = -40 c to +150 c. typical values are given at t j = 25c pos. parameter symbol limit values unit conditions min. typ. max. loss of ground 6.6.1 output leakage current while gnd disconnected i out(gnd) ? ? 2 ma v s = 32v v in = 0v reverse polarity 6.6.2 drain source diode voltage during reverse polarity - v ds(rev) ? 600 ? mv i l = - 2a, t j = 150c v in = 0v overvoltage 6.6.3 over voltage protection v s(az) 41 47 52 v i s = 40ma overload condition 6.6.4 load current limitation i l(lim) ? ? 5 ? 9 ? 14 ? ? a t j = -40c, t j = 25c, t j = 150c 6.6.5 repetitive short circuit current limit i l(scr) ? ? 6.5 6.5 ? ? a one channel 1) two channel 1) parallel 6.6.6 thermal shutdown temperature t jsc 150 ? ? c ? 6.6.7 thermal shutdown hysteresis ? t jt ? 10 ? k ? 1) 1) not subject to production test, but specified by design
data sheet 18 rev. 1.0, 2008-03-18 BTS4130QGA diagnostic mechanism 7 diagnostic mechanism for diagnosis purpose, the BTS4130QGA provides status pin. 7.1 st 0/1/2/3 pin BTS4130QGA status pins are an open drain, active low circuit. figure 12 shows the equivalent circuitry. as long as no ?hard? failure mode occurs (short circuit to gnd / over temperature or open load in off), the signal is permanently high, and due to a required external pull-up to the logic voltage will exhibit a logic high in the application. a suggested value for the r pu st01 is 15 k ?. . figure 12 status output circuitry 7.2 st0/1/2/3 signal in case of failures table 2 gives a quick reference for the logical state of the st 0/1/2/3 pins during device operation. table 2 st 0/1 2/3 truth table device operation in0/2 in1/3 out0/2 out1/3 st 0/1 st2/3 normal operation l l l l h l h l h h l h l h h h h open load channel 0/2 l x > v (ol) x l 1) 1) l if potential at the output exceeds the openload detection voltage h x h x h open load channel 1/3 x l x > v (ol) l 1) x h x h h over temperature both channel l l l l h x h x l l h x l x l over temp channel 0/2 l x l x h h x l x l over temp channel 1/3 x l x l h x h x l l st pin quad shared diag. vsd gnd st 0/1 or st 2/3 r st 0/1 r st 2/3 zd esd r pu st 0/1 r pu st 2/3 v ccc or channel 0 or 2 diagnostic logic channel 1 or 3 diagnostic logic
data sheet 19 rev. 1.0, 2008-03-18 BTS4130QGA diagnostic mechanism 7.2.1 diagnostic in open load, channel off for open load diagnosis in off-state, an external output pull-up resistor ( r ol ) is recommended. for calculation of the pull-up resistor value, the leakage currents and the open load threshold voltage v ol(off) has to be taken into account. figure 13 gives a sketch of the situation and figure 14 shows the typical timing diagram. i leakage defines the leakage current in the complete system, including i l(off) (see chapter 5.4 ) and external leakages e.g. due to humidity, corrosion, etc... in the application. to reduce the stand-by current of the system, an open load resistor switch s ol is recommended. if the channel is off, the output is no longer pulled down by the load and v out voltage rises to nearly v s . this is recognized by the device as open load. the voltage threshold is given by v ol(off) . in that case, the st 0/1 signal is switched to a logical low v st01(l) . figure 13 open load detection in off electrical equivalent circuit figure 14 st 0/1 in open load condition out v s r leakage r ol s ol v bat v ol(off) i leakage i loff ol comp. open load in off.vsd gnd r gnd in v out st 0/1 or st 2/3 i l diagnostic in open load quad shared diag.vs d t t t t v st(high) v (ol) v st(low)
data sheet 20 rev. 1.0, 2008-03-18 BTS4130QGA diagnostic mechanism 7.2.2 st 0/1 signal in case of over temperature in case of over temperature, the junction temperature reaches the thermal shutdown temperature t jsc . in that case, the st 0/1 signal is toggling between v st01(l) and v st01(h) . figure 15 gives a sketch of the situation. figure 15 sense signal in overtemperature condition . in v out st 0/1 t j diagnostic in overload shared toggling.vs d t t t t t jsc ? t jsc
data sheet 21 rev. 1.0, 2008-03-18 BTS4130QGA diagnostic mechanism 7.3 electrical characteristics diagnostic functions electrical characteristics: diagnostics v s = 12 v, t j = -40 c to +150 c. typical values are given at t j = 25c pos. parameter symbol limit values unit conditions min. typ. max. load condition threshold for diagnostic 7.3.1 open load detection voltage v ol(off) 1.7 2.8 4.0 v ? st 0/1 or st 2/3 pin 7.3.2 status output (open drain) high level; zener limit voltage v st (high) 5.4 ? ? v i st = +1.6ma 1) , zener limit voltage 7.3.3 status output (open drain) low level v st (low) ? ? 0.6 v i st = +1.6ma 1) 1) if ground resistor r gnd is used, the voltage drop across this resistor has to be added diagnostic timing 7.3.4 status change after positive input slope with open load t dst(on_ol) ? 10 20 s ? 2) 2) not subject to production test, specified by design 7.3.5 status change after positive input slope with overload t dst(on_ovl) 30 ? ? s ? 2) 7.3.6 status change after negative input slope with open load t dst(off_ol) ? ? 500 s ? 7.3.7 status change after negative input slope with overtemperature t dst(off) ? ? 20 s ? 2)
data sheet 22 rev. 1.0, 2008-03-18 BTS4130QGA input pins 8 input pins 8.1 input circuitry the input circuitry is cmos compatible. the concept of the input pin is to react to voltage transition and not to voltage threshold. with the schmidt trigger, it is impossible to have the device in an un-defined state, if the voltage on the input pin is slowly increasing or decreasing. the output is either off or on but cannot be in an linear or undefined state. the input circuitry is compatible with pwm applications. figure 16 shows the electrical equivalent input circuitry. the pull down current source ensures the channel is off with a floating input. figure 16 input pin circuitry 8.2 electrical characteristics electrical characteristics: diagnostics v s = 12 v, t j = -40 c to +150 c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) typical values are given at t j = 25c pos. parameter symbol limit values unit conditions min. typ. max. input pins characteristics 8.2.1 low level input voltage v in(l) ? ? 1 v ? 1) 1) if ground resistor r gnd is used, the voltage drop across this resistor has to be added 8.2.2 high level input voltage v in(h) 2.5 ? ? v ? 1) 8.2.3 input voltage hysteresis v in(hys) ? 0.2 ? v ? 2) 2) not subject to production test, specified by design 8.2.4 low level input current i in(l) 5 ? 20 a v in = 0.4v 8.2.5 high level input current i in(h) 10 35 60 a v in = 5v 8.2.6 input resistance r i 2.5 4 6 k ? see figure 16 in esd to driver?s logic input circuitry.vsd r i i i
data sheet 23 rev. 1.0, 2008-03-18 BTS4130QGA application information 9 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 17 application diagram with BTS4130QGA note: this is a very simplified example of an application circuit. the function must be verified in the real application. 9.1 further application information ? for further information you may visit http://www.infineon.com/ out out in gnd vdd microcontroller (e.g. xc22xx) in0 in1 st0/1 gnd out0 out1 v s v bat v dd v dd out out in in2 in3 st2/3 out2 out3 v dd
data sheet 24 rev. 1.0, 2008-03-18 BTS4130QGA package outlines 10 package outlines figure 18 pg-dso-20-32 (plastic dual small outline package) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb- free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). 110 11 20 index marking 1) does not include plastic or metal protrusions of 0.15 max per side 2) does not include dambar protrusion of 0.05 max per side gps05094 2.65 max 0.1 0.2 -0.1 2.45 -0.2 +0.15 0.35 1.27 2) 0.2 24x -0.2 7.6 1) 0.35 x 45? 0.23 8? max +0.09 +0.8 ?.3 10.3 0.4 12.8 -0.2 1)
data sheet 25 rev. 1.0, 2008-03-18 BTS4130QGA revision history 11 revision history version date changes 1.0 2008-03-18 creation of the data sheet
edition 2008-03-18 published by infineon technologies ag 81726 munich, germany ? 2008 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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