3.3v, 180mhz, multi-output zero delay buffer cypress semiconductor corporation 525 los coches st. document#: 38-07084 rev. *a 06/18/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 1 of 8 http://www.cypress.com z9951 product features ? 180mhz clock support ? supports powerpc tm , intel and risc processors ? 9 clock outputs: frequency configurable ? two reference clock inputs for dynamic toggling ? oscillator or pecl reference input ? output disable control ? spread spectrum compatible ? 3.3v power supply ? pin compatible with mpc951 ? industrial temp. range: -40c to +85c ? 32-pin tqfp package block diagram figure 1 frequency table sel (a:d) qa qb qc (0,1) qd (0:4) 0000 vco/2 vco/4 vco/4 vco/4 0001 vco/2 vco/4 vco/4 vco/8 0010 vco/2 vco/4 vco/8 vco/4 0011 vco/2 vco/4 vco/8 vco/8 0100 vco/2 vco/8 vco/4 vco/4 0101 vco/2 vco/8 vco/4 vco/8 0110 vco/2 vco/8 vco/8 vco/4 0111 vco/2 vco/8 vco/8 vco/8 1000 vco/4 vco/4 vco/4 vco/4 1001 vco/4 vco/4 vco/4 vco/8 1010 vco/4 vco/4 vco/8 vco/4 1011 vco/4 vco/4 vco/8 vco/8 1100 vco/4 vco/8 vco/4 vco/4 1101 vco/4 vco/8 vco/4 vco/8 1110 vco/4 vco/8 vco/8 vco/4 1111 vco/4 vco/8 vco/8 vco/8 table 1 pin configuration z9951 ref_sel pll_en tclk vss qa vddc qb vss pecl_clk# mr/oe# vddc qd4 vss qd3 vddc qd2 qc0 vddc qc1 vss qd0 vddc qd1 vss vdd fb_in sela selb selc seld vss pecl_clk 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 phase detector vco 200- 480mhz lpf 2/ 4 4/ 8 4/ 8 4/ 8 qa qb qc0 qc1 qd0 qd1 qd2 qd3 qd4 sela pll_en tclk ref_sel pecl_clk pecl_clk# fb_in selb selc mr/oe# power-on reset seld
3.3v, 180mhz, multi-output zero delay buffer cypress semiconductor corporation 525 los coches st. document#: 38-07084 rev. *a 06/18/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 2 of 8 http://www.cypress.com z9951 pin description pin name pwr i/o type description 8 pecl_clk i pu pecl input clock. 9 pecl_clk# i pecl input clock. 30 tclk i external test clock input. 28 qa vddc o clock output. see frequency table. 26 qb vddc o clock output. see frequency table. 22, 24 qc(1,0) vddc o clock outputs. see frequency table. 12, 14, 16, 18, 20 qd(4:0) vddc o clock outputs. see frequency table. 2 fb_in ipd feedback clock input. connect to an output for normal operation. 10 mr/oe# i master reset/output enable input. when asserted high, resets all of the internal flip-flops and also disables all of the outputs. when pulled low, releases the internal flip-flops from reset and enables all of the outputs. 31 pll_en i pll enable input. when asserted high, pll is enabled. and when set low, pll is bypassed. 32 ref_sel i reference select input. when high, tclk is the reference clock and when low, pecl clock is selected. 3, 4, 5, 6 sel(a:d) i frequency select inputs. see frequency table. if sel_ = 1, then qa divider = 4, qb:d divider = 8 if sel_ = 0, then qa divider = 2, qb:d divider = 4 11, 15, 19, 23, 27 vddc 3.3v power supply for output clock buffers. 1 vdd 3.3v power supply for pll 7, 13, 17, 21, 25, 29 vss common ground pd = internal pull-down, pu = internal pull-up.
3.3v, 180mhz, multi-output zero delay buffer cypress semiconductor corporation 525 los coches st. document#: 38-07084 rev. *a 06/18/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 3 of 8 http://www.cypress.com z9951 maximum ratings maximum input voltage relative to vss: vss - 0.3v maximum input voltage relative to vdd: vdd + 0.3v storage temperature: -65 c to + 150 c operating temperature: -40 c to +85 c maximum esd protection 2kv maximum power supply: 5.5v maximum input current: 20ma this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) 3.3v, 180mhz, multi-output zero delay buffer cypress semiconductor corporation 525 los coches st. document#: 38-07084 rev. *a 06/18/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 4 of 8 http://www.cypress.com z9951 ac parameters 1 symbol parameter min typ max units conditions tr / tf tclk input rise / fall 3.0 ns fref reference input frequency note 2 note 2 mhz frefdc reference input duty cycle 25 75 % fvco pll vco lock range 200 480 mhz tlock maximum pll lock time 10 ms tr / tf output clocks rise / fall time 4,5 0.10 1.0 ns 0.8v to 2.0v - 180 qa = ( 2) 120 qa/qb = ( 4) fout maximum output frequency 60 mhz qb = ( 8) foutdc output duty cycle 4,5 tcycle/2 ? 1 tcycle/2 + 1 ns tpzl, tpzh output enable time (all outputs) 6 ns tplz, tphz output disable time (all outputs) 7 ns tccj cycle to cycle jitter (peak to peak) 4,5 +/- 100 ps tclk to fb_in delay 3 50 250 400 ps tpd pecl_clk to fb_in delay 3 -950 -770 -600 ps fref = 50mhz, feedback = vco/8 tskew0 any output to any output skew 4,5 - 200 350 ps vdd = vddc = 3.3v +/- 5%, ta = -40 c to +85 c note 1: parameters are guaranteed by design and characterization. not 100% tested in production. note 2: maximum and minimum input reference is limited by the vco lock range. note 3: the tpd window is specified for a 50mhz input reference clock. the window will enlarge/reduce proportionally from the minimum limits with an increase/decrease of the input reference clock period. note 4: driving series or parallel terminator 50 ? (or 50 ? to vdd/2) transmission lines. note 5: outputs loaded with 30pf each
3.3v, 180mhz, multi-output zero delay buffer cypress semiconductor corporation 525 los coches st. document#: 38-07084 rev. *a 06/18/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 5 of 8 http://www.cypress.com z9951 description the z9951 has an integrated pll that provides low skew and low jitter clock outputs for high performance microprocessors. the pll is ensured stable operation given that the vco is configured to run between 200 mhz to 480 mhz. this allows a wide range of output frequencies from 25mhz to 180mhz. the phase detector compares the input reference clock to the external feedback input. for normal operation, the external feedback input, fb_in, is connected to one of the outputs. the internal vco is running at multiples of the input reference clock set by sel(a:d) select inputs, see table 2. the vco frequency is then divided down to provide the required output frequencies. the use of even dividers ensures that the output duty cycle remains at 50%. sela qa selb qb selc qc seld qd 0 2 0 4 0 4 0 4 1 4 1 8 1 8 1 8 table 2 zero delay buffer when used as a zero delay buffer the z9951 will likely be in a nested clock tree application. for these applications the z9951 offers a low voltage pecl clock input as a pll reference. this allows the user to use lvpecl as the primary clock distribution device to take advantage of its far superior skew performance. the z9951 then can lock onto the lvpecl reference and translate with near zero delay to low skew outputs. by using one of the outputs as a feedback to the pll the propagation delay through the device is eliminated. the pll works to align the output edge with the input reference edge thus producing a near zero delay. the reference frequency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. because the static phase offset is a function of the reference clock the tpd of the z9951 is a function of the configuration used.
3.3v, 180mhz, multi-output zero delay buffer cypress semiconductor corporation 525 los coches st. document#: 38-07084 rev. *a 06/18/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 6 of 8 http://www.cypress.com z9951 package drawing and dimensions 32 pin tqfp outline dimensions inches millimeters symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a2 0.037 - 0.041 0.95 - 1.05 d - 0.354 - - 9.00 - d 1 - 0.276 - - 7.00 - b 0.012 - 0.018 0.30 - 0.45 e 0.031 bsc 0.80 bsc l 0.018 - 0.030 0.45 - 0.75 d d 1 a 1 b e 12 a l
3.3v, 180mhz, multi-output zero delay buffer cypress semiconductor corporation 525 los coches st. document#: 38-07084 rev. *a 06/18/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 7 of 8 http://www.cypress.com z9951 ordering information part number package type production flow Z9951AA 32 pin tqfp industrial, -40 c to +85 c note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: cypress Z9951AA date code, lot # Z9951AA package a = tqfp revision device number notice cypress semiconductor corp. reserves the right to make changes to its products in order to improve design, performance or reliability. cypress semiconductor corp. assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by cypress semiconductor corp. for the use of its products in the life supporting and medical applications.
3.3v, 180mhz, multi-output zero delay buffer cypress semiconductor corporation 525 los coches st. document#: 38-07084 rev. *a 06/18/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 8 of 8 http://www.cypress.com z9951 document title: z9951 3.3v, 180 mhz, multi-output zero delay buffer document number: 38-07084 rev. ecn no. issue date orig. of change description of change ** 107120 06/12/01 ika convert from imi to cypress *a 108063 07/03/01 ndp changed commercial to industrial (see page 7) delete pull down in pin 9,10,30& 32; delete pull up in pin 3,4,5,6, & 31 (see page 2)
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