philips semiconductors pck857 50-150mhz differential 1:10 sdram clock driver product data supersedes data of 2000 jun 15 2003 jul 31 integrated circuits
philips semiconductors product data pck857 50-150 mhz differential 1:10 sdram clock driver 2 2003 jul 31 853-2199 23880 features optimized for clock distribution in ddr (double data rate) sdram applications 1-to-10 differential clock distribution very low skew ( < 100 ps) and jitter ( < 100 ps) 3 v av cc and 2.5 v v cc sstl_2 interface clock inputs and outputs cmos control signal input test mode enables buffers while disabling pll low current power-down mode ? tolerant of spread spectrum input clock ? full ddr solution provided when used with sstl16857 and cbt3857 description zero delay buffer to distribute an sstl differential clock input pair to 10 sstl_2 differential output pairs. outputs are slope controlled. external feedback pin for synchronization of the outputs to the input. a cmos style enable/disable pin is provided for low power disable. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 21 22 23 24 41 42 43 44 45 46 47 48 gnd y 0 y 0 v cc y 1 y 1 gnd y 2 gnd y 2 v cc v cc clk clk v cc av cc agnd gnd y 3 y 3 v cc y 4 y 4 gnd gnd y 5 y 5 v cc y 6 y 6 gnd gnd y 7 y 7 v cc g fbin fbin v cc fbout fbout gnd y 8 y 8 v cc y 9 y 9 sw00358 gnd ordering information packages temperature range order code drawing number 48-pin plastic tssop 0 to +85 c PCK857DGg sot362-1
philips semiconductors product data pck857 50-150 mhz differential 1:10 sdram clock driver 2003 jul 31 3 pin description pins symbol i/o description 17 agnd ground analog ground. agnd provides the ground reference for the analog circuitry. 16 av cc power analog power supply. av cc provides the power reference for the analog circuitry. in addition, av cc can be used to bypass the pll for test purposes. when av cc is strapped to ground, pll is bypassed and clk is buffered directly to the device outputs. during disable (g = 0), the pll is powered down. 13, 14 clk, clk i clock input. clk provides the clock signal to be distributed by the pck857 clock driver. clk is used to provide the reference signal to the integrated pll that generates the clock output signals. clk must have a fixed frequency and fixed phase for the pll to obtain phase lock. once the circuit is powered up and a valid clk is applied, a stabilization time is required for the pll to phase lock the feedback signal to its reference signal. 36, 35 fb in , fb in i feedback input. fb in provides the feedback signal to the internal pll. fb in must be hard-wired to fb out to complete the pll. the integrated pll synchronizes clk and fb in so that there is nominally zero phase error between clk and fb in . 32, 33 fb out , fb out o feedback output. fb out is dedicated for external feedback. it switches at the same frequency as clk. when externally wired to fb in , fb out completes the feedback loop of the pll. 37 g i output bank enable. g is the output enable for outputs y and y . when g is low outputs y are disabled to a high-impedance state. when g is high, all outputs y are enabled and switch at the same frequency as clk. 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 gnd ground ground 4, 11, 12, 15, 21, 28, 34, 38, 45 v cc power power supply 3, 5, 10, 20, 22, 46, 44, 39, 29, 27 y0, y1, y2, y3, y4, y5, y6, y7, y8, y9 o clock outputs. these outputs provide low-skew copies of clk. 2, 6, 9, 19, 23, 47, 43, 40, 30, 26 y0 , y1 , y2 , y3 , y4 , y5 , y6 , y7 , y8 , y9 o clock outputs. these outputs provide low-skew copies of clk . function table inputs outputs pll on/off g clk clk y y fbout fbout l l h z z z 1 z 1 off l h l z z z 1 z 1 off h l h l h l h on h h l h l h l on x 2 < 20 mhz < 20 mhz z z z 1 z 1 off notes: h = high voltage level l = low voltage level z = high impedance off-state x = don?t care 1. subject to change. may cause conflict with fbin pins. 2. additional feature that senses when the clock input is less than 20 mhz and places the part in sleep mode.
philips semiconductors product data pck857 50-150 mhz differential 1:10 sdram clock driver 2003 jul 31 4 block diagram pll g clk clk fb in fb in av cc y 0 y 0 y 1 y 1 y 2 y 2 y 3 y 3 y 4 y 4 y 5 y 5 y 6 y 6 y 7 y 7 y 8 y 8 y 9 y 9 fb out fb out sw00395 dc electrical characteristics over recommended operating conditions. voltages are referenced to gnd (ground = 0 v). limits symbol parameter test conditions min typ max unit v ik input voltage all input pins v cc = 2.3 v; i i = -18 ma -1.2 v v cc = min to max; i oh = -1 ma v cc -0.1 v oh high-level output voltage v cc = 2.3 v; i oh = -12 ma 1.7 v v cc = min to max; i ol = 1 ma 0.1 v ol low-level output voltage v cc = 2.3 v; i ol = 12 ma 0.6 v i oh high-level output current v cc = 2.3 v; v o = 1 v -18 -32 ma i ol low-level output current v cc = 2.3 v; v o = 1.2 v 26 35 ma g v cc = 2.7 v; v i = 0 v to 2.7 v 10 10 a i oz high-impedance output current v cc = 2.7 v; v o = v cc or gnd 10 a v oc output crossing point voltage (v cc /2)-0.1 v cc /2 (v cc /2)+0.1 v i ccz supply current, disabled av cc and v cc = max, g = l or no input clk signal 500 800 a i cc supply current on av cc v cc = 2.7 v, all outputs switching environment; f o = 167 mhz, 16 pf in 60 ? see figure 3 235 330 ma ai cc supply current on av cc av cc = 3.6 v; f o = 167 mhz 9 12 ma c i input capacitance v cc = 2.5 v;v i = v cc or gnd 2 pf c o output capacitance v cc = 2.5 v; v o = v cc or gnd 3 pf
philips semiconductors product data pck857 50-150 mhz differential 1:10 sdram clock driver 2003 jul 31 5 absolute maximum ratings 1,2 limits symbol parameter condition min max unit v cc /av cc supply voltage range -0.5 4.6 v v i input voltage note 2 -0.5 v ddq + 0.5 v v o output voltage note 2 -0.5 v ddq + 0.5 v i ik input diode current v i < o or v i > v cc 50 ma i ok output diode current v o < o or v o > v cc 50 ma i o output source or sink current v o = o to v cc 50 ma t stg storage temperature range -65 +150 c ja package thermal impedance note 3 89 c/w notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3. the package thermal impedance is calculated in accordance with jesd51. recommended operating conditions limits symbol parameter conditions min typ max unit v cc supply voltage 2.3 2.5 2.7 v av cc analog supply voltage 3.0 3.3 3.6 v v il g input 0.3 xv cc v v ih g input 0.7 xv cc v v i clk, fb in -0.3 v cc + 0.3 v i oh high-level output current -12 ma i ol low-level output current 12 ma timing requirements over recommended ranges or supply voltage and operating free-air temperature parameter conditions min max unit f c clock frequency 66 167 mhz input clock duty cycle 40% 60% stabilization time 1 100 s note: 1. time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal. for phase l ock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at clk. until phase lock is obtained, the specifications for pr opagation delay, skew, and jitter parameters given in the switching characteristics are not applicable. this parameter does not apply for input modulation under ssc application.
philips semiconductors product data pck857 50-150 mhz differential 1:10 sdram clock driver 2003 jul 31 6 ac characteristics gnd = 0 v; t r = t f 2.5 ns; c l = 50 pf; r l = 1 k ? limits symbol parameter waveform condition min typ max unit t plh 1 low to high propagation figure 4 clk to any output 1.5 3.5 6 ns t phl 1 high to low propagation figure 4 clk to any output 1.5 3.5 6 ns f phaserror phase error -150 0 150 ps f sk output clock skew figure 1 100 ps fdif sk differential clock skew 100 ps f sl output clock skew rate 1 1.5 v/ns jitter pp peak-to-peak jitter (long term) -100 100 ps jitter cc cycle-to-cycle jitter (short term) figure 3 > -100 < 100 ps f dc duty cycle figure 2 45 55 % c in input capacitance 2.5 4 pf t r , t f output rise and fall times 20%-80% 650 800 950 ps note: 1. refers to transition of reinverting output. 184/200-pin ddr sdram dimm sdram sdram sdram sdram sdram sdram sdram sdram sdram the pll clock distribution device and sstl registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation sw00393 cbt3857 (9) cbt cbt cbt cbt cbt cbt cbt cbt cbt sdram sdram sdram sdram sdram sdram sdram sdram sdram sstl16857 pck857 sstl16857 back side front side
philips semiconductors product data pck857 50-150 mhz differential 1:10 sdram clock driver 2003 jul 31 7 ac waveforms skew any two outputs sw00396 figure 1. skew between any two outputs. t 1 t 2 45% t 1 t 1 t 2 55% sw00397 figure 2. duty cycle limits and measurement t 1 t 2 |t 1 ? t 2 | 100ps sw00398 figure 3. jitter limit and measurement t pd sw00693 clk in yx or fb in figure 4. propagation delay time; t plh , t phl test circuit 60 ? 25pf v t v cc 2 sw00694 v t
philips semiconductors product data pck857 50-150 mhz differential 1:10 sdram clock driver 2003 jul 31 8 tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1
philips semiconductors product data pck857 50-150 mhz differential 1:10 sdram clock driver 2003 jul 31 9 revision history rev date description _3 20030731 product data (9397 750 11764); ecn 853-2199 30051 of 18 june 2003; supersedes data of 2000 june 15 (9397 750 07193). modifications: ? corrections and minor changes to existing product specifications. _2 20000715 product data (9397 750 07193); ecn 853-2199 23880 of 2000 june 15.
philips semiconductors product data pck857 50-150 mhz differential 1:10 sdram clock driver 2003 jul 31 10 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products ? including circuits, standard cells, and/or software ? described or contained herein in order to improve design and/or performance. when the product is in full production (status ? production ? ), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2003 all rights reserved. printed in u.s.a. p date of release: 07-03 document order number: 9397 750 11764 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii
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