View GS1560A_2030190.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: july 2003 document no. 27360 - 2 preliminary data sheet GS1560A key features ? smpte 292m and smpte 259m-c compliant descrambling and nrzi nrz decoding (with bypass) dvb-asi sync word detection and 8b/10b decoding auto-configuration for hd-sdi, sd-sdi and dvb-asi serial loop-through cable driver output selectable as reclocked or non-reclocked dual serial digital input buffers with 2 x 1 mux integrated serial digital signal termination integrated reclocker automatic or manual rate selection / indication (hd/sd) descrambler bypass option adjustable loop bandwidth user selectable additional processing features including: - crc, trs, anc data checksum, line number and edh crc error detection and correction - programmable anc data detection - illegal code remapping internal flywheel for noise immune h, v, f extraction fifo load pulse 20-bit / 10-bit cmos parallel output data bus 148.5mhz / 74.25mhz / 27mhz / 13.5mhz parallel digital output automatic standards detection and indication 1.8v core power supply and 3.3v charge pump power supply 3.3v digital i/o supply jtag test interface small footprint compatible with gs1561, gs1532, gs9060 and gs9062 applications ? smpte 292m serial digital interfaces smpte 259m-c serial digital interfaces dvb-asi serial digital interfaces description the GS1560A is a reclocking deserializer with a serial loop- through cable driver. when used in conjunction with the gs1524 automatic cable equalizer and the go1525 voltage controlled oscillator, a receive solution can be realized for hd-sdi, sd-sdi and dvb-asi applications. in addition to reclocking and deserializing the input data stream, the GS1560A performs nrzi-to-nrz decoding, descrambling as per smpte 292m/259m-c, and word alignment when operating in smpte mode. when operating in dvb-asi mode, the device will word align the data to k28.5 sync characters and 8b /10b decode the received stream. two serial digital input buffers are provided with a 2x1 multiplexer to allow the device to select from one of two serial digital input signals. the integrated reclocker feat ures a very wide input jitter tolerance of 0.3 ui (total 0.6 ui), a rapid asynchronous lock time, and full complian ce with dvb-asi data streams. a integrated cable driver is pr ovided for serial input loop- through applications and can be selected to output either buffered or reclocked data. this cable driver also features an output mute on loss of signal, high impedance mode, adjustable signal swing, and automatic dual slew-rate selection depending on hd/sd operational requirements. the GS1560A also includes a range of data processing functions such as error detection and correction, automatic standards detection, and edh support. the device can also detect and extract sm pte 325m payload identifier packets and independently identify the received video standard. this information is read from internal registers via the host interface port. line-based crc errors, line number errors, trs errors, edh crc errors and ancillary data checksum errors can all be detected. a single ?data_er ror? pin is provided which is a logical 'or'ing of all det ectable errors. individual error status is stored in internal ?error_status? registers. finally, the device can correct detected errors and insert new trs id words, line-based crc words, ancillary data checksum words, edh crc words, and line numbers. illegal code re-mapping is also available. all processing function may be individually enabled or disabled via host interface control. GS1560A hd-linx ? ii multi-rate deserializer with loop-through cable driver
gennum corporation 27360 - 2 2 of 55 GS1560A GS1560A functional block diagram ddi_1 term 1 term 2 ddi_1 ddi_2 ddi_2 reclocker sdo sdo sdo_en/dis rset s->p smpte de- scramble, word alignment and flywheel h v f dout[19:0] ip_sel carrier_detect rc_byp (o/p mute) pll_lock reset_trst asi_sync_det host interface / jtag test cs_tms sclk_tck sdin_tdi sdout_tdo fifo_ld data_error yanc canc reset jtag/host ioproc_en/dis crc check line mumber check trs check csum check anc data detection k28.5 sync detect, dvb-asi word alignment and 8b/10b decode crc correct line mumber correct trs correct csum correct edh check & correct illegal code re- map 20bit/10bit i/o buffer & mux fw_en/dis cp_cap dvb_asi pll_lock vco vco lf lb_cont vco_v cc vco_gnd sd/hd master/slave pclk locked lock detect cd1 cd2 smpte_bypass smpte_sync_det rclk_ctrl rclk_bypass
gennum corporation 27360 - 2 3 of 55 GS1560A table of contents 1. pin out .................................................................................................................... ...................... 5 1.1 pin assignment............................................................................................................ .... 5 1.2 pin descriptions .......................................................................................................... .... 6 2. electrical characteristics ................................................................................................. ....... 15 2.1 absolute maxiumum ratings ........................................................................................ 15 2.2 dc electrical characteristics...................................................................................... 16 2.3 ac electrical characteristics...................................................................................... 17 2.4 input/output circuits .................................................................................................. 19 2.5 host interface map....................................................................................................... 2 0 3. detailed description ....................................................................................................... ............ 23 3.1 functional overview .................................................................................................... 23 3.2 serial digital input ...................................................................................................... .23 3.2.1 input signal selection .................................................................................................. ..............................23 3.2.2 carrier detect input.................................................................................................... ................................23 3.2.3 single input configuration .............................................................................................. ........................23 3.3 serial digital reclocker ............................................................................................... 23 3.3.1 external vco............................................................................................................ .......................................24 3.3.2 loop bandwidth .......................................................................................................... ...................................24 3.4 serial digital loop-through output ............................................................................. 24 3.4.1 output swing ............................................................................................................ ......................................24 3.4.2 reclocker bypass control................................................................................................ .......................24 3.4.3 serial digital output mute .............................................................................................. ..........................24 3.5 serial-to-parallel conversion...................................................................................... 25 3.6 modes of operation ...................................................................................................... 25 3.6.1 lock detect............................................................................................................. ........................................25 3.6.2 master mode ............................................................................................................. ......................................26 3.6.3 slave mode.............................................................................................................. .........................................26 3.7 smpte functionality ..................................................................................................... 27 3.7.1 smpte descrambling and word alignment ................................................................................... .......27 3.7.2 internal flywheel....................................................................................................... ..................................27 3.7.3 switch line lock handling ............................................................................................... .........................27 3.7.4 hvf timing signal generation ............................................................................................ .......................30 3.8 dvb-asi functionality .................................................................................................... 3 2 3.8.1 dvb-asi 8b/10b decoding and word alignment .............................................................................. ......32 3.8.2 status signal outputs ................................................................................................... .............................32 3.9 data through mode ...................................................................................................... 32 3.10 additional processing functions ............................................................................... 33 3.10.1 fifo load pulse ........................................................................................................ ....................................33 3.10.2 ancillary data detection and indication ................................................................................ ..........34 3.10.3 smpte 352m payload identifier .......................................................................................... ......................36 3.10.4 automatic video standard and data format detection...............................................................36 3.10.5 error detection and indication......................................................................................... ...................39 3.10.6 error correction and insertion ......................................................................................... .................43 3.10.7 edh flag detection..................................................................................................... ................................45 3.11 parallel data outputs ............................................................................................... 46 3.11.1 parallel data bus buffers .............................................................................................. ........................46 3.11.2 parallel output in smpte mode.......................................................................................... ....................47 3.11.3 parallel output in dvb-asi mode ........................................................................................ ...................47 3.11.4 parallel output in data-through mode................................................................................... ..........47 3.11.5 parallel output clock (pclk) ........................................................................................... .....................47
gennum corporation 27360 - 2 4 of 55 GS1560A 3.12 gspi host interface ..................................................................................................... 4 9 3.12.1 command word description............................................................................................... .....................49 3.12.2 data read and write timing ............................................................................................. ........................50 3.12.3 configuration and status registers ..................................................................................... .............50 3.13 jtag ..................................................................................................................... ........ 51 3.14 device power up.......................................................................................................... 51 3.15 device reset............................................................................................................. .... 51 4. application reference design ............................................................................................... ..... 52 4.1 typical application circuit (part a).............................................................................. 52 4.2 typical application circuit (part b).............................................................................. 53 5. references & relevant standards ............................................................................................ 54 6. package & ordering information............................................................................................. .. 54 6.1 package dimensions ...................................................................................................... 54 6.2 ordering information................................................................................................... 55 7. revision history ........................................................................................................... ............... 55
gennum corporation 27360 - 2 5 of 55 GS1560A 1. pin out 1.1 pin assignment
gennum corporation 27360 - 2 6 of 55 GS1560A 1.2 pin descriptions pin number name timing type description 1 cp_vdd - power power supply connection for the charge pump. connect to +3.3v dc analog. 2 pdbuff_gnd - power ground connection for the phase detector and serial digital input buffers. connect to analog gnd. 3 pd_vdd - power power supply connection for the phase detector. connect to +1.8v dc analog. 4 buff_vdd - power power supply connection for the serial digital input buffers. connect to +1.8v dc analog. 5cd1 non synchronous input status signal input signal levels are lvcmos/lvttl compatible. used to indicate the presence of a seri al digital input signal. normally generated by a gennum automatic cable equalizer. when low, the serial digital input si gnal received at the ddi1 and ddi1 pins is considered valid. when high, the associated serial digita l input signal is considered to be invalid. in this case, the locked sig nal is set low and all parallel outputs are muted. 6,8 ddi1, ddi1 analog input differential input pair for serial digital input 1. 7 term1 analog input termination for serial digital input 1. ac couple to pdbuff_gnd. 9 dvb_asi non synchronous input / output control signal input / status signal output signal levels are lvcmos/lvttl compatible. this pin will be an input set by the ap plication layer in slave mode, and will be an output set by the device in master mode. master mode (master/slave = high) the dvb_asi signal will be high only when the device has locked to a dvb-asi compliant data stream. it will be low otherwise. slave mode (master/slave = low) when set high in conjunction with sd/hd = high and smpte_bypass = low, the device will be configured to operate in dvb-asi mode. when set low, the device will not support the decoding or word alignment of received dvb-asi data. 10 ip_sel non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select ddi1 / ddi1 or ddi2 / ddi2 as the serial digital input signal, and cd1 or cd2 as the carrier detect input signal. when set high, ddi1 / ddi1 is selected as the serial digital input and cd1 is selected as the carrier detect input signal. when set low, ddi2 / ddi2 serial digital input and cd2 carrier detect input signal is selected.
gennum corporation 27360 - 2 7 of 55 GS1560A 11 sd/hd non synchronous input / output control signal input / status signal output signal levels are lvcmos/lvttl compatible. this pin will be an input set by the ap plication layer in slave mode, and will be an output set by the device in master mode. master mode (master/slave = high) the sd/hd signal will be low whenever the received serial digital signal is 1.485gb/s or 1.485/1.001gb/s. the sd/hd signal will be high whenever t he received serial digital signal is 270mb/s. slave mode (master/slave = low) when set low, the device will be configured for the reception of 1.485gb/s or 1.485/1.001gb/s signals only and will not lock to any other serial digital signal. when set high, the device will be configured for the reception of 270mb/s signals only and will not lock to any other serial digital signal. 12 20bit/10bit non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select the output data bus width in smpte or data-through modes. this signal is ignored in dvb-asi mode. when set high, the parallel output will be 20-bit demultiplexed data. when set low, the parallel outputs will be 10-bit multiplexed data. 13 ioproc_en/dis non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable i/o processing features. when set high, the following i/o processing features of the device are enabled: edh crc error correction (sd-only) anc data checksum correction line-based crc error correction (hd-only) line number error correction (hd-only) trs error correction illegal code remapping to enable a subset of these features, keep ioproc_en/dis high and disable the individual feature(s) in the ioproc_disable register accesible via the host interface. when set low, the i/o processing f eatures of the device are disabled, regardless of whether the features are enabled in the ioproc_disable register. 14 cd2 non synchronous input status signal input signal levels are lvcmos/lvttl compatible. used to indicate the presence of a seri al digital input signal. normally generated by a gennum automatic cable equalizer. when low, the serial digital input si gnal received at the ddi2 and ddi2 pins is considered valid. when high, the associated serial digita l input signal is considered to be invalid. in this case, the locked sig nal is set low and all parallel outputs are muted. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 27360 - 2 8 of 55 GS1560A 15,17 ddi_2, ddi_2 analog input differential input pair for serial digital input 2. 16 term2 analog input termination for serial digital input 2. ac couple to pdbuff_gnd. 18 smpte_bypass non synchronous input / output control signal input / status signal output signal levels are lvcmos/lvttl compatible. this pin will be an input set by the ap plication layer in slave mode, and will be an output set by the device in master mode. master mode (master/slave = high) the smpte_bypass signal will be high only when the device has locked to a smpte compliant data stream. it will be low otherwise. slave mode (master/slave = low) when set high in conjunction with dvb_asi = low, the device will be configured to operate in smpte mode. all i/o processing features may be enabled in this mode. when set low, the device will not support the descrambling, decoding or word alignment of received smpte data . no i/o processing features will be available. 19 rset analog input used to set the serial digital loop-through output signal amplitude. connect to cd_vdd through 281 ? +/- 1% for 800mv p-p single-ended output swing. 20 cd_vdd - power power supply connection for t he serial digital cable driver. connect to +1.8v dc analog. 21 sdo_en/dis non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable the seri al digital output loop-through stage. when set low, the serial digital output signals sdo and sdo are disabled and become high impedance. when set high, the serial digital output signals sdo and sdo are enabled. 22 cd_gnd - power ground connection for the serial digital cable driver. connect to analog gnd. 23, 24 sdo, sdo analog output serial digital loop-through output signal operating at 1.485gb/s, 1.485/1.001gb/s, or 270mb/s. the slew rate of these outputs is aut omatically controlled to meet smpte 292m and 259m specifications according to the setting of the sd/hd pin. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 27360 - 2 9 of 55 GS1560A 25 reset_trst non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to reset the internal operating conditions to default settings and to reset the jtag test sequence. host mode (jtag/host = low) when asserted low, all functional blocks will be set to default conditions and all input and output signals become high impedance, including the serial digital outputs sdo and sdo. must be set high for normal device operation. jtag test mode (jtag/host = high) when asserted low, all functional blocks will be set to default and the jtag test sequence will be held in reset. when set high, normal operation of the jtag test sequence resumes. 26 jtag/host non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to select jtag test mode or host interface mode. when set high, cs _tms, sdout_tdo, sdi_tdi and sclk_tck are configured for jtag boundary scan testing. when set low, cs _tms, sdout_tdo, sdi_tdi and sclk_tck are configured as gspi pins for normal host interface operation. 27 cs _tms synchronous with sclk_tck input control signal input signal levels are lvcmos/lvttl compatible. chip select / test mode select host mode (jtag/host = low) cs _tms operates as the host interface chip select, cs , and is active low. jtag test mode (jtag/host = high) cs _tms operates as the jtag test mo de select, tms, and is active high. 28 sdout_tdo synchronous with sclk_tck output control signal output signal levels are lvcmos/lvttl compatible. serial data output / test data output host mode (jtag/host = low) sdout_tdo operates as the host interf ace serial output, sdout, used to read status and configuration informati on from the internal registers of the device. jtag test mode (jtag/host = high) sdout_tdo operates as the jtag test data output, tdo. 29 sdin_tdi synchronous with sclk_tck input control signal input signal levels are lvcmos/lvttl compatible. serial data in / test data input host mode (jtag/host = low) sdin_tdi operates as the host interface serial input, sdin, used to write address and configuration information to the internal registers of the device. jtag test mode (jtag/host = high) sdin_tdi operates as the jtag test data input, tdi. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 27360 - 2 10 of 55 GS1560A 30 sclk_tck non synchronous input control signal input signal levels are lvcmos/lvttl compatible. serial data clock / test clock. host mode (jtag/host = low) sclk_tck operates as the host interface burst clock, sclk. command and data read/write words are clocke d into the device synchronously with this clock. jtag test mode (jtag/host = high) sclk_tck operates as the jtag test clock, tck. 31 data_error synchronous with pclk output status signal output signal levels are lvcmos/lvttl compatible. the data_error signal will be low when an error within the received data stream has been detected by the device. this pin is a logical 'or'ing of all detectable errors listed in the internal error_status register. once an error is detected, data_error will remain low until the start of the next video frame / field, or until t he error_status register is read via the host interface. the data_error signal will be high when the received data stream has been detected without error. note: it is possible to program which error conditions are monitored by the device by setting appropriate bits of the error_mask register high. all error conditions are detected by default. 32 fifo_ld synchronous with pclk output control signal output signal levels are lvcmos/lvttl compatible. used as a control signal for external fifo(s). normally high but will go lo w for one pclk period at sav. 33, 68 core_gnd - power ground connection for the di gital core logic. connect to digital gnd. 34 f synchronous with pclk output status signal output signal levels are lvcmos/lvttl compatible. used to indicate the odd / even field of the video signal. the f signal will be high for the entire period of field 2 as indicated by the f bit in the received trs signals. the f signal will be low for all lines in field 1 and for all lines in progressive scan systems. 35 v synchronous with pclk output status signal output signal levels are lvcmos/lvttl compatible. used to indicate the portion of the video field / frame that is used for vertical blanking. the v signal will be high for the entire vertical blanking period as indicated by the v bit in the received trs signals. the v signal will be low for all lines outside of the vertical blanking interval. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 27360 - 2 11 of 55 GS1560A 36 h synchronous with pclk output status signal output signal levels are lvcmos/lvttl compatible. used to indicate the portion of the video line containing active video data. h signal timing is configurable via the h_config bit of the ioproc_disable register accessible via the host interface. active line blanking (h_config = 0 h ) the h signal will be high for the entire horizontal blanking period, including the eav and sav trs word s, and low otherwise. this is the default setting. trs based blanking (h_config = 1 h ) the h signal will be high for the ent ire horizontal blanking period as indicated by the h bit in the receive d trs id words, and low otherwise. 37, 64 core_vdd - power power supply connection for the digital core logic. connect to +1.8v dc digital. 38, 39, 42?48, 50 dout[0:9] synchronous with pclk output parallel data bus signal levels are lvcmos/lvttl compatible. dout9 is the msb and dout0 is the lsb. hd 20-bit mode sd/hd = low 20bit/10bit = high chroma data output in smpte mode smpte_bypass =high dvb_asi = low data output in data-through mode smpte_bypass = low dvb_asi = low hd 10-bit mode sd/hd = low 20bit/10bit = low forced low in all modes. sd 20-bit mode sd/hd = high 20bit/10bit = high chroma data output in smpte mode smpte_bypass = high dvb_asi = low data output in data-through mode smpte_bypass = low dvb_asi = low forced low in dvb-asi mode smpte_bypass = low dvb_asi = high sd 10-bit mode sd/hd = high 20bit/10bit = low forced low in all modes. 40, 49, 60 io_gnd - power ground connection for digi tal i/o buffers. connect to digital gnd. 41, 53, 61 io_vdd - power power supply connection for digital i/o buffers. connect to +3.3v dc digital. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 27360 - 2 12 of 55 GS1560A 51, 52, 54?59, 62, 63 dout[10:19] synchronous with pclk output parallel data bus signal levels are lvcmos/lvttl compatible. dout19 is the msb and dout10 is the lsb. hd 20-bit mode sd/hd = low 20bit/10bit = high luma data output in smpte mode smpte_bypass = high dvb_asi = low data output in data-through mode smpte_bypass = low dvb_asi = low hd 10-bit mode sd/hd = low 20bit/10bit = low multiplexed luma and chroma data output in smpte mode smpte_bypass = high dvb_asi = low data output in data-through mode smpte_bypass = low dvb_asi = low sd 20-bit mode sd/hd = high 20bit/10bit = high luma data output in smpte mode smpte_bypass = high dvb_asi = low data output in data-through mode smpte_bypass = low dvb_asi = low dvb-asi data in dvb-asi mode smpte_bypass = low dvb_asi = high sd 10-bit mode sd/hd = high 20bit/10bit = low multiplexed luma and chroma data output in smpte mode smpte_bypass = high dvb_asi = low data input in data through mode smpte_bypass = low dvb_asi = low dvb-asi data in dvb-asi mode smpte_bypass = low dvb_asi = high 65 yanc synchronous with pclk output status signal output signal levels are lvcmos/lvttl compatible. used to indicate the presence of ancillary data in the video stream. hd mode (sd/hd = low) the yanc signal will be high when the device has detected vanc or hanc data in the luma video stream and low otherwise. sd mode (sd/hd = low) for 20-bit demultiplexed data (20bit/10bit = high), the yanc signal will be high when vanc or hanc data is detected in the luma video stream and low otherwise. for 10-bit multiplexed data (20bit/10bit = low), the yanc signal will be high when vanc or hanc data is detected anywhere in the data stream and low otherwise. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 27360 - 2 13 of 55 GS1560A 66 canc synchronous with pclk output status signal output signal levels are lvcmos/lvttl compatible. used to indicate the presence of ancillary data in the video stream. hd mode (sd/hd = low) the canc signal will be high when the device has detected vanc or hanc data in the chroma video stream and low otherwise. sd mode (sd/hd = low) for 20-bit demultiplexed data (20bit/10bit = high), the canc signal will be high when vanc or hanc data is detected in the chroma video stream and low otherwise. for 10-bit multiplexed data (20bit/10bit = low), the canc signal will be high when vanc or hanc data is detected anywhere in the data stream and low otherwise. 67 fw_en/dis non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to enable or disable the noise immune flywheel of the device. when set high, the internal flywheel is enabled. this flywhe el is used in the extraction and generation of trs ti ming signals, in automatic video standards detection, and in manual switch line lock handling. when set low, the internal flywheel is disabled and trs correction and insertion is unavailable. 69 pclk - output parallel data bus clock signal levels are lvcmos/lvttl compatible. hd 20-bit mode pclk = 74.25mhz or 74.25/1.001mhz hd 10-bit mode pclk = 148.5mhz or 148.5/1.001mhz sd 20-bit mode pclk = 13.5mhz sd 10-bit mode pclk = 27mhz 70 rc_byp non synchronous input /output control signal input / status signal output signal levels are lvcmos/lvttl compatible. this pin will be an input set by the ap plication layer in slave mode, and will be an output set by the device in master mode. master mode (master/slave = high) the rc_byp signal will be high only when the device has successfully locked to a smpte or dvb-asi compliant input data stream. in this case, the serial digital loop-through output will be a reclocked version of the input. the rc_byp signal will be low whenever the input does not conform to a smpte or dvb-asi compliant data stream . in this case, the serial digital loop-through output will be a buffered version of the input. slave mode (master/slave = low) when set high, the serial digital output will be a reclocked version of the input signal regardless of whether the device is in smpte, dvb-asi or data-through mode. when set low, the serial digital output will be a buffered version of the input signal in all modes. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 27360 - 2 14 of 55 GS1560A 71 master/slave non synchronous input control signal input signal levels are lvcmos/lvttl compatible. used to determine the input / output selection for the dvb_asi, sd/hd , rc_byp and smpte_bypass pins. when set high, the GS1560A is set to operate in master mode where dvb_asi, sd/hd , rc_byp and smpte_bypass become status signal output pins set by the device. in this mode, the GS1560A will automatically detect, reclock, dese rialize and process sd smpte, hd smpte, or dvb-asi input data. when set low, the GS1560A is set to operate in slave mode where dvb_asi, sd/hd , rc_byp and smpte_bypass become control signal input pins. in this mode, the applic ation layer must set these external device pins for the correct reception of either smpte or dvb-asi data. slave mode also supports the reclock ing and deserializing of data not conforming to smpte or dvb-asi streams. 72 locked synchronous with pclk output status signal output signal levels are lvcmos / lvttl compatible. the locked signal will be high whenever the device has correctly received and locked to smpte compliant data in smpte mode or dvb- asi compliant data in dvb-asi mode, or when the reclocker has achieved lock in data-through mode. it will be low otherwise. 73, 74 vco, vco analog input differential inputs for the external vco reference signal. for single ended devices such as the go1525, vco should be ac coupled to vco_gnd. vco is nominally 1.485ghz. 75 vco_gnd - output power ground reference for the external voltage controlled oscillator. connect to pins 2, 4, 6, and 8 of the go1525. this pin is an output. should be isolated from all other grounds. 76 vco_vcc - output power power supply for the external voltag e controlled oscillator. connect to pin 5 of the go1525. this pin is an output. should be isolated from all other power supplies. 77 lf analog output control voltage to external vo ltage controlled oscillator. nominally +1.25v dc. 78 cp_cap analog input pll lock time constant capacitor connection. normally connected to vco_gnd through 2.2nf. 79 lb_cont analog input control voltage to set the loop bandwidth of the integrated reclocker. normally connected to vco_gnd through 40k ? . 80 cp_gnd - power ground connection for the charge pump. connect to analog gnd. 1.2 pin descriptions (continued) pin number name timing type description
gennum corporation 27360 - 2 15 of 55 GS1560A 2. electrical characteristics figure 1 reflow solder profile 2.1 absolute maxiumum ratings parameter value/units supply voltage core -0.3v to +2.1v supply voltage i/o -0.3v to +4.6v input voltage range (any input) -2.0v to + 5.25v ambient operating temperature -20c < t a < 85c storage temperature -40c < t stg < 125c lead temperature (soldering, 10 sec) 230c notes: 1. see reflow solder profile 25?c 100?c 150?c 183?c 230?c 220?c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3?c/sec max 6?c/sec max
gennum corporation 27360 - 2 16 of 55 GS1560A 2.2 dc electrical characteristics t a = 0c to 70c, unless otherwise specified. parameter symbol conditions min typ max units test level notes system operation temperature range t a 0-70c- 1 function temperature range -25 - 85 c - 2 digital core supply voltage core_vdd 1.65 1.8 1.95 v 1 1 digital i/o supply voltage io_vdd 3.0 3.3 3.6 v charge pump supply voltage cp_vdd 3.0 3.3 3.6 v phase detector supply voltage pd_vdd 1.65 1.8 1.95 v input buffer supply voltage buff_vdd 1.65 1.8 1.95 v cable driver supply voltage cd_vdd 1.71 1.8 1.89 v external vco supply voltage output vco_vcc 2.25 2.50 2.75 v 1 - +1.8v supply current i 1v8 - - 245 ma 7 6 +3.3v supply current i 3v3 --55ma7 - total device power p d - - 625 mw 7 6 esd protection on all pins - 1 - - kv - 3 digital i/o input logic low v il -- 0.8v1 - input logic high v ih 2.1 - - v 1 - output logic low v ol -0.20.4v 1 - output logic high v oh io_vdd - 0.4 -- v 1 - input input common mode voltage v cmin -1.45- v 6 4 rset voltage v rset rset=281 ? 0.54 0.6 0.66 v 1 5 output output common mode voltage v cmout 75 ? load, rset=281 ?, sd and hd 0.8 1.0 1.2 v 1 - test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing desi gn/characterization data of similar product. 9. indirect test. notes 1. all dc and ac electrical parameters within specification. 2. guaranteed functional. 3. mil std 883 esd protection will be applied to all pins on the device. 4. input common mode is set by internal biasing resistors. 5. set by the value of the rset resistor. 6. loop-through enabled.
gennum corporation 27360 - 2 17 of 55 GS1560A 2.3 ac electrical characteristics t a = 0c to 70c, unless otherwise shown parameter symbol conditions min typ max units test level notes system serial digital input jitter tolerance ijt nominal loop bandwidth 0.6 - - ui 1 1 master mode asynchronous lock time no data to hd - - 468 us 6,7 2 hd to sd - - 260 hd to dvb-asi - - 135 no data to sd - - 340 sd to hd - - 256 sd to dvb-asi - - 173 no data to dvb-asi - - 65 dvb-asi to sd - - 227 dvb-asi to hd - - 215 slave mode asynchronous lock time no data to hd - - 240 us 6,7 2 no data to sd - - 197 no data to dvb-asi - - 68 device latency 10-bit sd - 21 - pclk 6 - 20-bit hd - 21 - pclk 6 - dvb-asi - 11 - pclk 6 - reset pulse width t reset 1- -ms76 serial digital differential input serial input data rate dr ddi - 1.485, 1.485/1.001, 270 -gb/s gb/s mb/s 1- serial digital input signal swing ? v ddi differential with internal 100 ? input termination 200 600 1000 mv p-p 1- serial digital output serial output data rate dr sdo - 1.485, 1.485/1.001, 270 -gb/s gb/s mb/s 1- serial output swing ? v sdo rset = 281 ? load = 75 ? - 800 - mvp-p 1 - serial output risetime 20% ~ 80% tr sdo orl compensation using recommended circuit ? hd signal - 200 260 ps 1 - orl compensation using recommended circuit ? sd signal 400 550 1500 ps
gennum corporation 27360 - 2 18 of 55 GS1560A serial output fall time 20% ~ 80% tf sdo orl compensation using recommended circuit ? hd signal - 235 260 ps 1 - orl compensation using recommended circuit ? sd signal 400 550 1500 ps serial output intrinsic jitter t ij pseudorandom and pathological hd signal - 90 125 ps 1 3 pseudorandom and pathological sd signal - 270 350 ps serial output duty cycle distortion dcd sdo hd (1.485gb/s) - 10 - ps 1 4 sd (270mb/s) - 20 - ps parallel output parallel clock frequency f pclk 13.5 - 148.5 mhz 1 parallel clock duty cycle dc pclk 40 50 60 % 1 output data hold time t oh 20-bit hd 1.0 - - ns 1 5 10-bit sd 19.5 - - ns output data delay time t od 20-bit hd - - 4.5 ns 1 5 10-bit sd - - 22.8 ns output data rise/fall time tr/tf - - 1.5 ns 3 5 gspi gspi input clock frequency f sclk --6.6mhz1- gspi input clock duty cycle dc sclk 40 50 60 % 3 - gspi input data setup time 0 - - ns 3 - gspi input data hold time - - 1.43 ns 3 - gspi output data hold time 2.10 - - ns 3 - gspi output data delay time - - 7.27 ns 3 - test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1, 2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product. 9. indirect test. notes 1. 6mhz sinewave modulation. 2. hd = 1080i, sd = 525i 3. serial digital output reclocked ( rc_byp = high). 4. serial duty cycle distortion is defined here to be the difference between the width of a ?1? bit, and the width of a ?0? bit. 5. with 15pf load. 6. see section 3.15, figure 22. 2.3 ac electrical characteristics (continued) t a = 0c to 70c, unless otherwise shown parameter symbol conditions min typ max units test level notes
gennum corporation 27360 - 2 19 of 55 GS1560A 2.4 input/output circuits all resistors in ohms, all capacitors in farads, unless otherwise shown. figure 2 serial digital input figure 3 vco input figure 4 pll loop bandwidth control figure 5 serial digital output figure 6 vco control output & pll lock time capacitor vdd 50 50 ddi ddi 45k 150k vdd 25 25 vco vco 1.5k 5k 800mv 8k lb_cont sdo sdo 300 cp_cap lf
gennum corporation 27360 - 2 20 of 55 GS1560A 2.5 host interface map register name a ddress 15 14 13 12 11 10 9876543210 error_mask 026h not used not used not used not used not used vd_std_ err_ mask ff_crc_ err_ mask ap_crc_ err_ mask lock_ err_ mask ccs_err_ mask ycs_err_ mask ccrc_ err_ mask ycrc_ err_ mask lnum_er r_mask sav_err_ mask eav_err_ mask ff_line_end_f1 025h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f1 024h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_end_f0 023h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f0 022h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f1 021h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f1 020h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f0 019h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f0 018h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 raster_structure4 017h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 raster_structure3 016h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 raster_structure2 015h not used not used not used not used b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 raster_structure1 014h not used not used not used not used b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 video_format_out_b 013h vfo4-b7 vfo 4-b6 vfo4-b5 vfo4-b4 vfo4-b3 vfo4-b2 vfo4-b1 vfo4-b0 vfo3-b7 vfo3-b6 vfo3 -b5 vfo3-b4 vfo3-b3 vfo3-b2 vfo3-b1 vfo3-b0 video_format_out_a 012h vfo2-b7 vfo 2-b6 vfo2-b5 vfo2-b4 vfo2-b3 vfo2-b2 vfo2-b1 vfo2-b0 vfo1-b7 vfo1-b6 vfo1 -b5 vfo1-b4 vfo1-b3 vfo1-b2 vfo1-b1 vfo1-b0 011h 010h anc_type5 009hb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type4 008hb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type3 007hb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type2 006hb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type1 005hb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 video_standard 004h not used vds-b4 vds-b3 vds-b2 vds-b1 vds-b0 int_prog std_ lock cdf-b3 cdf-b2 cdf-b1 cdf-b0 ydf-b3 ydf-b2 ydf-b1 ydf-b0 edh_flag 003h not used anc-ues anc-ida anc-idh anc-eda anc-edh ff-ues ff-ida ff-idh ff-eda ff-edh ap-ues ap-ida ap-idh ap-eda ap-edh 002h error_status 001h not used not used not used not used not used vd_std_ err ff_crc_ err ap_crc_ err lock_ err ccs_err ycs_err ccrc_ err ycrc_ err lnum_er r sav_err eav_err ioproc_disable 000h not used not used not used not used not used not used not used h_confi g not used not used illegal_ remap edh_crc _ins anc_ csum_ins crc_ins lnum_ ins trs_ins
gennum corporation 27360 - 2 21 of 55 GS1560A 2.5.1 host interface map (r/w only registers) register name a ddress 15 14 13 12 11 10 9876543210 error_mask 026h vd_std_ err_ mask ff_crc_ err_ mask ap_crc_ err_ mask lock_ err_ mask ccs_err_ mask ycs_err_ mask ccrc_ err_ mask ycrc_ err_ mask lnum_er r_mask sav_err_ mask eav_err_ mask ff_line_end_f1 025h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f1 024h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_end_f0 023h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ff_line_start_f0 022h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f1 021h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f1 020h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_end_f0 019h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 ap_line_start_f0 018h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 017h 016h 015h 014h 013h 012h 011h 010h anc_type5 009hb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type4 008hb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type3 007hb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type2 006hb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type1 005hb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 004h 003h 002h 001h ioproc_disable 000h h_confi g illegal_ remap edh_crc _ins anc_ csum_ins crc_ins lnum_ ins trs_ins
gennum corporation 27360 - 2 22 of 55 GS1560A 2.5.2 host interface map (read only registers) register name a ddress 15 14 13 12 11 10 9876543210 026h 025h 024h 023h 022h 021h 020h 019h 018h raster_structure4 017h b10b9b8b7b6b5b4b3b2b1b0 raster_structure3 016h b10b9b8b7b6b5b4b3b2b1b0 raster_structure2 015h b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 raster_structure1 014h b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 video_format_out_b 013h vfo4-b7 vfo 4-b6 vfo4-b5 vfo4-b4 vfo4-b3 vfo4-b2 vfo4-b1 vfo4-b0 vfo3-b7 vfo3-b6 vfo3 -b5 vfo3-b4 vfo3-b3 vfo3-b2 vfo3-b1 vfo3-b0 video_format_out_a 012h vfo2-b7 vfo 2-b6 vfo2-b5 vfo2-b4 vfo2-b3 vfo2-b2 vfo2-b1 vfo2-b0 vfo1-b7 vfo1-b6 vfo1 -b5 vfo1-b4 vfo1-b3 vfo1-b2 vfo1-b1 vfo1-b0 011h 010h 009h 008h 007h 006h 005h video_standard 004h vds-b4 vds-b3 vds-b2 vds-b1 vds-b0 int_prog std_ lock cdf-b3 cdf-b2 cdf-b1 cdf-b0 ydf-b3 ydf-b2 ydf-b1 ydf-b0 edh_flag 003h anc-ues anc-ida anc-idh anc-eda anc-edh ff-ues ff-ida ff-idh ff-eda ff-edh ap-ues ap-ida ap-idh ap-eda ap-edh 002h error_status 001h vd_std_ err ff_crc_ err ap_crc_ err lock_ err ccs_err ycs_err ccrc_ err ycrc_ err lnum_er r sav_err eav_err 000h
gennum corporation 27360 - 2 23 of 55 GS1560A 3. detailed description 3.1 functional overview the GS1560A is a multi-rate reclocking deserializer with an integrated serial digital loop -through output. when used in conjunction with the multi-rate gs1524 adaptive cable equalizer and the external go1525 voltage controlled oscillator, a receive solution at 1.485gb/s, 1. 485/1.001gb/s or 270mb/s is realized. the device has two basic modes of operation which determine preceisely how smpte or dvb-asi compliant input data streams are reclocked and processed. in master mode, (master/slave = high), the GS1560A will automatically detect, reclock, deserialize and process sd smpte 259m-c, hd smpte 292m, or dvb-asi input data. in slave mode, (master/slave = low), the application layer must set external device pins for the correct reception of either smpte or dvb-asi data. slave mode also supports the reclocking and deserializing of data not conforming to smpte or dvb-asi streams. the provided serial loop-through outputs may be selected as either buffered or reclocked versions of the input signal and feature a high impedance mode, output mute on loss of signal and adjustable signal swing. in the digital signal pro cessing core, several data processing functions are implemented including error detection and correction and automatic video standards detection. these features ar e all enabled by default, but may be individually disabl ed via internal registers accessible through the gspi host interface. finally, the GS1560A contains a jtag interface for boundary scan test implementations. 3.2 serial digital input the GS1560A contains two current mode differential serial digital input buffers, allowing the device to be connected to two smpte 259m-c or 292m compliant input signals. both input buffers have internal 50 ? termination resistors which are connected to groun d via the term1 and term2 pins. the input common mode level is set by internal biasing resistors such that the serial digital input signals must be ac coupled into the device. gennum recommends using a capacitor value of 4.7uf to accommodate pathological signals. the input buffers use a separate power supply of +1.8v dc supplied via the buff_vdd and pdbuff_gnd pins. 3.2.1 input signal selection a 2x1 input multiplexer is prov ided to allow the application layer to select between the two serial digital input streams using a single external pin. when ip_sel is set high, serial digital input 1 (ddi1 / ddi1 ) is selected as the input to the GS1560A's reclocker stage. when ip_sel is set low, serial digital input 2 (ddi2 / ddi2 ) is selected. 3.2.2 carrier detect input for each of the differential inputs, an associated carrier detect input signal is included, (cd1 and cd2 ). these signals are generated by ge nnum's family of automatic cable equalizers. when low, cdx indicates that a valid serial digital data stream is being delivered to the GS1560A by the equalizer. when high, the serial digital input to the device should be considered invalid. if no equalizer preceeds the device, the application layer should set cd1 and cd2 accordingly. note: if the gs1524 automati c cable equalizer is used, the mute/cd output signal from that device must be translated to ttl levels be fore passing to the GS1560A cdx inputs. see section 4.1 fo r a recommended transistor network that will set the correct voltage levels. a 2x1 input multiplexer is also provided for these signals. the internal carrier_detect signal is determined by the setting of the ip_sel pin and is used by the lock detect block of the GS1560A to determine the lock status of the device, (see section 3.6.1). 3.2.3 single input configuration if the application requires a single differential input, the second set of inputs may be left unconnected. tie the associated carrier detect pin high, and leave termination pin unconnected. 3.3 serial digital reclocker the output of the 2x1 serial digital input multiplexer passes to the GS1560A's internal r eclocker stage. the function of this block is to lock to the input data stream, extract a clean clock, and retime the serial digital data to remove high frequency jitter. the reclocker was designed with a 'hexabang' phase and frequency detector. that is, the pfd used can identify six 'degrees' of phase / freque ncy misalignment between the input data stream and the cl ock signal provided by the vco, and correspondingly signal the charge pump to produce six different control voltages. this results in fast and accurate locking of the pll to the data stream.
gennum corporation 27360 - 2 24 of 55 GS1560A in master mode, the operating center frequency of the reclocker is toggled between 270mb/s and 1.485gb/s by the lock detect block, (see section 3.6.1). in slave mode, however, the center frequency is determined entirely by the sd/hd input control signal set by the application layer. if lock is achieved, the reclocker provides an internal pll_lock signal to the lock detect block of the device. 3.3.1 external vco the GS1560A requires the external go1525 voltage controlled oscillator as part of the reclocker's phase-locked loop. this external vco implementation was chosen to ensure high quality reclocking. power for the external vco is generated entirely by the GS1560A from an integrated voltage regulator. the internal regulator uses +3.3v dc supplied via the cp_vdd / cp_gnd pins to provide +2.5v dc on the vco_vcc / vco_gnd pins. the control voltage to the vc o is output from the GS1560A on the lf pin and requires 4.7k ? pull-up and pull-down resistors to ensure correct operation. the go1525 produces a 1.485ghz reference signal for the reclocker, input on the vco pin of the GS1560A. both lf and vco signals should be referenced to the supplied vco_gnd as shown in the recommended application circuit of section 4.1. 3.3.2 loop bandwidth the loop bandwidth of the inte grated reclocker is nominally 1.4mhz, but may be increased or decreased via the lb_cont pin. it is recommended that this pin be connected to vco_gnd through 39.2k ? to maximize the input jitter tolerance of the device. 3.4 serial digital loop-through output the GS1560A contains an integrated current mode differential serial digital cab le driver with automatic slew rate control. when enabled, this serial digital output provides an active loop-through of the input signal. to enable the loop-thr ough output, sdo_en/dis must be set high by the application layer. setting the sdo_en/dis signal low will cause the sdo and sdo output pins to become high impedance, resulting in reduced device power consumption. with suitable external return loss matching circuitry, the GS1560A's loop-through outpu ts will provide a minimum output return loss of -15db at sd rates. gennum recommends using the gs1528 sdi dual slew-rate cable driver to meet output return loss specifications at hd rates. the integrated cable driver uses a separate power supply of +1.8v dc supplied via the cd_vdd and cd_gnd pins. 3.4.1 output swing nominally, the voltage swing of the serial digital loop- through output is 800mv p-p single-ended into a 75 ? load. this is set externally by connecting the rset pin to cd_vdd through 281 ? . the loop-through output sw ing may be decreased by increasing the value of the rset resistor. the relationship is approximated by the curve shown in figure 7. alternatively, the serial digi tal output can drive 800mvp-p into a 50 ? load. since the output swing is reduced by a factor of approximately one third when the smaller load is used, the rset resistor must be 187 ? to obtain 800mvp-p. figure 7 serial digital loop-through output swing 3.4.2 reclocker bypass control the serial digital loop-through output may be either a buffered version of the serial digital input signal, or a reclocked version of that signal. when operating in slave mode, the application layer may choose the reclocked output by setting rc_byp to logic high. if rc_byp is set low, the data stream will bypass the internal reclocker and the serial digital output will be a buffered version of the input. when operating in master mode, the device will assert the rc_byp pin high only when it has successfully locked to a smpte or dvb-asi input data stream, (see section 3.6.1). in this case, the serial digita l loop-through output will be a reclocked version of the input. 3.4.3 serial digital output mute the GS1560A will automatically mute the serial digital loop- through output in both master and slave modes when the internal carrier_detect signal indicates an invalid serial input. the loop-through output will also be muted in slave mode when sdo/sdo is selected as reclocked, (rc_byp = high), but the lock detect bl ock has failed to lock to the data stream, (locked = low). 300 400 500 600 700 800 900 1000 250 300 350 400 450 500 550 600 650 700 rset( ? ) ? vsdo(mvp-p) 200 75 ? load 50 ? load
gennum corporation 27360 - 2 25 of 55 GS1560A table 1 summarizes the possible st ates of the serial digital loop-through output data stream. 3.5 serial-to-parallel conversion the retimed data and phase-locked clock signals from the reclocker are fed to the serial-to-parallel converter. the function of this block is to extract 10-bit or 20-bit parallel data words from the reclocked serial data stream and present them to the smpte and dvb-asi word alignment blocks simultaneously. 3.6 modes of operation the GS1560A has two basic modes of operation which determine how the lock detect block controls the integrated reclocker. master mode is enabled when the application layer sets the master/slave pin high, and slave mode is enabled when master/slave is set low. 3.6.1 lock detect the lock detect block controls the center frequency of the integrated reclocker to ensure lock to the received serial digital data stream is achieved, and indicates via the locked output pin that th e device has detected the appropriate sync words. lock detection is a continuous process, which begins at device power up or after a system reset, and continues until the device is powered down or held in reset. the lock detection algorithm first determines if a valid serial digital input signal has been presented to the device by sampling the internal carrier_detect signal. as described in section 3.2.2, this signal will be low when a good serial digital input signal has been detected. if the carrier_detect signal is high, the serial data into the device is considered invalid, and the vco frequency will be set to the center of the pull range. the locked pin will be low and all outputs of the device except for the pclk output will be muted. instea d, the pclk output frequency will operate within +/-3% of t he rates shown in table 16 of section 3.11.5. note: when the device is op erating in dvb-asi slave mode only, the parallel outputs will not mute when the carrier_detect signal is high. the locked signal will function normally. if a valid input signal has been detected, and the device is in master mode, the lock algorithm will enter a hunt phase where four attempts are made to detect the presence of either smpte trs sync words or dvb-asi sync words. at each attempt, the center frequency of the reclocker will be toggled between 270m b/s and 1.485gb/s. assuming that a valid smpte or dvb-asi signal has been applied to the device, asynchronous lock times will be as listed in ac characteristics, (see section 2.3) in slave mode, the application layer fixes the center frequency of the reclocker such that the lock algorithm will attempt to lock within the single data rate determined by the setting of the sd/hd pin. asynchronous lock times are also listed in the ac characteristics, (see section 2.3). note: the pclk output will continue to operate during the lock detection process. the frequency may toggle between 148mhz and 27mhz when the 20bit/10bit pin is set low, or between 74mhz and 13. 5mhz when 20bit/10bit is set high. for smpte and dvb-asi inputs, the lock detect block will only assert the locked output signal high if (1) the reclocker has locked to the input data stream as indicated by the internal pll_lock sig nal, and (2) trs or dvb-asi sync words have been correctly identified. if after four attempts lock has not been achieved, the lock detection algorithm will enter into pll lock mode. in this mode, the reclocker will attempt to lock to the input data stream without detecting smpte trs or dvb-asi sync words. this unassisted process can take up to 10ms to achieve lock. table 1 serial digital loop-through output status slave mode sdo cd locked rc_byp (input) reclocked low high high buffered low x low muted low low high muted high low* x master mode sdo cd locked rc_byp (output) reclocked low high high buffered low low low muted high low* low *note: locked = high if and only if cd = low
gennum corporation 27360 - 2 26 of 55 GS1560A when reclocker lock as indicated by the internal pll_lock signal is achieved in this mode, one of the following will occur: 1. in slave mode, data will be passed directly to the parallel outputs without any further processing taking place and the locked signal will be asserted high if and only if the smpte_bypass and dvb_asi input pins are set low; or 2. in master mode, the locked signal will be asserted low, the parallel outputs will be latched to logic low, and the smpte_bypass and dvb_asi output signals will also be set low. 3.6.2 master mode recall that the GS1560A is said to be in master mode when the master/slave input signal is set high. in this case, the following four device pins become output status signals: smpte_bypass dvb_asi sd/hd rc_byp the combined setting of t hese four pins will indicate whether the device has locked to valid smpte or dvb-asi data at sd or hd rates. table 2 shows the possible combinations. 3.6.3 slave mode the GS1560A is said to be in slave mode when the master/slave input signal is set lo w. in this case, the four device pins listed in section 3.6.2 become input control signals. it is required that the applic ation layer set the first three inputs to reflect the appropriate input data format (smpte_bypass , dvb_asi, and sd/hd ). if just one of these three is configured incorrectly, the device will not lock to the input data stream, and the data_error pin will be set low. the fourth input signal, rc_byp , allows the application layer to determine whether the serial digital loop-through output will be a reclocked or buffered version of the input, (see section 3.4.2). table 3 shows the required settings for various input formats. table 2 master mode output status signals format pin settings smpte_bypass dvb_asi sd/hd rc_byp hd smpte high low low high sd smpte high low high high dvb-asi low high high high not smpte or dvb-asi* low low high or low low *note: when the device locks to the data stream in pll l ock mode, the parallel outputs will be latched low, and the serial loop-through output will be a buffered version of the input. table 3 slave mode input control signals format pin settings smpte_bypass dvb_asi sd/hd hd smpte high low low sd smpte high low high dvb-asi low high high not smpte or dvb-asi* low low high or low *note: see section 3.9 for a complete description of data-through mode.
gennum corporation 27360 - 2 27 of 55 GS1560A 3.7 smpte functionality the GS1560A is said to be in smpte mode once the device has detected smpte trs sync words and locked to the input data stream as describe d in section 3.6.1. the device will remain in smpte mode until such time that smpte trs sync words fail to be detected. the lock detect block may also drop out of smpte mode under the following conditions: reset_trst is asserted low cdx is high smpte_bypass is asserted low in slave mode dvb_asi is asserted high in slave mode trs word detection is a continuous process and both 8-bit and 10-bit trs words will be iden tified by the device in both sd and hd modes. in master mode, the GS1560A sets the smpte_bypass pin high and the dvb_asi pin low to indicate that it has locked to a smpte input data stream. when operating in slave mode, the application layer must assert the dvb_asi pin low and the smpte_bypass pin high in order to enable smpte operation. 3.7.1 smpte descrambling and word alignment after serial-to-parallel conversion, the internal 10-bit or 20- bit data bus is fed to the smpte descramble and word alignment block. the function of this block is to carry out nrzi-to-nrz decoding, descra mbling according to smpte 259m or 292m, and word alignment of the data to the trs sync words. word alignment occurs when three consecutive valid trs words (sav and eav inclusive) with the same bit alignment have been detected (1? video lines). in normal operation, re-synchronization of the word alignment process will only take place when two consecutive identical trs word positions have been detected. when automatic or manual switch line lock handling is 'actioned', (see section 3.7.3), word alignment re-synchronization will occur on the next received trs code word. 3.7.2 internal flywheel the GS1560A has an internal flywheel which is used in the generation of internal / external timing signals, in the detection and correction of cer tain error conditions and in automatic video standar ds detection. it is only operational in smpte mode. the flywheel consists of a number of counters and comparators operating at vid eo pixel and video line rates. these counters maintain information about the total line length, active line length, total number of lines per field / frame, and total active lines per field / frame for the received video stream. the flywheel 'learns' the video standard by timing the horizontal and vertical reference information contained in the trs id words of the received video stream. full synchronization of the flywheel to the received video standard therefore requires one complete video frame. once synchronization has been achieved, the flywheel will continue to monitor the received trs timing information to maintain synchronization. the fw_en/dis input pin controls the synchronization mechanism of the flywheel. when this input signal is low, the flywheel will re-synchronize all pixel and line based counters on every received trs id word. when fw_en/dis is held high, re-syn chronization of the pixel and line based counters will only take place when a consistent synchronization er ror has been detected. two consecutive video lines with iden tical trs timing different to the current flywheel timing must occur to initiate re- synchronization of the counters. this provides a measure of noise immunity to internal and external timing signal generation. the flywheel will be disabled should the locked signal or the reset_trst signal be low. a low to high transistion on either signal will cause the flywheel to re- acquire synchronization on the next received trs word, regardless of the setting of the fw_en/dis pin. 3.7.3 switch line lock handling the principal of switch line lock handling is that the switching of synchronous vide o sources will only disturb the horizontal timing and alignment of the stream, whereas the vertical timing remains in synchronization. to account for the horizontal disturbance caused by a synchronous switch, it is nece ssary to re-synchronize the flywheel immediately after the switch has taken place. rapid re-synchronization of the GS1560A to the new video standard can be achieved by controlling the flywheel using the fw_en/dis pin. at every pclk cycle the de vice samples the fw_en/dis pin. when a logic low to high transition at this pin is detected anywhere within the active line, the flywheel will re-synchronize immediately to the next trs word. this is shown in figure 8. to ensure switch line lock handling, t he fw_en/dis signal should be low for a minimum of one pclk cycle (maximum one video line) anywhere within the active portion of the line on which the switch has taken place.
gennum corporation 27360 - 2 28 of 55 GS1560A figure 8 switch line locking the ability to manually re-synchronize the flywheel is also important when switching asynchronous sources or to implement other non-standardized video switching functions. the GS1560A also implements automatic switch line lock handling. by utilizing the synchronous switch points defined by smpte rp168 for all major video standards with the automatic video standards de tect function, the device automatically re-synchronizes the flywheel at the switch point. this function will occur regardless of the setting of the fw_en/dis pin. the switch line is defined as follows: for 525 line interlaced syst ems: re-sync takes place at the end of lines 10 & 273. for 525 line progressive systems: re-sync takes place at the end of line 10. for 625 line interlaced syst ems: re-sync takes place at the end of lines 6 & 319. for 625 line progressive systems: re-sync takes place at the end of line 6. for 750 line progressive systems: re-sync takes place at the end of line 7. for 1125 line interlaced systems: re-sync takes place at the end of lines 7 & 568. for 1125 line progressive systems: re-sync takes place at the end of line 7. a full list of all major video st andards and switching lines is shown in table 4. note 1 : the flywheel timing will define the line count such that the line numbers shown in table 4 may not correspond directly to the digital line counts. note 2: unless indicated by smpte 352m payload identifier packets, the GS1560A will not distinguish between 50/60 frames psf and 25/30 fr ames interlaced for the 1125 line video systems; 24 psf will be identified. eav anc active picture eav anc sav eav anc active picture sav eav anc active picture sav eav anc sav video source 1 eav anc active picture eav anc sav eav anc active picture sav eav anc sav active picture eav anc sav video source 2 eav anc active picture sav eav anc sav data in active picture eav anc sav anc active picture eav anc sav switch point flywheel trs position eav anc active picture sav eav anc sav anc active picture data out active picture eav anc sav eav anc sav fw_en/dis switch video source 1 to 2 flywheel re-synch eav anc active picture eav anc sav eav anc active picture sav eav anc active picture sav eav anc sav video source 1 eav anc active picture eav anc sav eav anc active picture sav eav anc sav active picture eav anc sav video source 2 eav anc active picture sav eav anc sav data in active picture eav anc sav active picture eav anc sav switch point flywheel trs position eav anc active picture sav eav anc sav active picture data out switch video source 2 to 1 eav anc sav active picture eav anc sav flywheel re-synch fw_en/dis
gennum corporation 27360 - 2 29 of 55 GS1560A table 4 switch line position for digital systems system video format sampling signal standard parallel interface serial interface switch line no. hd-sdti 1920x1080 (psf) 4:2:2 274m 274m + 348m 292m 7 1920x1080 (2:1) 7, 569 1280x720 (1:1) 296m 296m + 348m 7 sdti 720x576/50 (2:1) 4:2:2 bt.656 bt.656 + 305m 259m 6, 319 720x483/59.94 (2:1) 125m 125m + 305m 10, 273 750 1280x720/60 (1:1) 4:2:2 296m 296m 7 1280x720/50 (1:1) 1280x720/30 (1:1) 1280x720/25 (1:1) 1280x720/24 (1:1) 1125 1920x1080/60 (1:1) 4:2:2 274m + rp211 292m 7 1920x1080/50 (1:1) 1920x1080/30 (1:1) 1920x1080/25 (1:1) 1920x1080/24 (1:1) 1920x1080/30 (psf) 1920x1080/25 (psf) 1920x1080/24 (psf) 1920x1080/60 (2:1) 7, 569 1920x1080/50 (2:1) 525 960x483/59.94 (2:1) 4:2:2 267m 349m 292m 10, 273 960x483/59.94 (2:1) 267m 259m 720x483/59.94 (2:1) 4:4:4:4 349m 292m 720x483/59.94 (2:1) 347m 344m 720x483/59.94 (2:1) rp174 344m 720x483/59.94 (2:1) rp175 rp175 720x483/59.94 (2:1) 4:2:2 125m 349m 292m 720x483/59.94 (2:1) 125m 259m 720x483/59.94 (1:1) 4:2:2 293m 349m 292m 10 720x483/59.94 (1:1) 347m 344m 720x483/59.94 (1:1) 293m 294m 720x483/59.94 (1:1) 4:2:0 349m 292m 720x483/59.94 (1:1) 293m 294m
gennum corporation 27360 - 2 30 of 55 GS1560A 3.7.4 hvf timing signal generation the GS1560A extracts critical timing parameters from either the received trs signals (fw_en/dis = low), or from the internal flywheel-timing generator (fw_en/dis = high). horizontal blanking period (h), vertical blanking period (v), and even / odd field (f) timing are all extracted and presented to the applicatio n layer via the h:v:f status output pins. the h signal timing is configurable via the h_config bit of the internal ioproc_disable re gister as either active line based blanking, or trs base d blanking, (see section 3.10.6). active line based blanking is enabled when the h_config bit is set low. in this mode, the h output is high for the entire horizontal blanking period, including the eav and sav trs words. this is the default h timing used by the device. when h_config is set high, trs based blanking is enabled. in this case, the h output will be high for the entire horizontal blanking period as indicated by the h bit in the received trs id words. the timing of these signals is shown in figure 9. 625 720x576/50 (1:1) 4:2:2 bt.1358 349m 292m 6 720x576/50 (1:1) 347m 344m 720x576/50 (1:1) bt.1358 bt.1362 720x576/50 (1:1) 4:2:0 349m 292m 720x576/50 (1:1) bt.1358 bt.1362 960x576/50 (2:1) 4:2:2 bt.601 349m 292m 6, 319 960x576/50 (2:1) bt.656 259m 720x576/50 (2:1) 4:4:4:4 bt.799 349m 292m 720x576/50 (2:1) 347m 344m 720x576/50 (2:1) bt.799 344m 720x576/50 (2:1) bt.799 - 720x576/50 (2:1) 4:2:2 bt.601 349m 292m 720x576/50 (2:1) 125m 259m table 4 switch line position for digital systems (continued) system video format sampling signal standard parallel interface serial interface switch line no.
gennum corporation 27360 - 2 31 of 55 GS1560A figure 9 h, v, f timing h:v:f timing - hd 20-bit output mode pclk luma data out chroma data out h xyz (eav) 000 000 3ff xyz (eav) 000 000 3ff v f xyz (sav) 000 000 3ff xyz (sav) 000 000 3ff h;v:f timing at sav - hd 10-bit output mode 000 000 3ff 3ff xyz (sav) 000 000 xyz (sav) pclk h v f h:v:f timing at eav - hd 10-bit output mode pclk 000 000 3ff 3ff xyz (eav) 000 000 xyz (eav) multiplexed y/cr/cb data out h v f multiplexed y/cr/cb data out h:v:f timing - sd 20-bit output mode pclk chroma data out luma data out h 000 3ff xyz (eav) 000 v f 000 3ff xyz (sav) 000 h:v:f timing - sd 10-bit output mode multiplexed y/cr/cb data out pclk h v f xyz (eav) 000 000 3ff xyz (sav) 000 000 3ff h signal timing: h_config = low h_config = high
gennum corporation 27360 - 2 32 of 55 GS1560A 3.8 dvb-asi functionality the GS1560A is said to be in dvb-asi mode once the device has detected 32 consecutive dvb-asi words without a single word or disparit y error being generated. the device will remain in dvb-asi mode until 32 consecutive dvb-asi word or disparity errors are detected, or until smpte trs id words have been detected. the lock detect block may al so drop out of dvb-asi mode under the following conditions: reset_trst is asserted low cdx is high smpte_bypass is asserted high in slave mode dvb_asi is asserted low in slave mode k28.5 sync patterns in the received dvb-asi data stream will be detected by the device in either inverted or non- inverted form. in master mode, the GS1560A sets the smpte_bypass pin low and the dvb_asi pin high to indicate that it has locked to a dvb-asi input da ta stream. when operating in slave mode, the application layer must set the sd/hd pin high, in addition to setting smpte_bypass low and dvb_asi high, in order to enable dvb-asi operation. 3.8.1 dvb-asi 8b/10b decoding and word alignment after serial-to-parallel conversion, the internal 10-bit data bus is fed to the dvb-as i 8b/10b decode and word alignment block. the function of this block is to word align the data to the k28.5 sync characters, and 8b/10b decode and bit-swap the data to achieve bit alignment with the data outputs. the extracted 8-bit data will be presented to dout[17:10], bypassing all internal smpte mode data processing. note: when operating in dvb-asi mode, dout[9:0] become high impedance. 3.8.2 status signal outputs in dvb-asi mode, the dout19 and dout18 pins will be configured as dvb-asi st atus signals syncout and worderr respectively. syncout will be high whenev er a k28.5 sync character is present on the output. this output may be used to drive the write enable signal of an external fifo, thus providing a means of removing the k28.5 sync characters from the data stream. parallel dvb-asi data may then be clocked out of the fifo at some rate less than 27mhz. see figure 10. worderr will be high whenever the device has detected a running disparity error or illegal code word. figure 10 dvb-asi fifo im plementation using the GS1560A 3.9 data through mode the GS1560A may be configured by the application layer to operate as a simple serial-to-parallel converter. in this mode, the device presents data to the output data bus without performing any decodin g, descrambling or word- alignment. data through mode is enabled only when the master/slave , smpte_bypass , and dvb_asi input pins are set low. under these conditions, the lock detection algorithm enters pll lock mode, (see section 3.6.1), such that the device may reclock data not conforming to smpte or dvb-asi streams. when operating in master mode, the GS1560A will set the smpte_bypass and dvb_asi signals to logic low if presented with a data stream without smpte trs id words or dvb-asi sync words. the locked and data bus outputs will be forced low and the serial digital loop-through output will be a buffered version of the input. 8 8 aout ~ hout worderr pclk = 27mhz syncout ddi clk_in clk_out fifo ddi read_clk <27mhz fe ff ts we worderr GS1560A
gennum corporation 27360 - 2 33 of 55 GS1560A 3.10 additional processing functions the GS1560A contains an additional data processing block which is available in smpte mode only, (see section 3.7). 3.10.1 fifo load pulse to aid in the application-sp ecific implementation of auto- phasing and line synchronization functions, the GS1560A will generate a fifo load pulse to reset line-based fifo storage. the fifo_ld output pin will normally be high but will go low for one pclk period, ther eby generating a fifo write reset signal. the fifo load pulse will be ge nerated such that it is co- timed to the sav xyz code wo rd presented to the output data bus. this ensures that the next pclk cycle will correspond to the first active sample of the video line. figure 11 shows the timing relationship between the fifo_ld signal and the output video data. figure 11 fifo_ld pulse timing pclk luma data out chroma data out fifo_ld 3ff 3ff 3ff 3ff 000 000 000 000 xyz (sav) 000 000 000 000 xyz (sav) xyz (sav) xyz (sav) multiplexed y/cr/cb data out pclk fifo_ld fifo load pulse - hd 10bit output mode fifo load pulse - hd 20bit output mode 3ff 3ff 000 000 000 000 xyz (sav) multiplexed y/cr/cb data out pclk pclk luma data out chroma data out fifo_ld fifo_ld xyz (sav) fifo load pulse - sd 10bit output mode fifo load pulse - sd 20bit output mode
gennum corporation 27360 - 2 34 of 55 GS1560A 3.10.2 ancillary data detection and indication the GS1560A will detect all types of ancillary data in either the vertical or horizontal blanking spaces and indicate via the status signal output pins yanc and canc the position of ancillary data in the ou tput data stream. these status signal outputs are synchronous with pclk and can be used as clock enables to external lo gic, or as write enables to an external fifo or other memory device. when operating in hd mode, (sd/hd = low), the yanc signal will be high whenever ancillary data is detected in the luma data stream, and the canc signal will be high whenever ancillary data is detected in the chroma data stream. in sd mode, (sd/hd = high), the yanc and canc signal operation will depend on the out put data format. for 20-bit demultiplexed data, (see se ction 3.11), the yanc and canc signals will operate independently. however, for 10- bit multiplexed data, the yanc and canc signals will both be high whenever ancillary data is detected. the signals will be high from the start of the ancillary data preamble and will remain high until after the ancillary data checksum. the operation of the yanc and canc signals is shown in figure 12. figure 12 yanc and canc output signal timing anc data detection - hd 20bit output mode anc data detection - hd 10bit output mode 000 000 000 000 3ff 3ff 3ff 3ff 3ff 3ff 3ff 3ff did ydid did dbn dbn anc data anc data anc data anc data dc dc blank blank csum csum canc ycsum ccsum yanc canc pclk luma data out chroma data out multiplexed y/cr/cb data out yanc canc pclk blank did dbn anc data anc data anc data anc data anc data anc data anc data anc data blank csum csum 3ff 000 000 did 3ff dbn dc 3ff 3ff dc anc data anc data detection - sd 20bit output mode anc data detection - sd 10bit output mode pclk multiplexed y/cr/cb data out yanc/canc pclk luma data out chroma data out yanc canc
gennum corporation 27360 - 2 35 of 55 GS1560A 3.10.2.1 programmable ancillary data detection although the GS1560A will detect all types of ancillary data by default, it also allows the host interface to specifically program up to five different ancillary data types for detection. this is accomplished via the anc_type register (table 5). for each data type to be detected, the host interface must program the did and/or sdid of the ancillary data type of interest. the GS1560A will compare the received did and/or sdid with the programmed values and assert yanc and canc only if an exac t match is found. if any did or sdid value is set to zero in the anc_type register, no comparison or match will be made for that value. for example, if the did is programmed but the sdid is set to zero, the device will detect all ancillary data types matching the did value, regardless of the sdid. in the case where all five did and sdid values are set to zero, the GS1560A will detect all ancillary data types. this is the default setting after device reset. where one or more, but less than five, did and/or sdid values have been programmed, then only those matching ancillary data types will be detected and indicated. note 1: the GS1560A will always detect edh ancillary data packets for edh error detection purposes, regardless of which did/sdid values have been programmed for ancillary data indication, (see section 3.10.5.2). note 2: see smpte 291m for a definition of ancillary data terms. table 5 host interface description for programmable ancillary data type registers register name bit name description r/w default anc_type1 address: 005h 15-8 anc_type1[15:8] used to program the did for ancillary data detection at the yanc and canc output r/w 0 7-0 anc_type1[7:0] used to program the sdid for ancillary data detection at the yanc and canc output. should be set to zero if no sdid is present in the ancillary data product to be detected. r/w 0 anc_type2 address: 006h 15-8 anc_type2[15:8] used to program the did for ancillary data detection at the yanc and canc output r/w 0 7-0 anc_type2[7:0] used to program the sdid for ancillary data detection at the yanc and canc output. should be set to zero if no sdid is present in the ancillary data product to be detected. r/w 0 anc_type3 address: 007h 15-8 anc_type3[15:8] used to program the did for ancillary data detection at the yanc and canc output r/w 0 7-0 anc_type3[7:0] used to program the sdid for ancillary data detection at the yanc and canc output. should be set to zero if no sdid is present in the ancillary data product to be detected. r/w 0 anc_type4 address: 008h 15-8 anc_type4[15:8] used to program the did for ancillary data detection at the yanc and canc output r/w 0 7-0 anc_type4[7:0] used to program the sdid for ancillary data detection at the yanc and canc output. should be set to zero if no sdid is present in the ancillary data product to be detected. r/w 0 anc_type5 address: 009h 15-8 anc_type5[15:8] used to program the did for ancillary data detection at the yanc and canc output r/w 0 7-0 anc_type5[7:0] used to program the sdid for ancillary data detection at the yanc and canc output. should be set to zero if no sdid is present in the ancillary data product to be detected. r/w 0
gennum corporation 27360 - 2 36 of 55 GS1560A 3.10.3 smpte 352m payload identifier the GS1560A can receive and de tect the presence of the smpte 352m payload identifier ancillary data packet. this four word payload identifier packet may be used to indicate the transport mechanism, frame rate and line scanning / sampling structure. upon reception of this packet, the device will extract the four words describing the video format being transported and make this information available to the host interface via the four video_format_out registers (table 6). the video_format_out registers will only be updated if the received checksum is the same as the locally calculated checksum. these registers will be cleared to zero, indicating an undefined format, if the device loses lock to the input data stream (locked = low), or if the smpte_bypass pin is asserted low. this is also the default setting after device reset. the smpte 352m packet should be received once per field for interlaced systems and once per frame for progressive systems. if the packet is not received for two complete video frames, the video_format_out registers will be cleared to zero. 3.10.4 automatic video standard and data format detection the GS1560A can independently detect the input video standard and data format by using the timing parameters extracted from the received trs id words. this information is presented to the host interface via the video_standard register (table 7). total samples per line, active samples per line, total lines per field/frame and active lines per field/frame are also calculated and presented to the host interface via the raster_structure registers (table 8). these line and sample count registers are updated once per frame at the end of line 12. this is in addition to the information contained in the vide o_standard register. after device reset, the four raster_structure registers default to zero. 3.10.4.1 video standard indication the video standard codes reported in the vd_std[4:0] bits of the video_standard register represent the smpte standards as shown in table 9. in addition to the 5-bit video standard code word, the video_standard register also contains two status bits. the std_lock bit will be set high whenever the flywheel has achieved full synchronization. the int_prog bit will be set high if the detected video standard is progressive and low if the detected video standard is interlaced. the vd_std[4:0], std_lock and int_prog bits of the video_standard register will default to zero after device reset. these bits will also default to zero if the device loses lock to the input da ta stream, (locked = low), or if the smpte_bypass pin is asserted low. table 6 host interface description for smpte 352m payload identifier registers register name bit name description r/w default video_format_out_b address: 013h 15-8 smpte352m byte 4 data will be available in this register when video payload indentification packets are detected in the data stream. r0 7-0 smpte352m byte 3 data will be available in this register when video payload indentification packets are detected in the data stream. r0 video_format_out_a address: 012h 15-8 smpte352m byte 2 data will be available in this register when video payload indentification packets are detected in the data stream. r0 7-0 smpte352m byte 1 data will be available in this register when video payload indentification packets are detected in the data stream. r0
gennum corporation 27360 - 2 37 of 55 GS1560A table 7 host interface description for video standard and data format register register name bit name description r/w default video_standard address: 004h 15 not used 14-10 vd_std[4:0] video data standard (see table 12) r 0 9 int_prog interlace/progressive: set high if detected video standard is progressive and is set low if it is interlaced. r0 8 std_lock standard lock: set high when flywheel has achieved full synchronization. r0 7-4 cdata_format[3:0] chroma data format. set high in sd mode. indicates chroma data format in hd mode (see table 10). rf h 3-0 ydata_format[3:0] luma data format. indicates luma data format in hd mode and data format in sd mode (see table 10). rf h table 8 host interface description for raster structure registers register name bit name description r/w default raster_structure1 address: 014h 15-12 not used 11-0 raster_structure1[11:0] words per active line. r 0 raster_structure2 address: 015h 15-12 not used 11-0 raster_structure2[11:0] words per total line. r 0 raster_structure3 address: 016h 15-11 not used 10-0 raster_structure3[10:0] total lines per frame. r 0 raster_structure4 address: 017h 15-11 not used 10-0 raster_structure4[10:0] active lines per field. r 0
gennum corporation 27360 - 2 38 of 55 GS1560A table 9 supported video standards vd_std[4:0] smpte standard video format length of hanc length of active video total samples smpte352m lines 00h 296m (hd) 1280x720/60 (1:1) 358 1280 1650 13 01h 1280x720/60 (1:1) - em 198 1440 1650 13 02h 1280x720/30 (1:1) 2008 1280 3300 13 03h 1280x720/30 (1:1) - em 408 2880 3300 13 04h 1280x720/50 (1:1) 688 1280 1980 13 05h 1280x720/50 (1:1) - em 240 1728 1980 13 06h 1280x720/25 (1:1) 2668 1280 3960 13 07h 1280x720/25 (1:1) - em 492 3456 3960 13 08h 1280x720/24 (1:1) 2833 1280 4125 13 09h 1280x720/24 (1:1) - em 513 3600 4125 13 0ah 274m (hd) 1920x1080/60 (2:1) or 1920x1080/30 (psf) 268 1920 2200 10, 572 0bh 1920x1080/30 (1:1) 268 1920 2200 18 0ch 1920x1080/50 (2:1) or 1920x1080/25 (psf) 708 1920 2640 10, 572 0dh 1920x1080/25 (1:1) 708 1920 2640 18 0eh 1920x1080/25 (1:1) - em 324 2304 2640 18 0fh 1920x1080/25 (psf) - em 324 2304 2640 10, 572 10h 1920x1080/24 (1:1) 818 1920 2750 18 11h 1920x1080/24 (psf) 818 1920 2750 10, 572 12h 1920x1080/24 (1:1) - em 338 2400 2750 18 13h 1920x1080/24 (psf) - em 338 2400 2750 10, 572 14h 295m (hd) 1920x1080/50 (2:1) 444 1920 2376 10, 572 15h 260m (hd) 1920x1035/60 (2:1) 268 1920 2200 10, 572 16h 125m (sd) 1440x487/60 (2:1) (or dual link progressive) 268 1440 1716 3, 276 17h 1440x507/60 (2:1) 268 1440 1716 3, 276 19h 525-line 487 generic - - 1716 3, 276 1bh 525-line 507 generic - - 1716 3, 276 18h itu-r bt.656 (sd) 1440x576/50 (2:1) (or dual link progressive) 280 1440 1728 9, 322 1ah 625-line generic (em) - - 1728 9, 322 1dh unknown hd - - - - - 1eh unknown sd - - - - - 1ch, 1fh reserved
gennum corporation 27360 - 2 39 of 55 GS1560A 3.10.4.2 data format indication the luma and chroma data format codes will be reported in the ydata_format[3:0] and cdata_format[3:0] bits of the video_standard register when the device is operating in hd mode, (sd/hd = low). in sd or dvb-asi mode, the data format code will only appear in the ydata_format[3:0] bits. the cdata_format[3:0] bits will be set to 'f h '. these codes represent the data formats listed in table 10. the ydata_format[3:0] and cdata_format[3:0] bits of the video_standard register will default to 'f h ' after device reset. these bits will also default to 'f h ' if the device loses lock to the input data stream, (locked = low), or if data-through mode is enabled, (see section 3.9). 3.10.5 error detection and indication the GS1560A contains a nu mber of error detection functions to enhance operation of the device when operating in smpte mode. the se functions, (except lock error detection), will not be av ailable in either dvb-asi or data-through operating modes. see section 3.8 and section 3.9. the device maintains an error status register at address 000 h called error_status (table 11). each type of error has a specific flag or bit in this register which is set high whenever that error is detected. the error_status register will be cleared at the start of each video field or when read by the host interface, which ever condition occurs first. all bits of the error_status register except the lock_err bit will also be cleared if a change in the video standard is detected, or und er the following conditions: reset_trst is held low locked is asserted low smpte_bypass is asserted low in slave mode in addition to the error_status register, a register called error_mask (table 12) is in cluded which allows the host interface to select the specific error conditions that will be detected. there is one bit in the error_mask register for each type of error represented in the error_status register. the bits of the error_mask register will default to '0' after device reset, thus enabling all error types to be detected. the host interface may disable individual error detection by setting the corresponding bi t high in this register. error conditions are also indicated to the application layer via the status signal pin data_error . this output pin is a logical 'or'ing of each error status flag stored in the error_status register. data_error is normally high, but will be set low by the device when an error condition that has not been ma sked is detected. table 10 data format codes ydata_format[3:0] or cdata_format[3:0] data format applicable standards 0h sdti dvcpro - no ecc smpte 321m 1h sdti dvcpro - ecc smpte 321m 2h sdti dvcam smpte 322m 3h sdti cp smpte 326m 4h other sdti fixed block size - 5h other sdti variable block size - 6h sdi - 7h dvb-asi - 8h tdm data smpte 346m 9h ~ eh reserved fh unknown data format -
gennum corporation 27360 - 2 40 of 55 GS1560A table 11 host interface description for error status register register name bit name description r/w default error_status address: 001h 15-11 not used 10 vd_std_err video standard error flag. set high when a mismatch between the received smpte352m packets and the calculated video standard occurs. r0 9 ff_crc_err full field crc error flag. set high in sd mode when a full field (ff) crc mismatch has b een detected in field 1 or 2. r0 8 ap_crc_err active picture crc error flag. set high in sd mode when an active picture (ap) crc mismatch has been detected in field 1 or 2. r0 7 lock_err lock error flag. set high whenever the lock pin is low (indicating the device not correctly locked). r0 6 ccs_err chroma checksum error flag. set high when ancillary data packet checksum error has been detected in the c channel. r0 5 ycs_err luma checksum error flag. set high when ancillary data packet checksum error has been detected in the y channel. r0 4 ccrc_err chroma crc error flag. set high in hd mode when a mismatch occurs between the calculated and received crc values in the c channel. r0 3 ycrc_err luma crc error flag. set high in hd mode when a mismatch occurs between the calculated and received crc values in the y channel. r0 2 lnum_err line number error flag. set high in hd mode when a mismatch occurs between the cal culated and received line numbers. r0 1 sav_err start of active video error flag. set high when trs errors are detected in either 8-bit or 10-bit trs words. in hd mode only y channel trs codes will be checked. fw_en/dis must be set high. r0 0 eav_err end of active video error flag. set high when trs errors are detected in either 8-bit or 10-bit trs words. in hd mode only y channel trs codes will be checked. fw_en/dis must be set high. r0
gennum corporation 27360 - 2 41 of 55 GS1560A 3.10.5.1 video standard error detection if a mismatch between the re ceived smpte 352m packets and the calculated video stand ard occurs, the GS1560A will indicate a video standard error by setting the vd_std_err bit of the error_status register high. 3.10.5.2 edh crc error detection the GS1560A calculates full field (ff) and active picture (ap) crc words according to smpte rp165 in support of error detection and handling packets in sd signals. these calculated crc values are compared with the received crc values. if a mismatch is detected, the error is flagged in the ap_crc_err and/or ff_crc_err bits of the error_status register. these two flags are shared between fields 1 and 2. the ap_crc_err bit will be set high when an active picture crc mismatch has been detected in field 1 or 2. the ff_crc_err bit will be set high when a full field crc mismatch has been detected in field 1 or 2. edh crc errors will only be indicated when the device is operating in sd mode (sd/hd = high), and when the device has correctly received edh packets. smpte rp165 specifies the ca lculation ranges and scope of edh data for standard 525 and 625 component digital interfaces. the GS1560A will utilize these standard ranges by default. if the received video format does not correspond to 525 or 625 digital component video standards as determined by the flywheel pixel and line counters, then one of two schemes for determining the edh calculation ranges will be employed: 1. ranges will be based on the line and pixel ranges programmed by the host interface; or 2. in the absence of user-programmed calculation ranges, ranges will be determined from the received trs timing information. the registers available to the host interface for programming edh calculation ranges include active picture and full field line start and end positions for both fields. table 13 shows the relevant re gisters, which default to '0' after device reset. if any or all of these register values are zero, then the edh crc calculation ranges will be determined from the flywheel generated h signal. the first active and full field pixel will always be the first pixel after the sav trs code word. the last active and full field pixel will always be the last pixel before the start of the eav trs code words. table 12 host interface description for error mask register register name bit name description r/w default error_mask address: 026h 15-11 not used 10 vd_std_err_mask video standard error flag mask bit. r/w 0 9 ff_crc_err_mask full field cr c error flag mask bit. r/w 0 8 ap_crc_err_mask active pictur e crc error flag mask bit. r/w 0 7 lock_err_mask lock error flag mask bit. r/w 0 6 ccs_err_mask chroma checksum error flag mask bit. r/w 0 5 ycs_err_mask luma checksum error flag mask bit. r/w 0 4 ccrc_err_mask chroma crc error flag mask bit. r/w 0 3 ycrc_err_mask luma crc error flag mask bit. r/w 0 2 lnum_err_mask line number error flag mask bit. r/w 0 1 sav_err_mask start of active video error flag mask bit. r/w 0 0 eav_err_mask end of active video error flag mask bit. r/w 0
gennum corporation 27360 - 2 42 of 55 GS1560A table 13 host interface description for edh calculation range registers register name bit name description r/w default ap_line_start_f0 address: 018h 15-10 not used 9-0 ap_line_start_f0[9:0] field 0 active picture start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_line_end_f0 address: 019h 15-10 not used 9-0 ap_line_end_f0[9:0] field 0 active pi cture end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_line_start_f1 address: 020h 15-10 not used 9-0 ap_line_start_f1[9:0] field 1 active picture end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_line_end_f1 address: 021h 15-10 not used 9-0 ap_line_end_f1[9:0] field 1 active picture end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_line_start_f0 address: 022h 15-10 not used 9-0 ff_line_start_f0[9:0] fi eld 0 full field start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_line_end_f0 address: 023h 15-10 not used 9-0 ff_line_end_f0[9:0] field 0 full field start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_line_start_f1 address: 024h 15-10 not used 9-0 ff_line_start_f1[9:0] fi eld 1 full field start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_line_end_f1 address: 025h 15-10 not used 9-0 ff_line_end_f1[9:0] field 1 full fiel d end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0
gennum corporation 27360 - 2 43 of 55 GS1560A 3.10.5.3 lock error detection the locked pin of the GS1560A indicates the lock status of the reclocker and lock detect blocks of the device. only when the locked pin is asserted high has the device correctly locked to the receiv ed data stream, (see section 3.6.1). the GS1560A will also indicate lock error to the host interface when locked = low by setting the lock_err bit in the error_stat us register high. 3.10.5.4 ancillary data checksum error detection the GS1560A will calculate checksums for all received ancillary data and compare the calculated values to the received checksum words. if a mismatch is detected, the error is flagged in the ccs_e rr and/or ycs_err bits of the error_status register. when operating in hd mode, (sd/hd = low), the device will make comparisons on both the y and c channels separately. if an error condition in the y channel is detected, the ycs_err bit will be set high. if an error condition in the c channel is detected, the ccs_err bit will be set high. when operating in sd mode, (sd/hd = high), only the ycs_err bit will be set high when checksum errors are detected. although the GS1560A will calculate and compare checksum values for all ancillary data types by default, the host interface may program the device to check only certain types of ancillary data checksums. this is accomplished via the anc_type register as described in section 3.10.2.1. 3.10.5.5 line based crc error detection the GS1560A will calculate line based crc words for hd video signals for both the y and c data channels. these calculated crc values are compared with the received crc values and any mismatch is flagged in the ycrc_err and/or ccrc_err bits of th e error_status register. line based crc error flags will only be generated when the device is operating in hd mode, (sd/hd = low). if a crc error is detected in the y channel, the ycrc_err bit in the error status register will be set high. if a crc error is detected in the c channel, the ccrc_err bit in the error status register is set high. y and c crc errors will also be generated if crc values are not received. 3.10.5.6 hd line number error detection when operating in hd mode, the GS1560A will calculate line numbers based on the timing generated by the internal flywheel. these calculated line numbers are compared with the received line numbers for the y channel data and any mismatch is flagged in the lnum_err bit of the error_status. line number errors will also be generated if line number values are not received. 3.10.5.7 trs error detection trs errors flags are generated by the GS1560A when: 1. the received trs timing d oes not correspond to the internal flywheel timing; or 2. the received trs hamming codes are incorrect. both 8-bit and 10-bit sav and eav trs words are checked for timing and data integrity errors. these are flagged via the sav_err and/or eav_err bits of the error_status register. timing-based trs errors will only be generated if the fw_en/dis pin is set high. note: in hd mode, (sd/hd = low), only the y channel trs codes will be checked for errors. 3.10.6 error correction and insertion in addition to signal error detection and indication, the GS1560A may also correct certain types of errors by inserting corrected code words, checksums and crc values into the data stream. these features are only available in smpte mode and ioproc_en/dis must be set high. individual correction features may be enabled or disabled via the ioproc_disable register (table 14). all of the ioproc_disable register bits default to '0' after device reset, enabling all of the processing features. to disable any individual error correction feature, the host interface must set the corresponding bit high in the ioproc_disable register.
gennum corporation 27360 - 2 44 of 55 GS1560A 3.10.6.1 illegal code remapping if the illegal_remap bi t of the ioproc_disable register is set low, th e GS1560A will remap all codes within the active picture between the values of 3fch and 3ffh to 3fbh. all codes within the active picture area between the values of 000h and 003h will be re-mapped to 004h. in addition, 8-bit trs and ancillary data preambles will be remapped to 10-bit values if this feature is enabled. 3.10.6.2 edh crc error correction the GS1560A will generate and insert active picture and full field crc words into the edh data packets received by the device. this feature is only available in sd mode and is enabled by setting the edh_crc_ins bit of the ioproc_disable register low. edh crc calculation ranges are described in section 3.10.5.2. note: although the GS1560A will modify and insert edh crc words and edh packet checksums, edh error flags will not be updated by the device. 3.10.6.3 ancillary data checksum error correction when ancillary data checksum error correction and insertion is enabled, the GS1560A will generate and insert ancillary data checksums for all ancillary data words by default. where user specified ancillary data has been programmed into the device (see section 3.10.2.1), only the checksums for the programmed ancillary data types will be corrected. this feature is enabled when the anc_csum_ins bit of the ioproc_disable register is set low. 3.10.6.4 line based crc correction the GS1560A will generate and insert line based crc words into both the y and c channels of the data stream. this feature is only available in hd mode and is enabled by setting the crc_ins bit of the ioproc_disable register low. table 14 host interface description for internal processing disable register register name bit bit name description r/w default ioproc_disable address: 000h 15-9 not used 8 h_config horizontal sync timing output configuration. set low for active line blanking timing . set high for h blanking based on the h bit setting of the trs words. see figure 8. 0 7 not used 6 not used 5 illegal_remap illegal code re-mapping. correction of illegal code words within the active picture. set high to disable. the ioproc_en/dis pin must be set high. r/w 0 4 edh_crc_ins error detection & hand ling (edh) cyclical redundancy check (crc) error correction insertion. in sd mode set high to disable. the ioproc_en/dis pin must be set high. r/w 0 3 anc_csum_ins ancillary data check-sum insertion. set high to disable. the ioproc_en/dis pin must be set high. r/w 0 2 crc_ins y and c line based crc insertion. in hd mode, inserts line based crc words in both the y and c channels. set high to disable. the ioproc_en/dis pin must be set high. r/w 0 1 lnum_ins y and c line number insertion. in hd mode set high to disable. the ioproc_en/dis pin must be set high. r/w 0 0 trs_ins timing reference signal insertion. set high to disable. the ioproc_en/dis pin must be set high. r/w 0
gennum corporation 27360 - 2 45 of 55 GS1560A 3.10.6.5 hd line number error correction in hd mode, the GS1560A will calculate and insert line numbers into the y and c channels of the output data stream. line number generation is in accordance with the relevant hd video standard as determined by the device, (see section 3.10.4). this feature is enabled when sd/hd = low, and the lnum_ins bit of the ioproc_disable register is set low. 3.10.6.6 trs error correction when trs error correction and insertion is enabled, the GS1560A will generate and insert 10-bit trs code words as required. trs word generation will be performed in accordance with the timing parameters generate d by the flywheel to provide an element of noise immunity. as a result, trs correction will only take place if the flywheel is enabled, (fw_en/dis = high). in addition, the trs_ins bit of the ioproc_disable register must be set low. 3.10.7 edh flag detection as described in section 3.10.5.2, the GS1560A can detect edh packets in the received data stream. the edh flags for ancillary data, active picture and full field areas are extracted from the detected edh packets and placed in the edh_flag register of the device (table 15). one set of flags is provided for both fields 1 and 2. field 1 flag data will be overwrit ten by field 2 flag data. the edh_flag register may be read by the host interface at any time during the recei ved frame except on the lines defined in smpte rp165 where these flags are updated. note 1: by programming t he anc_type1 register (005h) with the did word for edh ancillary packets, the application layer may detect a high-to-low transition on either the yanc or canc output pin of the GS1560A to determine (a) when edh packets have been received by the device, and (b) when the edh_flag register can be read by the host interface. see section 3.10.2 for more information on ancillary data detection and indication. note 2: the bits of the edh_fl ag register are sticky and will not be cleared by a read operation. if the GS1560A is decoding a source containing edh packets, where edh flags may be set, and the source is replaced by one without edh packets, the edh_flag register will not be cleared. note 3: the GS1560A will dete ct edh flags, but will not update the flags if an e dh crc error is detected. gennum's gs1532 multi-rate serializer allws the host to individually set edh flags.
gennum corporation 27360 - 2 46 of 55 GS1560A 3.11 parallel data outputs data outputs leave the device on the rising edge of pclk as shown in figure 13 and figure 14. the data may be scrambled or unscrambled, framed or unframed, and may be presented in 10-bit or 20-bit format. the output data bus width is controlled independently from the internal data bus width by the 20bit/10bit input pin. likewise, the output data format is defined by the setting of the external sd/hd , smpte_bypass and dvb_asi pins. recall that in slave mode, these pins are set by the application layer as inputs to the device. in master mode, however, the GS1560A sets t hese pins as output status signals. 3.11.1 parallel data bus buffers the parallel data outputs of the GS1560A are driven by high-impedance buffers which support both lvttl and lvcmos levels. these buffers use a separate power supply of +3.3v dc supplied via the io_vdd and io_gnd pins. all output buffers, including the pclk output, may be driven to a high-impedance state if the reset_trst signal is asserted low. note that the timing charact eristics of the parallel data output buffers are optimized for 10-bit hd operation. as shown in figure 13, the output data hold time for hd is 1.5ns. due to this optimization, however, the output data hold time for sd data is so small that the rising edge of the pclk is nearly incident with the data transition. to improve output hold time at sd rates, the pclk output is inverted is sd mode, (sd/hd = high). this is shown in figure 14. table 15 host interface description for edh flag register register name bit name description r/w default edh_flag address: 003h 15 not used 14 anc-ues out ancillary unknown error status flag. r 0 13 anc-ida out ancillary internal devi ce error detected already flag. r 0 12 anc-idh out ancillary internal device error detected here flag. r 0 11 anc-eda out ancillary error detected already flag. r 0 10 anc-edh out ancillary error detected here flag. r 0 9 ff-ues out full field unknown error status flag. r 0 8 ff-ida out full field internal device error detected already flag. r 0 7 ff-idh out full field internal device error detected here flag. r 0 6 ff-eda out full field error detected already flag. r 0 5 ff-edh out full field error detected here flag. r 0 4 ap-ues out active picture unknown error status flag. r 0 3 ap-ida out active picture internal device error detected already flag. r 0 2 ap-idh out active picture internal device error detected here flag. r 0 1 ap-eda out active picture error detected already flag. r 0 0 ap-edh out active picture error detected here flag. r 0
gennum corporation 27360 - 2 47 of 55 GS1560A figure 13 hd pclk to data timing figure 14 sd pclk to data timing 3.11.2 parallel output in smpte mode when the device is operating in smpte mode, (see section 3.7), both sd and hd data may be presented to the output bus in either multiplexed or demultiplexed form depending on the setting of the 20bit/10bit input pin. in 20-bit mode, (20bit/10bit = high), the output data will be word aligned, demultiplexed luma and chroma data. luma words will always appear on dout[19:10] while chroma words will occupy dout[9:0]. in 10-bit mode, (20bit/10bit = low), the output data will be word aligned, multiplexed luma and chroma data. the data will be presented on dout[19: 10], and the device will force dout[9:0] low. 3.11.3 parallel output in dvb-asi mode when operating in dvb-asi mode, (see section 3.8), the GS1560A automatically configures the output port for 10-bit operation regardless of the setting of the 20bit/10bit pin. the extracted 8-bit data words will be presented on dout[17:10] such that dout17 = hout is the most significant bit of the decoded transport stream data and dout10 = aout is the least significant bit. in addition, dout19 and dout18 will be configured as the dvb-asi status signal s syncout and worderr respectively. see section 3.8. 2 for a description of these dvb-asi specific output signals. dout[9:0] will be forced low when the GS1560A is operating in dvb-asi mode. 3.11.4 parallel output in data-through mode when operating in data-through mode, (see section 3.9), the GS1560A presents data to the output data bus without performing any decoding, desc rambling or word-alignment. as described in section 3.9, the data bus outputs will be forced to logic low if the device is set to operate in master mode but cannot identify smpte trs id or dvb-asi sync words in the input data stream. 3.11.5 parallel output clock (pclk) the frequency of the pclk output signal of the GS1560A is determined by the output data format. table 16 below lists the possible output signal fo rmats and their corresponding parallel clock rates. note that dvb-asi output will always be in 10-bit format, regardless of the setting of the 20bit/10bit pin. pclk dout[19:0] data control signal output t oh t od hd mode pclk dout[19:0] data control signal output t oh t od sd mode
gennum corporation 27360 - 2 48 of 55 GS1560A table 16 parallel data output format output data format status / control signals* dout [19:10] dout [9:0] pclk 20bit/10 bit sd/hd smpte_bypass dvb_asi smpte mode 20bit demultiplexed sd high high high low luma chroma 13.5mhz 10bit multiplexed sd low high luma / chroma forced low 27mhz 20bit demultiplexed hd high low luma chroma 74.25 or 74.25/1.001mhz 10bit multiplexed hd low low luma / chroma forced low 148.5 or 148.5/1.001mhz dvb-asi mode 10bit dvb-asi high high low high dvb-asi data forced low 27mhz low data-through mode** 20bit demultiplexed sd high high low low data data 13.5mhz 10bit multiplexed sd low high data forced low 27mhz 20bit demultiplexed hd high low data data 74.25 or 74.25/1.001mhz 10bit multiplexed hd low low data forced low 148.5 or 148.5/1.001mhz *note1: recall that sd/hd , smpte_bypass , and dvb_asi are input control pins in slave mode to be set by the application layer, but are output status signals set by the device in master mode. **note 2: data-through mode is only avai lable in slave mode (see section 3.9).
gennum corporation 27360 - 2 49 of 55 GS1560A 3.12 gspi host interface the gspi, or gennum serial peripheral interface, is a 4-wire interface provided to allow the host to enable additional features of the device and /o r to provide additional status information through configurat ion registers in the GS1560A. the gspi comprises a serial data input signal sdin, serial data output signal sdout, an active low chip select cs , and a burst clock sclk. because these pins are shared with the jtag interface port, an additional control signal pin jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals are provided by the host interface. the sdout pin is a high-impedance output allowing multiple devices to be connected in parallel and selected via the cs input. the interface is illustrated in figure 15. all read or write access to the GS1560A is initiated and terminated by the host processor. each access always begins with a 16-bit command word on sdin indicating the address of the register of in terest. this is followed by a 16- bit data word on sdin in write mode, or a 16-bit data word on sdout in read mode. figure 15 gennum serial peripheral interface (gspi) 3.12.1 command word description the command word is transmitted msb first and contains a read/write bit, nine reserved bits and a 6-bit register address. set r/w = '1' to read and r/w = '0' to write from the gspi. command words are clocked into the GS1560A on the rising edge of the serial clock sclk. the appropriate chip select, cs , signal must be asserted low a minimum of 1.5ns (t 0 in figure 18 and figure 19) before the first clock edge to ensure proper operation. each command word must be followed by only one data word to ensure proper operation. figure 16 command word figure 17 data word sclk cs sdout sdin sclk cs sdin sdout application host GS1560A r/w rsv rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv msb lsb d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 msb lsb
gennum corporation 27360 - 2 50 of 55 GS1560A 3.12.2 data read and write timing read and write mode timing for the gspi interface is shown in figure 18 and figure 19 respectively. the maximum sclk frequency allowed is 6.6mhz. when writing to the registers via the gspi, the msb of the data word may be presented to sdin immediately following the falling edge of the lsb of the command word. all sdin data is sampled on the rising edge of sclk. when reading from the regist ers via the gspi, the msb of the data word will be available on sdout 12ns following the falling edge of the lsb of the command word, and thus may be read by the host on the very next rising edge of the clock. the remaining bits are clocked out by the GS1560A on the negative edges of sclk. figure 18 gspi read mode timing figure 19 gspi write mode timing 3.12.3 configuration and status registers table 17 summarizes the GS1560A's internal status and configuration registers. all of these registers are available to the host via the gspi and are all individually addressable. where status registers contain less than the full 16 bits of information however, two or more registers may be combined at a single logical address. sdout r/w rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 sclk cs sdin rsv t 0 t 2 t 3 input data setup time duty cycle t 4 period t 5 t 6 output data hold time r/w rsv rsv a0 a1 a2 a3 a4 a5 rsv rsv rsv rsv rsv rsv d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 sclk cs sdin rsv t 0 t 2 t 3 input data setup time duty cycle t 4 period table 17 GS1560A internal registers address register name see section 000h ioproc_disable section 3.10.6 001h error_status section 3.10.5 003h edh_flag section 3.10.7 004h video_standard section 3.10.4 005h - 009h anc_type section 3.10.2.1 012h - 013h video_format section 3.10.3 014h - 017h raster_structure section 3.10.4 018h - 025h edh_calc_ranges section 3.10.5.2 026h error_mask section 3.10.5
gennum corporation 27360 - 2 51 of 55 GS1560A 3.13 jtag when the jtag/host input pin of the GS1560A is set high, the host interface port will be configured for jtag test operation. in this mode, pins 27 through 30 become tms, tdo, tdi, and tck. in addition, the reset_trst pin will operate as the test reset pin. boundary scan testing using the jtag interface will be enabled in this mode. there are two methods in which jtag can be used on the GS1560A: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly; or 2. under control of the host for applications such as system power on self tests. when the jtag tests are applied by ate, care must be taken to disable any other devices driving the digital i/o pins. if the tests are to be applied only at ate, this can be accomplished with tri-state buff ers used in conjunction with the jtag/host input signal. this is shown in figure 20. figure 20 in-circuit jtag alternatively, if the test capab ilities are to be used in the system, the host may still cntrol the jtag/host input signal, but some means for tri-stating the host must exist in order to use the interface at ate. this is represented in figure 21. figure 21 system jtag please contact your gennum representative to obtain the bsdl model for the GS1560A. 3.14 device power up because the GS1560A is designed to operate in a multi-volt environment, any power up sequence is allowed. the charge pump, phase detector, core logic, serial digital input/output buffers and digital i/o buffers should all be powered up within 1ms of one another. device pins may also be driven prior to power up without causing damage. to ensure that all internal registers are cleared upon power- up, the application layer must hold the reset_trst signal low for a minimum of 1ms after the core power supply has reached the minimum level specified in the dc electrical characteristics table (see se ction 2.2). see figure 22. 3.15 device reset in order to initialize all internal operating conditions to their default states the application layer must hold the reset_trst signal low for a minimum of t reset = 1ms. when held in reset, all device outputs will be driven to a high-impedance state. figure 22 reset pulse application host GS1560A cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe application host GS1560A cs_tms sclk_tck sdin_tdi sdout_tdo jtag_host in-circuit ate probe tri-state core_vdd reset_trst t reset +1.65v +1.8v reset reset t reset
gennum corporation 27360 - 2 52 of 55 GS1560A 4. application reference design 4.1 typical application circuit (part a) eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc eq_vcc gs1524 14 15 1 2 3 4 7 5 6 16 9 10 11 13 8 12 vee vcc cli vcca veea sdi rsvd sdi veea mute/cd bypass mcladj vee sdo rsvd sdo 2n4400 1 3 2 0 2n4402 1 2 3 37r4 10k 0 gs1524 14 15 1 2 3 4 7 5 6 16 9 10 11 13 8 12 vee vcc cli vcca veea sdi rsvd sdi veea mute/cd bypass mcladj vee sdo rsvd sdo 1u header 1 2 3 10n 75 6.4n 2n4402 1 2 3 1k 75 2k2 pot 2n4400 1 3 2 10k 75 6.4n 37r4 pot 1u 0 10n 1u 0 1u 1k 10n header 1 2 3 10n 2k2 75 ddi2 ddi2b sdi cd2b cd1b sdi ddi1b ddi1 1u 1u gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq gnd_eq
gennum corporation 27360 - 2 53 of 55 GS1560A 4.2 typical applic ation circuit (part b) lock yanc canc ipsel sd/hdb 20bit/10bitb ioproc_en/disb data0 data7 data12 data1 data8 data13 data14 data16 data3 data6 data2 data11 data4 data17 data10 data15 data18 data9 data5 master/slaveb rc_bypb fw_en/ disb sdo_en/disb jtag/hostb data19 master/slaveb ioproc_en/disb 20bit/10bitb data_errorb yanc canc +1.8v +3.3v +1.8v_a +1.8v +3.3v +3.3v vco_vcc +1.8v_a +1.8v_a +3.3v vco_vcc vco_vcc +1.8v_a GS1560A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 55 54 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 cp_vdd pdbuff_gnd pd_vdd buff_vdd cd1 ddi_1 term1 ddi_1 dvb_asi ipsel sd/hd 20bit/10bit ioproc_en/dis cd2 ddi_2 term2 ddi_2 smpte_bypass rset cd_vdd sdo_en/dis cd_gnd sdo sdo reset_trst jtag/host cs_tms sdout_tdo sdin_tdi sclk_tck data_error fifo_ld core_gnd f v h core_vdd dout0 dout1 io_gnd io_vdd dout2 dout3 dout4 dout5 dout6 dout7 dout8 io_gnd dout9 dout10 dout11 io_vdd dout13 dout12 dout14 dout15 dout16 dout17 io_gnd io_vdd dout18 dout19 core_vdd yanc canc fw_en/dis core_gnd pclk rc_byp master/slave locked vco vco vco_gnd vco_vcc lf cp_cap lb_cont cp_gnd 75 go1525 5 4 8 2 7 1 3 6 vctr gnd gnd gnd vcc o/p nc gnd 10n l 75 281 +/-1% 1u 1u c 0 bnc 10n 10n r l 2k2 10n r c 2k2 100n 2k2 10n 10n bnc 10n 4u7 10n 10n 0 39k2 1u 4u7 4k7 10n 2k2 1u 4u7 2n2 1u 10n 10n 75 10n 4k7 0 10n 10n 1u 10n f v h pclk data[19..0] ddi1 ddi1b ddi2b ddi2 cd1b cd2b dvb_asi sd/hdb reset_trstb data_errorb lock canc fifo_ldb yanc smpte_bypassb sclk_tck sdout_tdo sdin_tdi csb_tms master/slaveb rc_bypb jtag/hostb ipsel fw_en/disb sdo_en/disb 20bit/10bitb ioproc_en/disb note: to guarantee -15db output return loss at hd rates, it is recommended that the gs1528 multi-rate cable driver be used. r, l, c form the output return loss compensation network. values are subject to change. note: smpte_bypassb, sd/hdb, dvb_asi, and rc_bypb are inputs in slave mode (master/slaveb = low), and are outputs in master mode (master/slaveb = high). jtag/hostb ipsel fw_en/disb sdo_en/disb smpte_bypassb sd/hdb dvb_asi rc_bypb pclk data_errorb fifo_ldb lock fifo_ldb dvb_asi smpte_bypassb gnd_eq gnd_eq gnd_a gnd_a gnd_a gnd_a gnd_a gnd_d gnd_d gnd_d gnd_d gnd_a gnd_d gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco gnd_vco 4u7 4u7 4u7
gennum corporation 27360 - 2 54 of 55 GS1560A 5. references & relevant standards smpte 125m component video signal 4:2:2 ? bit parallel interface smpte 260m 1125 / 60 hi gh definition production system ? digital representation and bit parallel interface smpte 267m bit parallel digital interface ? compo nent video signal 4:2:2 16 x 9 aspect ratio smpte 274m 1920 x 1080 scanning analog and parallel digital interfaces for multiple picture rates smpte 291m ancillary data packet and space formatting smpte 292m bit-serial digital interface for high-definition television systems smpte 293m 720 x 483 active line at 59.94 hz prog ressive scan production ? digital representation smpte 296m 1280 x 720 scanning, analog and digital representation and analog interface smpte 352m video payload identificati on for digital television interfaces smpte rp165 error detection checkwords and status flags for use in bit-serial digital interfaces for television smpte rp168 definition of vertical interval s witching point for synchronous video switching 6. package & ordering information 6.1 package dimensions tolerances of form and position symbol min nom max min nom max millimeter inch 80l b e aaa ccc bbb d2 e2 0.22 0.65 bsc 0.026 bsc 12.35 0.20 0.20 0.10 0.008 0.008 0.004 0.486 0.486 12.35 0.30 0.38 0.009 0.012 0.015 notes: diagram shown is representative only. table x is fixed for all pin sizes, and table y is specific to the 80-pin package. table y ddd 0.13 0.005 table x control dimensions are in millimeters. 1. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 2. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages.
27360 - 2 55 of 55 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nishi shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ? copyright march 2003 gennum corporation. all rights reserved. printed in canada. GS1560A caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation document identification preliminary data sheet the product is in a preproduction phase and specifications are subject to change without notice. 6.2 ordering information part number package temperature range GS1560Acf 80-pin lqfp 0c to 70c 7. revision history version ecr date changes and/or modifications 0 128756 march 2003 new document 1 129161 april 2003 condensed front page description. edited pin descriptions and ac/dc characteristics tables. corrected host interface maps. added detailed descriptions of all major functional bl ocks. changed gspi timing diagrams. updated typical application ci rcuit. added reference list. 2 129633 july 2003 cleaned up host interface tables, added missing information, corrected pin names and other minor typos. added section 3.15.

▲Up To Search▲

Price & Availability of GS1560A

	To Download GS1560A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .