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independent clock quad hotlink ii? reclocking deserialize r CYV15G0404RB cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-02102 rev. *b revised july 8, 2005 features ? second-generation hotlink ? technology ? compliant to smpte 292 m and smpte 259m video standards ? quad channel video reclocking deserializer ? 195- to 1500-mbps serial data signaling rate ? simultaneous operation at different signaling rates ? supports reception of either 1.485 or 1.485/1.001 gbps data rate with the same training clock ? supports half-rate and full-rate clocking ? internal phase-locked loops (plls) with no external pll components ? selectable differential pecl-compatible serial inputs ? internal dc-restoration ? synchronous lvttl parallel interface ? jtag boundary scan ? built-in self-test (bist) for at-speed link testing ? link quality indicator ? analog signal detect ? digital signal detect ? low-power 3w @ 3.3v typical ? single 3.3v supply ? thermally enhanced bga ? pb-free package option available ?0.25 bicmos technology functional description the CYV15G0404RB inde pendent clock quad hotlink ii? deserializing reclocker is a point-to-point or point-to-multi- point communications building block enabling transfer of data over a variety of high-speed serial links including smpte 292 and smpte 259 video applications. it supports signaling rates in the range of 195 to 1500 mbps per serial link. the four channels are independent and can simultaneously operate at different rates. each receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an output register. the received serial data can also be reclocked and retransmitted through the reclocker serial outputs. figure 1 illustrates typical connections between independent video co-processors and corresponding CYV15G0404RB reclocking deserializer and cyv15g0403tb serializer chips. the CYV15G0404RB satisfies the smpte-259m and smpte-292m compliance as per smpte eg34-1999 patho- logical test requirements. as a second-generation hotlink device, the CYV15G0404RB extends the hotlink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and bist) with other hotlink devices. each channel of the CYV15G0404RB quad hotlink ii device accepts a serial bit-stream from one of two selectable pecl- compatible differential line receivers, and using a completely integrated clock and data recovery pll, recovers the timing information necessary for data reconstruction. the recovered bit-stream is reclocked and retransmitted through the reclocker serial outputs. also, the recovered serial data is deserialized and presented to the destination host system. each channel contains an independent bist pattern checker. this bist hardware allows at-speed testing of the high-speed serial data paths in each receive section of this device, each transmit section of a connected hotlink ii device, and across the interconnecting links. the CYV15G0404RB is ideal for smpte applications where different data rates and serial interface standards are necessary for each channel. some applications include multi- format routers, switchers, fo rmat converters, sdi monitors, and camera control units. figure 1. hotlink ii? system connections video coprocessor 10 10 10 10 video coprocessor 10 10 10 10 serial links independent cyv15g0403tb independent reclocking deserializer serializer channel CYV15G0404RB channel reclocked outputs reclocked outputs
CYV15G0404RB document #: 38-02102 rev. *b page 2 of 26 CYV15G0404RB deserializing reclocker logic block diagram x10 deserializer reclocker rx rxda[9:0] routa1 routa2 ina1 ina2 trgclka x10 deserializer reclocker rx rxdb[9:0] routb1 routb2 inb1 inb2 trgclkb x10 deserializer reclocker rx rxdc[9:0] routc1 routc2 inc1 inc2 trgclkc x10 deserializer reclocker rx rxdd[9:0] routd1 routd2 ind1 ind2 trgclkd
CYV15G0404RB document #: 38-02102 rev. *b page 3 of 26 reclocking deserializer path block diagram ina1+ ina1? ina2+ ina2? insela clock & data recovery pll shifter lfia 10 rxda[9:0] receive signal monitor output register rxclka+ rxclka? 2 rxpllpda spdsela ulca rxratea 10 bist lfsr 10 rxbista[1:0] ldtden sdasel[2..1]a[1:0] routa1+ routa1? routa2+ routa2? roe[2..1]a trgclka x2 trgratea biststa character-rate clock a reclocker reclkoa register recovered character clock recovered serial data repdoa clock multiplier a output pll roe[2..1]a inb1+ inb1? inb2+ inb2? inselb clock & data recovery pll shifter lfib 10 rxdb[9:0] receive signal monitor output register rxclkb+ rxclkb? 2 rxpllpdb spdselb ulcb rxrateb 10 bist lfsr 10 rxbistb[1:0] ldtden sdasel[2..1]b[1:0] routb1+ routb1? routb2+ routb2? roe[2..1]b trgclkb x2 trgrateb biststb character-rate clock b reclocker reclkob register recovered character clock recovered serial data repdob clock multiplier b output pll roe[2..1]b = internal signal jtag boundary scan controller tdo tms tclk tdi reset trst
CYV15G0404RB document #: 38-02102 rev. *b page 4 of 26 reclocking deserializer path block diagram (continued) = internal signal inc1+ inc1? inc2+ inc2? inselc clock & data recovery pll shifter lfic 10 rxdc[9:0] receive signal monitor output register rxclkc+ rxclkc? 2 rxpllpdc spdselc ulcc rxratec 10 bist lfsr 10 rxbistc[1:0] ldtden sdasel[2..1]c[1:0] routc1+ routc1? routc2+ routc2? roe[2..1]c trgclkc x2 trgratec biststc character-rate clock c reclocker reclkoc register recovered character clock recovered serial data repdoc clock multiplier c output pll roe[2..1]c ind1+ ind1? ind2+ ind2? inseld clock & data recovery pll shifter lfid 10 rxdd[9:0] receive signal monitor output register rxclkd+ rxclkd? 2 rxpllpdd spdseld ulcd rxrated 10 bist lfsr 10 rxbistd[1:0] ldtden sdasel[2..1]d[1:0] routd1+ routd1? routd2+ routd2? roe[2..1]d trgclkd x2 trgrated biststd character-rate clock d reclocker reclkod register recovered character clock recovered serial data repdod clock multiplier d output pll roe[2..1]d
CYV15G0404RB document #: 38-02102 rev. *b page 5 of 26 wren addr[3:0] data[7:0] device configuration and control block diagram = internal signal rxrate[a..d] rxbist[a..d] sdasel[a..d][1:0] rxpllpd[a..d] roe[2..1][a..d] glen[11..0] fglen[2..0] device configuration and control interface
CYV15G0404RB document #: 38-02102 rev. *b page 6 of 26 pin configuration (top view) [1] note: 1. nc = do not connect. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a in c1? rout c1? in c2? rout c2? v cc in d1? rout d1? gnd in d2? rout d2? in a1? rout a1? gnd in a2? rout a2? v cc in b1? rout b1? in b2? rout b2? b in c1+ rout c1+ in c2+ rout c2+ v cc in d1+ rout d1+ gnd in d2+ rout d2+ in a1+ rout a1+ gnd in a2+ rout a2+ v cc in b1+ rout b1+ in b2+ rout b2+ c tdi tms inselc inselb v cc ulcd ulcc gnd data [7] data [5] data [3] data [1] gnd v cc spd seld v cc ldtd en trst gnd tdo d tclk reset inseld insela v cc ulca spd selc gnd data [6] data [4] data [2] data [0] gnd gnd ulcb v cc nc v cc scan en2 tmen3 e v cc v cc v cc v cc v cc v cc v cc v cc f rx dc[8] rx dc[9] v cc v cc v cc rx db[0] re clkob rx db[1] g gnd wren gnd gnd spd selb nc spd sela rx db[3] h gnd gnd gnd gnd gnd gnd gnd gnd j gnd gnd gnd gnd bist stb rx db[2] rx db[7] rx db[4] k rx dc[4] trg clkc? gnd gnd rx db[5] rx db[6] rx db[9] lfib l rx dc[5] trg clkc+ lfic gnd rx db[8] rx clkb+ rx clkb? gnd m rx dc[6] rx dc[7] v cc re pdoc trg clkb+ trg clkb? re pdob gnd n gnd gnd gnd gnd gnd gnd gnd gnd p rx dc[3] rx dc[2] rx dc[1] rx dc[0] gnd gnd gnd gnd r bist stc re clkoc rx clkc+ rx clkc? v cc v cc v cc v cc t v cc v cc v cc v cc v cc v cc v cc v cc u v cc v cc v cc v cc v cc rx dd[4] rx dd[3] gnd gnd addr [0] trg clkd? gnd gnd gnd v cc v cc rx da[4] v cc bist sta rx da[0] v v cc v cc v cc rx dd[8] v cc rx dd[5] rx dd[1] gnd bist std addr [2] trg clkd+ re clkoa gnd gnd v cc v cc rx da[9] rx da[5] rx da[2] rx da[1] w v cc v cc lfid rx clkd? v cc rx dd[6] rx dd[0] gnd addr [3] addr [1] rx clka+ re pdoa gnd gnd v cc v cc lfia trg clka+ rx da[6] rx da[3] y v cc v cc rx dd[9] rx clkd+ v cc rx dd[7] rx dd[2] gnd re clkod nc gnd rx clka? gnd gnd v cc v cc re pdod trg clka? rx da[8] rx da[7]
CYV15G0404RB document #: 38-02102 rev. *b page 7 of 26 pin configuration (bottom view) [1] 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a rout b2? in b2? rout b1? in b1? v cc rout a2? in a2? gnd rout a1? in a1? rout d2? in d2? gnd rout d1? in d1? v cc rout c2? in c2? rout c1? in c1? b rout b2+ in b2+ rout b1+ in b1+ v cc rout a2+ in a2+ gnd rout a1+ in a1+ rout d2+ in d2+ gnd rout d1+ in d1+ v cc rout c2+ in c2+ rout c1+ in c1+ c tdo gnd trst ldtd en v cc spd seld v cc gnd data [1] data [3] data [5] data [7] gnd ulcc ulcd v cc inselb inselc tms tdi d tmen3 scan en2 v cc nc v cc ulcb gnd gnd data [0] data [2] data [4] data [6] gnd spd selc ulca v cc insela inseld reset tclk e v cc v cc v cc v cc v cc v cc v cc v cc f rx db[1] re clkob rx db[0] v cc v cc v cc rx dc[9] rx dc[8] g rx db[3] spd sela nc spd selb gnd gnd wren gnd h gnd gnd gnd gnd gnd gnd gnd gnd j rx db[4] rx db[7] rx db[2] bist stb gnd gnd gnd gnd k lfib rx db[9] rx db[6] rx db[5] gnd gnd trg clkc? rx dc[4] l gnd rx clkb? rx clkb+ rx db[8] gnd lfic trg clkc+ rx dc[5] m gnd re pdob trg clkb? trg clkb+ re pdoc v cc rx dc[7] rx dc[6] n gnd gnd gnd gnd gnd gnd gnd gnd p gnd gnd gnd gnd rx dc[0] rx dc[1] rx dc[2] rx dc[3] r v cc v cc v cc v cc rx clkc? rx clkc+ re clkoc bist stc t v cc v cc v cc v cc v cc v cc v cc v cc u rx da[0] bist sta v cc rx da[4] v cc v cc gnd gnd gnd trg clkd? addr [0] gnd gnd rx dd[3] rx dd[4] v cc v cc v cc v cc v cc v rx da[1] rx da[2] rx da[5] rx da[9] v cc v cc gnd gnd re clkoa trg clkd+ addr [2] bist std gnd rx dd[1] rx dd[5] v cc rx dd[8] v cc v cc v cc w rx da[3] rx da[6] trg clka+ lfia v cc v cc gnd gnd re pdoa rx clka+ addr [1] addr [3] gnd rx dd[0] rx dd[6] v cc rx clkd? lfid v cc v cc y rx da[7] rx da[8] trg clka? re pdod v cc v cc gnd gnd rx clka? gnd nc re clkod gnd rx dd[2] rx dd[7] v cc rx clkd+ rx dd[9] v cc v cc
CYV15G0404RB document #: 38-02102 rev. *b page 8 of 26 pin definitions CYV15G0404RB quad hotlink ii deserializing reclocker name i/o characteristics signal description receive path data and status signals rxda[9:0] rxdb[9:0] rxdc[9:0] rxdd[9:0] lvttl output, synchronous to the rxclk output parallel data output . rxdx[9:0] parallel data out puts change relative to the receive interface clock. if rxclkx is a full-rate clock, the rxclkx clock outputs are complementary clocks operating at th e character rate. the rxdx[9:0] outputs for the associated receive channels follow rising edge of rxclkx+ or falling edge of rxclkx?. if rxclkx is a half-rate clock, the rxclkx clock outputs are complementary clocks operating at half t he character rate. t he rxdx[9:0] outputs for the associated receive channels follow both the falling and rising edges of the associated rxclkx clock outputs. when bist is enabled on the receive c hannel, the bist status is presented on the rxdx[1:0] and biststx outputs. see table 5 for each status reported by the bist state machine. also, while bist is enabled, the rxdx[9:2] outputs should be ignored. biststa biststb biststc biststd lvttl output, synchronous to the rxclkx output bist status output. when rxbistx[1:0] = 10, bi ststx (along with rxdx[1:0]) displays the status of the bist reception. see table 5 for the bist status reported for each combination of biststx and rxdx[1:0]. when rxbistx[1:0] 10, biststx should be ignored. repdoa repdob repdoc repdod asynchronous to reclocker output channel enable / disable reclocker powered down status output. repdox is asserted high, when the associated channel?s reclocker output logic is powered down. this occurs when roe2x and roe1x are both disabled by setting roe2x = 0 and roe1x = 0. receive path clock signals trgclka trgclkb trgclkc trgclkd differential lvpecl or single-ended lvttl input clock cdr pll training clock . trgclkx clock inputs are used as the reference source for the frequency detector (range controller) of the associated receive pll to reduce pll acquisition time. in the presence of valid serial data, t he recovered clock output of the receive cdr pll (rxclkx) has no frequency or phase relationship with trgclkx. when driven by a single-ended lvcmos or lvttl clock source, connect the clock source to either the true or co mplement trgclkx input, and leave the alternate trgclkx input ope n (floating). w hen driven by an lvpecl clock source, the clock must be a differential clock, using both inputs. rxclka rxclkb rxclkc rxclkd lvttl output clock receive clock output . rxclkx is the receive interface clock used to control timing of the rxdx[9:0] parallel outputs . these true and co mplement clocks are used to control timing of data output transf ers. these clocks are output continu- ously at either the half-character rate (1/20 th the serial bit-rate) or character rate (1/10 th the serial bit-rate) of the data being received, as selected by rxratex. reclkoa reclkob reclkoc reclkod lvttl output reclocker clock output . reclkox output clock is synthesized by the associated reclocker output pll and o perates synchronous to the internal recovered character clock. reclkox oper ates at either the same frequency as rxclkx (rxratex = 0), or at twice the frequency of rxclkx (rxratex = 1).the reclocker clock outputs have no fixed phase relationship to rxclkx. device control signals reset lvttl input, asynchronous, internal pull-up asynchronous device reset . reset initializes all state machines, counters, and configuration latches in th e device to a known state. reset must be asserted low for a minimum pulse width. when the reset is removed, all state machines, counters and configuration latches are at an initial state. see table 3 for the initialize values of the device configuration latches.
CYV15G0404RB document #: 38-02102 rev. *b page 9 of 26 ldtden lvttl input, internal pull-up level detect transition density enable . when ldtden is high, the signal level detector, range controller, and transition density detector are all enabled to determine if the rxpll tracks trgclkx or the selected input serial data stream. if the signal level detector, range controller, or transition density detector are out of their respective limits while ldtden is high, the rxpll locks to trgclkx until such a time they become valid. the sdasel[a..d][1:0] inputs are used to configure the trip level of the signal level detector. the transition density detector limit is one transition in every 60 consecutive bits. when ldtden is low, only the range controller is used to determine if the rxpll tracks trgclkx or the selected input serial data stream. it is recommended to set ldtden = high. ulca ulcb ulcc ulcd lvttl input, internal pull-up use local clock . when ulcx is low, the rxpll is forced to lock to trgclkx instead of the received serial data stream. while ulcx is low, the lfix for the associated channel is low indicating a link fault. when ulcx is high, the rxpll performs clock and data recovery functions on the input data streams. this function is used in applications in which a stable rxclkx is needed. in cases when there is an absence of valid data transitions for a long period of time, or the high-gain differential serial inputs (inx) are left floating, there may be brief frequency e xcursions of the rxclkx outputs from trgclkx. spdsela spdselb spdselc spdseld 3-level select [2] static control input serial rate select . the spdselx inputs specify the operating signaling-rate range of each channel?s receive pll. low = 195 ? 400 mbd mid = 400 ? 800 mbd high = 800 ? 1500 mbd. insela inselb inselc inseld lvttl input, asynchronous receive input selector . the inselx input determines which external serial bit stream is passed to the receiver?s clock and data recovery circuit. when inselx is high, the primary differential serial data input, inx1, is selected for the associated receive channel. when inselx is low, the secondary differential serial data input, inx2, is selected for the associated receive channel. lfia lfib lfic lfid lvttl output, asynchronous link fault indication output . lfix is an output status indicator signal. lfix is the logical or of six internal conditions. lfix is asserted low when any of the following conditions is true: ? received serial data rate outside expected range ? analog amplitude below expected levels ? transition density lower than expected ? receive channel disabled ?ulcx is low ? absence of trgclkx. device configuration and control bus signals wren lvttl input, asynchronous, internal pull-up control write enable . the wren input writes the values of the data[7:0] bus into the latch specified by the add ress location on the addr[3:0] bus. [3] addr[3:0] lvttl input asynchronous, internal pull-up control addressing bus . the addr[3:0] bus is the input address bus used to configure the device. the wren input writes the values of the data[7:0] bus into the latch specified by the addre ss location on the addr[3:0] bus. [3] table 3 lists the configuration latches within the de vice, and the initialization value of the latches upon the assertion of reset . ta ble 4 shows how the latches are mapped in the device. notes: 2. 3-level select inputs are used for static configuration. these ar e ternary inputs that make use of logic levels of low, mid, and high. the low level is usually implemented by direct connection to v ss (ground). the high level is usually implemented by direct connection to v cc (power). the mid level is usually implemented by not connecting the input (left floating), which allows it to self bias to the proper level. 3. see device configuration and control interface for detailed information on the operation of the configuration interface. pin definitions (continued) CYV15G0404RB quad hotlink ii deserializing reclocker name i/o characteristics signal description
CYV15G0404RB document #: 38-02102 rev. *b page 10 of 26 data[7:0] lvttl input asynchronous, internal pull-up control data bus . the data[7:0] bus is the input data bus used to configure the device. the wren input writes the values of the data[7:0] bus into the latch specified by address location on the addr[3:0] bus. [3 ] table 3 lists the configu- ration latches within the device, and the initialization value of the latches upon the assertion of reset . table 4 shows how the latches are mapped in the device. internal device configuration latches rxrate[a..d] internal latch [4] receive clock rate select . sdasel[2..1][a..d] [1:0] internal latch [4] signal detect amplitude select . rxpllpd[a..d] internal latch [4] receive channel power control . rxbist[a..d][1:0] internal latch [4] receive bist disabled . roe2[a..d] internal latch [4] reclocker differential serial output driver 2 enable . roe1[a..d] internal latch [4] reclocker differential serial output driver 1 enable . glen[11..0] internal latch [4] global latch enable . fglen[2..0] internal latch [4] force global latch enable . factory test modes scanen2 lvttl input, internal pull-down factory test 2. scanen2 input is for factory testing only. this input may be left as a no connect, or gnd only. tmen3 lvttl input, internal pull-down factory test 3 . tmen3 input is for factory testing only. this input may be left as a no connect, or gnd only. analog i/o routa1 routb1 routc1 routd1 cml differential output primary differential serial data output . the routx1 pecl-compatible cml outputs (+3.3v referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be ac-coupled for pecl- compatible connections. routa2 routb2 routc2 routd2 cml differential output secondary differential serial data output . the routx2 pecl-compatible cml outputs (+3.3v referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be ac-coupled for pecl-compatible connections. ina1 inb1 inc1 ind1 differential input primary differential serial data input . the inx1 input accepts the serial data stream for deserialization. the inx1 serial stream is passed to the receive cdr circuit to extract the data content when inselx = high. ina2 inb2 inc2 ind2 differential input secondary differential serial data input . the inx2 input accepts the serial data stream for deserialization. the inx2 serial stream is passed to the receiver cdr circuit to extract the dat a content when inselx = low. jtag interface tms lvttl input, internal pull-up test mode select . used to control access to the jtag test modes. if maintained high for 5 tclk cycles, the jtag test controller is reset. tclk lvttl input, internal pull-down jtag test clock . tdo 3-state lvttl output test data out . jtag data output buffer. high-z while jtag test mode is not selected. tdi lvttl input, internal pull-up test data in . jtag data input port. trst lvttl input, internal pull-up jtag reset signal . when asserted (low), this input asynchronously resets the jtag test access port controller. note: 4. see device configuration and control interface for detailed information on the internal latches. pin definitions (continued) CYV15G0404RB quad hotlink ii deserializing reclocker name i/o characteristics signal description
CYV15G0404RB document #: 38-02102 rev. *b page 11 of 26 CYV15G0404RB hotlink ii operation the CYV15G0404RB is a highly configurable, independent clocking, quad-channel reclocking deserializer designed to support reliable transfer of large quantities of digital video data, using high-speed serial links from multiple sources to multiple destinations. this device supports four 10-bit channels. CYV15G0404RB receive data path serial line receivers two differential line receivers, inx1 and inx2, are available on each channel for accepting serial data streams. the active serial line receiver on a channel is selected using the associated inselx input. the serial line receiver inputs are differential, and can accommodate wire interconnect and filtering losses or transmissi on line attenuation greater than 16 db. for normal operation, these inputs should receive a signal of at least vi diff > 100 mv, or 200 mv peak-to-peak differential. each line receiver can be dc- or ac-coupled to +3.3v powered fiber-optic interface modules (any ecl/pecl family, not limited to 100k pecl) or ac-coupled to +5v powered optical modules. the common-mode tolerance of these line receivers accommodates a wide range of signal termination voltages. each receiver provides internal dc- restoration, to the center of the receiver?s common mode range, for ac-coupled signals. signal detect/link fault each selected line receiver (i.e., that routed to the clock and data recovery pll) is simultaneously monitored for ? analog amplitude above amplitude level selected by sdaselx ? transition density above the specified limit ? range controls report the received data stream inside normal frequency range (1500 ppm [21] ) ? receive channel enabled ? presence of reference clock ?ulcx is not asserted. all of these conditions must be valid for the signal detect block to indicate a valid signal is present. this status is presented on the lfix (link fault indicator) output associated with each receive channel, which changes synchronous to the receive interface clock. analog amplitude while most signal monitors are based on fixed constants, the analog amplitude level detection is adjustable to allow operation with highly attenuated signals, or in high-noise environments. the analog amplitude level detection is set by the sdaselx latch via device configuration interface. the sdaselx latch sets the trip point for the detection of a valid signal at one of three levels, as listed in table 1 . this control input affects the analog monitors for all receive channels. the analog signal detect monitors are active for the line receiver as selected by the associated inselx input. transition density the transition detection logi c checks for the absence of transitions spanning greater than six transmission characters (60 bits). if no transitions are present in the data received, the detection logic for that channel asserts lfix . range controls the cdr circuit includes logic to monitor the frequency of the pll voltage controlled oscillator (vco) used to sample the incoming data stream. this logic ensures that the vco operates at, or near the rate of the incoming data stream for two primary cases: ? when the incoming data stream resumes after a time in which it has been ?missing.? ? when the incoming data stream is outside the acceptable signaling rate range. to perform this function, the frequency of the rxpll vco is periodically compared to the frequency of the trgclkxinput. if the vco is running at a frequency beyond 1500 ppm [21] as defined by the trgclkx frequency, it is periodically forced to the correct frequency (as defined by trgclkx, spdselx, and trgratex) and then released in an attempt to lock to the input data stream. the sampling and relock period of the range control is calcu- lated as follows: range_control_ sampling_period = (recovered byte cloc k period) * (4096). during the time that the range control forces the rxpll vco to track trgclkx, the lfix output is asserted low. after a valid serial data stream is applied, it may take up to one range control sampling period before the pll locks to the input data st ream, after which lfix should be high. power v cc +3.3v power . gnd signal and power ground for all internal circuits . pin definitions (continued) CYV15G0404RB quad hotlink ii deserializing reclocker name i/o characteristics signal description table 1. analog amplitude detect valid signal levels [5] sdasel typical signal with peak amplitudes above 00 analog signal detector is disabled 01 140 mv p-p differential 10 280 mv p-p differential 11 420 mv p-p differential note: 5. the peak amplitudes listed in this table are for typical wa veforms that have generally 3?4 trans itions for every ten bits. in a worse case environment the signals may have a sine-wave appearance (highest tr ansition density with repeating 0101...). signal peak amplitudes levels within this environment type could increase the values in the table above by approximately 100 mv.
CYV15G0404RB document #: 38-02102 rev. *b page 12 of 26 the operating serial signaling-rate and allowable range of trgclk frequencies are listed in table 2 . receive channel enabled the CYV15G0404RB contains four receive channels that can be independently enabled and disabled. each channel can be enabled or disabled separately through the rxpllpdx input latch as controlled by the device configuration interface. when the rxpllpdx latch = 0, the associated pll and analog circuitry of the channel is disabled. any disabled channel indicates a constant link fault condition on the lfix output. when rxpllpdx = 1, the associated pll and receive channel is enabled to receive a serial stream. note . when a disabled receive channel is reenabled, the status of the associated lfix output and data on the parallel outputs for the associated channel may be indeterminate for up to 2 ms. clock/data recovery the extraction of a bit-rate clock and recovery of bits from each received serial stream is performed by a separate cdr block within each receive channel. the clock extraction function is performed by an integrated pll that tracks the frequency of the transitions in the incoming bit stream and align the phase of the internal bit-rate clock to the transitions in the selected serial data stream. each cdr accepts a character-rate (bit-rate 10) or half- character-rate (bit-rate 20) training clock from the associated trgclkx input. this trgclkx input is used to ? ensure that the vco (within the cdr) is operating at the correct frequency (rather than a harmonic of the bit-rate) ? reduce pll acquisition time ? limit unlocked frequency excursions of the cdr vco when there is no input data present at the selected serial line receiver. regardless of the type of signa l present, the cdr attempts to recover a data stream from it. if the signalling rate of the recovered data stream is outside the limits set by the range control monitors, the cdr tracks trgclkx instead of the data stream. once the cdr output (rxclk) frequency returns back close to trgclkx frequency, the cdr input is switched back to the input data stream. if no data is present at the selected line receiver, this switching behavior may result in brief rxclk frequency excursions from trgclkx. however, the validity of the in put data stream is indicated by the lfix output. the frequency of trgclkx is required to be within 1500ppm [21] of the frequency of the clock that drives the reference clock input of the remote transmitter to ensure a lock to the incoming data stream. this large ppm tolerance allows the cdr pll to reliably receive a 1.485 or 1.485/1.001 gbps smpte hd-sdi data stream with a constant trgclk frequency. for systems using multiple or redundant connections, the lfix output can be used to select an alternate data stream. when an lfix indication is detected, external logic can toggle selection of the associated inx1 and inx2 input through the associated inselx input. when a port switch takes place, it is necessary for the receive pll for that channel to reacquire the new serial stream. reclocker each receive channel performs a reclocker function on the incoming serial data. to do this, the clock and data recovery pll first recovers the clock from the data. the data is retimed by the recovered clock and then passed to an output register. also, the recovered character clock from the receive pll is passed to the reclocker output pll which generates the bit clock that is used to clock the retimed data into the output register. this data stream is then transmitted through the differential serial outputs. reclocker serial output drivers the serial output interface dr ivers use differential current mode logic (cml) drivers to provide source-matched drivers for 50 ? transmission lines. these drivers accept data from the reclocker output register in the reclocker channel. these drivers have signal swings equivalent to that of standard pecl drivers, and are capable of driving ac-coupled optical modules or transmission lines. reclocker output channels enabled each driver can be enabled or disabled separately via the device configuration interface. when a driver is disabled via t he configuration interface, it is internally powered down to reduce device power. if both reclocker serial drivers for a channel are in this disabled state, the associated inter nal reclocker logic is also powered down. the deserialization logic and parallel outputs will remain enabled. a devi ce reset (reset sampled low) disables all output drivers. note . when the disabled reclocker function (i.e., both outputs disabled) is re-enabled, the data on the reclocker serial outputs may not meet all timing specifications for up to 250 s. output bus each receive channel presents a 10-bit data signal (and a bist status signal when rxbistx[1:0] = 10). receive bist operation each receiver channel contains an internal pattern checker that can be used to validate both device and link operation. these pattern checkers are enabled by the associated rxbistx[1:0] latch via the dev ice configuration interface. when enabled, a register in the associated receive channel becomes a signature pattern generator and checker by logically converting to a linear feedback shift register (lfsr). this lfsr generates a 511-character sequence. this provides a predictable yet ps eudo-random sequence that can be matched to an identical lfsr in the attached trans- mitter(s). when synchronized with the received data stream, the associated receiver che cks each character from the table 2. operating speed settings spdselx trgratex trgclkx frequency (mhz) signaling rate (mbps) low 1 reserved 195?400 0 19.5?40 mid (open) 1 20?40 400?800 0 40?80 high 1 40?75 800?1500 0 80?150
CYV15G0404RB document #: 38-02102 rev. *b page 13 of 26 deserializer with each character generated by the lfsr and indicates compare errors and bist status at the rxdx[1:0] and biststx bits of the output register. the bist status bus {biststx, rxdx[0], rxdx[1]} indicates 010b or 100b for one character period per bist loop to indicate loop completion. this status can be used to check test pattern progress. the specific status reported by the bist state machine is listed in ta ble 5 . these same codes are reported on the receive status outputs. if the number of invalid characters received ever exceeds the number of valid characters by 16, the receive bist state machine aborts the compare operations and resets the lfsr to look for the start of the bist sequence again. a device reset (reset sampled low) presets the bist enable latches to disable bist on all channels. bist status state machine when a receive path is enabled to look for and compare the received data stream with the bist pattern, the {biststx, rxdx[0], rxdx[1]} bits identify the present state of the bist compare operation. the bist state machine has multiple states, as shown in figure 2 and table 5 . when the receive pll detects an out-of- lock condition, the bist state is forced to the start-of-bist state, regardless of the pres ent state of the bist state machine. if the number of detected errors ever exceeds the number of valid matches by greater than 16, the state machine is forced to the wait_for_bist state where it monitors the receive path for the first character of the next bist sequence. power control the CYV15G0404RB supports user control of the powered up or down state of each transmit and receive channel. the receive channels are controlled by the rxpllpdx latch via the device configuration interface. when rxpllpdx = 0, the associated pll and analog circuitry of the channel is disabled. the transmit channels are co ntrolled by the oe1x and the oe2x latches via the device configuration interface. the reclocker function is controlled by the roe1x and the roe2x latches via the device configuration interface. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. when the reclocker serial drivers are disabled, the reclocker function will be disabled, but the deserialization logic and parallel outputs will remain enabled. device reset state when the CYV15G0404RB is reset by assertion of reset , all state machines, counters, and configuration latches in the device are initialized to a reset state. see table 3 for the initialize values of the configuration latches. following a device reset, it is necessary to enable the receive channels used for normal operation. this can be done by sequencing the appropriate valu es on the device configuration interface. [3] device configuration and control interface the CYV15G0404RB is highly c onfigurable via the configu- ration interface. the configurat ion interface allows the device to be configured globally or allows each channel to be configured independently. table 3 lists the configuration latches within the device including the initialization value of the latches upon the assertion of reset . table 4 shows how the latches are mapped in the device. each row in the table 4 maps to a 8-bit latch bank. ther e are 16 such write-only latch banks. when wren = 0, the logic value in the data[7:0] is latched to the latch bank specifie d by the values in addr[3:0]. the second column of table 4 specifies the channels associated with the corresponding latch bank. for example, the first three latch banks (0,1 and 2) consist of configuration bits for channel a. the latch banks 12, 13 and 14 consist of global configuration bits and the last latch bank (15) is the mask latch bank that can be co nfigured to perform bit-by-bit configuration. global enable function the global enable function, cont rolled by the glenx bits, is a feature that can be used to reduce the number of write opera- tions needed to setup the latch banks. this function is beneficial in system s that use a common configuration in multiple channels. the glenx bit is present in bit 0 of latch banks 0 through 11 only. its default value (1) enables the global update of the latch bank's contents. setting the glenx bit to 0 disables this functionality. latch banks 12, 13, and 14 are used to load values in the related latch banks in a global manner. a write operation to latch bank 12 could do a global write to latch banks 0, 3, 6, and 9 depending on the value of glenx in these latch banks; latch bank 13 could do a global write to latch banks 1, 4, 7 and 10; and latch banks 14 could do a global write to latch banks 2, 5, 8 and 11. the glenx bit cannot be modified by a global write operation. force global enable function fglenx forces the global update of the target latch banks, but does not change the contents of the glenx bits. if fglenx = 1 for the associated global channel, fglenx forces the global update of the target latch banks. mask function an additional latch bank (15) is used as a global mask vector to control the update of the c onfiguration latch banks on a bit- by-bit basis. a logic 1 in a bit location allows for the update of that same location of the target latch bank(s), whereas a logic 0 disables it. the reset value of this latch bank is ffh, thereby making its use optional by default. the mask latch bank is not maskable. the fglen functionality is not affected by the bit 0 value of the mask latch bank. latch types there are two types of latch banks: static (s) and dynamic (d). each channel is configured by 2 static and 1 dynamic latch banks. the s type contain those settings that normally do not change for a given application, whereas the d type controls the settings that could change during the applicat ion's lifetime. the first and second rows of each channel (address numbers 0, 1, 3, 4, 6, 7, 9, and 10) ar e the static control latches. the third row of latches for each channel (address numbers 2, 5,
CYV15G0404RB document #: 38-02102 rev. *b page 14 of 26 8, and 11) are the dynamic cont rol latches that are associated with enabling dynamic functions within the device. latch bank 14 is also useful for those users that do not need the latch-based programmable feature of the device. this latch bank could be used in thos e applications that do not need to modify the default value of the static latch banks, and that can afford a global (i.e., not independent) control of the dynamic signals. in this case, this feature becomes available when addr[3:0] is left unchanged with a value of ?1110? and wren is left asserted. the signals present in data[7:0] effec- tively become global control pins, and for the latch banks 2, 5, 8 and 11. static latch values there are some latches in the table that have a static value (ie. 1, 0, or x). the latches that have a ?1? or ?0? must be configured with their corresponding value each time that their associated latch bank is configured. the la tches that have an ?x? are don?t cares and can be configured with any value table 3. device configuration and control latch descriptions name signal description rxratea rxrateb rxratec rxrated receive clock rate select . the initialization value of the rxratex latch = 1. rx ratex is used to select the rate of the rxclkx clock output. when rxratex = 1, the rxclkx clock outputs ar e complementary clocks th at follow the recovered clock operating at half the character rate. data for the associated receive channels should be latched alternately on the rising edge of rxclkx+ and rxclkx?. when rxratex = 0, the rxclkx clock outputs ar e complementary clocks th at follow the recovered clock operating at the character rate. data for the associated receive channels should be latched on the rising edge of rxclkx+ or falling edge of rxclkx?. sdasel1a[1:0] sdasel1b[1:0] sdasel1c[1:0] sdasel1d[1:0] primary serial data input sign al detector amplitude select . the initialization value of the sdasel1x[1:0] latch = 10. sdasel1x[1:0] selects the trip point for the detection of a valid signal for the inx1 primary differential serial data inputs. when sdasel1x[1:0] = 00, the analog signal detector is disabled. when sdasel1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mv. when sdasel1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mv. when sdasel1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mv. sdasel2a[1:0] sdasel2b[1:0] sdasel2c[1:0] sdasel2d[1:0] secondary serial data input signal detector amplitude select . the initialization value of the sdasel2x[1:0] latch = 10. sdasel2x[1:0] selects the trip point for the detection of a valid signal for the inx2 secondary differential serial data inputs. when sdasel2x[1:0] = 00, the analog signal detector is disabled when sdasel2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mv. when sdasel2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mv. when sdasel2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mv. trgratea trgrateb trgratec trgrated training clock rate select . the initialization value of the trgratex latch = 0. trgratex is used to select the clock multiplier for the training clock inpu t to the associated cdr pll. when trgratex = 0, the associated trgclkx input is not multiplied before it is passed to the cdr pll. when trgratex = 1, the trgclkx input is multiplied by 2 before it is passed to the cdr pll. trgratex = 1 and spdselx = low is an invalid state and this combination is reserved. rxpllpda rxpllpdb rxpllpdc rxpllpdd receive channel enable . the initialization value of the rxpllpdx latch = 0. rxpllpdx selects if the associated receive channel is enabled or powered- down. when rxpllpdx = 0, the associated receive pll and analog circuitry are powered-down. when rxpllpdx = 1, the associated receive pll and analog circuitry are enabled. rxbista[1:0] rxbistb[1:0] rxbistc[1:0] rxbistd[1:0] receive bist disable / smpte receive enable . the initialization value of the rxbistx[1:0] latch = 11. for smpte data reception, rxbistx[1:0] should not rema in in this initialization state (11). rxbistx[1:0] selects if receive bist is disabled or enabled and sets the associated channel for smpte data reception. when rxbistx[1:0] = 01, the receiver bist functi on is disabled and the associated channel is set to receive smpte data. when rxbistx[1: 0] = 10, the receive bist functi on is enabled and the associated channel is set to receive bist data. rxbistx[1:0] = 00 and rxbistx[1:0] = 11 are invalid states. roe2a roe2b roe2c roe2d reclocker secondary differential serial data output driver enable . the initialization value of the roe2x latch = 0. roe2x selects if the rout2 se condary differential output drivers are enabled or disabled. when roe2x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. when roe2x = 0, the associated serial data output driver is disabled. when a driver is disabled via the c onfiguration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. a device reset (r eset sampled low) disables all output drivers.
CYV15G0404RB document #: 38-02102 rev. *b page 15 of 26 device configuration strategy the following is a series of ordered events needed to load the configuration latches on a per channel basis: 1. pulse reset low after device power-up. this operation resets all four channels. 2. set the static latch banks for the target channel. may be performed using a global oper ation, if the application permits it. [optional step if the default settings match the desired configuration.] 3. set the dynamic bank of latches for the target channel. enable the receive plls and set each channel for smpte data reception (rxbistx[1:0] = 01) or bist data reception (rxbistx[1:0] = 10). may be performed using a global operation, if the applicatio n permits it. [required step.] roe1a roe1b roe1c roe1d reclocker primary differential se rial data output driver enable . the initialization value of the roe1x latch = 0. roe1x selects if the rout1 primary differ ential output drivers are enabled or disabled. when roe1x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. when roe1x = 0, the associated serial data output driver is disabled. when a driver is disabled via the configuration interface, it is internally powered down to reduce device power. if both serial drivers for a channel are in this disabled state, the asso ciated internal logic for that channel is also powered down. a device reset (reset sampled low) disables a ll output drivers. glen[11..0] global enable . the initialization value of the glenx latch = 1. the glenx is used to reconfigure several channels simultaneously in applications where severa l channels may have the same configuration. when glenx = 1 for a given address, that address is allowe d to participate in a gl obal configuration. when glenx = 0 for a given address, that address is disabl ed from participating in a global configuration. fglen[2..0] force global enable . the initialization value of the fglenx latch is na. the fglenx latch forces a global enable no matter what the setting is on the glen x latch. if fglenx = 1 for the associated global channel, fglen forces the global u pdate of the target latch banks. table 3. device configuration and control latch descriptions (continued) name signal description table 4. device control latch configuration table addr channel type data7 data6 data5 data4 data3 data2 data1 data0 reset value 0 (0000b) a s 1 0 x x 0 0 rxratea glen0 10111111 1 (0001b) a s sdasel2a[1] sdasel2a[0] sdasel1a[1] sdasel1a[0] x x trgratea glen1 10101101 2 (0010b) a d rxbista[1] rxpllpda rxbista[0] x roe2a roe1a x glen2 10110011 3 (0011b) b s 1 0 x x 0 0 rxrateb glen3 10111111 4 (0100b) b s sdasel2b[1] sdasel2b[0] sdasel1b[1] sdasel1b[0] x x trgrateb glen4 10101101 5 (0101b) b d rxbistb[1] rxpllpdb rxbistb[0] x roe2b roe1b x glen5 10110011 6 (0110b) c s 1 0 x x 0 0 rxratec glen6 10111111 7 (0111b) c s sdasel2c[1] sdasel2c[0] sdasel1c[1] sdasel1c[0] x x trgratec glen7 10101101 8 (1000b) c d rxbistc[1] rxpllpdc rxbistc[0] x roe2c roe1c x glen8 10110011 9 (1001b) d s 1 0 x x 0 0 rxrated glen9 10111111 10 (1010b) d s sdasel2d[1] sdasel2d[0] sdasel1d[1] sdasel1d[0] x x trgrated glen10 10101101 11 (1011b) d d rxbistd[1] rxpllpdd rxbistd[0] x roe2d roe1d x glen11 10110011 12 (1100b) global s 1 0 x x 0 0 rxrategl fglen0 n/a 13 (1101b) global s sdasel2gl[1] sdasel2gl[0] sdasel1gl[1] sdasel1gl[0] x x trgrategl fglen1 n/a 14 (1110b) global d rxbistgl[1] rxpllpdgl rxbistgl[0] x roe2gl roe1gl x fglen2 n/a 15 (1111b) mask d d7 d6 d5 d4 d3 d2 d1 d0 11111111
CYV15G0404RB document #: 38-02102 rev. *b page 16 of 26 jtag support the CYV15G0404RB contains a jtag port to allow system level diagnosis of device interconnect. of the available jtag modes, boundary scan, and bypass are supported. this capability is present only on the lvttl inputs and outputs and the trgclkx clock input. the high-speed serial inputs and outputs are not part of the jtag test chain. 3-level select inputs each 3-level select inputs reports as two bits in the scan register. these bits report t he low, mid, and high state of the associated input as 00, 10, and 11 respectively jtag id the jtag device id for the CYV15G0404RB is ?0c811069?x. table 5. receive bist status bits {biststx, rxdx[0], rxdx[1]} description receive bist status (receive bist = enabled) 000, 001 bist data compare . character compared correctly. 010 bist last good . last character of bist sequence detected and valid. 011 reserved. 100 bist last bad . last character of bist sequence detected invalid. 101 bist start . receive bist is enabled on this channel, but character compares have not yet commenced. this also indicates a pll out of lock condition. 110 bist error . while comparing characters, a mismatch was found in one or more of the character bits. 111 bist wait . the receiver is comparing characters. but ha s not yet found the start of bist character to enable the lfsr.
CYV15G0404RB document #: 38-02102 rev. *b page 17 of 26 receive bist detected low monitor data received {biststx, rxdx[0], no rx pll out of lock yes, {biststx, rxdx[0], rxdx[1]} = bist_data_comp are (000, 001) compare next character auto-abort condition mismatch end-of-bist state yes, {biststx, rxdx[0], rxdx[1]} = bist_last_bad (100) yes no no, {biststx, rxdx[0], rxdx[1]} = bist_error (110) match end-of-bist state yes, {biststx, rxdx[0], rxdx[1]} = bist_last_g ood (010) no {biststx, rxdx[0], rxdx[1]} = bist_data_compare (000, 001) figure 2. receive bist state machine start of bist detected {biststx, rxdx[0], rxdx[1]} = bist_wait (111) bist_start (101) rxdx[1]} =
CYV15G0404RB document #: 38-02102 rev. *b page 18 of 26 maximum ratings above which the useful life may be impaired. user guidelines only, not tested storage temperature .............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ............... ?0.5v to +3.8v dc voltage applied to lvttl outputs in high-z state .......................................?0.5v to v cc + 0.5v output current into lvttl outputs (low)..................60 ma dc input voltage....................................?0.5v to v cc + 0.5v static discharge voltage.......................................... > 2000 v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma power-up requirements the CYV15G0404RB requires one power supply. the voltage on any input or i/o pin cannot exceed the power pin during power-up. operating range range ambient temperature v cc commercial 0c to +70c +3.3v 5% CYV15G0404RB dc electrical characteristics parameter description test conditions min. max. unit lvttl-compatible outputs v oht output high voltage i oh = ? 4 ma, v cc = min. 2.4 v v olt output low voltage i ol = 4 ma, v cc = min. 0.4 v i ost output short circuit current v out = 0v [6] , v cc = 3.3v ?20 ?100 ma i ozl high-z output leakage current v out = 0v, v cc ?20 20 a lvttl-compatible inputs v iht input high voltage 2.0 v cc + 0.3 v v ilt input low voltage ?0.5 0.8 v i iht input high current trgclkx input, v in = v cc 1.5 ma other inputs, v in = v cc +40 a i ilt input low current trgclkx input, v in = 0.0v ?1.5 ma other inputs, v in = 0.0v ?40 a i ihpdt input high current with internal pull-down v in = v cc +200 a i ilput input low current with internal pull-up v in = 0.0v ?200 a lvdiff inputs: trgclkx v diff [7] input differential voltage 400 v cc mv v ihhp highest input high voltage 1.2 v cc v v illp lowest input low voltage 0.0 v cc /2 v v comref [8] common mode range 1.0 v cc ? 1.2v v 3-level inputs v ihh three-level input high voltage min. v cc max. 0.87 * v cc v cc v v imm three-level input mid voltage min. v cc max. 0.47 * v cc 0.53 * v cc v v ill three-level input low voltage min. v cc max. 0.0 0.13 * v cc v i ihh input high current v in = v cc 200 a i imm input mid current v in = v cc /2 ?50 50 a i ill input low current v in = gnd ?200 a differential cml seri al outputs: routa1 , routa2 , routb1 , routb2 , routc1 , routc2 , routd1 , routd2 v ohc output high voltage (v cc referenced) 100 ? differential load v cc ? 0.5 v cc ? 0.2 v 150 ? differential load v cc ? 0.5 v cc ? 0.2 v v olc output low voltage (v cc referenced) 100 ? differential load v cc ? 1.4 v cc ? 0.7 v 150 ? differential load v cc ? 1.4 v cc ? 0.7 v notes: 6. tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 7. this is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. a logic-1 exists when the true (+) input is more positive than the complement ( ? ) input. a logic-0 exists when the complement ( ? ) input is more positive than true (+) input. 8. the common mode range defines the allo wable range of trgclkx+ and trgclkx ? when trgclkx+ = trgclkx ? . this marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0.
CYV15G0404RB document #: 38-02102 rev. *b page 19 of 26 v odif output differential voltage |(out+) ? (out ? )| 100 ? differential load 450 900 mv 150 ? differential load 560 1000 mv differential serial line receiver inputs: ina1 , ina2 , inb1 , inb2 , inc1 , inc2 , ind1 , ind2 v diffs [7] input differential voltage |(in+) ? (in ? )| 100 1200 mv v ihe highest input high voltage v cc v v ile lowest input low voltage v cc ? 2.0 v i ihe input high current v in = v ihe max. 1350 a i ile input low current v in = v ile min. ?700 a vi com [9] common mode input range ((v cc ? 2.0v)+0.5)min, (v cc ? 0.5v) max. +1.25 +3.1 v power supply typ. max. i cc [10,11] max power supply current trgclkx = max commercial 910 1270 ma industrial 1320 ma i cc [10,11] typical power supply current trgclkx = 125 mhz commercial 900 1270 ma industrial 1320 ma CYV15G0404RB dc electrical characteristics (continued) parameter description test conditions min. max. unit ac test loads and waveforms 2.0v 0.8v gnd 2.0v 0.8v 80% 20% 80% 20% r l (includes fixture and probe capacitance) 3.0v v th =1.4v 270 ps 270 ps [13] v th =1.4v 3.3v r1 r2 r1 = 590 ? r2 = 435 ? (includes fixture and probe capacitance) c l 7 pf (a) lvttl output test load r l = 100 ? (b) cml output test load c l (c) lvttl input test waveform (d) cml/lvpecl input test waveform 1ns 1 ns v ihe v ile v ihe v ile [12] [12] CYV15G0404RB ac electrical characteristics parameter description min. max unit CYV15G0404RB receiver lvttl switching characteristics over the operating range f rs rxclkx clock output frequency 9.75 150 mhz t rxclkp rxclkx period = 1/f rs 6.66 102.56 ns t rxclkd rxclkx duty cycle centered at 50% (full rate and half rate) ?1.0 +1.0 ns t rxclkr [14] rxclkx rise time 0.3 1.2 ns t rxclkf [14] rxclkx fall time 0.3 1.2 ns notes: 9. the common mode range defines the allowable range of input+ and input ? when input+ = input ? . this marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. 10. maximum i cc is measured with v cc = max, t a = 25c, with all channels and serial line drivers ena bled, sending a continuous alternating 01 pattern, and outputs unloaded. 11. typical i cc is measured under similar conditions except with v cc = 3.3v, t a = 25c, with all channels enabled and one serial line driver per transmit channel sending a continuous alternating 01 pattern. the redundant outputs on each channel are powered down and the parallel outputs ar e unloaded. 12. cypress uses constant current (ate) load configurations and forcing functions. this figure is for reference only. 13. the lvttl switching threshold is 1.4v. all timing references are made relative to where the signal edges cross the threshold voltage. 14. tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
CYV15G0404RB document #: 38-02102 rev. *b page 20 of 26 t rxdv? [18] status and data valid time to rxclkx (rxratex = 0) (full rate) 5ui?2.0 [19] ns status and data valid time to rxclkx (rxratex = 1) (half rate) 5ui?1.3 [19] ns t rxdv+ [18] status and data valid time to rxclkx (rxratex = 0) 5ui?1.8 [19] ns status and data valid time to rxclkx (rxratex = 1) 5ui?2.6 [19] ns f ros reclkox clock frequency 19.5 150 mhz t reclko reclkox period=1/f ros 6.66 51.28 ns t reclkod reclkox duty cycle centered at 60% high time ?1.9 0 ns CYV15G0404RB trgclkx switching characteristics over the operating range f trg trgclkx clock frequency 19.5 150 mhz trgclk trgclkx period = 1/f ref 6.6 51.28 ns t trgh trgclkx high time (trgratex = 1)(half rate) 5.9 ns trgclkx high time (trgratex = 0)(full rate) 2.9 [14] ns t trgl trgclkx low time (trgratex = 1)(half rate) 5.9 ns trgclkx low time (trgratex = 0)(full rate) 2.9 [14] ns t trgd [20] trgclkx duty cycle 30 70 % t trgr [14, 15, 16, 17] trgclkx rise time (20%?80%) 2 ns t trgf [14, 15, 16, 17] trgclkx fall time (20%?80%) 2 ns t trgrx [21] trgclkx frequency referenced to received clock frequency ?0.15 +0.15 % CYV15G0404RB bus configuration write timing characteristics over the operating range t datah bus configuration data hold 0 ns t datas bus configuration data setup 10 ns t wrenp bus configuration wren pulse width 10 ns CYV15G0404RB jtag test clock characteristics over the operating range f tclk jtag test clock frequency 20 mhz t tclk jtag test clock period 50 ns CYV15G0404RB device reset characteristics over the operating range t rst device reset pulse width 30 ns CYV15G0404RB reclocker serial output characteristics over the operating range parameter description condition min. max. unit t b bit time 5128 660 ps t rise [14] cml output rise time 20 ? 80% (cml test load) spdselx = high 50 270 ps spdselx = mid 100 500 ps spdselx =low 180 1000 ps t fall [14] cml output fall time 80 ? 20% (cml test load) spdselx = high 50 270 ps spdselx = mid 100 500 ps spdselx =low 180 1000 ps notes: 15. the ratio of rise time to falling time must not vary by greater than 2:1. 16. for a given operating frequency, neither rise or fall specific ation can be greater than 20% of the clock-cycle period or the data sheet maximum time. 17. all transmit ac timing parameters measur ed with 1ns typical rise time and fall time. 18. parallel data output specifications are only valid if all outputs are loaded with similar dc and ac loads. 19. receiver ui (unit interval) is calculated as 1/(f trg * 20) (when trgratex = 1) or 1/(f trg * 10) (when trgratex = 0). in an operating link this is equivalent to t b . 20. the duty cycle specification is a simultaneous condition with the t refh and t refl parameters. this means that at fast er character rates the trgclkx duty cycle cannot be as large as 30%?70%. 21. trgclkx has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. trgclkx must be within 1500 ppm ( 0.15%) of the transmitter pll reference (refclkx) frequency. although transmitti ng to a hotlink ii receiver channel necessitates the frequency difference betw een the transmitter and receiver reference clocks to be within 1500-ppm, the stabili ty of the crystal needs to be within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standa rd. CYV15G0404RB ac electrical characteristics (continued) parameter description min. max unit
CYV15G0404RB document #: 38-02102 rev. *b page 21 of 26 pll characteristics parameter description condition min .typ.max.unit CYV15G0404RB reclocker output pll characteristics t jrgensd [14, 22] reclocker jitter generation - sd data rate trgclkx = 27 mhz 133 ps t jrgenhd [14, 22] reclocker jitter generation - hd data rate trgclkx = 148.5 mhz 107 ps CYV15G0404RB receive pll characteristics over the operating range t rxlock receive pll lock to input data stream (cold start) 376k ui receive pll lock to input data stream 376k ui t rxunlock receive pll unlock rate 46 ui capacitance [14] parameter description test conditions max. unit c inttl ttl input capacitance t a = 25c, f 0 = 1 mhz, v cc = 3.3v 7 pf c inpecl pecl input capacitance t a = 25c, f 0 = 1 mhz, v cc = 3.3v 4 pf switching waveforms for the CYV15G0404RB hotlink ii receiver notes: 22. receiver input stream is bist data from the transmit channel. this data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. the measurement was recorded after 10,000 histogram hits, time referenced to refclkx of the transmit channel. rxclkx+ rxdx[9:0] t rxdv+ t rxclkp receive interface read timing rxratex = 0 rxclkx? t rxdv ? rxclkx+ t rxdv+ t rxdv ? t rxclkp receive interface read timing rxratex = 1 rxclkx? rxdx[9:0]
CYV15G0404RB document #: 38-02102 rev. *b page 22 of 26 CYV15G0404RB hotlink ii bus configuration switching waveforms addr[3:0] t datas bus configuration write timing data[7:0] wren t datah t wrenp
CYV15G0404RB document #: 38-02102 rev. *b page 23 of 26 table 6. package coordinate signal allocation ball id signal name signal type ball id signal name signal type ball id signal name signal type a01 inc1? cml in c07 ulcc lvttl in pu f17 vcc power a02 routc1? cml out c08 gnd ground f18 rxdb[0] lvttl out a03 inc2? cml in c09 data[7] lvttl in pu f19 reclkob lvttl out a04 routc2? cml out c10 data[5] lvt tl in pu f20 rxdb[1] lvttl out a05 vcc power c11 data[3] lvttl in pu g01 gnd ground a06 ind1? cml in c12 data[1] lvttl in pu g02 wren lvttl in pu a07 routd1? cml out c13 gnd ground g03 gnd ground a08 gnd ground c14 vcc power g04 gnd ground a09 ind2? cml in c15 spdseld 3-l evel sel g17 spdselb 3-level sel a10 routd2? cml out c16 vcc power g18 nc no connect a11 ina1? cml in c17 ldtden lvttl in pu g19 spdsela 3-level sel a12 routa1? cml out c18 trst lvttl in pu g20 rxdb[3] lvttl out a13 gnd ground c19 gnd ground h01 gnd ground a14 ina2? cml in c20 tdo lvttl 3-s out h02 gnd ground a15 routa2? cml out d01 tclk lvttl in pd h03 gnd ground a16 vcc power d02 reset lvttl in pu h04 gnd ground a17 inb1? cml in d03 inseld lvttl in h17 gnd ground a18 routb1? cml out d04 insela lvttl in h18 gnd ground a19 inb2? cml in d05 vcc power h19 gnd ground a20 routb2? cml out d06 ulca lvttl in pu h20 gnd ground b01 inc1+ cml in d07 spdselc 3-level sel j01 gnd ground b02 routc1+ cml out d08 gnd ground j02 gnd ground b03 inc2+ cml in d09 data[6] lvttl in pu j03 gnd ground b04 routc2+ cml out d10 data[4] lvttl in pu j04 gnd ground b05 vcc power d11 data[2] lvttl in pu j17 biststb lvttl out b06 ind1+ cml in d12 data[0] lvttl in pu j18 rxdb[2] lvttl out b07 routd1+ cml out d13 gnd ground j19 rxdb[7] lvttl out b08 gnd ground d14 gnd ground j20 rxdb[4] lvttl out b09 ind2+ cml in d15 ulcb lvttl in pu k01 rxdc[4] lvttl out b10 routd2+ cml out d16 vcc power k02 trgclkc? pecl in b11 ina1+ cml in d17 nc no connect k03 gnd ground b12 routa1+ cml out d18 vcc power k04 gnd ground b13 gnd ground d19 scanen2 lvttl in pd k17 rxdb[5] lvttl out b14 ina2+ cml in d20 tmen3 lvttl in pd k18 rxdb[6] lvttl out b15 routa2+ cml out e01 vcc power k19 rxdb[9] lvttl out b16 vcc power e02 vcc power k20 lfib lvttl out b17 inb1+ cml in e03 vcc power l01 rxdc[5] lvttl out b18 routb1+ cml out e04 vcc power l02 trgclkc+ pecl in b19 inb2+ cml in e17 vcc power l03 lfic lvttl out b20 routb2+ cml out e18 vcc power l04 gnd ground c01 tdi lvttl in pu e19 vcc power l17 rxdb[8] lvttl out c02 tms lvttl in pu e20 vcc power l18 rxclkb+ lvttl out c03 inselc lvttl in f01 rxdc[8] lvttl out l19 rxclkb? lvttl out
CYV15G0404RB document #: 38-02102 rev. *b page 24 of 26 c04 inselb lvttl in f02 rxdc[9] lvttl out l20 gnd ground c05 vcc power f03 vcc power m01 rxdc[6] lvttl out c06 ulcd lvttl in pu f04 vcc power m02 rxdc[7] lvttl out m03 vcc power u03 vcc power w03 lfid lvttl out m04 repdoc lvttl out u04 vcc power w04 rxclkd? lvttl out m17 trgclkb+ pecl in u05 vcc power w05 vcc power m18 trgclkb? pecl in u06 rxdd[4] lvttl out w06 rxdd[6] lvttl out m19 repdob lvttl out u07 rxdd[3] lvttl out w07 rxdd[0] lvttl out m20 gnd ground u08 gnd ground w08 gnd ground n01 gnd ground u09 gnd ground w09 addr [3] lvttl in pu n02 gnd ground u10 addr [0] lvttl in pu w10 addr [1] lvttl in pu n03 gnd ground u11 trgclkd? pecl in w11 rxclka+ lvttl out n04 gnd ground u12 gnd ground w12 repdoa lvttl out n17 gnd ground u13 gnd ground w13 gnd ground n18 gnd ground u14 gnd ground w14 gnd ground n19 gnd ground u15 vcc power w15 vcc power n20 gnd ground u16 vcc power w16 vcc power p01 rxdc[3] lvttl out u17 rxda[4] lvttl out w17 lfia lvttl out p02 rxdc[2] lvttl out u18 vc c power w18 trgclka+ pecl in p03 rxdc[1] lvttl out u19 biststa lvttl out w19 rxda[6] lvttl out p04 rxdc[0] lvttl out u20 rxda[0] lvttl out w20 rxda[3] lvttl out p17 gnd ground v01 vcc power y01 vcc power p18 gnd ground v02 vcc power y02 vcc power p19 gnd ground v03 vcc powe r y03 rxdd[9] lvttl out p20 gnd ground v04 rxdd[8] lvttl out y04 rxclkd+ lvttl out r01 biststc lvttl out v05 vcc power y05 vcc power r02 reclkoc lvttl out v06 rxdd[5] lvttl out y06 rxdd[7] lvttl out r03 rxclkc+ lvttl out v07 rxdd[1] lvttl out y07 rxdd[2] lvttl out r04 rxclkc? lvttl out v08 gnd ground y08 gnd ground r17 vcc power v09 biststd lvttl out y09 reclkod lvttl out r18 vcc power v10 addr [2] lvttl in pu y10 nc no connect r19 vcc power v11 trgclkd+ pecl in y11 gnd ground r20 vcc power v12 reclkoa lvttl out y12 rxclka? lvttl out t01 vcc power v13 gnd ground y13 gnd ground t02 vcc power v14 gnd ground y14 gnd ground t03 vcc power v15 vcc power y15 vcc power t04 vcc power v16 vcc power y16 vcc power t17 vcc power v17 rxda[9] lvttl out y17 repdod lvttl out t18 vcc power v18 rxda[5] lvttl out y18 trgclka? pecl in t19 vcc power v19 rxda[2] lvttl out y19 rxda[8] lvttl out t20 vcc power v20 rxda[1] lvttl out y20 rxda[7] lvttl out u01 vcc power w01 vcc power u02 vcc power w02 vcc power table 6. package coordinate signal allocation (continued) ball id signal name signal type ball id signal name signal type ball id signal name signal type
CYV15G0404RB document #: 38-02102 rev. *b page 25 of 26 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges hotlink is a registered trademark and hotlink ii is a trademar k of cypress semiconductor. all product and company names mentioned in this document may be the tr ademarks of their respective holders. ordering information speed ordering code package name package type operating range standard CYV15G0404RB-bgc bl256 256-ball thermally enhanced ball grid array commercial standard CYV15G0404RB-bgxc bl256 pb-free 256-ball t hermally enhanced ball grid array commercial package diagram 256-lead l2 ball grid array (27 x 27 x 1.57 mm) bl256 51-85123-*e
CYV15G0404RB document #: 38-02102 rev. *b page 26 of 26 document history page document title: CYV15G0404RB independent cloc k quad hotlink ii? deserializing reclocker document number: 38-02102 rev. ecn no. issue date orig. of change description of change ** 246850 see ecn fre new data sheet *a 338721 see ecn sua added pb-free package option availability *b 384307 see ecn agt revised setup and hold times (t rxdv? , t rxdv+ )

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