philips semiconductors fast products product specification fast 74F807 octal shift/count registered transceiver with adder and parity (3state) 1 june 18, 1991 8531421 02931 features ? high speed parallel registers with positive edgetriggered dtype flipflops ? high speed full adder ? 8bit parity generator ? high impedance pnp inputs for light bus loading ? center v cc and gnd pins and con- trolled output buffers minimize groundbounce problems ? 3state glitchfree powerup and powerdown ? broadside pinout description the 74F807 is a registered transceiver that also has the capability to perform count, shift, and add functions. it is also has the capability to generate a parity bit output. all of this is done within a 28pin package. the mr input is an overriding asynchronous reset which forces the statout output low as well as the a and b busses. the a and b busses have separate oe inputs (oe a, oe b]. these inputs have no bearing on the internal functioning of this device only on the output states. both oe pins are enabled low. all operating modes, other than clear, 3state, and the two hold modes re- quire the rising edge of the clock. all setup and hold times must be observed for proper functioning. data on the internal register can be switched on either the a or b ports for output. depeding on the state of the select in- puts (s0, s1, s2), and carry in/ serial in/ clock enable (ci/si/ce), the 74F807 has nine distinct operating modes: 1. add mode w/carry in the ci/si/ce input is used as a carry in signal and the statout output is the carry out signal. (in add mode the cout is not registered. this means the carry output signal appears at the statout output one clock prior to the related data.). in this mode, the ci/si/ce input is added to the register contents and to the inputs. (the adder uses only the an inputs, not the bn inputs.) 2. add mode wo/carry in same as above except the ci/si/ce input is not included in the addition. 3. count w/count enable (count) the ci/si/ ce input is now used as the count enable input and the statout output is terminal count. in this mode the ci/si/ce input must be high to enable the count function. the register contents are incremented by one. 4. count w/count enable (hold) same as above except no incrementing occurs. 5. count wo/count enable same as num - ber 3 except the ci/si/ce input has no con - trol over counting or holding. 6. shift the ci/si/ce input now becomes the serial input and the statout output becomes the serial output. in this mode the ci/si/ce input is shifted into the q0 register , q0 into the q1 register etc. the q7 register is shifted into the statout. 7. load a inputs the ci/si/ce input has no bearing in either of the load modes. the statout output becomes the parity out. the parity out is high for an odd number of registered bits high, and low for even number of registered bits high (even parity). in this mode the an inputs are loaded into the internal register and output to the b bus. if oea = low the internal register would wrap around and be loaded again. 8. load b inputs same as number 7 except the a and b busses are switched. 9. hold again the ci/si/ce input is not used; the statout output is still the parity out. in this mode either the a bus, b bus or both can be held with the registered data. no other operation is performed. type typical f max typical supply current (total) 74F807 115mhz 155ma ordering information order code description commercial range v cc = 5v 10%, t amb = 0 c to +70 c 28pin plastic dip (300 mils) n74F807n 28pin sol 1 n74F807d 28pin plcc n74F807a note to ordering information 1. thermal mounting techiques are recommended. see smd process applications (page 17) for a discussion of thermal consideration for surface mounted devices.
philips semiconductors fast products product specification fast 74F807 octal shift/count registered transceiver with adder and parity (3state) june 18, 1991 2 input and output loading and fan out table pins description 74f (u.l.) high/low load value high/low an, bn data i/o inputs 3.5/0.166 70 m a/70 m a oea , oeb a output enable inputs 1.0/0.033 20 m a/20 m a ci/si/ce carry in/serial in/clock enable input 1.0/0.033 20 m a/20 m a cp clock input 1.0/0.033 20 m a/20 m a mr master reset input (active low) 1.0/0.033 20 m a/20 m a sn select inputs 1.0/0.033 20 m a/20 m a statout status out output 150/40 3ma/24ma an, bn data i/o outputs 150/40 3ma/24ma note to input and output loading and fan out table 1. one (1.0) f ast unit load is defined as: 20 m a in the high state and 0.6ma in the low state. pin configuration pin configuration plcc 1 2 3 4 5 6 7 8 9 10 19 20 21 22 23 24 25 26 27 28 oea oeb a0 a1 a2 a3 gnd gnd a4 a5 a6 a7 ci/si/ce cp 4 3 2 1 28 27 25 24 23 22 21 20 11 10 9 8 7 6 18 16 17 15 14 13 26 19 12 5 plcc a2 a3 gnd gnd a4 a5 a6 11 12 13 14 15 16 17 18 v cc oea a0 a1 mr stat out b0 b7 s2 cp ci/ si/ ce a7 mr statout b0 b1 b2 b3 b4 b5 b6 b7 s0 s1 s2 oeb s1 s0 b1 b2 b3 v cc b4 b5 b6 logic symbol iec/ieee symbol 2 1 en3 3 4 5 8 9 10 11 13 13 17 16 15 14 28 1 2 26 25 24 23 21 20 19 18 r en1 en2 0 3 m 1 15 27 status out oea oeb ci/si/ce mr v cc = pin 22 gnd = pin 7, 8 3 4 5 6 9 10 11 12 26 25 24 23 22 20 19 18 1 2 13 28 statout 27 b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7
philips semiconductors fast products product specification fast 74F807 octal shift/count registered transceiver with adder and parity (3state) june 18, 1991 3 logic diagram qn shiftout oea oeb cp mr ci/si/ce s0 v cc = pin 22, gnd = pin 7, 8 1 2 14 28 13 17 le an qin cin adder sumn cout 8 8 8 8 le dn data registers cp tc r tcin tc register cp qin p0 parity qin an bn sumn ci/si/ce 2 7, 9 12 26 23, 21 18 27 8 8 8 8 rcout r e g i s t e r c o n t r o l statout a0 a7 b0 b7 16 15 s1 s2 hold load a load b cnte cntne cnt shift add
philips semiconductors fast products product specification fast 74F807 octal shift/count registered transceiver with adder and parity (3state) june 18, 1991 4 function table inputs internal register output operating mode mr cp so s1 s2 ci/si/ce qn statout l x x x x x l l clear h l l l ci/si/ce ci/si/ce + an0 + qn0 cout add mode w/carry in h l l h x an0 + qn0 cout add mode wo/carry in h l h l h qn0 + 1 tc (1) count w/count enable (count) h x l h h l qn0 tc (1) count w/count enable (hold) h l h h x qn0 + 1 tc (1) count wo/count enable h h l l ci/si/ce (3) q7 shift h h l h x an0 parity (2) load a ports h h h l x bn0 parity (2) load b ports h x h h h x qn0 parity (2) hold notes to function table 1. h = highvoltage level 2. l = lowvoltage level 3. a, b, q = lower case indicate the state of the referenced output prior to the lowtohigh clock transition 4. x = don't care 5. z = high impedance ooff)o state 6. = lowtohigh clock transition. 7. (1) = t erminal count is high when the output is a terminal count (hhhhhhhh). 8. (2) = parity is high for odd number of internal register bits high, low for even number of internal register bits high. 9. (3) = ci/si/ce q0 q1, etc. oe function table inputs outputs mode oe a oe b an bn l l active output active output enable a and b outputs l h active output input enable a outputs, b inputs h l input active output a inputs, enable b outputs h h input input a and b are inputs note: the outputs, whether an or bn, are equal to the internal register qn. absolute maximum ratings (operation beyond the limits set forth in this table may impair the useful life of the device. unless otherwise noted, these limits are over the operating freeair temperature range.) symbol parameter rating unit v cc supply voltage 0.5 to +7.0 v v in input voltage 0.5 to +7.0 v i in input current 30 to +5 ma v out v oltage applied to output in high output state 0.5 to v cc v i out current applied to output in low output state 48 ma t amb operating free air temperature range 0 to +70 c tstg storage temperature range 65 to +150 c note: when outputs are disabled the internal registers (qn) operate as usual.
philips semiconductors fast products product specification fast 74F807 octal shift/count registered transceiver with adder and parity (3state) june 18, 1991 5 recommended operating conditions limits symbol parameter min nom max unit v cc supply voltage 4.5 5.0 5.5 v v ih highlevel input voltage 2.0 v v il lowlevel input voltage 0.8 v i ik input clamp current 18 ma i oh highlevel output current 3 ma i ol lowlevel output current 24 ma t amb operating free air temperature range 0 +70 c dc electrical characteristics (over recommended operating free-air temperature range unless otherwise noted.) symbol parameter test limits unit conditions 1 min typ 2 max v oh high-level output voltage v cc = min, v il = max, 10%v cc 2.4 v v ih = min, i oh = max 5%v cc 2.7 3.4 v v ol low-level output voltage v cc = min, v il = max, 10%v cc 0.35 0.50 v v ih = min, i ol = max 5%v cc 0.35 0.50 v v ik input clamp voltage v cc = min, i i = i ik 0.73 -1.2 v i i input current at maximum input voltage v cc = max, v i = 7.0v 100 m a i ih highlevel input current v cc = max, v i = 2.7v 20 m a i il lowlevel input current v cc = max, v i = 0.5v 20 m a i ozh + i ih offstate output current, highlevel voltage applied an, bn v cc = max, v o = 2.7v 50 m a i ozl + i il offstate output current, lowlevel voltage applied v cc = max, v o = 0.5v 50 m a i os shortcircuit output current 3 v cc = max -60 -150 ma i cc supply current (total) v cc = max 155 210 ma notes to dc electrical characteristics 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions for the applicable type. 2. all typical values are at v cc = 5v, t amb = 25 c. 3. not more than one output should be shorted at a time. for testing i os , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. in any sequence of parameter tests, i os tests should be performed last.
philips semiconductors fast products product specification fast 74F807 octal shift/count registered transceiver with adder and parity (3state) june 18, 1991 6 ac electrical characteristics limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test v cc = +5.0v v cc = +5.0v 10% unit condition c l = 50pf, r l = 500 w c l = 50p, r l = 500 w min typ max min max f max maximum clock frequency waveform 1 100 115 70 mhz t plh t phl propagation delay cp to an or bn (load) waveform 1 9.0 5.0 10.5 6.5 11.5 9.5 8.0 4.5 13.5 10.0 ns t plh t phl propagation delay cp to an or bn (shift) waveform 1 9.0 4.5 10.5 6.5 12.5 9.5 8.0 4.5 15.0 10.0 ns t plh t phl propagation delay cp to an or bn (count) waveform 1 9.0 5.0 11.5 6.5 14.0 9.5 8.0 4.5 15.5 10.0 ns t plh t phl propagation delay cp to bn (add) waveform 1 9.0 5.0 10.5 6.5 11.5 9.5 8.0 4.5 13.5 10.0 ns t plh t phl propagation delay cp to statout (load a) waveform 1 17.5 12.5 19.5 14.5 22.5 17.0 15.5 11.5 26.5 19.0 ns t plh t phl propagation delay cp to statout (shift) waveform 1 11.0 7.0 13.0 8.5 15.5 11.5 9.5 6.5 18.0 12.0 ns t plh t phl propagation delay cp to statout (count) waveform 1 10.5 6.5 12.0 8.0 15.0 11.0 9.0 6.0 17.0 11.5 ns t plh t phl propagation delay cp to statout (add) waveform 1 13.0 8.5 15.0 10.5 18.0 13.0 11.5 8.0 20.5 14.0 ns t phl propagation delay mr to an or bn (load a) waveform 3 6.5 8.0 11.0 6.0 12.0 ns t phl propagation delay mr to statout (load a) waveform 3 14.0 16.0 18.5 13.0 20.5 ns t phl propagation delay mr to statout (shift) waveform 3 8.5 10.0 12.5 8.0 14.0 ns t phl propagation delay mr to statout (count) waveform 3 8.5 10.0 12.5 8.0 14.0 ns t phl propagation delay mr to statout (add) waveform 3 10.5 12.0 14.5 9.5 16.0 ns t plh t phl propagation delay an to statout (add) waveform 4 6.5 8.0 14.0 14.0 23.5 22.5 5.5 7.5 26.5 27.0 ns t plh t phl propagation delay ci/si/ce to statout waveform 4 19.5 21.0 21.5 22.5 24.0 25.5 17.0 20.0 28.0 29.5 ns t plh t phl propagation delay sn to statout (load a) waveform 4 8.0 7.5 10.0 11.5 12.5 15.5 7.0 7.0 14.5 17.0 ns t plh t phl propagation delay sn to statout (load b) waveform 4 6.5 8.0 10.0 12.0 13.0 15.0 5.5 7.0 15.0 16.5 ns t plh t phl propagation delay sn to statout (add) waveform 4 19.0 18.5 21.0 20.0 23.5 23.0 17.0 17.5 27.5 26.0 ns t plh t phl propagation delay sn to statout (shift) waveform 4 6.0 8.0 8.0 9.5 10.5 12.0 5.0 7.0 12.0 13.5 ns t pzh t pzl output enable time, oea to an or oeb to bn waveform 6 waveform 7 2.5 4.0 4.5 5.5 7.0 8.5 2.0 3.5 8.0 9.0 ns t phz t plz output disable time, oea to an or oeb to bn waveform 6 waveform 7 2.0 3.5 4.5 5.5 7.5 8.5 2.0 3.0 9.0 9.5 ns
philips semiconductors fast products product specification fast 74F807 octal shift/count registered transceiver with adder and parity (3state) june 18, 1991 7 ac setup requirements limits t amb = +25 c t amb = 0 c to +70 c symbol parameter test v cc = +5.0v v cc = +5.0v 10% unit condition c l = 50pf, r l = 500 w c l = 50pf, r l = 500 w min typ max min max t su (h) t su (l) setup time, high or low an, bn to cp (load) waveform 5 6.0 9.5 6.5 12.0 ns t h ( h ) t h ( l ) hold time, high or low an, bn to cp (load) waveform 5 0.0 0.0 0.0 0.0 ns t su (h) t su (l) setup time, high or low an, bn to cp (add) waveform 5 10.5 16.5 12.0 21.5 ns t h ( h ) t h ( l ) hold time, high or low an, bn to cp (add) waveform 5 0.0 0.0 0.0 0.0 ns t su (h) t su (l) setup time, high or low sn to cp (add) waveform 5 16.0 16.0 20.0 28.5 ns t su (h) t su (l) setup time, high or low sn to cp (count) waveform 5 16.5 19.5 19.0 22.5 ns t su (h) t su (l) setup time, high or low sn to cp (shift) waveform 5 11.0 7.0 13.0 8.0 ns t su (h) t su (l) setup time, high or low sn to cp (load) waveform 5 17.5 6.5 20.5 7.0 ns t h ( h ) t h ( l ) hold time, high or low sn to cp (all modes) waveform 5 0.0 0.0 0.0 0.0 ns t su (h) t su (l) setup time, high or low ci/si/ce to cp (add) waveform 5 10.0 18.0 11.5 22.0 ns t su (h) t su (l) setup time, high or low ci/si/ce to cp (count) waveform 5 8.5 16.0 10.0 18.5 ns t su (h) t su (l) setup time, high or low ci/si/ce to cp (shift) waveform 5 5.0 9.0 5.5 10.5 ns t h ( h ) t h ( l ) hold time, high or low ci/si/ce to cp (all modes) waveform 5 0.0 0.0 0.0 0.0 ns t w (h) t w (l) cp pulse width, high or low waveform 1 5.5 4.5 6.0 4.5 ns t w (l) mr pulse width, low waveform 3 4.5 5.0 ns t rec recovery time, mr to cp waveform 2 2.0 2.0 ns
philips semiconductors fast products product specification fast 74F807 octal shift/count registered transceiver with adder and parity (3state) june 18, 1991 8 ac waveforms v m v m v m v m waveform 4. propagation delay for select to st atout , ci/si/ce to statout or data to statout w aveform 5. data setup and hold times w aveform 6. 3state output enable time to high level and output disable time from high level w aveform 7. 3-state output enable time to low level and output disable time from low level v m v m v m v m v m v m t s ul) t su (h) t h (l) t h (h) v m v m v m t phz t pzh v oh -0.3v 0v v m v m v m t plz t pzl v ol +0.3v oeb or oea bn or an an, bn, sn, ci/si/ce statout t plh t phl v m t w (l) v m v m v m waveform 2. master reset to clock recovery time cp t rec an, sn, ci/si/ce oeb or oea bn or an v m v m v m v m waveform 3. propagation delay for master reset to data or master reset to statout mr t phl t plh bn or an statout t w (l) mr cp waveform 1. propagation delay for clock input to output, clock pulse width, and maximum clock frequency cpba or cpab v m v m v m t w (h) 1/f max v m v m t plh t w (l) t phl an or bn statout notes to ac waveforms 1. for all waveforms, v m = 1.5v. 2. the shaded areas indicate when the input is permitted to change for predictable output performance. test circuit and waveforms t w 90% v m 10% 90% v m 10% 90% v m 10% 90% v m 10% negative pulse positive pulse t w amp (v) 0v 0v t thl ( t f ) input pulse requirements rep. rate t w t tlh t thl 1mhz 500ns 2.5ns 2.5ns input pulse definition v cc family 74f d.u.t. pulse generator r l c l r t v in v out test circuit for 3state outputs definitions: r l = load resistor; see ac electrical characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac electrical characteristics for value r t = t ermination resistance should be equal to z out of pulse generators. t thl ( t f ) t tlh ( t r ) t tlh ( t r ) amp (v) amplitude 3.0v 1.5v v m r l 7.0v switch position test switch closed open all other t plz , t pzl .
|
