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? 1 ? e01664-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD4000R 120 pin lqfp (plastic) fingerprint verification system lsi description the CXD4000R is an ic that inputs the signal from a sony fingerprint sensor and performs fingerprint verification. this chip integrates a cpu, a/d converter, dram, usb controller and other circuits. features combination with a sony fingerprint sensor and a flash memory realizes a fingerprint verification system with a 3-chip configuration 16-bit microcomputer spc970 usb controller (conforms to rev 1.1) fingerprint verification block adoption of sony's original verification algorithm also provides excellent results for blurred and deformed fingerprints false rejection ratio: 1% or less, false acceptance ratio: 0.1% or less (with 2 trials) verification time per finger: approximately 40ms (clock frequency: 48mhz, excluding fingerprint image loading time) microcomputer block cpu: spc970 series 16-bit cpu core internal ram: 4k bytes external flash memory: 16-bit, 2m bytes external expansion sram: 8-bit/16-bit, 2m bytes each general purpose register: 16 bits 8 lines 32 banks processing rate: 41.6ns (f sys : 24mhz) peripheral hardware serial interface 1 channel (clock synchronous serial interface or asynchronous serial interface) 16-bit timer 4 channels external memory interface 8-bit a/d converter (also used as sensor input) 8-bit d/a converter 1 channel general-purpose i/o: 12 (also used as interrupt inputs, etc.) usb controller conforms to rev 1.1 usb transceiver circuit supports full-speed (12mbps) applications fingerprint verification units (stand-alone) cellular phones personal computers structure silicon gate cmos ic absolute maximum ratings supply voltage v dd v ss ? 0.5 to +4.6 v input voltage v i v ss ? 0.5 to v dd + 0.5 v output voltage v o v ss ? 0.5 to v dd + 0.5 v storage temperature tstg ?55 to +150 c recommended operating conditions supply voltage v dd 3.0 to 3.6 v input voltage v i v ss to v dd v output voltage v o v ss to v dd v operating temperature topr 0 to +70 c i/o pin capacitance input pin capacitance c i 9 (max.) pf output pin capacitance c o 11 (max.) pf i/o pin capacitance c i/o 11 (max.) pf note) measurement conditions: v dd = v i = 0v, f = 1mhz
? 2 ? CXD4000R block diagram and pin configuration port a port b usart usb driver usb controller cpu main ram dram timer adc dac interrupt controller clock generator verification sram binarization block correlation positional correlation verification register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 adc_avs ain1 ain2 adc_avd v ss rst v dd v ss v ss v ss v ss v ss v ss v dd v ss v ss v ss v ss v ss dac_bir aout dac_avd dac_avs v ss nc nc v ss xtal extal v dd v ss v ss v ss nc nc nc v ss cs2 cs1 cs0 rd wr a0 v dd a1 a2 v ss a3 a4 a5 a6 a7 a8 v ss a9 a10 a11 v dd v ss a12 d15 d14 d13 d12 d11 v ss d10 d9 v dd d8 d7 d6 d5 v ss d4 d3 d2 d1 d0 a20 v ss a19 a18 v dd a17 a16 a15 v ss a14 a13 nc sens_xsp sens_gain1 sens_gain0 sens_clk v ss v dd pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb3 pb2 v dd v ss pb1 pb0 siocs sck so si usb_avs dp dm usb_avd sens_gain2
? 3 ? CXD4000R pin description pin no. 1 2 3 4 5 6 7 8 to 13 14 15 to 19 20 21 22 23 24 25, 26 27 28 29 30 31 to 33 34 to 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 symbol i/o description remarks adc_avs ain1 ain2 adc_avd v ss rst v dd v ss v dd v ss dac_avs dac_bir aout dac_avd v ss nc v ss xtal extal v dd v ss nc v ss cs2 cs1 cs0 rd wr a0 v dd a1 a2 v ss a3 a4 a5 i i i i o o i o o o o o i/o i/o i/o i/o i/o i/o a/d converter gnd. a/d converter analog input. a/d converter analog input. a/d converter power supply. gnd. low level active system reset. power supply. gnd. power supply. gnd. d/a converter gnd. bias resistor connection for d/a converter output buffer (operational amplifier). d/a converter analog output. d/a converter power supply. gnd. no connected. gnd. oscillator connection for clock oscillation. oscillator connection for clock oscillation. power supply. gnd. no connected. gnd. external expansion 16-bit sram chip select. external expansion 8-bit sram chip select. flash memory chip select. external memory read strobe. external memory write strobe. external memory address bus. power supply. external memory address bus. external memory address bus. gnd. external memory address bus. external memory address bus. external memory address bus. sensor input pull-up with an external 33k ? resistor
? 4 ? CXD4000R pin no. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 symbol i/o description remarks a6 a7 a8 v ss a9 a10 a11 v dd v ss a12 a13 a14 v ss a15 a16 a17 v dd a18 a19 v ss a20 d0 d1 d2 d3 d4 v ss d5 d6 d7 d8 v dd d9 d10 v ss d11 d12 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o external memory address bus. external memory address bus. external memory address bus. gnd. external memory address bus. external memory address bus. external memory address bus. power supply. gnd. external memory address bus. external memory address bus. external memory address bus. gnd. external memory address bus. external memory address bus. external memory address bus. power supply. external memory address bus. external memory address bus. gnd. external memory address bus. external memory data bus. external memory data bus. external memory data bus. external memory data bus. external memory data bus. gnd. external memory data bus. external memory data bus. external memory data bus. external memory data bus. power supply. external memory data bus. external memory data bus. gnd. external memory data bus. external memory data bus. pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally
? 5 ? CXD4000R pin no. 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 symbol i/o description remarks d13 d14 d15 usb_avd dm dp usb_avs si so sck siocs pb0 pb1 v ss v dd pb2 pb3 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 v dd v ss sens_clk sens_gain0 sens_gain1 sens_gain2 sens_xsp nc i/o i/o i/o i/o i/o i o i/o i i i i i i/o i/o i/o i/o i/o i/o i/o i/o o o o o o external memory data bus. external memory data bus. external memory data bus. usb power supply. usb d ? usb d+ usb gnd. serial data input. serial data output. serial clock i/o. serial chip select input. (port b) input port/external interrupt request input. (port b) input port/external interrupt request input. gnd. power supply. (port b) input port/external interrupt request input. (port b) input port/external interrupt request input. (port a) i/o port. (port a) i/o port. (port a) i/o port. (port a) i/o port. (port a) i/o port. (port a) i/o port. (port a) i/o port. (port a) i/o port/external 16-bit sram upper byte control. power supply. gnd. sensor clock output. sensor gain output. sensor gain output. sensor gain output. sensor start pulse output. no connected. pulled-up internally pulled-up internally pulled-up internally pulled-up internally tri-state, pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally pulled-down internally pulled-down internally pulled-down internally pulled-down internally pulled-up internally pulled-up internally pulled-up internally pulled-up internally
? 6 ? CXD4000R electrical characteristics dc characteristics (within the recommended operating range) item input voltage (1) (digital) input voltage (2) (usb interface) input voltage (3) (a/d input) output voltage (1) (digital) output voltage (2) (digital) output voltage (3) (usb interface) output voltage (4) (d/a output) high level input voltage low level input voltage differential input sensitivity differential common mode range single-ended receiver high level input voltage single-ended receiver low level input voltage analog input level high level output voltage low level output voltage high level output voltage low level output voltage low level output voltage high level output voltage analog output level v ih v il vdi vcm v ih v il v in v oh1 v ol1 v oh2 v ol2 v ol v oh v on symbol i oh = ? 4ma i ol = 4ma i oh = ? 2ma i ol = 2ma rl = 1.5k ? to 3.6v rl = 15k ? to gnd conditions 0.7v dd 0.2 0.8 2.0 0 0.1v dd v dd ? 0.4 0 v dd ? 0.4 0 ? 2.8 0 min. 0.2v dd ? 2.5 v dd 0.8 0.9v dd v dd 0.4 v dd 0.4 0.3 3.6 v dd max. v v v v v v v v v v v v v v unit inputs other than ? 3 and ? 4 ? 3 ? 4 ? 1 ? 2 ? 3 ? 5 applicable pins ? 1 a0 to a20, pa0 to pa7, sck, so ? 2 d0 to d15, sens_clk, sens_gain0 to sens_gain2, sens_xsp, cs0 to cs2, rd, wr ? 3 dp, dm ? 4 ain1, ain2 ? 5 aout
? 7 ? CXD4000R ac characteristics (1) oscillation inverter i/o characteristics (within the recommended operating range) note) when using usb, the oscillation frequency should be 48mhz ?0.25%. item microcomputer system clock period verification engine clock period symbol t sys t eng conditions min. max. 41.57 83.13 166.26 332.51 20.79 41.57 83.13 166.26 332.51 unit ns ns ns ns ns ns ns ns ns frequency division value 1/2 (clock frequency = f ex /2) frequency division value 1/4 (clock frequency = f ex /4) frequency division value 1/8 (clock frequency = f ex /8) frequency division value 1/16 (clock frequency = f ex /16) frequency division value 1/1 (clock frequency = f ex ) frequency division value 1/2 (clock frequency = f ex /2) frequency division value 1/4 (clock frequency = f ex /4) frequency division value 1/8 (clock frequency = f ex /8) frequency division value 1/16 (clock frequency = f ex /16) 100 200 400 800 50 100 200 400 800 (3) reset input (within the recommended operating range) fig. 1. reset input timing rst t rst item reset input low level width symbol t rst pins rst conditions min. max. 4/f ex + 20 unit ns clock oscillation stabilized ? item logical vth input voltage output voltage feedback resistor oscillation frequency symbol lvth v ih v il v oh v ol rfb f ex pins extal extal xtal extal xtal extal xtal conditions min. typ. max. 0.7v dd v dd /2 250k 20 unit v v v v v ? mhz feed current where i oh = ? 3.0ma pull-in current where i ol = 3.0ma v in = v dd or vss v dd /2 1m 0.3v dd v dd /2 2.5m 48.12 (2) frequency division clock timing (within the recommended operating range)
? 8 ? CXD4000R (4) interrupt input (within the recommended operating range) fig. 2. interrupt input timing pb0 to pb3 t il t ih item external interrupt high and low level width symbol t ih t il pins pb0 to pb3 conditions min. max. 20 t sys + 20 32/f ex + 20 128/f ex + 20 unit ns ns ns ns noise filer not selected noise filter selected ? ? ? ? cpu clock ps5 ps7 (6) d/a converter characteristics (within the recommended operating range) (5) a/d converter characteristics (within the recommended operating range) item resolution conversion rate supply current standby current reference current integral non-linearity error differential non-linearity error symbol f cmax iop istb iref el ad ed ad conditions min. max. 0.5 ? ? ? ? ? unit bits mhz ma ? ? lsb lsb v in = 0.1avd to 0.9avd, f in = 1khz, ramp wave f in = 100khz, sine wave adc standby endpoint method ty p . 8 2.9 ? 628 0.7 0.65 12 ? 1 ? ? ? item resolution linearity error differential linearity error output full-scale voltage symbol el da ed da vfs measurement conditions min. max. ? ? ? ? unit bits lsb lsb v endpoint method ty p . 8 0.34 0.17 dac_avd ? 1lsb ? ? ? ?
? 9 ? CXD4000R (7) serial transfer sck = output mode (within the recommended operating range) ? 1 output disabled state (set to high level by an internal pull-up resistor.) fig. 7-1. serial transfer timing (sck: output mode) t scke t sckc1 t sih1 t sis1 t sckhw1 t sckd t scklw1 t csh t sod ? 1 t sckl1 ? 1 si input so t soe t soee siocs sck (output) item siocs high level width siocs sck enable siocs sck disable siocs so enable siocs so disable siocs sck low sck high pulse width sck low pulse width sck cycle time si input data setup time (activated by sck ) si input data hold time (activated by sck ) sck so delay time symbol t csh t scke t sckd t soe t sod t sckl1 t sckhw1 t scklw1 t sckc1 t sis1 t sih1 t soee conditions min. 2 t sys + 20 4 t sys 8/f ex ? 20 8/f ex ? 20 16/f ex 2 t sys + 50 0 unit ns ns ns ns ns ns ns ns ns ns ns ns cs automatic transfer mode max. 2 t sys + 50 2 t sys + 50 2 t sys + 50 2 t sys + 50 30
? 10 ? CXD4000R sck = input mode (within the recommended operating range) fig. 7-2. serial transfer timing (sck: input mode) item siocs high level width siocs sck low ? 2 siocs so enable siocs so disable sck high pulse width sck low pulse width sck cycle time si input data setup time (activated by sck ) si input data hold time (activated by sck ) sck so delay time symbol t csh t sckl2 t soe t sod t sckh2 t sckl2 t sckc2 t sis2 t sih2 t soee2 conditions min. 2 t sys + 20 4 t sys + 20 t sys + 20 t sys + 20 2 t sys + 40 20 20 unit ns ns ns ns ns ns ns ns ns ns cs automatic transfer mode max. 2 t sys + 50 2 t sys + 50 3 t sys + 50 ? 2 even if sck goes to low level before siocs falls, this is ignored. t sckh2 t soe t sod t csh t sckc2 t sih2 t sis2 t soee2 t sckhw2 t scklw2 t sckl2 si input so siocs sck (input)
? 11 ? CXD4000R (8) external memory interface read timing (within the recommended operating range) ? 1 bwtn: number of waits setting ? 2 prescribed from the timing at which any of a0 to a20, csn or rd first becomes invalid. item chip select pulse width ? 1 read strobe pulse width ? 1 address csn rd read data setup time read data hold time ? 2 symbol t rcs t rd t csrd t ds t dh min. (2 + bwtn) t sys ? 20 (1 + bwtn) t sys ? 20 t sys ? 20 50 0 unit ns ns ns ns ns max. (2 + bwtn) t sys + 20 (1 + bwtn) t sys + 20 t sys + 20 ? ? fig. 8-1. external memory interface timing (read) t1 t ds t2 t rd t rcs t csrd t dh d0 to d15 a0 to a20 csn rd
? 12 ? CXD4000R write timing (within the recommended operating range) item chip select pulse width read strobe pulse width address csn wr wr address csn write data enable wr wr write data disable symbol t wcs t wr t cswr t wrcs t dwr t wrd min. (3 + bwtn) t sys ? 20 (1 + bwtn) t sys ? 20 t sys/2 ? 20 t sys/2 ? 20 (1.5 + bwtn) t sys ? 20 10 unit ns ns ns ns ns ns max. (3 + bwtn) t sys + 20 (1 + bwtn) t sys + 20 t sys/2 + 20 t sys/2 + 20 (1.5 + bwtn) t sys + 20 t sys/2 + 20 fig. 8-2. external memory interface timing (write) t1 t dwr t wrd t2 t wr t wcs t cswr t3 t wrcs a0 to a20 csn wr d0 to d15
? 13 ? CXD4000R (9) usb interface (within the recommended operating range) item output impedance rise time fall time rise/fall ratio output signal crossover voltage symbol zdrv tr tf tr/tf vcrs conditions min. max. 28 4 4 0.9 1.3 unit ? ns ns ? v cl = 50pf cl = 50pf cl = 50pf cl = 50pf 43 20 20 1.1 2.0 ? 1 connect the dp and dm pins to the usb cable through 27 ? resistors. fig. 9. usb interface connection circuit CXD4000R 27 ? ? 1 27 ? ? 1 1.5k ? v dd dm dp
? 14 ? CXD4000R sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder plating copper alloy 0.5 0.22 0.05 m 0.1 detail a detail b 0.22 0.05 (0.2) (0.125) 0.145 0.03 1.7 max 1.4 0.1 b a 120pin lqfp (plastic) lqfp-120p-l01 lqfp120-p-1616 0.8g 130 31 60 61 90 91 120 0.1 s s s 18.0 0.2 16.0 0.1 (17.0) (0.5) 0? to 10? 0.1 0.05 0.6 0.15 0.25 package outline unit: mm sony corporation lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18m spec.

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