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| direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 1 of 18 http://www.cypress.com approved product c9821 product features ? high speed clock support - provides a 267 to 400mhz differential clock source for direct rambus ? memory systems for an 1.6 gbps data transfer rate ? synchronization flexibility - provides signals to synchronize the clock domains of the rambus ? channel with an external system or processor clock, provided by c9801, c9812, c9830, c9840, c9850, c9851, and the c9853. ? power management support permits channel clocks to be enabled and disabled as required ? supports independent channel clocking ? 24 pin 150 mil ssop package ? supports intel architecture platforms block diagram pll phase aligner test logic refclk mult 0:1 pclkm synclkn s0:2 stopb clk clkb output control logic figure: 1 product description the c9821 is a rambus ? compliant drcg clock synchronizer. it contains a phase locked loop that provides complimentary rambus ? memory clocks. included in its functionality is the control logic to phase and frequency synchronizing the device?s output clocks with the system reference clock. power management logic is also provided for mobile application and green pc functionality. also included are separate power pins for each internal functional block so as to minimize interaction of these sections with each other and thus maximize the device performance. pin configuration vddlr refclk vddp vssp vssi pclkm synclkn vssc vddc vddlpd stopb pwrdnb s0 s1 vddo vsso clk n/c clkb vsso vddo mult0 mult1 s2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 figure: 2
direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 2 of 18 http://www.cypress.com approved product c9821 pin description pin no. pin name i/o description 2 refclk i reference clock input. normally supplied by a system clock source generator. 6 pclkm i phase detector input: the phase difference between this signal and synclkn is used to synchronize the rambus ? channel clock with the system clock. the memory controller provides both the pclkm and synclkn. if the gear ratio is not used, connect this pin to ground. 7 synclkn i phase detector input: the phase difference between this signal and pclkm is used to synchronize the rambus ? channel clock with the system clock. the memory controller provides pclkm and synclkn. if the gear ratio is not used, connect this pin to ground. 11 stopb i clock stop. when this input is driven to low state, the differential rambus ? channel clocks are disabled. 12 pwrdnb i power down. when this input is driven to a logic low level, the differential rambus ? channel clocks are disabled and the system clock generator is placed in a power-down mode. 15, 14 mult (0:1) i pll multiplier select: these inputs select the pll prescaler and feedback dividers to determine the multiply ratio for the pll from the input reflck. 18, 20 clkb, clk o differential rambus ? channel clock outputs. 24, 23 13 s0, s1, s2 i these input pins control the operating mode of the device. 19 nc - no connect. do not connect any voltage levels to this pin. 1 vddir refv base voltage reference level for the device?s input reference clock. 10 vddipd refv base voltage reference for the pclkm, synclkn, and stopb. 9 vddc p power supply connection for the devices phase aligner circuitry. connected to 3.3v supply. 3 vddp p power supply for analog pll circuitry. connected to 3.3v supply. 16, 22 vddo p power supply clock output buffers. connected to 3.3v supply. care should be taken when routing these power supply connections so as to not have their power supply current is adequately bypassed (as close to the device as possible) and their switching noise (surges) does not couple into the other device power supplies. 8 vssc p power supply ground return connection for the devices phase aligner circuitry. connected to system ground. 5 vssi p reference supply ground for control input signals. 4 vssp p power supply ground return connection for analog pll circuitry. should be connected to system ground potential through a well bypassed path. 17, 21 vsso p system ground for clock output buffers. care should be taken when routing these power return connections so as to not have their power return current shared with other power return paths of the device. a bypass capacitor (0.1 f) should be placed as close as possible to each vdd pin. if these bypass capacitors are not close to the pins their high frequency filtering characteristic will be canceled by the lead inductance?s of the traces. direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 3 of 18 http://www.cypress.com approved product c9821 system clock configuration figure 3 shows the clocking configuration for an example direct rambus subsystem. the configuration shows the interconnection of the system clock source, the c9821, and the clock signals of a memory controller asic. the asic contains the rac, the rambus memory controller protocol engine (rmc), and logic to support synchronizing the channel clock with the controller clock (this diagram represents the differential clocks as a single busclk wire). m n c9801 c9812 c9830 c9840 c9850 c9851 c9853 pll phase align d c9821 dll 4 rmc pclk refclk s0/s1/s2 stopb busclk rac synclk gear ratio logic synclk/n pclk/m figure: 3 ddll system architecture this configuration achieves frequency-lock between the controller and rambus channel clocks (pclk and synclk). these clock signals are matched and phase-aligned at the rmc/rac boundary in order to allow data transfers to occur across this boundary without additional latency. the main clock source drives the system clock (pclk) to the asic, and also drives the reference clock (refclk) to the c9821. refclk is not the same frequency as pclk. a pll inside the c9821 multiplies refclk to generate the desired frequency for busclk. busclk is driven on the rambus channel through a terminated transmission line. at the mid- point of the channel, the rac senses busclk using its own dll for clock alignment, followed by a fixed divide-by-4 circuit that generates synclk. pclk is the clock used in the rambus memory controller (rmc) in the asic. synclk is the clock used at the asic interface of the rac. the c9821 together with the gear ratio logic enables the controller to exchange data directly from the pclk domain to the synclk domain without incurring additional latency for synchronization. in general, pclk and synclk can run at different frequencies, so the gear ratio logic must select the appropriate m and n dividers such that the frequencies of pclk/m and synclkn are equal. in one example, pclk = 133 mhz and synclk = 100 mhz, and m = 4 while n = 3, giving pclk/m = synclk/n = 33 mhz. the asic drives the output clocks, pclk and synclk/n from the gear ratio logic to the c9821 phase detector inputs. the routing of the pclk/m and synclk/n signal traces must be matched in impedance and propagation delay on the asic as well as on the board. these signals are not part of the rambus channel and board designers must match their routing. direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 4 of 18 http://www.cypress.com approved product c9821 system clock configuration (cont.) after comparing the phases of pclk/m and synclk/n, the c9821 phase detector drives a phase aligner that adjusts the phase of the c9821 output clock, busclk. since the other elements in the distributed loop have a fixed delay, adjusting busclk adjusts the phase of synclk and thus the phase of synclk/n. in this manner, the distributed loop adjusts the phase of synclk/n to match that of pclk/m, eliminating the phase error at the input of the c9821. when the clocks are aligned, data can be exchanged directly from the pclk domain to the synclk domain. the gear ratio logic supports four clock ratios (1.0, 1.33, 1.5), where the ratio is defined as the ratio of pclk/synclk. since busclk - 4*synclk, this ratio also is equal to 4*pclk/busclk. in addition, the device is able to receive input signals that are generated from different voltage power supplies. the controller output voltage supply is connected to the pin vddipd of the c9821, and is used as the reference for the two-phase detector input signal, pclkm and synclkn. the output voltage supply is also used as the reference for the output enable/disable signal, stopb. the reference clock comes from the main clock source chip. the main clock source output voltage supply is connected to the pin vddlr of c9821, and is used as the reference for the refclk input signal. table of frequencies and gear ratios gear ratio timing diagram pclk synclk pclk/m = synclk/n figure: 4 direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 5 of 18 http://www.cypress.com approved product c9821 table of frequencies and gear ratios (cont.) pclk refclk busclk synclk a b m n ratio f@pd 67 33 267 67 8 1 2 2 1.0 33 100 50 300 75 6 1 8 6 1.33 12.5 100 50 400 100 8 1 2 2 1.0 25 133 67 400 100 6 1 8 6 1.33 16.7 133 67 356 89 16 3 6 4 1.5 22 150 75 400 100 16 3 6 4 1.5 25 table 1a. frequencies, dividers, and gear ratios a: feedback divider in the drcg pll. b: refclk divider in the drcg pll m: pclk divider in the gear ratio logic. n: synclk divider in the gear ratio logic. table 1a above shows several supported pclk and busclk frequencies, the corresponding a and b dividers required in the drcg pll, and the corresponding m and n dividers in the gear ratio logic. the column ratio gives the gear ratio as defined by pclk/synclk (same as m/n). the column f@pd gives the divided down frequency (in mhz) at the phase detector, where f@pd = pclk/m = synclk/n. table 1b below show examples of clk/clkb frequencies for different drcg input frequencies. mult0 mult1 drcg input frequency clk and clkb output frequency 0 0 89 mhz 400 mhz 0 1 50 mhz 300 mhz 1 0 50 mhz 267 mhz 1 1 50 mhz 400 mhz 0 0 66 mhz 300 mhz 0 1 66 mhz 400 mhz 1 0 66 mhz 356 mhz 1 1 33 mhz 267 mhz table 1b: clk and clkb example frequencies selection logic mult0 mult1 a b 0092 0161 10163 1181 table 2: pll divider selection direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 6 of 18 http://www.cypress.com approved product c9821 selection logic (cont.) table 2 shows the logic for selecting the pll prescaler and feedback dividers to determine the multiply ratio for the pll from the input refclk. divider a sets the feedback and divider b sets the prescaler, so the pll output is set by: pllclk = refclk*a/b. mode stopb clk clkb normal 1 paclk paclkb clk stop 0 v x,stop v x,stop table 3: clk stop mode selection table 3 shows the logic for enabling the clock outputs, using the stopb input signal. when stopb is high, the drcg is in its normal mode, and clk and clkb are complementary outputs following the phase aligner output (paclk). when stopb is low, the drcg is in the clk stop mode, the output drivers are both disabled (set to hi-z), and the clk and clkb outputs both drive dc voltages (v x,stop ) as given in table 11. the level of v x,stop is set by internal resistor dividers. mode s0 s1 s2 bypclk (int.) clk clkb normal 0 0 0 gnd paclk paclkb bypass 1 0 0 pllclk pllclk pllclkb test 1 1 0 refclk refclk refclkb vendor test a 0 0 1 - - - vendor test b 1 0 1 - - - reserved 1 1 1 - - - output test (oe) 0 1 x - hi-z hi-z table 4: bypass and test mode selection power management functions mode pwrdnb clk clkb normal 1 paclk paclkb powerdown 0 gnd gnd table 5: powerdown mode selection table 5 shows the logic for selecting the powerdown mode, using the pwrdnb input signal. pwrdnb is active low (enabled when 0). when pwrdnb is disabled, the drcg is in its normal mode. when pwrdnb is enabled, the drcg is put into a powered-off state, and the clk and clkb outputs are both low (ground). direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 7 of 18 http://www.cypress.com approved product c9821 power management functions (cont.) the device is able to turn off the rambus channel clock to minimize power for mobile and other power-sensitive applications. in the ?clock off? mode, the device remains on while the output is disabled, allowing fast transitions between the clock-off and clock-on states. this mode could be used in conjunction with the nap mode of the rdrams and rambus asic cell (rac). when output clocks are in a power down mode they are driven to and held at a logic low level by the device. in the ?power down? mode, the device is completely powered down for minimum power dissipation. this mode is used in conjunction with the power down modes of the rdrams and rac. the device has three operating states: normal, clock off and powerdown. in normal mode, the clock source is on, and the output is enabled. in clock off mode, the clock source is on, but the output is disabled (stopb asserted). in powerdown mode, the device is powered down with the control signal pwrdnb equal to 0. the control signals mult0, mult1, s0, s1, and s2 must be stable before power is applied to the device, and can only be changed in power-down mode (pwrdnb=0). power management modes state pwrdnb stopb normal 1 1 clock off 1 0 powerdown 0 x table 6: control signals for clock source states upon applying power to the device, the device can enter any state, depending on the settings of the control signals, pwrdnb and stopb. the clock source output need not be glitch-free during state transitions. direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 8 of 18 http://www.cypress.com approved product c9821 state transitions the clock source has three fundamental operating states. figure 5 shows the state diagram with each transition labeled a through j. note that the clock source output need not be glitch-free during state transitions. figure 5: clock source state diagram upon powering up the device, the device can enter any state, depending on the settings of the control signals pwrdnb and stopb. in powerdown mode, the clock source is powered down with the control signal, pwrdnb, equal to 0. the control signals s0, s1, and s2 must be stable before power is applied to the device, and can only be changed in powerdown mode (pwrdnb=0). the reference inputs, vddir and vddipd, may remain on or may be grounded during the powerdown mode. the control signals mult0, mult1 can be used in two ways. if they are changed during powerdown mode, then the powerdown transition timings determine the settling time of the drcg. however, the mult0 and mult1 control signals can also be changed during normal mode. when the mult control signals are ?hot swapped? in this manner, the mult transition timings determine the settling time of the drcg. in clk stop mode, the clock source is on, but the output is disabled (stopb de-asserted). the vddipd reference input may remain on or may be grounded during the clk stop mode. the vddir reference input must remain on during the clk stop mode. normal powerdown clk stop vdd turn-on vdd turn-on vdd turn-on g j f e h c d a b direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 9 of 18 http://www.cypress.com approved product c9821 state transitions and timing diagrams t powerup t poweron output clock not specified, glitches may occur. clock enabled and glitch free t clkon t clksetl t clkoff t stop t on pwrdnb clk/clkb powerdown exit and entry stopb clk/clkb output enable control figure: 7 figure: 6 clock output settled within 50 ps of the phase before disabled. direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 10 of 18 http://www.cypress.com approved product c9821 mult transition timing diagram clk/clkb mult0 and/ or mult1 t mult figure: 8 transition specifications transition from to transition latency (target spec) description symbol max a powerdown normal tpowerup 3 ms time from pwrdnb to clk/clkb output settled (excluding tdistlock). c powerdown clk stop tpowerup 3 ms time from pwrdnb to when the internal pll and clock has turned on and settled. g vdd on normal tpowerup 3 ms time from vdd is applied and settled to clk/clkb output settled (excluding tdistlock). h vdd on clk stop tpowerup 3 ms time from vdd is applied and settled to the internal pll and clock has turned on and settled. j normal normal tmult 1 ms time from mult0 or mult1 change to clk/clkb output re-settled (excluding tdistlock). e clk stop normal tclkon 10 ns time from stopb to when clk/clkb provides glitch-free clock edges. e clk stop normal tclksetl 20 cycles time from stopb to clk/clkb output settled to within 50 ps of the phase before stopb was disabled. f normal clk stop tclkoff 5 ns time from stopb to clk/blkb output disabled. b,d normal or clk stop powerdown tpowerdn 1ms time from pwerdnb to the device in powerdown. table 7: state transition latency specifications direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 11 of 18 http://www.cypress.com approved product c9821 transition specifications (cont.) figure 7 shows that the clk stop to normal transition goes through three phases. during tclkon, the clock output is not specified and can have glitches. for tclkon < t direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 13 of 18 http://www.cypress.com approved product c9821 device parameters characteristic symbol min typ max units conditions output duty cycle over 10,000 cycles dc 40% 50% 60% t cycle clock cycle time t cycle 2.5 - 3.75 ns jitter over 1-6 clock cycles at 400 mhz a - 100 ps jitter over 1-6 clock cycles at 356 mhz a tj - 140 ps jitter over 1-6 clock cycles at 300 mhz a - 140 ps jitter over 1-6 clock cycles at 267 mhz a - 160 ps phase aligner phase step size (at clk/clkb) t step 2ps phase detector phase error for distributed loop measured at pcklm-synclkn (rising edges) (does not include clock jitter) t err,pd -100 - 100 ps pll output phase error when tracking ssc t err,ssc -100 - 100 ps output voltage during clk stop (stopb=0) v x,stop 1.1 - 2.0 v output crossing-point voltage v x 1.3 - 1.8 v output voltage swing b v cos 0.4 - 0.6 v output high voltage v oh --2.0 v output low voltage v ol 1.0 - - v output dynamic resistance (at pins) c r out 12 - 50 ? output current during hi-z (s0=1, s1=1) i oz -- 50 a output current during clk stop (stopb=0) i oz,stop - 500 a cycle-to-cycle duty cycle error at 400 mhz - - 50 ps cycle-to-cycle duty cycle error at 300 mhz t dc,err - - 70 ps cycle-to-cycle duty cycle error at 267 mhz - - 80 ps output rise and fall times (measured at 20% - 80% of output voltage) t cr, t cf 160 - 400 ps difference between rise and fall times on the same pin of a single device (20% - 80%) t cr, t cf - 100 ps =3.3v 5 %, ta = 0oc to +70oc a. output short-term jitter spec is peak to peak. b. v cos = v oh ? v ol c. r out = ? v o / ? i o . this is defined at the output pins, not at the measurement point. table 11: device characteristics direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 14 of 18 http://www.cypress.com approved product c9821 ac operating conditions characteristic symbol min typ max units refclk input cycle time t cycle,in 10 - 40 ns faster speed bin for refclk input cycle time a 6 a -40 ns input cycle-to-cycle jitter b t j,in - - 250 ps input duty cycle over 10,000 cycles d cin c 40% - 60% t cycle input frequency of modulation f min,in c 30 - 33 khz modulation index for triangular modulation p m,in c --0.6 % modulation index for non-triangular modulation - - 0.5 d % phase detector input cycle time at pclkm and synclkn t cycle, pd 30 - 100 ns initial phase error at phase detector inputs (required range of phase aligner) t err,init -0.5 - 0.5 t cycle,pd phase detector input duty cycle over 10,000 cycles d cin,pd 25% - 75% t cycle,pd input slew rate (measured at 20% - 80% of input voltage) for pclkm, synclkn, and refclk t i,sr 1- 4 v/ns input capacitance at pclkm, synclkn, and refclk e c in,pd -- 7 pf input capacitance matching at pclkm and synclkn e ? c in,pd --0.5 pf input capacitance at scalable cmos pins (excluding pclkm, synclkn, and refclk) e c in,cmos - - 10 pf a. faster speed bin for future systems (not a requirement now), and applicable for v ddi,r >1.7v only b. refclk jitter measured at v ddi,r (nom)/2 c. if input modulation is used, input modulation is allowed but not required. d. the amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew generated by the specified 0.6% triangular modulation. typically, the amount of allowed non-triangular modulation is about 0.5%. e. capacitance measured at freq = 1 mhz, dc bias = 0.9v, and v ac <100mv table 12: ac operating conditions direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 15 of 18 http://www.cypress.com approved product c9821 test circuit logic select jumper a b pd vdd vss testclk scope ch1 ch2 clk clkb refclk test board m counter n counter variable delay (50 - 200 psec). variable delay (50 - 200 psec). s0 s1 s2 pll drcg figure 9: characterization test fixture direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 16 of 18 http://www.cypress.com approved product c9821 output buffer termination drcg 27 ohm 28 ohm 28 ohm measurement point measurement point 10 pf 10 pf 100 pf 39 ohm 39 ohm 68 ohm 68 ohm c9821 27 ohm figure 10: output termination direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 17 of 18 http://www.cypress.com approved product c9821 package drawing and dimensions 24 pin qsop outline dimensions inches millimeters symbol min nom max min nom max a 0.053 0.064 0.069 1.35 1.63 1.75 a 1 0.004 0.006 0.010 0.102 0.152 0.254 a2 0.055 - 0.059 1.40 - 1.50 b 0.008 - 0.012 0.203 - 0.305 c 0.007 - 0.010 0.178 - 0.254 d 0.337 0.341 0.344 8.56 8.66 8.74 e 0.150 0.154 0.157 3.81 3.91 3.99 e 0.025 bsc 0.635 bsc h 0.228 0.235 0.244 5.79 5.97 6.20 l 0.016 0.025 0.050 0.406 0.635 1.27 a 0o - 8o 0o - 8o ordering information part number package type production flow C9821GQ 24 pin qsop commercial, 0oc to +70oc note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: date code C9821GQ lot # C9821GQ package q = qsop (150 mil. ssop) revision device number notice cypress semiconductor corporation reserves the right to change or modify the information contained in this data sheet, without notice. cypress semiconductor corporation does not assume any liability arising out of the application or use of any product or circuit described herein cypress semiconductor corporation does not convey any license under its patent rights nor the rights of others. cypress semicon ductor corporation does not authorize its products for use as critical components in life-support systems or critical medical instrum ents, where a malfunction or failure may reasonably be expected to result in significant injury to the user. a b e a a 1 a 2 d e h l c direct rambus ? plus clock generator cypress semiconductor corporation 525 los coches st. document#: 38-07092 rev. ** 05/03/2001 milpitas, ca 95035. tel: 408-263-6300, fax: 408-263-6571 page 18 of 18 http://www.cypress.com approved product c9821 document title: c9821 direct rambus? plus clock generator document number: 38-07092 rev. ecn no. issue date orig. of change description of change ** 107128 06/14/01 ika convert from imi to cypress |
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