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p5z22v10 5v zero power, totalcmos ? , universal pld device product specification supersedes data of 1997 apr 04 ic27 data handbook 1997 may 02 integrated circuits
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 2 1997 may 02 8531977 18019 features ? industry's first totalcmos ? 22v10 both cmos design and process technologies ? fast zero power (fzp ? ) design technique provides ultra-low power and high speed static current of less than 75 m a dynamic current 1/10 to 1/1000 that of competing devices pin-to-pin delay of only 7.5ns ? true zero power device with no turbo bits or power down schemes ? function/jedec map compatible with bipolar uvcmos eecmos 22v10s ? multiple packaging options featuring pcb-friendly flow-through pinouts (sol and tssop) 24-pin tssopeuses 93% less in-system space than a 28-pin plcc 24-pin sol 28-pin plcc with standard jedec pin-out ? available in commercial and industrial operating ranges ? advanced 0.5 m e 2 cmos process ? 1000 erase/program cycles guaranteed ? 20 years data retention guaranteed ? varied product term distribution with up to 16 product terms per output for complex functions ? programmable output polarity ? synchronous preset/asynchronous reset capability ? security bit prevents unauthorized access ? electronic signature for identification ? design entry and verification using industry standard cae tools ? reprogrammable using industry standard device programmers description the p5z22v10 is the first spld to combine high performance with low power, without the need for aturbo bitso or other power down schemes. to achieve this, philips semiconductors has used their fzp ? design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in plds since the bipolar era) with a cascaded chain of pure cmos gates. this results in the combination of low power and high speed that has previously been unattainable in the pld arena. for 3v operation, philips semiconductors offers the p3z22v10 that offers high speed and low power in a 3v implementation. the p5z22v10 uses the familiar and/or logic array structure, which allows direct implementation of sum-of-products equations. this device has a programmable and array which drives a fixed or array. the or sum of products feeds an aoutput macro cello (omc), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. ordering information order code package propagation delay temperature range operating range drawing number p5z22v10-7a 28-pin plcc 7.5ns 0 to +70 c v cc = 5.0v 5% sot261-3 p5z22v10-7d 24-pin sol 7.5ns 0 to +70 c v cc = 5.0v 5% sot137-1 p5z22v10-7dh 24-pin tssop 7.5ns 0 to +70 c v cc = 5.0v 5% sot355-1 p5z22v10da 28-pin plcc 10ns 0 to +70 c v cc = 5.0v 5% sot261-3 p5z22v10dd 24-pin sol 10ns 0 to +70 c v cc = 5.0v 5% sot137-1 p5z22v10ddh 24-pin tssop 10ns 0 to +70 c v cc = 5.0v 5% sot355-1 p5z22v10ida 28-pin plcc 10ns 40 to +85 c v cc = 5.0v 10% sot261-3 p5z22v10idd 24-pin sol 10ns 40 to +85 c v cc = 5.0v 10% sot137-1 p5z22v10iddh 24-pin tssop 10ns 40 to +85 c v cc = 5.0v 10% sot355-1
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 3 pin configurations 28-pin plcc 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 nc io/clk i1 i2 f7 f6 f5 nc f4 f3 f2 i3 i4 i5 nc i6 i7 i8 i9 i10 gnd nc i11 f0 f1 f8 f9 v cc sp00474 24-pin sol and 24-pin tssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 io/clk i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 v cc f9 f8 f7 f6 f5 f4 f2 f3 f1 f0 i11 gnd ap00475 pin descriptions pin label description i1 i11 dedicated input nc not connected f0 f9 macrocell input/output i0/clk dedicated input/clock input v cc supply voltage gnd ground
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 4 logic diagram note: programmable connection. 1 1 0 0 0 1 0 1 d ar q q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 q 1 1 0 0 0 1 0 1 d ar q sp 0 1 ar sp 0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536 3940 43 0 3 4 7 8 1112 1516 1920 2324 2728 3132 3536 3940 43 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk/i0 i1 i2 i3 i4 i5 i6 i7 i10 i8 i9 gnd i11 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 v cc 0 1 9 10 20 21 33 34 48 49 65 66 82 83 97 98 110 111 121 122 130 131 sp00059
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 5 output macro cell clk/i0 i1 i11 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 programmable and array (44 132) 1 11 8 101214 1616141210 8 sp00060a output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell reset preset figure 1. functional diagram functional description the p5z22v10 implements logic functions as sum-of-products expressions in a programmable-and/fixed-or logic array. user-defined functions are created by programming the connections of input signals into the array. user-configurable output structures in the form of i/o macrocells further increase logic flexibility. architecture overview the p5z22v10 architecture is illustrated in figure 1. twelve dedicated inputs and 10 i/os provide up to 22 inputs and 10 outputs for creation of logic functions. at the core of the device is a programmable electrically-erasable and array which drives a fixed-or array. with this structure, the p5z22v10 can implement up to 10 sum-of-products logic expressions. associated with each of the 10 or functions is an i/o macrocell which can be independently programmed to one of 4 different configurations. the programmable macrocells allow each i/o to create sequential or combinatorial logic functions with either active-high or active-low polarity. and/or logic array the programmable and array of the p5z22v10 (shown in the logic diagram) is formed by input lines intersecting product terms. the input lines and product terms are used as follows: 44 input lines: 24 input lines carry the true and complement of the signals applied to the 12 input pins 20 additional lines carry the true and complement values of feedback or input signals from the 10 i/os 132 product terms: 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) used to form logical sums 10 output enable terms (one for each i/o) 1 global synchronous preset product term 1 global asynchronous clear product term at each input-line/product-term intersection there is an eeprom memory cell which determines whether or not there is a logical connection at that intersection. each product term is essentially a 44-input and gate. a product term which is connected to both the true and complement of an input signal will always be false, and thus will not affect the or function that it drives. when all the connections on a product term are opened, a don't care state exists and that term will always be true. variable product term distribution the p5z22v10 provides 120 product terms to drive the 10 or functions. these product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see logic diagram). this distribution allows optimum use of device resources.
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 6 f 0 1 1 0 0 1 0 0 1 clk 1 ar sp s 1 s 0 s 1 s 0 output configuration 0 = unprogrammed fuse 1 = programmed fuse dq q 0 0 1 1 0 1 0 1 registered/active-low/macrocell feedback registered/active-high/macrocell feedback combinatorial/active-low/pin feedback combinatorial/active-high/pin feedback sp00484 figure 2. output macro cell logic diagram f clk ar sp s 0 = 0 s 1 = 0 dq q a. registered/active-low f clk ar sp s 0 = 1 s 1 = 0 dq q b. registered/active-high f s 0 = 0 s 1 = 1 c. combinatorial/active-low d. combinatorial/active-high f s 0 = 1 s 1 = 1 sp00376 figure 3. output macro cell configurations programmable i/o macrocell the output macrocell provides complete control over the architecture of each output. the ability to configure each output independently permits users to tailor the configuration of the p5z22v10 to the precise requirements of their designs. macrocell architecture each i/o macrocell, as shown in figure 2, consists of a d-type flip-flop and two signal-select multiplexers. the configuration of each macrocell of the p5z22v10 is determined by the two eeprom bits controlling these multiplexers. these bits determine output polarity, and output type (registered or non-registered). equivalent circuits for the macrocell configurations are illustrated in figure 3. output type the signal from the or array can be fed directly to the output pin (combinatorial function) or latched in the d-type flip-flop (registered function). the d-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. when the synchronous preset term is satisfied, the q output of the register will be set high at the next rising edge of the clock input. satisfying the asynchronous clear term will set q low, regardless of the clock state. if both terms are satisfied simultaneously, the clear will override the preset.
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 7 program/erase cycles the p5z22v10 is 100% testable, erases/programs in seconds, and guarantees 1000 program/erase erase cycles. output polarity each macrocell can be configured to implement active-high or active-low logic. programmable polarity eliminates the need for external inverters. output enable the output of each i/o macrocell can be enabled or disabled under the control of its associated programmable output enable product term. when the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the i/o pin. otherwise, the output buffer is driven into the high-impedance state. under the control of the output enable term, the i/o pin can function as a dedicated input, a dedicated output, or a bi-directional i/o. opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. conversely, if every connection is intact, the enable term will always be logically false and the i/o will function as a dedicated input. register feedback select when the i/o macrocell is configured to implement a registered function (s1 = 0) (figures 3a or 3b), the feedback signal to the and array is taken from the q output. bi-directional i/o select when configuring an i/o macrocell to implement a combinatorial function (s1 = 1) (figures 3c or 3d), the feedback signal is taken from the i/o pin. in this case, the pin can be used as a dedicated input, a dedicated output, or a bi-directional i/o. power-on reset to ease system initialization, all flip-flops will power-up to a reset condition and the q output will be low. the actual output of the p5z22v10 will depend on the programmed output polarity. the v cc rise must be monotonic. design security the p5z22v10 provides a special eeprom security bit that prevents unauthorized reading or copying of designs programmed into the device. the security bit is set by the pld programmer, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. once the security bit is set, it is impossible to verify (read) or program the p5z22v10 until the entire device has first been erased with the bulk-erase function. totalcmos ? design technique for fast zero power philips is the first to offer a totalcmos ? spld, both in process technology and design techni que. philips employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate implementation allows philips to offer splds which are both high performance and low power, breaking the paradigm that to have low power, you must accept low performance. refer to figure 4 and table 1 showing the i dd vs. frequency of our p5z22v10 totalcmos ? spld. table 1. typical i dd vs. frequency v dd = 5v @ 25 c frequency (mhz) typical i dd (ma) 1 0.5 10 1.9 20 3.5 30 5.0 40 6.5 50 8.1 60 9.5 70 10.9 80 12.4 90 13.9 100 15.4 110 16.7 120 18.1 130 19.4 140 20.7 150 22.1 160 23.5 170 24.8 180 26.2 190 27.5 200 28.7

typical i dd (ma) frequency (mhz) sp00486 figure 4. typical i dd vs. frequency @ v dd = 5v, 25 c (10-bit counter)
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 8 absolute maximum ratings 1 symbol parameter limits unit symbol parameter min. max. unit v dd supply voltage 0.5 7.0 v v i input voltage 1.2 v dd + 0.5 v v out output voltage 0.5 v dd + 0.5 v i in input current 30 30 ma i out output current 100 100 ma t r allowable thermal rise ambient to junction 0 75 c t j junction temperature range 40 150 c t stg storage temperature range 65 150 c esd static discharge voltage (human body) 1000 v note: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only. functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implie d. operating range product grade temperature voltage commercial 0 to +70 c 5.0 5% v industrial 40 to +85 c 5.0 10% v
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 9 dc electrical characteristics for commercial grade devices commercial: 0 c t amb +70 c; 4.75 v dd 5.25v symbol parameter test conditions limits units symbol parameter test conditions min. typ. max. units v il input voltage low v dd = 4.75v 0.8 v v ih input voltage high v dd = 5.25v 2 v v i input clamp voltage v dd = 4.75v; i in = 18ma 1.2 v v ol output voltage low v dd = 4.75v; i ol = 8ma 0.5 v v oh output voltage high v dd = 4.75v; i ol = 4ma 2.4 v i i input leakage current v in = 0 to v dd 10 10 m a i oz 3-stated output leakage current v in = 0 to v dd 10 10 m a i ddq standby current v dd = 5.25v; t amb = 0 c 60 75 m a i ddd 1 dynamic current v dd = 5.25v; t amb = 0 c @ 1mhz 1 2 ma i ddd 1 dynamic current v dd = 5.25v; t amb = 0 c @ 50mhz 10 15 ma i sc short circuit output current 1 pin/time for no longer than 1 second 30 100 ma c in input pin capacitance t amb = 25 c; f = 1mhz 10 pf c clk clock input capacitance t amb = 25 c; f = 1mhz 5 12 pf c i/o i/o pin capacitance t amb = 25 c; f = 1mhz 10 pf note: 1. these parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. inputs are tied to v dd or ground. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where cur rent may be affected. ac electrical characteristics for commercial grade devices commercial: 0 c t amb +70 c; 4.75 v dd 5.25v symbol parameter 7 d unit symbol parameter min. max. min. max. unit t pd input or feedback to non-registered output 7.5 10 ns t su setup time from input, feedback or sp to clock 3 4 ns t co clock to output 6.75 8 ns t cf clock to feedback 1 2 3 ns t h hold time 0 0 ns t ar asynchronous reset to registered output 15 15 ns t arw asynchronous reset width 5 5 ns t arr asynchronous reset recovery time 5 5 ns t spr synchronous preset recovery time 5 5 ns t wl width of clock low 3 3 ns t wh width of clock high 3 3 ns t r input rise time 20 20 ns t f input fall time 20 20 ns f max1 maximum internal frequency 2 1/(t su + t cf ) 200 143 mhz f max2 maximum external frequency 1 1/(t su + t co ) 103 83 mhz f max3 maximum clock frequency 1 1/(t wl + t wh ) 167 167 mhz t ea input to output enable 9 10 ns t er input to output disable 9 10 ns capacitance c in input pin capacitance 10 10 pf c out output capacitance 12 12 pf notes: 1. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified w here frequency may be affected. 2. these parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. inputs are tied to v dd or ground. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where fre quency may be affected.
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 10 dc electrical characteristics for industrial grade devices industrial: 40 c t amb +85 c; 4.5 v dd 5.5v symbol parameter test conditions limits units symbol parameter test conditions min. typ. max. units v il input voltage low v dd = 4.5v 0.8 v v ih input voltage high v dd = 5.5v 2 v v i input clamp voltage v dd = 4.5v; i in = 18ma 1.2 v v ol output voltage low v dd = 4.5v; i ol = 8ma 0.5 v v oh output voltage high v dd = 4.5v; i ol = 4ma 2.4 v i i input leakage current v in = 0 to v dd 10 10 m a i oz 3-stated output leakage current v in = 0 to v dd 10 10 m a i ddq standby current v dd = 5.5v; t amb = 40 c 70 95 m a i ddd 1 dynamic current v dd = 5.5v; t amb = 40 c @ 1mhz 1 3 ma i ddd 1 dynamic current v dd = 5.5v; t amb = 40 c @ 50mhz 10 20 ma i sc short circuit output current 1 pin/time for no longer than 1 second 30 100 ma c in input pin capacitance t amb = 25 c; f = 1mhz 10 pf c clk clock input capacitance t amb = 25 c; f = 1mhz 5 12 pf c i/o i/o pin capacitance t amb = 25 c; f = 1mhz 10 pf note: 1. these parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. inputs are tied to v dd or ground. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where cur rent may be affected. ac electrical characteristics for industrial grade devices industrial: 40 c t amb +85 c; 4.5 v dd 5.5v symbol parameter limits unit symbol parameter min. max. unit t pd input or feedback to non-registered output 10 ns t su setup time from input, feedback or sp to clock 5 ns t co clock to output 8.5 ns t cf clock to feedback 1 4 ns t h hold time 0 ns t ar asynchronous reset to registered output 15 ns t arw asynchronous reset width 5 ns t arr asynchronous reset recovery time 5 ns t spr synchronous preset recovery time 5 ns t wl width of clock low 3 ns t wh width of clock high 3 ns t r input rise time 20 ns t f input fall time 20 ns f max1 maximum internal frequency 2 1/(t su + t cf ) 111 mhz f max2 maximum external frequency 1 1/(t su + t co ) 74 mhz f max3 maximum clock frequency 1 1/(t wl + t wh ) 167 mhz t ea input to output enable 11 ns t er input to output disable 11 ns capacitance c in input pin capacitance 10 pf c out output capacitance 12 pf notes: 1. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified w here frequency may be affected. 2. these parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. inputs are tied to v dd or ground. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where fre quency may be affected.
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 11 test load circuit +5v c l r 1 r 2 s 1 c 2 c 1 note: c 1 and c 2 are to bypass v cc to gnd. r 1 = 300 w , r 2 = 390 w , c l = 35pf. v cc gnd ck i n i 0 f 0 f n dut oe inputs sp00481 thevenin equivalent 35pf 170 w dut output v l = 2.83v sp00482 voltage waveform 90% 10% 1.5ns 1.5ns +3.0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00368
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 12 switching waveforms t s notes: 1. v t = 1.5v. 2. input pulse amplitude 0v to 3.0v. 3. input rise and fall times 2.0ns max. combinatorial output clock width input to output disable/enable asynchronous reset synchronous preset t pd v t v t input or feedback combinatorial output v t v t v t input or feedback clock registered output t s t h t co v t t wh clock t wl t er t ea v oh 0.5v v ol + 0.5v input output v t v t v t v t v t t arw t ar t arr clock registered output input asserting asynchronous reset t h v t v t v t v t t spr input asserting synchronous preset clock registered output t co sp00065 registered output aando array (i, b) i, b p, d code o state inactive 1 code state code state code state true hle p, d i, b i, b p, d i, b i, b p, d i, b i, b i, b complement don't care sp00008 i, b i, b i, b i, b note: 1. this is the initial state.
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 13 plcc28: plastic leaded chip carrer; 28 leads; pedestal sot261-3
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 14 so24: plastic small outline package; 24 leads; body width 7.5 mm sot137-1
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 15 tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1
philips semiconductors product specification p5z22v10 5v zero power, totalcmos ? , universal pld device 1997 may 02 16 philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performanc e. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under a ny patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copy right, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appl iances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonab ly be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or sel ling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. ? copyright philips electronics north america corporation 1997 all rights reserved. printed in u.s.a.

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