 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ctm CTMRM/d configurable timer module reference manual !motorola modular microcontroller family !motorola reference manual modular microcontroller family ctm f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m 1 2 3 4 5 6 7 8 9 10 a b c d functional overview bus interface unit submodule (biusm) interrupts counter prescaler submodule (cpsm) free-running counter submodule (fcsm) modulus counter submodule (mcsm) single action submodule (sasm) double action submodule (dasm) pulse width modulation submodule (pwmsm) electrical specifications register summary ctm example ?ctm2 glossary index f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m 1 2 3 4 5 6 7 8 9 10 a b c d functional overview bus interface unit submodule (biusm) interrupts counter prescaler submodule (cpsm) free-running counter submodule (fcsm) modulus counter submodule (mcsm) single action submodule (sasm) double action submodule (dasm) pulse width modulation submodule (pwmsm) electrical specifications register summary ctm example ?ctm2 glossary index f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 all products are sold on motorola? terms & conditions of supply. in ordering a product covered by this document the customer agrees to be bound by those terms & conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this notice). a copy of motorola? terms & conditions of supply is availab le on request. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation consequential or incidental damages. ?ypical?parameters can and do vary in different applications. all operating parameters, including ?ypicals? must be validated for each customer application by customer? technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and ! are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. the customer should ensure that it has the most up to date version of the document by contacting its local motorola office. this document supersedes any earlier documentation relating to the products referred to herein. the information contained in this document is current at the date of publication. it may subsequently be updated, revised or withdrawn. ?motorola ltd., 1997 gjl-ekb all trade marks recognized. this document contains information on new products. speci?ations and information herein are subject to change without notice. ctm con?urable timer module reference manual f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 conventions where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this document. register and bit mnemonics are de?ed in the paragraphs describing them. a horizontal bar over a signal name indicates that the signal is active-low, e.g. reset . unless stated otherwise, shaded cells in a register diagram indicate that the bits are either unimplemented bits or reserved, and always read as zero. in register diagrams, ? indicates that the state on reset is unde?ed. when a bit is ?et? it has the value 1 (one). when a bit is ?lear? it has the value 0 (zero). when a bit is ?eset? it has its default value, which may be 1 or 0. reference documents cpu16 central processor unit reference manual (cpu16rm/d) cpu32 central processor unit reference manual (cpu32rm/ad) gpt general purpose timer reference manual (gptrm/ad) an introduction to the hc16 for hc11 users (an461/d ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m customer feedback questionnaire (CTMRM) motorola wishes to continue to improve the quality of its documentation. we would welcome your feedback on the publication you have just received. having used the document, please complete this card (or a photocopy of it, if you prefer). 1. how would you rate the quality of the document? check one box in each category. excellent poor excellent poor organization tables readability table of contents understandability index accuracy page size/binding illustrations overall impression comments: 2. what is your intended use for this document? if more than one option applies, please rank them (1, 2, 3). selection of device for new application other please specify: system design training purposes 3. how well does this manual enable you to perform the task(s) outlined in question 2? completely not at all comments: 4. how easy is it to ?d the information you are looking for? easy dif?ult comments: 5. is the level of technical detail in the following sections suf?ient to allow you to understand how the device functions? too little detail too much detail comments: 6. have you found any errors? if so, please comment: 7. from your point of view, is anything missing from the document? if so, please say what: ?cut along this line to remove ctmlop ?his line does not form part of the document 11/nov/97@15:52 table of contents/list of figures/list of tables section 1 functional overview section 2 bus interface unit submodule (biusm) section 3 interrupts section 4 counter prescaler submodule (cpsm) section 5 free-running counter submodule (fcsm) section 6 modulus counter submodule (mcsm) section 7 single action submodule (sasm) section 8 double action submodule (dasm) section 9 pulse width modulation submodule (pwmsm) section 10 electrical specifications appendix a register summary appendix b ctm example ?ctm2 appendix c glossary appendix d index f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m 11/nov/97@15:52 ?his line does not form part of the document ctmlop 13. currently there is some discussion in the semiconductor industry regarding a move towards providing data sheets in electron ic form. if you have any opinion on this subject, please comment. 14. we would be grateful if you would supply the following information (at your discretion), or attach your card. name: phone no: position: fax no: department: company: address: thank you for helping us improve our documentation, graham livey, technical publications manager, motorola ltd., scotland . ?cut along this line to remove ?second fold back along this line ?third fold back along this line ?last tuck this edge into opposite ?p 8. how could we improve this document? 9. how would you rate motorola s documentation? excellent poor ?in general ?against other semiconductor suppliers 10. which semiconductor manufacturer provides the best technical documentation? 11. which company (in any ?ld) provides the best technical documentation? 12. how many years have you worked with microprocessors? less than 1 year 1? years 3? years more than 5 years by air mail par avion ne pas affranchir ibrs number phq-b/207/g ccri numero phq-b/207/g reponse payee grande-bretagne motorola ltd., colvilles road, kelvin industrial estate, east kilbride, g75 8br. great britain. f.a.o. technical publications manager (re: CTMRM/d) no stamp required ?first fold back along this line ! motorola ltd. semiconductor products sector section f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola i table of contents paragraph number page number title table of contents 1 functional overview 1.1 ctm features .........................................................................................................1-1 1.2 ctm description ....................................................................................................1-2 1.3 byte/word/long word accesses ..............................................................................1-3 1.3.1 8-bit (byte) accesses ........................................................................................1-3 1.3.2 16-bit (word) aligned accesses ........................................................................1-4 1.3.3 16-bit (word) misaligned accesses...................................................................1-4 1.3.4 32-bit (long word) aligned accesses ................................................................1-5 1.3.5 32-bit (long word) misaligned accesses ...........................................................1-5 1.3.6 3-byte accesses ...............................................................................................1-5 1.4 the time base bus system.....................................................................................1-5 1.5 pin descriptions .....................................................................................................1-6 1.6 input capture (ic) concepts ...................................................................................1-6 1.7 output compare (oc) concepts.............................................................................1-7 1.8 pulse accumulator (pa) concepts ..........................................................................1-8 1.9 pulse width modulation (pwm) concepts ..............................................................1-9 1.10 using and clearing ?g bits ...................................................................................1-10 2 bus interface unit submodule (biusm) 2.1 biusm description.................................................................................................2-1 2.2 freeze action on the biusm..................................................................................2-1 2.3 lpstop action on the biusm...............................................................................2-1 2.4 stop and wait action on the biusm ..................................................................2-2 2.5 biusm registers ....................................................................................................2-2 2.5.1 biumcr ?biusm module con?uration register ..........................................2-2 2.5.2 biutest ?biusm test con?uration register ...............................................2-4 2.5.3 biutbr ?biusm time base register .............................................................2-5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola ii ctm reference table of contents paragraph number page number title 3 interrupts 3.1 interrupt levels on the imb.....................................................................................3-1 3.2 arbitration ..............................................................................................................3-2 3.3 ctm daisy-chain priority........................................................................................3-2 4 counter prescaler submodule (cpsm) 4.1 cpsm description..................................................................................................4-1 4.2 freeze action on the cpsm...................................................................................4-2 4.3 cpsm registers .....................................................................................................4-2 4.3.1 cpcr ?cpsm control register......................................................................4-2 4.3.2 cptr ?cpsm test register ...........................................................................4-3 5 free-running counter submodule (fcsm) 5.1 fcsm description..................................................................................................5-1 5.2 the fcsm counter ................................................................................................5-1 5.3 fcsm clock sources..............................................................................................5-2 5.3.1 fcsm external event counting.........................................................................5-2 5.4 the fcsm time base bus driver............................................................................5-3 5.5 fcsm interrupts ....................................................................................................5-3 5.6 freeze action on the fcsm...................................................................................5-3 5.7.1 fcsmsic ?fcsm status/interrupt/control register .......................................5-4 5.7.2 fcsmcnt ?fcsm counter register .............................................................5-6 6 modulus counter submodule (mcsm) 6.1 mcsm description .................................................................................................6-1 6.2 the mcsm modulus latch .....................................................................................6-2 6.3 the mcsm counter ...............................................................................................6-2 6.3.1 loading the mcsm counter register ................................................................6-2 6.3.1.1 using the mcsm as a free-running counter...............................................6-3 6.4 mcsm clock sources.............................................................................................6-3 6.4.1 mcsm external event counting........................................................................6-3 6.5 the mcsm time base bus driver ...........................................................................6-4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola iii table of contents paragraph number page number title 6.6 mcsm interrupts....................................................................................................6-4 6.7 freeze action on the mcsm ..................................................................................6-4 6.8 mcsm registers .....................................................................................................6-4 6.8.1 mcsmsic ?mcsm status/interrupt/control register......................................6-5 6.8.2 mcsmcnt ?mcsm counter register ............................................................6-7 6.8.3 mcsmml ?mcsm modulus latch register ....................................................6-8 7 single action submodule (sasm) 7.1 sasm description ..................................................................................................7-1 7.2 sasm modes of operation.....................................................................................7-2 7.2.1 clearing and using the flag bits ....................................................................7-2 7.2.2 input capture (ic) mode ...................................................................................7-4 7.2.3 output compare (oc) mode ............................................................................7-4 7.2.4 output compare and toggle (oct) mode ........................................................7-5 7.2.5 output port (op) mode ....................................................................................7-5 7.3 sasm interrupts ....................................................................................................7-6 7.4 freeze action on the sasm ...................................................................................7-6 7.5 sasm registers......................................................................................................7-6 7.5.1 sica ?sasm status/interrupt/control register a............................................7-7 7.5.2 sdata ?sasm data register a......................................................................7-10 7.5.3 sicb ?sasm status/interrupt/control register b............................................7-10 7.5.4 sdatb ?sasm data register b .....................................................................7-11 8 double action submodule (dasm) 8.1 dasm description ..................................................................................................8-2 8.2 32-bit coherent access ..........................................................................................8-3 8.3 dasm modes of operation.....................................................................................8-3 8.3.1 disable (dis) mode..........................................................................................8-4 8.3.2 input pulse width measurement (ipwm) mode................................................8-4 8.3.3 input period measurement (ipm) mode ...........................................................8-5 8.3.4 input capture (ic) mode ...................................................................................8-7 8.3.5 output compare (ocb and ocab) modes ......................................................8-7 8.3.5.1 single shot output pulse operation .............................................................8-8 8.3.5.2 single output compare operation ...............................................................8-9 8.3.5.3 output port bit operation ............................................................................8-9 8.3.6 output pulse width modulation (opwm) mode................................................8-10 8.4 dasm interrupts ....................................................................................................8-12 8.5 freeze action on the dasm...................................................................................8-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola iv ctm reference table of contents paragraph number page number title 8.6 dasm registers .....................................................................................................8-13 8.6.1 dasmsic ?dasm status/interrupt/control register ......................................8-14 8.6.2 dasma ?dasm data register a ....................................................................8-18 8.6.3 dasmb ?dasm data register b ....................................................................8-18 8.7 dasm examples ....................................................................................................8-20 8.7.1 ic mode example.............................................................................................8-20 8.7.2 ipm mode example ..........................................................................................8-21 8.7.3 ocb mode example.........................................................................................8-22 8.7.4 pwm mode example........................................................................................8-24 9 pulse width modulation submodule (pwmsm) 9.1 pwmsm features ..................................................................................................9-1 9.2 pwmsm description..............................................................................................9-2 9.2.1 output ?p-?p and pin.....................................................................................9-2 9.2.2 clock selection.................................................................................................9-2 9.2.3 the pwmsm counter (pwmc)........................................................................9-3 9.2.4 pwmsm period registers and comparator.......................................................9-4 9.2.5 pwmsm pulse width registers and comparator...............................................9-4 9.2.5.1 0% and 100% ?ulses ................................................................................9-5 9.2.6 pwmsm coherency .........................................................................................9-5 9.2.7 pwmsm interrupts...........................................................................................9-6 9.2.8 freeze action on the pwmsm .........................................................................9-6 9.3 pwm frequency, pulse width and resolution..........................................................9-6 9.3.1 pwm frequency ...............................................................................................9-7 9.3.2 pwm pulse width .............................................................................................9-7 9.3.3 pwm period and pulse width register values...................................................9-8 9.4 pwmsm register map and registers......................................................................9-9 9.4.1 pwmsic ?status, interrupt and control register ...........................................9-9 9.4.2 pwma ?pwm period register .......................................................................9-12 9.4.3 pwmb ?pwm pulse width register ...............................................................9-13 9.4.4 pwmc ?pwm counter register .....................................................................9-14 10 electrical specifications 10.1 fcsm and mcsm timing information ..................................................................10-1 10.2 sasm timing information.............................................................................................................10-6 10.3 dasm timing information .....................................................................................10-9 10.4 pwmsm timing information .................................................................................10-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola v ctm reference table of contents paragraph number page number title appendix a register and bit summary a.1 biusm registers and bits...................................................................................... a-1 a.1.1 biumcr ?biusm module con?uration register ......................................... a-1 a.1.1.1 stop ?stop enable................................................................................ a-1 a.1.1.2 frz ?freeze enable............................................................................... a-1 a.1.1.3 vect7, vect6 ?interrupt vector base number bits............................... a-2 a.1.1.4 iarb[2:0] ?interrupt arbitration identi?ation bits ................................... a-2 a.1.1.5 tbrs1, tbrs0 ?time base register bus select bits .............................. a-2 a.1.2 biutest ?biusm test con?uration register .............................................. a-2 a.1.3 biutbr ?biusm time base register ............................................................ a-2 a.2 cpsm registers and bits....................................................................................... a-3 a.2.1 cpcr ?cpsm control register..................................................................... a-3 a.2.1.1 prun ?prescaler running bit ................................................................. a-3 a.2.1.2 div23 ?divide by 2 or divide by 3 bit...................................................... a-3 a.2.1.3 psel1, psel0 ?prescaler division ratio select bits ............................... a-3 a.2.2 cptr ?cpsm test register .......................................................................... a-3 a.3 fcsm registers and bits ....................................................................................... a-4 a.3.1 fcsmsic ?fcsm status/interrupt/control register ...................................... a-4 a.3.1.1 cof ?counter over?w ?g bit .............................................................. a-4 a.3.1.2 il[2:0] ?interrupt level bits ...................................................................... a-4 a.3.1.3 iarb3 ?interrupt arbitration bit 3 ............................................................ a-4 a.3.1.4 drva, drvb ?drive time base bus bits ................................................. a-5 a.3.1.5 in ?input pin status bit............................................................................ a-5 a.3.1.6 clk[2:0] ?counter clock select bits........................................................ a-5 a.3.2 fcsmcnt ?fcsm counter register ............................................................ a-5 a.4 mcsm registers and bits ...................................................................................... a-6 a.4.1 mcsmsic ?mcsm status/interrupt/control register..................................... a-6 a.4.1.1 cof ?counter over?w ?g bit .............................................................. a-6 a.4.1.2 il[2:0] ?interrupt level bits ...................................................................... a-6 a.4.1.3 iarb3 ?interrupt arbitration bit 3 ............................................................ a-6 a.4.1.4 drva, drvb ?drive time base bus bits ................................................. a-7 a.4.1.5 in2 ?clock input pin status bit ................................................................ a-7 a.4.1.6 in1 ?modulus load input pin status bit.................................................... a-7 a.4.1.7 edgen, edgep ?modulus load edge sensitivity bits............................ a-7 a.4.1.8 clk[2:0] ?counter clock select bits........................................................ a-7 a.4.2 mcsmcnt ?mcsm counter register........................................................... a-8 a.4.3 mcsmml ?mcsm modulus latch register ................................................... a-8 a.5 sasm registers and bits ....................................................................................... a-9 a.5.1 sica ?sasm status/interrupt/control register a........................................... a-9 a.5.1.1 flag ?event ?g bit............................................................................... a-9 a.5.1.2 il[2:0] ?interrupt level bits ...................................................................... a-9 a.5.1.3 iarb3 ?interrupt arbitration bit 3 ............................................................ a-9 a.5.1.4 ien ?interrupt enable bit......................................................................... a-9 a.5.1.5 bsl ?time base bus select bit ............................................................... a-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola vi ctm reference table of contents paragraph number page number title a.5.1.6 in ?input pin status bit............................................................................ a-10 a.5.1.7 force ?force compare control bit ....................................................... a-10 a.5.1.8 edout ?edge detect and output level bit.............................................. a-10 a.5.1.9 mode1, mode0 ?sasm operating mode select bits............................ a-10 a.5.2 sdata ?sasm data register a..................................................................... a-11 a.5.3 sicb ?sasm status/interrupt/control register b........................................... a-11 a.5.3.1 flag ?event ?g bit............................................................................... a-11 a.5.3.2 bsl ?time base bus select bit ............................................................... a-11 a.5.3.3 in ?input pin status bit............................................................................ a-11 a.5.3.4 force ?force compare control bit ....................................................... a-12 a.5.3.5 edout ?edge detect and output level bit.............................................. a-12 a.5.3.6 mode1, mode0 ?sasm operating mode select bits............................ a-12 a.5.4 sdatb ?sasm data register b .................................................................... a-12 a.6 dasm registers and bits....................................................................................... a-13 a.6.1 dasmsic ?dasm status/interrupt/control register ...................................... a-13 a.6.1.1 flag ?flag status bit ............................................................................. a-13 a.6.1.2 il[2:0] ?interrupt level bits ...................................................................... a-13 a.6.1.3 iarb3 ?interrupt arbitration bit 3 ............................................................ a-13 a.6.1.4 wor ?wired-or bit ............................................................................... a-13 a.6.1.5 bsl ?bus select bit ................................................................................ a-14 a.6.1.6 in ?input pin status bit............................................................................ a-14 a.6.1.7 forca ?force a bit............................................................................... a-14 a.6.1.8 forcb ?force b bit............................................................................... a-14 a.6.1.9 edpol ?edge polarity bit....................................................................... a-14 a.6.1.10 mode[3:0] ?mode select bits................................................................. a-15 a.6.2 dasma ?dasm data register a ................................................................... a-15 a.6.3 dasmb ?dasm data register b ................................................................... a-16 a.7 pwmsm registers and bits ................................................................................... a-17 a.7.1 pwmsic ?pwmsm status, interrupt and control register............................ a-17 a.7.1.1 flag ?period completion status bit ....................................................... a-17 a.7.1.2 il[2:0] ?interrupt level bits ...................................................................... a-17 a.7.1.3 iarb3 ?interrupt arbitration bit 3 ............................................................ a-17 a.7.1.4 pin ?output pin status bit....................................................................... a-17 a.7.1.5 load ?period and pulse width register load control bit ......................... a-18 a.7.1.6 pol ?output pin polarity control bit........................................................ a-18 a.7.1.7 en ?pwmsm enable control bit ............................................................. a-18 a.7.1.8 clk[2:0] ?clock rate selection bits......................................................... a-19 a.7.2 pwma ?pwm period register ...................................................................... a-19 a.7.3 pwmb ?pwm pulse width register .............................................................. a-19 a.7.4 pwmc ?pwm counter register .................................................................... a-20 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola vii table of contents paragraph number page number title appendix b ctm example ?ctm2 b.1 ctm2 registers ..................................................................................................... b-4 b.1.1 ctm2 bus interface unit submodule registers................................................. b-5 b.1.2 ctm2 counter prescaler submodule registers ................................................ b-5 b.1.3 ctm2 free-running counter submodule registers ........................................... b-5 b.1.4 ctm2 modulus counter submodule registers ................................................. b-5 b.1.5 ctm2 double action submodule registers ...................................................... b-6 appendix c glossary appendix d index f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola viii ctm reference table of contents this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola ix list of figures figure number page number title list of figures 1-1 ctm architecture block diagram.............................................................................1-2 1-2 8-bit (byte) access (even addresses)......................................................................1-3 1-3 8-bit (byte) access (odd addresses) .......................................................................1-4 1-4 16-bit (word) aligned access...................................................................................1-4 1-5 simpli?d block diagram of 16-bit input capture .....................................................1-7 1-6 simpli?d block diagram of 16-bit output compare.................................................1-7 1-7 simpli?d block diagram of a typical pulse accumulator ........................................1-8 1-8 pwm example waveforms ......................................................................................1-9 1-9 simpli?d block diagram of a typical 16-bit pwm system ......................................1-10 4-1 cpsm block diagram ..............................................................................................4-1 5-1 fcsm block diagram ..............................................................................................5-2 6-1 mcsm block diagram .............................................................................................6-1 7-1 sasm block diagram ..............................................................................................7-1 7-2 sasm block diagram (channel a)...........................................................................7-3 8-1 dasm block diagram ..............................................................................................8-1 8-2 input pulse width measurement example ...............................................................8-5 8-3 input period measurement example .......................................................................8-6 8-4 dasm input capture example .................................................................................8-7 8-5 single-shot output pulse example ..........................................................................8-9 8-6 single shot output transition example.....................................................................8-10 8-7 dasm output pulse width modulation example ......................................................8-11 9-1 pulse width modulation submodule block diagram.................................................9-3 10-1 fcsm and mcsm time base timing diagram example.........................................10-3 10-2 fcsm and mcsm clock pin to counter timing diagram ........................................10-4 10-3 mcsm load pin to counter timing diagram ...........................................................10-4 10-4 fcsm and mcsm pin to in bit timing diagram.....................................................10-5 10-5 fcsm and mcsm cof bit to interrupt request timing diagram ...........................10-5 10-6 sasm input capture timing diagram .....................................................................10-7 10-7 sasm pin to in bit timing diagram........................................................................10-7 10-8 sasm output compare timing diagram.................................................................10-8 10-9 sasm flag bit to interrupt request timing diagram ............................................10-8 10-10 dasm input capture timing diagram .....................................................................10-10 10-11 dasm pin to in bit timing diagram........................................................................10-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola x ctm reference list of figures figure number page number title 10-12 dasm output compare timing diagram................................................................. 10-11 10-13 dasm flag bit to interrupt request timing diagram ............................................ 10-11 10-14 pwmsm minimum output pulse example timing diagram .................................... 10-13 10-15 pwmsm cpsm enable to pwm output set timing diagram ................................. 10-13 10-16 pwmsm enable to output set timing diagram ...................................................... 10-14 10-17 pwmsm flag bit to interrupt request timing diagram ........................................ 10-14 b-1 con?urable timer module 2 (ctm2) .....................................................................b-2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola xi list of tables ta b l e number page number title list of tables 2-1 biusm register map ...............................................................................................2-2 3-1 ctm submodule and interrupt vector number convention......................................3-3 4-1 cpsm register map ................................................................................................4-2 5-1 fcsm register map ................................................................................................5-4 6-1 mcsm register map................................................................................................6-5 7-1 sasm register map ................................................................................................7-7 8-1 dasm modes of operation......................................................................................8-3 8-2 dasm pwm example output frequencies/resolutions at f sys = 16 mhz................8-12 8-3 dasm register map ................................................................................................8-13 9-1 pwm pulse and frequency ranges (in hz) using /2 option (16.78 mhz).................9-6 9-2 pwm pulse and frequency ranges (in hz) using /3 option (16.78 mhz).................9-7 9-3 pwmsm register map ............................................................................................9-9 9-4 pwmsm output pin polarity selection.....................................................................9-11 9-5 pwmsm clock rate selection ..................................................................................9-13 10-1 fcsm timing characteristics.................................................................................10-1 10-2 mcsm timing characteristics ................................................................................10-2 10-3 sasm timing characteristics.................................................................................10-6 10-4 dasm timing characteristics.................................................................................10-9 10-5 pwmsm timing characteristics.............................................................................10-12 b-1 time base bus allocation....................................................................................... b-3 b-2 ctm2 interrupt priority, vector allocation and pin allocation .................................. b-3 b-3 ctm2 register map................................................................................................ b-4 b-4 biusm register map .............................................................................................. b-5 b-5 cpsm register map ............................................................................................... b-5 b-6 fcsm register map ............................................................................................... b-5 b-7 mcsm register map............................................................................................... b-5 b-8 dasm register map ............................................................................................... b-6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola xii ctm reference list of tables this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 1-1 functional overview 1 1 functional overview the con?urable timer module (ctm) is an integral module of motorola s family of modular microcontrollers. members of this family are normally composed of several modules, interconnected by means of the intermodule bus (imb). the ctm is unusual in the sense that it is, in itself, modular and is composed of submodules, making it easily con?urable for different kinds of applications. 1.1 ctm features modular architecture counter submodules: clock prescaler 16-bit free-running counter 16-bit modulus counter action submodules: single action input capture/output compare channels double action input capture/output compare channels, with pwm (pulse width modulation) mode pwm channels i/o pin for each input capture/output compare output-only pin for each pwm channel external clock input capability interrupt capability on all capture/compare/pwm channels and on counter over?w conditions two, three or four time base buses, allowing great ?xibility in ctm con?uration f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 1-2 ctm reference functional overview 1 1.2 ctm description the highly modular architecture of the ctm is illustrated in figure 1-1. submodules are located on either side of the ctm s internal submodule bus (smb). all data and control signals within the ctm are passed over this bus. the smb is connected to the outside world via a special ctm submodule, known as the bus interface unit submodule (biusm), which is connected to the intermodule bus (imb) and hence to the main cpu. this con?uration allows the cpu to access the data and control registers in each ctm submodule on the smb. four local time base buses (tbb1 ?tbb4) are arranged in such a way that each ctm submodule can be connected to two of them. as can be seen in figure 1-1, ctm submodules numbered 1 to m-1 can be connected to tbb3 and tbb4 and ctm submodules m to n can be connected to tbb1 and tbb2. control bits within each ctm submodule allow the software to connect the submodule to the desired time base bus(es). during the design of the ctm module, the four local time base figure 1-1 ctm architecture block diagram submodule m bus interface unit submodule (biusm) intermodule bus (imb) time base bus 1 (tbb1) time base bus a (tbba) time base bus 3 (tbb3) time base bus 4 (tbb4) submodule bus (smb) submodule n submodule m+1 submodule m-1 submodule 1 submodule 2 time base bus b (tbbb) time base bus 2 (tbb2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 1-3 functional overview 1 buses can be connected together (as shown by the dotted lines in figure 1-1) to form two time base buses tbba (tbb1/tbb4) and tbbb (tbb2/tbb3). the time base buses are each 16-bits wide and are used to transfer timing information from counters to action submodules. each ctm submodule can either be a clock source module (and drive one or two of the time base buses) or an action submodule (and read and react to the timing information on the time base buses). every ctm module implementation must include at least a biusm and some form of clock submodule. all other submodules are optional and would be selected from a library of ctm submodules at the design stage, as required by the user to meet the needs of his application. 1.3 byte/word/long word accesses all ctm registers and data buses are 16 bits wide. consequently, 16-bit (word) accesses are the normal case. 8-bit and 32-bit accesses are also permitted; however, as there is no pipelining in the ctm, 8-bit coherency is not supported. 1.3.1 8-bit (byte) accesses 8-bit accesses are illustrated in figure 1-2 for even addresses and figure 1-3 for odd addresses. 1.3.2 16-bit (word) aligned accesses 16-bit aligned access is the normal case and such accesses of counter or action submodule registers is coherent. this is illustrated in figure 1-4. figure 1-2 8-bit (byte) access (even addresses) read ($00) write data 7:0 data 15:8 $00 imb smb ctm register read write data 7:0 data 15:8 data 15:8 data 7:0 write read f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 1-4 ctm reference functional overview 1 1.3.3 16-bit (word) misaligned accesses a 16-bit misaligned access consists of two 8-bit accesses, the ?st to an odd address (see figure 1-3), the second to the following even address (see figure 1-2). a 16-bit misaligned access is treated by the biu as an 8-bit odd address access. it is then the responsibility of the bus master to access the following byte. as in the case of the 8-bit access, since there is no pipelining, coherency is not supported. note: neither cpu16 nor cpu32 (see section on reference documents at the beginning ot this document) support 16-bit misaligned accesses. figure 1-3 8-bit (byte) access (odd addresses) figure 1-4 16-bit (word) aligned access read write data 7:0 data 15:8 $00 imb smb ctm register read write data 7:0 data 15:8 data 15:8 data 7:0 write read ($00) read or write data 15:0 imb smb ctm register data 15:0 data 15:0 read or write f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 1-5 functional overview 1 1.3.4 32-bit (long word) aligned accesses a long word aligned access consists of two 16-bit aligned accesses (see figure 1-4). when a long word access is attempted, a signal line is activated on the smb during the access of the high order byte. this allows the ctm architecture to be compatible with submodules supporting long word coherency. 1.3.5 32-bit (long word) misaligned accesses a long word misaligned access consists of three accesses: ?st a byte access to an odd address (see figure 1-3), followed by a 16-bit aligned access to the following even address (see figure 1-4), followed by a byte access to the remaining even address (see figure 1-2). note that the latter two accesses (16-bit aligned access followed by byte access to an even address) represent what is called a 3-byte access. as there is no pipelining, coherency is not supported. note: neither cpu16 nor cpu32 support 32-bit misaligned accesses. 1.3.6 3-byte accesses a 3-byte access is normally part of a long word misaligned access. it consists of a 16-bit aligned access (see figure 1-4), followed by a byte access to the remaining even address (see figure 1-2). a 3-byte access is treated by the biusm as a 16-bit aligned access. it is then the responsibility of the bus master to access the following byte. as there is no pipelining, coherency is not supported. 1.4 the time base bus system the time base bus system is composed of four 16-bit buses: tbb1, tbb2, tbb3 and tbb4 (see figure 1-1). typically, tbb2 and tbb3 are tied together to form a global bus (tbbb) while tbb1 and tbb4 remain as partial buses (collectively called tbba). how the submodules are connected to these time base buses is different for each ctm con?uration. this is shown generically in figure 1-1, where all counter and action submodules in the right half of the diagram (numbered from 1 to m-1) can be connected to tbb3 and/or tbb4, and all submodules in the left half of the diagram (numbered from m to n) can be connected to tbb1 and/or tbb2. an example of how the time base buses are con?ured and how the submodules are connected to them in a practical ctm module (ctm2) is provided in appendix b. the time base buses are precharge/discharge type buses with wired-or capability, so that no hardware damage occurs when several counters are driving the same bus at the same time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 1-6 ctm reference functional overview 1 depending on software options, counter and action submodules located in the left half of figure 1-1 (submodules m to n) can be connected to buses tbb1 or tbb2, while counter and action submodules located in the right half of figure 1-1 (submodules 1 to m-1) can be connected to buses tbb3 and tbb4. 1.5 pin descriptions input/output requirements are speci? to each ctm submodule; pin allocation and functionality is described in the relevant sections of this document. 1.6 input capture (ic) concepts a typical 16-bit input capture function is shown in figure 1-5. it has three basic parts: edge select logic, a 16-bit input capture latch and a 16-bit free-running counter. the edge select logic determines the input signal transition (rising or falling) that triggers the input capture circuitry. when the selected transition occurs, the contents of the counter are latched into the input capture latch. this action sets a status ?g indicating that an input capture has occurred. an interrupt is generated if enabled. the value of the count latched or ?aptured is the time of the event. because this value is stored in the input capture register when the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. however, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. by recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. to measure a period, two successive edges of the same polarity are captured. to measure a pulse width, consecutive edges of opposing polarity are captured. for example, to measure the high time of a pulse, the input transition time is captured on the rising edge and subtracted from the time captured on the subsequent falling edge. when the period or pulse width is less than a full 16-bit counter over?w period, the measurement is very straightforward. in practice, however, software usually must keep track of the number of over?ws of the 16-bit counter in order to extend the range. another typical use of the input capture function is to establish a time reference. in this case it may be used in conjunction with an output compare function in the same timer. for example, consider the case where it is required to generate an output signal transition a speci? number of clock cycles after detecting an event (edge). the input capture function can be used to record the time at which the event occurred. a number corresponding to the desired delay can then be added to this captured value and stored in an output compare register. because input capture and output compare functions are referenced to the same 16-bit counter, the delay can be controlled to the resolution of the free-running counter, independent of software latencies. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 1-7 functional overview 1 1.7 output compare (oc) concepts output compare functions are used to cause events to occur at speci? times, i.e. to cause signal transitions to occur on an output pin. a typical 16-bit output compare function is shown in figure 1-6; it comprises a 16-bit compare register, a 16-bit comparator and a 16-bit free-running counter. when the value stored in the compare register matches the value of the free-running counter, the comparator sets an output compare ?g. other events can occur when the output compare ?g is set: an interrupt may be generated (if interrupts are enabled) and the logic levels on pins associated with the output compare function may change. the output compare function can generate an output of a speci? duration and polarity. a 16-bit value corresponding to the time a when a pin state change will occur is written to the output figure 1-5 simpli?d block diagram of 16-bit input capture figure 1-6 simpli?d block diagram of 16-bit output compare 16-bit free-running counter input capture latch edge select logic clock data bus event 16-bit free running counter 16-bit comparator clock 16-bit output compare register output match = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 1-8 ctm reference functional overview 1 compare register. the output compare function is con?ured to generate a high or low output automatically on the pin, or to toggle the state on the pin, when the match occurs. the output compare register is loaded with a new value after the compare occurs. typically, more than one output compare function is associated with each pin; because pin state changes occur automatically at speci? values of the free-running counter, the pulse width can be controlled to the resolution of the free-running counter independent of software latencies. a periodic pulse of a speci? frequency and duty cycle can be generated by repeating the above steps. 1.8 pulse accumulator (pa) concepts pulse accumulator systems are usually based on 8 or 16 bits. a typical 16-bit pulse accumulator is shown in figure 1-7; it consists of a 16-bit counter and edge select logic, and has two modes of operation: event counting mode and gated mode. in event counting mode, the counter is incremented each time an event occurs. in gated mode, an internal clock source increments the counter while a selected level is present on the input pin (the gate). when the signal on the input pin is negated, the counter is stopped. two status flags are available: one to indicate the occurrence of an event, and the other to indicate counter over?w. either of these ?gs can cause the processor to be interrupted. the pulse accumulator can be used, for example, to count the number of items going by on a conveyor belt or the number of teeth that have gone by on a crankshaft timing gear. as each item or tooth is detected, the counter is incremented (event counting mode). the counter therefore contains the number of items (or teeth). the ?g indicates the occurrence of an event (an item or tooth went by). if interrupts are enabled, an interrupt is generated. software can read the counter at this time. figure 1-7 simpli?d block diagram of a typical pulse accumulator 16-bit counter 16-bit counter clock event & event event counting mode gated time accumulator mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 1-9 functional overview 1 the gated mode of operation can be used to measure the pulse width or period of an input signal. when the input to the pulse accumulator is active, the counter begins counting the input clock. when the signal is negated it stops counting. if the counter is set to zero before the pulse starts, the count value multiplied by the clock period gives the width of the input pulse to the nearest clock period. this could be used to determine how long a stimulus is present. in an 8-bit pulse accumulator only 255 events can be counted before the counter over?ws; the over?w ?g can be used to extend the counter range beyond this value if required. 1.9 pulse width modulation (pwm) concepts a pwm waveform is created when the mark-to-space ratio of a periodic rectangular signal can be varied. if the waveform can be incrementally changed by 1/65536 of its period, it has 16 bits of resolution (see figure 1-8). a typical 16-bit pwm system (motorola s general purpose timer, or gpt) is shown in figure 1-9. each time the counter over?ws from $ffff to $0000, the zero detector sets the output latch (output pin in high state). the zero detector is used as the reference to start the high time. as the counter is incremented, the counter value is compared with the contents of the pulse width register. when the comparator detects a match, the latch is reset. by changing the value in the pulse width register, the duty cycle is continuously variable in 1/65536 increments. if the pulse width register contains $0000, the output latch will always be in the reset condition (output pin in low state). if the pulse width register is loaded with $0001, the output latch will be set for one count before being reset for the remainder of the period. if the register contains $8000 (32768 in decimal), the latch will be set for 32768 counts of the timer before being reset, resulting in a duty cycle of 50%. provision is usually made to allow a 100% duty cycle (output latch always set; output pin always high) to be generated. varying the input clock frequency to the pwm counter also varies the period of the pwm signal. figure 1-8 pwm example waveforms 65536 increments 1/65536 32768/65536 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 1-10 ctm reference functional overview 1 typically, pwm systems are provided with increased ?xibility via additional features such as output polarity selection, variable resolution and variable pulse periods. 1.10 using and clearing ?g bits to clear any ?g bit in the ctm, the software must ?st read the register containing the ?g in question (usually the sic register), then write a zero to the ?g bit. these two steps do not have to be done on consecutive instructions. writing a one to the ?g bit has no effect. note: the ?g clearing mechanism will work only if no ?g setting event occurs between the read and write operations; if a ?g setting event occurs between the read and write operations, the ?g bit will not be cleared. figure 1-9 simpli?d block diagram of a typical 16-bit pwm system 16-bit pulse width register 16-bit comparator output compare register output latch r s zero detector clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 2-1 bus interface unit submodule (biusm) 2 2 bus interface unit submodule (biusm) 2.1 biusm description the biusm connects the ctm s smb to the imb and allows the ctm submodules to communicate with the bus master (usually a cpu). the biusm also communicates interrupt requests, from the ctm submodules to the imb, and transfers the interrupt level, arbitration bit and vector number to the cpu during the interrupt acknowledge cycle. the biusm contains a module con?uration register, a time base bus register and a test register (for factory testing only). 2.2 freeze action on the biusm when the imb freeze condition is detected, the frz bit in the biusm module con?uration register determines whether or not the freeze condition is passed on to the other ctm submodules. if frz = 0, the freeze condition is ignored; if frz = 1, the biusm passes the freeze signal from the imb through to the ctm submodules. each ctm submodule then reacts to the freeze signal as de?ed by its own internal circuitry and control bits. 2.3 lpstop action on the biusm when the cpu is stopped by an lpstop instruction (from cpu32 or cpu16), the system clock (f sys ) is stopped, thereby shutting down all dependent modules, including the ctm, until the low-power stop mode is exited. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 2-2 ctm reference bus interface unit submodule (biusm) 2 2.4 stop and wait action on the biusm when the stop instruction on cpu32 or the wait instruction on cpu16 is executed, only the cpu is stopped; the ctm continues to operate as normal. (to stop the ctm operation selectively, refer to the description of the stop bit in section 2.5.1). 2.5 biusm registers the biusm register map comprises four 16-bit register locations. as shown in table 2-1, the register block contains the three biusm registers and one reserved register. the biusm register block always occupies the ?st four register locations in the ctm register space and cannot be relocated within the ctm structure. all unused bits and reserved address locations return zero when read by the software. writing to unused bits and reserved address locations has no effect. note: all biusm register addresses in this section are speci?d as offsets from the base address of the ctm. 2.5.1 biumcr ?biusm module con?uration register the biumcr register contains nine de?ed bits that allow the software to control ?e functions of the ctm: enabling/disabling of the module, response to freeze, vector base address, interrupt arbitration number and access to the time base buses (via the time base register). (1) offset from the base address of the ctm. (1) offset from the base address of the ctm. table 2-1 biusm register map address (1) 15 8 7 0 $00 biusm module con?uration register (biumcr) $02 biusm test register (biutest) $04 biusm time base register (biutbr) $06 bit: 15 14 13 12 11 10 9876543210 biumcr $00 (1) stop frz vect7 vect6 iarb2 iarb1 iarb0 tbrs1 tbrs0 reset: 0001100000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 2-3 bus interface unit submodule (biusm) 2 stop ?stop enable the stop bit, while asserted, activates the freeze signal on the smb regardless of the state of the freeze signal on the imb. this completely stops the operation of the ctm. note that some submodules may validate this signal with internal enable bits. the biusm continues to operate to allow the cpu access to the submodule s registers. the smb freeze signal remains active until reset or until the stop bit is negated by the cpu (via the imb). the stop bit is cleared by reset. 1 (set) stops operation of the ctm. 0 (clear) allows operation of the ctm. frz ?freeze enable the frz bit, while asserted, activates the freeze signal on the smb when the freeze signal on the imb is active. this completely stops the operation of the ctm. note that some submodules may validate this signal with internal enable bits. the biusm continues to operate to allow the cpu access to the submodule s registers. the smb freeze signal remains active until the frz bit is cleared or the imb freeze signal is negated. the frz bit is cleared by reset. 1 (set) halts the ctm sub module when the freeze signal appears on the imb. 0 (clear) ignores the freeze signal on the imb. vect7, vect6 ?interrupt vector base number bits the interrupt vector base number bits select the interrupt vector base number for the ctm. of the 8 bits necessary for vector number de?ition, the six least signi?ant bits are programmed by hardware on a submodule basis, while the two remaining bits are provided by vect7 and vect6. this places the ctm vectors in one of four possible positions in the interrupt vector table, as follows. note: the reader should refer also to section 3.4 and to the relevant cpu reference manuals for more detailed information on interrupt vector tables. vect7 vect6 resulting vector base number 0 0 $00 0 1 $40 1 0 $80 1 1 $c0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 2-4 ctm reference bus interface unit submodule (biusm) 2 iarb[2:0] ?interrupt arbitration identi?ation bits the interrupt arbitration bit ?ld (iarb), composed of iarb[2:0] in the biumcr and the iarb3 bit within each submodule, provides ?teen different arbitration identi?ation numbers that can be used to arbitrate between interrupt requests occurring on the imb with the same interrupt priority level. the iarb ?ld defaults to zero on reset, thus preventing the module from arbitrating during an interrupt arbitration acknowledge cycle (iack). if no imb arbitration takes place during the iack cycle the spurious interrupt vector is generated by the sim (system integration module). this tells the system that the interrupt arbitration number has not been initialized. the seven levels of interrupt are the primary means by which interrupt priority is established. the 4-bit interrupt arbitration number is the secondary priority, allowing up to 15 requests at each primary level. during the iack cycle the request with the highest arbitration number gets serviced (binary 1111 is the highest priority and binary 0001 is the lowest). many imb modules have one software assignable arbitration number for the whole module. the ctm allows two different arbitration numbers to be used by providing each submodule with its own iarb3 bit (which can be set or cleared in software). once iarb[2:0] are assigned in the biusm, they apply to all ctm interrupt requests. therefore, ctm submodule interrupts can be interleaved in priority with requests from other modules at the same interrupt level. iarb[2:0] are all cleared by reset. tbrs1, tbrs0 ?time base register bus select bits these bits specify which time base bus is accessed when the time base register (biutbr) is read. 2.5.2 biutest ?biusm test con?uration register the biutest register is located at ctm base address offsets $02 and $03 and is reserved for factory testing of the ctm. tbrs1 tbrs0 time base bus 0 0 tbb1 0 1 tbb2 1 0 tbb3 1 1 tbb4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 2-5 bus interface unit submodule (biusm) 2 2.5.3 biutbr ?biusm time base register in normal operation, the biutbr is a read-only register used to read the value present on one of the time base buses. the time base bus being accessed is determined by tbrs1 and tbrs0 in the biumcr. writing to the biutbr has no effect, except in certain test modes. (1) offset from the base address of the ctm. bit: 15 14 13 12 11 10 9876543210 biutbr $04 (1) msb lsb reset: 0000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 2-6 ctm reference bus interface unit submodule (biusm) this page intentionally left blank 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 3-1 interrupts 3 3 interrupts this section describes the interrupt functions of the ctm and its submodules and how these interrupts are passed to the cpu via the imb. interrupt requests from the ctm are treated as exceptions by the cpu and are dealt with by the cpu s exception processing routines. for a more detailed description of exception processing in imb based microprocessors, please refer to the following motorola publications: cpu16 central processor unit reference manual (cpu16rm/d) cpu32 central processor unit reference manual (cpu32rm/ad) 3.1 interrupt levels on the imb the ctm and its submodules are capable of generating interrupts on eight different levels on the intermodule bus (imb). interrupt levels, arbitration and a hardwired daisy-chain priority system of the submodules in the ctm allow each of the many interrupt sources on the imb to be uniquely identi?d and to have a unique vector address. each ctm submodule contains an interrupt control register that sets the interrupt priority for the submodule to one of eight levels (il[2:0]). level 7 is the highest priority level and level 0 disables interrupts. (note that the cpsm and the biusm do not have the capability to generate interrupts and do not have interrupt vectors associated with them.) when an interrupt is requested and is at a higher level than the current interrupt level set by the interrupt or exception level mask in the cpu s status register, the cpu starts an interrupt acknowledge (iack) cycle. the ctm compares the interrupt level it requested with the interrupt level acknowledged by the cpu during the iack cycle. if the levels match, arbitration with other modules requesting service on the same interrupt level begins. an interrupt of the same level as the cpu s current interrupt or exception level mask cannot be executed until the mask level reduces below that level, except for level 7 interrupts. level 7 is non maskable and exception processing on this level will be interrupted by other level 7 interrupts. a higher level exception will interrupt a lower level exception routine, which must then wait until the exception mask returns to its original level before continuing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 3-2 ctm reference interrupts 3 3.2 arbitration the interrupt and exception processing system on imb family devices is very similar to that used in the m68000 microprocessor family architecture, and is designed to support a very large number of interrupt sources. within each of the eight interrupt request levels, de?ed by il[2:0], there are sixteen different arbitration priority levels, de?ed by iarb[3:0], available to each imb module. level 15 is the highest arbitration priority level and level 1 is the lowest. level 0 is a special case and is treated by the cpu as a spurious interrupt. interrupting modules present their arbitration id (iarb[3:0]) on the imb and the module with the highest id wins. note: simultaneous interrupts on the same interrupt level are arbitrated on the basis of the four arbitration bits iarb[3:0]. consequently, no two imb modules may have the same iarb ?ld value. in the ctm, iarb[2:0] are contained within the biusm module con?uration register (biumcr) and are common to all the ctm submodules, and each ctm submodule contains its own il[2:0] and iarb3 bits. this allows each ctm submodule to request interrupts with one of two arbitration levels on any one of the 8 available interrupt levels. for example, if the iarb[2:0] bits in the biumcr are set to 101, each submodule can have an arbitration priority level of 0101 (5) or 1101 (13), depending on the state of the iarb3 bit. 3.3 ctm daisy-chain priority to allow resolution between ctm submodule interrupts on the same interrupt level (il[2:0]) and with the same arbitration priority (iarb3), the six hardwired vector bits (vect[5:0]) in each submodule provide a hardware system of priority, or daisy-chain, within the ctm. the submodules are daisy-chained in descending order of their vector numbers, i.e. submodule 0 has the highest position in the daisy-chain and will win over all other submodules generating simultaneous interrupts on the same level with the same arbitration. the position of each submodule in the daisy-chain is speci? to each different ctm variant. this is shown generically in table 3-1. for an example of the daisy-chain structure of a speci? ctm implementation, ctm2, see appendix b. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 3-3 interrupts 3 3.4 interrupt vector number and vector address if the ctm wins an arbitration sequence, it generates a uniquely coded 8-bit interrupt vector number that indicates which timer submodule is requesting service. the two highest order bits (vect[7:6]) of the interrupt vector number come from the biumcr and establish the vector base number of the ctm at $00, $40, $80 or $c0. the remaining bits of the interrupt vector number (vect[5:0]) are hardwired into each ctm submodule and are unique for each interrupt source. the vector address is obtained by multiplying the vector base number by two. (see table 3-1.) note: some ctm submodules, e.g. the sasm, have more than one interrupt source and therefore have a corresponding number of vectors and uniquely coded vector base numbers. (1) vbn = $00, $3f, $7f or $bf depending on the state of the vect[7:6] bits in the biusm. table 3-1 ctm submodule and interrupt vector number convention submodule number interrupt vector number (1) (vbn + vect[5:0]) daisy-chain priority 0 vbn highest 1 vbn + 1 lowest 2 vbn + 2 3 vbn + 3 4 vbn + 4 61 vbn + $3d 62 vbn + $3e 63 vbn + $3f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 3-4 ctm reference interrupts this page intentionally left blank 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 4-1 counter prescaler submodule (cpsm) 4 4 counter prescaler submodule (cpsm) 4.1 cpsm description the counter prescaler submodule (cpsm) is a programmable divider system that provides the ctm counters with a choice of six clock signals (pclkx) derived from the main mcu system clock (f sys ). the ?st counter prescaler stage generates pclk1 by dividing f sys by 2 or by 3. the output of this ?st counter is then applied to an 8-bit prescaler which divides the clock signal further (by 2, 4, 8 and 16) to produce pclk2, pclk3, pclk4 and pclk5 (respectively). the division ratio for pclk6 is software selectable (using the psel[1:0] control bits in the counter prescaler control register) from divide by 32, 64, 128 and 256. a block diagram of the cpsm is given in figure 4-1. the clock division ratios available on pclkx are also shown in the table in section 4.3.1. these clock signals are provided on the smb and may be used by any or all ctm submodules. figure 4-1 cpsm block diagram f sys 8-bit pclk2 = pclk3 = pclk4 = pclk5 = pclk6 = first cpsm select pclk1 = /2 /4 /8 /16 /32 prescaler /64 /128 /256 prun div23 psel1 psel0 cpcr prescaler /2 or /3 f sys /2 f sys /4 f sys /8 f sys /16 f sys /32 f sys /64 f sys /128 f sys /256 f sys /512 f sys /3 f sys /6 f sys /12 f sys /24 f sys /48 f sys /96 f sys /192 f sys /384 f sys /768 div23 = /3 div23 = /2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 4-2 ctm reference counter prescaler submodule (cpsm) 4 4.2 freeze action on the cpsm when the imb freeze signal is recognized, the cpsm counters stop counting and remain set at their current values. when the freeze signal is negated, the counters start incrementing from their current values, as if nothing had happened. all registers are accessible during freeze. 4.3 cpsm registers the cpsm register map comprises four 16-bit register locations. as shown in table 4-1, the register block contains two cpsm registers and two reserved registers. the cpsm register block always immediately follows the biusm register block in the cpsm register map. all unused bits and reserved address locations return zero when read by the software. writing to unused bits and reserved address locations has no effect. note: all cpsm register addresses in this section are speci?d as offsets from the base address of the ctm. 4.3.1 cpcr ?cpsm control register prun ?prescaler running bit the prun bit is a read/write control bit that allows the software to switch the prescaler counter on and off. (1) offset from the base address of the ctm. (1) offset from the base address of the ctm. table 4-1 cpsm register map address (1) 15 8 7 0 $08 cpsm control register (cpcr) $0a cpsm test register (cptr) $0c $0e bit: 15 14 13 12 11 10 9876543210 cpcr $08 (1) prun div23 psel1 psel0 reset: 0000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 4-3 ctm reference counter prescaler submodule (cpsm) 4 1 (set) prescaler is running. 0 (clear) prescaler divider is held in reset and is not running. this bit allows the counters in various ctm submodules to be synchronized. it is cleared by reset. div23 ?divide by 2 or divide by 3 bit the div23 bit is a read/write control bit that selects the division ratio of the ?st prescaler counter. it may be changed by the software at any time and is cleared on reset. 1 (set) first prescaler stage divides by 3. 0 (clear) first prescaler stage divides by 2. psel1, psel0 ?prescaler division ratio select bits these control bits select the division ratio of the programmable prescaler output signal, pclk6. 4.3.2 cptr ?cpsm test register this test register is located at ctm address offsets $0a and $0b and is reserved for factory testing of the cpsm. prescaler control register bits prescaler division ratio prun div23 psel1 psel0 pclk1 pclk2 pclk3 pclk4 pclk5 pclk6 0xxx000000 1000248163264 10012481632128 10102481632256 10112481632512 11003612244896 110136122448192 111036122448384 111136122448768 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 4-4 ctm reference counter prescaler submodule (cpsm) this page intentionally left blank 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 5-1 free-running counter submodule (fcsm) 5 5 free-running counter submodule (fcsm) 5.1 fcsm description the free-running counter submodule (fcsm) provides a multipurpose xed time base for use in a wide range of applications, such as input capture, output compare and pwm signal generation. the fcsm can also be con?ured to operate as an event counter; in this case, a ?g is set after a prede?ed number of events (internal clocks or external events). a block diagram of the fcsm is shown in figure 5-1. the main components of the fcsm are a 16-bit loadable free-running up-counter, a clock selector, a time base bus driver and an interrupt interface. note: in order to be able to count, the fcsm requires the cpsm clock signals to be present. on coming out of reset, the fcsm will not count internal or external events until the prescaler in the cpsm starts running (when the software sets the prun bit). this allows all counters in the ctm submodules to be synchronized. 5.2 the fcsm counter the fcsm counter section comprises a 16-bit register and a 16-bit up-counter. reading the register transfers the contents of the counter to the data bus, while a write to the register loads the counter with the new value. over?w of the counter is de?ed to be the transition from $ffff to $0000. an over?w condition causes the cof ?g bit in the fcsmsic register to be set. note: reset presets the counter register to $0000. writing $0000 to the counter register while the counter s value is $ffff does not set the cof ?g and does not generate an interrupt request. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 5-2 ctm reference free-running counter submodule (fcsm) 5 5.3 fcsm clock sources the user can choose from eight software selectable counter clock sources: six prescaler outputs (pclkx) input pin rising edge detection on the input pin ctmc input pin falling edge detection on the input pin ctmc the clock source is selected by the clk[2:0] bits in the fcsm status, interrupt and control register fcsmsic (see section 5.7.1). when the clk[2:0] bits are being changed, internal circuitry ensures that spurious edges occurring on the ctmc pin do not affect the fcsm. note that the read-only in bit of the fcsmsic register re?cts the state of the input pin ctmc. the input pin is schmitt triggered and is synchronized with the system clock (f sys ). 5.3.1 fcsm external event counting when an external clock source (on the input pin) is selected, the fcsm is in the event counter mode. the counter can simply count the number of events occurring on the input pin. alternatively, the fcsm can be programmed to generate an interrupt when a prede?ed number of events have been counted; this is done by presetting the counter with the two s complement value of the figure 5-1 fcsm block diagram 16-bit up counter il2 il1 il0 iarb3 cof edge time base buses input pin il1 interrupt clock in clk1 clk0 clk2 over?w bus control register bits control register bits drva drvb control register bits 6 clocks (pclkx) from prescaler submodule bus control select select detect ctmc tbba tbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 5-3 free-running counter submodule (fcsm) 5 desired number of events. when using the external clock source, the maximum guaranteed external frequency is f sys /4. 5.4 the fcsm time base bus driver the drva and drvb bits in the fcsmsic register select the time base buses to be driven (see section 5.7.1). which of the time base buses is driven depends on where the fcsm is physically placed in any particular ctm implementation. see section 1.4 for more information on the structure of the time base buses. for examples of fcsm waveforms and timings, please refer to section 10.1. warning: it is not recommended that the two time base buses be driven at the same time. 5.5 fcsm interrupts a valid fcsm interrupt can be generated when the cof bit in the fcsmsic register is set (as a result of the counter over?wing). if the interrupt priority level of the fcsm is non-zero, as de?ed by the three il bits in the fcsmsic register, a valid interrupt request will occur on the imb. 5.6 freeze action on the fcsm when the imb freeze signal is recognized, the fcsm counter stops counting and remains set at its current value. when the freeze signal is negated, the counter starts incrementing from its current value, as if nothing had happened. all registers are accessible during freeze. during freeze, the in bit in the fcsmsic register continues to re?ct the state of the signal on the input pin ctmc (see section 5.7.1). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 5-4 ctm reference free-running counter submodule (fcsm) 5 5.7 fcsm registers the fcsm register map comprises four 16-bit register locations. as shown in table 5-1, the register block contains two fcsm registers and two reserved registers. all unused bits and reserved address locations return zero when read by the software. writing to unused bits and reserved address locations has no effect. in ctm implementations featuring multiple fcsms, each fcsm has its own set of registers. note: all register addresses in this section are offsets from the base address of the fcsm. 5.7.1 fcsmsic ?fcsm status/interrupt/control register cof ?counter over?w ?g bit this status ?g bit indicates whether or not a counter over?w has occurred. an over?w is de?ed to be the transition of the counter from $ffff to $0000. if the il ?ld is non-zero, an interrupt request is generated when the cof bit is set. 1 (set) counter over?w has occurred. 0 (clear) counter over?w has not occurred. this ?g bit is set only by the hardware and cleared only by the software or by a system reset. to clear the ?g, the software must ?st read the bit (as ?ne? then write a ?ero to the bit. note: the ?g clearing mechanism will work only if no ?g setting event occurs between the read and write operations; if a cof setting event occurs between the read and write operations, the cof bit will not be cleared. (1) offset from the base address of the fcsm submodule. (1) offset from the base address of the fcsm submodule. table 5-1 fcsm register map address (1) 15 8 7 0 $00 status, interrupt and control register (fcsmsic) $02 counter register(fcsmcnt) $04 $06 bit: 15 14 13 12 11 10 9876543210 fcsmsic $00 (1) cof il2 il1 il0 iarb3 drva drvb in clk2 clk1 clk0 reset: 00000000u0000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 5-5 free-running counter submodule (fcsm) 5 il[2:0] ?interrupt level bits the three interrupt level bits are read/write control bits that select the priority level of interrupt requests made by the fcsm. these bits can be read or written at any time and are cleared by reset. iarb3 ?interrupt arbitration bit 3 the read/write iarb3 bit works in conjunction with the iarb[2:0] ?ld in the biusm module con?uration register. each module that generates interrupt requests on the imb must have a unique value in the arbitration ?ld (iarb). this interrupt arbitration identi?ation number is used to arbitrate for the imb when modules generate simultaneous interrupts of the same priority (see section 3). the iarb3 bit is cleared by reset. drva, drvb ?drive time base bus bits drva and drvb are read/write bits that control the connection of the fcsm to the time base buses a and b. these bits are cleared by reset. (see section 1.4 for information on the time base buses.) warning: it is not recommended that the two time base buses be driven at the same time. in ?input pin status bit this read-only status bit re?cts the logic state of the fcsm input pin ctmc. writing a ?ero or a ?ne to this bit has no effect. reset has no effect on this bit. il2 il1 il0 selected level 0 0 0 interrupt disabled 0 0 1 interrupt level 1 (lowest) 0 1 0 interrupt level 2 0 1 1 interrupt level 3 1 0 0 interrupt level 4 1 0 1 interrupt level 5 1 1 0 interrupt level 6 1 1 1 interrupt level 7 (highest) drva drvb bus selected 0 0 neither time base bus a nor time base bus b is driven 0 1 time base bus b is driven 1 0 time base bus a is driven 1 1 both time base bus a and time base bus b are driven f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 5-6 ctm reference free-running counter submodule (fcsm) 5 clk[2:0] ?counter clock select bits these read/write control bits select one of six internal clock signals (pclkx) or one of two external conditions on the input pin (rising edge or falling edge). the maximum frequency of the external clock signals is f sys /4. 5.7.2 fcsmcnt ?fcsm counter register the fcsm counter register is a read/write register; it is cleared by reset. (1) offset from the base address of the fcsm submodule. clk2 clk1 clk0 free running counter clock source 0 0 0 prescaler output 1 (/2 or /3) 0 0 1 prescaler output 2 (/4 or /6) 0 1 0 prescaler output 3 (/8 or /12) 0 1 1 prescaler output 4 (/16 or /24) 1 0 0 prescaler output 5 (/32 or /48) 1 0 1 prescaler output 6 (/64 to /512 or /96 to /768) 1 1 0 ctmc pin input, negative edge 1 1 1 ctmc pin input, positive edge bit: 15 14 13 12 11 10 9876543210 fcsmcnt $02 (1) msb lsb reset: 0000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 6-1 modulus counter submodule (mcsm) 6 6 modulus counter submodule (mcsm) 6.1 mcsm description the mcsm is a versatile timer submodule capable of performing complex counting and timing functions, including modulus counting, in a wide range of applications. the mcsm may also be con?ured as an event counter, allowing the over?w ?g to be set after a prede?ed number of events (internal clocks or external events), or as a variable time source for pwm generation. note that the mcsm can also operate as a free running counter; in this case it behaves exactly like an fcsm. a block diagram of the mcsm is shown in figure 6-1. figure 6-1 mcsm block diagram 16-bit up counter il2 il1 il0 iarb3 cof edge time base buses clock input il1 interrupt clock in2 clk1 clk0 clk2 over?w bus control register bit control register bits 6 clocks (pclkx) from prescaler submodule bus control select select detect modulus control modulus register control register bits edgen edgep pin ctmc edge modulus load detect input pin ctml in1 control register bits write both drva drvb control register bits tbba tbbb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 6-2 ctm reference modulus counter submodule (mcsm) 6 the main components of the mcsm are a 16-bit modulus latch, a 16-bit loadable up-counter, counter loading logic, a clock selector, a time base bus driver and an interrupt interface. note: in order to be able to count, the mcsm requires the cpsm clock signals to be present. on coming out of reset, the mcsm will not count internal or external events until the prescaler in the cpsm starts running (when the software sets the prun bit). this allows all counters in the ctm submodules to be synchronized. 6.2 the mcsm modulus latch the 16-bit modulus latch is a read/write register that is used to reload the counter automatically with a predetermined value. the contents of the modulus latch register can be read at any time. writing to the register loads the modulus latch with the new value. this value is then transferred to the counter register on the next hardware load of that counter. however, writing to the corresponding counter register loads the modulus latch and the counter register immediately with the new value. the modulus latch register is cleared to $0000 by reset. 6.3 the mcsm counter the counter is composed of a 16-bit read/write register associated with a 16-bit incrementer. reading the counter transfers the contents of the counter register to the data bus; writing to the counter loads the modulus latch and the counter register immediately with the new value. the counter can be clocked with different clock sources (see section 6.4). note: reset presets the counter register to $0000. writing $0000 to the counter register while its value is $ffff does not set the cof ?g and does not generate an interrupt. 6.3.1 loading the mcsm counter register the counter register can be loaded by writing directly to it. the counter register is also loaded from the modulus latch each time a counter over?w occurs and the cof ?g bit in the mcsm status/interrupt/control register (mcsmsic) is set. note: when the modulus latch is loaded with $ffff, the over?w ?g is set on every counter clock pulse. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 6-3 modulus counter submodule (mcsm) 6 loading of the counter register from the modulus register can also be triggered an external event on the modulus load pin ctml. the edge on the ctml pin that triggers the loading of the counter register is selected by bits edgen and edgep in the mcsmsic register. hardware is provided to prevent the occurrence of spurious edges while changing the edgen and edgep bits. reset clears the edgen and edgep bits to zero, thereby preventing a signal on the ctml pin from loading the counter register until edgen and edgep have been initialized by the software. the modulus load input pin ctml is schmitt triggered and synchronized to the system clock (f sys ). note: the read-only in1 bit of the mcsmsic re?cts the state of the input pin ctml. 6.3.1.1 using the mcsm as a free-running counter the mcsm is a modulus counter. however it can be made to behave like a free-running counter by loading the modulus register with the value $0000. 6.4 mcsm clock sources the user can choose from eight software selectable counter clock sources: six prescaler outputs (pclkx) input pin rising edge detection on the input pin ctmc input pin falling edge detection on the input pin ctmc the clock source is selected by the clk[2:0] bits in the mcsm status, interrupt and control register mcsmsic (see section 6.8.1). when the clk[2:0] bits are being changed, internal circuitry ensures that spurious edges occurring on the ctmc pin do not affect the mcsm. the clock input pin ctmc is schmitt triggered and is synchronized with the system clock (f sys ). note: the read-only in2 bit of the mcsmsic register re?cts the state of the input pin ctmc. 6.4.1 mcsm external event counting when an external clock source (on the ctmc input pin) is selected, the mcsm is in the event counter mode. the counter can simply count the number of events occurring on the input pin. alternatively, the mcsm can be programmed to generate an interrupt when a prede?ed number of events have been counted; this is done by presetting the counter with the two s complement value of the desired number of events. when using the external clock source, the maximum external guaranteed frequency is f sys /4. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 6-4 ctm reference modulus counter submodule (mcsm) 6 6.5 the mcsm time base bus driver the drva and drvb bits in the mcsmsic register select the time base buses to be driven (see section 6.8.1). which of the time base buses is driven depends on where the mcsm is physically placed in any particular ctm implementation. see section 1.4 for information on the structure of the time base buses. for examples of mcsm waveforms and timings, please refer to section 10.1. warning: it is not recommended that the two time base buses be driven at the same time. 6.6 mcsm interrupts a valid mcsm interrupt can be generated when the cof bit in the mcsmsic register is set as a result of the counter over?wing. if the interrupt priority level of the mcsm is non-zero, as de?ed by the three il bits in the mcsmsic register, a valid interrupt request will occur on the imb. 6.7 freeze action on the mcsm when the imb freeze signal is recognized, the mcsm counter stops counting and remains set at its last value. when the freeze signal is negated, the counter starts incrementing from its last value, as if nothing had happened. all registers are accessible during freeze. during freeze, the in1 and in2 bits in the mcsmsic continue to re?ct the states of the signals on the input pins (see section 6.8.1). 6.8 mcsm registers the mcsm register map comprises four 16-bit register locations. as shown in table 6-1, the register block contains three fcsm registers and one reserved register. all unused bits and reserved address locations return zero when read by the software. writing to unused bits and reserved address locations has no effect. in ctm implementations featuring multiple mcsms, each mcsm has its own set of registers. note: all register addresses in this section are speci?d as offsets from the base address of the mcsm. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 6-5 modulus counter submodule (mcsm) 6 6.8.1 mcsmsic ?mcsm status/interrupt/control register cof ?counter over?w ?g bit this status ?g bit indicates whether or not a counter over?w has occurred. an over?w of the mcsm counter is de?ed to be the transition of the counter from $ffff to $xxxx, where $xxxx is the value contained in the modulus latch. if the il ?ld is non-zero, an interrupt request is generated when the cof bit is set. 1 (set) counter over?w has occurred. 0 (clear) counter over?w has not occurred. this ?g bit is set only by the hardware and cleared only by the software or by a system reset. to clear the ?g, the software must ?st read the bit (as ?ne? then write a ?ero to the bit. note: the ?g clearing mechanism will work only if no ?g setting event occurs between the read and write operations; if a cof setting event occurs between the read and write operations, the cof bit will not be cleared. (1) offset from the base address of the mcsm submodule. (1) offset from the base address of the mcsm submodule. table 6-1 mcsm register map address (1) 15 8 7 0 $00 mcsm status/interrupt/control register (mcsmsic) $02 mcsm counter (mcsmcnt) $04 mcsm modulus latch (mcsmml) $06 bit: 15 14 13 12 11 10 9876543210 mcsmsic $00 (1) cof il2 il1 il0 iarb3 drva drvb in2 in1 edgen edgep clk2 clk1 clk0 reset: 00000000uu000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 6-6 ctm reference modulus counter submodule (mcsm) 6 il[2:0] ?interrupt level bits the three interrupt level bits are read/write control bits that select the priority level of interrupt requests made by the mcsm. these bits can be read or written at any time and are cleared by reset. iarb3 ?interrupt arbitration bit 3 the read/write iarb3 bit works in conjunction with the iarb[2:0] ?ld in the biusm module con?uration register. each module that generates interrupt requests on the imb must have a unique value in the arbitration ?ld (iarb). this interrupt arbitration identi?ation number is used to arbitrate for the imb when modules generate simultaneous interrupts of the same priority (see section 3). the iarb3 bit is cleared by reset. drva, drvb ?drive time base bus bits drva and drvb are read/write bits that control the connection of the mcsm to the time base buses a and b. these bits are cleared by reset. (see section 1.4 for information on the time base buses.) warning: it is not recommended that the two time base buses be driven at the same time. in2 ?clock input pin status bit this read-only status bit re?cts the logic state of the clock input pin ctmc. writing a 0 or 1 to this bit has no effect. reset has no effect on this bit. il2 il1 il0 selected level 0 0 0 interrupt disabled 0 0 1 interrupt level 1 (lowest) 0 1 0 interrupt level 2 0 1 1 interrupt level 3 1 0 0 interrupt level 4 1 0 1 interrupt level 5 1 1 0 interrupt level 6 1 1 1 interrupt level 7 (highest) drva drvb bus selected 0 0 neither time base bus a nor time base bus b is driven 0 1 time base bus b is driven 1 0 time base bus a is driven 1 1 both time base bus a and time base bus b are driven f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 6-7 ctm reference modulus counter submodule (mcsm) 6 in1 ?modulus load input pin status bit this read-only status bit re?cts the logic state of the modulus load input pin ctml. writing a 0 or 1 to this bit has no effect. reset has no effect on this bit. edgen, edgep ?modulus load edge sensitivity bits these read/write bits select the sensitivity of the edge detection circuitry on the modulus load pin ctml. clk[2:0] ?counter clock select bits these read/write control bits select one of six internal clock signals (pclkx) or one of two external conditions on the input pin (rising edges or falling edges). the maximum frequency of the external clock signals is f sys /4. 6.8.2 mcsmcnt ?mcsm counter register the mcsm counter register is a read/write register. (1) offset from the base address of the mcsm submodule. edgen edgep in1 edge detector sensitivity 0 0 none 0 1 positive edge only 1 0 negative edge only 1 1 positive and negative edge clk2 clk1 clk0 free running counter clock source 0 0 0 prescaler output 1 (/2 or /3) 0 0 1 prescaler output 2 (/4 or /6) 0 1 0 prescaler output 3 (/8 or /12) 0 1 1 prescaler output 4 (/16 or /24) 1 0 0 prescaler output 5 (/32 or /48) 1 0 1 prescaler output 6 (/64 to /768) 1 1 0 ctmc pin input, negative edge 1 1 1 ctmc pin input, positive edge bit: 15 14 13 12 11 10 9876543210 mcsmcnt $02 (1) msb lsb reset: 0000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 6-8 ctm reference modulus counter submodule (mcsm) 6 6.8.3 mcsmml ?mcsm modulus latch register the mcsm modulus latch register is a read/write register. (1) offset from the base address of the mcsm submodule. bit: 15 14 13 12 11 10 9876543210 mcsmml $04 (1) msb lsb reset: 0000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 7-1 single action submodule (sasm) 7 7 single action submodule (sasm) 7.1 sasm description the dual-channel sasm provides two identical single-action channels, each having its own input/output pin but sharing the same interrupt circuitry (see figure 7-1). each channel can be con?ured independently by the software to perform either input capture or output compare. the single action submodule is so called because each sasm channel can perform a single timing action (input capture or output compare) before some software intervention is required. each channel can also work as a simple i/o pin. figure 7-1 sasm block diagram single action channel a i/o ctm time base buses submodule bus single action channel b pin i/o pin interrupt control il2 il0 iarb3 flag ien il1 flag f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 7-2 ctm reference single action submodule (sasm) 7 a more detailed block diagram of a sasm channel is shown in figure 7-2. each channel comprises: a time base bus selector (which selects the time base bus to be used by that channel for all timing functions), a 16-bit data register (which can be read by the software at any time and which is used for both input capture and output compare functions), a 16-bit comparator (which continuously compares the 16-bit value in the data register with the time base bus), an output ?p-?p (which holds the logic level to be sent to the output pin when a successful output compare occurs), an input edge detector (which detects the rising or falling edge that will trigger the input capture function), several status and control bits in the status/interrupt/control register sica or sicb, an interrupt section. note: during reset the output of the output ?p-?p is cleared (i.e. to ?ero?. 7.2 sasm modes of operation each sasm channel can operate in four different modes: 1. input capture (ic) (i.e. either as input capture on a rising or falling edge or as a read-only input port) 2. output compare (oc) 3. output compare and toggle (oct) 4. output port (op) note: for a channel operating in ic mode, the in bit in the sic register re?cts the logic state of the corresponding input pin (after being schmitt triggered and synchronized). when a channel is operating in oc, oct or op mode, the in bit in the sic register re?cts the logic state of the output of the output ?p-?p. 7.2.1 clearing and using the flag bits to clear a flag bit, the software must ?st read the channel s sic register, then write a zero to the flag bit. these two steps do not have to be done on consecutive instructions. this clearing sequence must be used in every mode of operation. writing a one to the flag bit has no effect. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 7-3 single action submodule (sasm) 7 warning: to avoid spurious interrupts, and to make sure that the flag bit is set according to the newly selected mode, the following sequence of operations should be adopted when changing mode: 1. disable sasm interrupts 2. change mode 3. reset the corresponding flag bit 4. re-enable sasm interrupts (if desired) note: when changing between output modes (op, oc or oct), it is not necessary to follow this procedure, as in these modes the flag bit merely indicates to the software that the compare value may be updated. figure 7-2 sasm block diagram (channel a) 16-bit comparator il2 il0 iarb3 flag 2 time base buses interrupt ien bus control register bits control register bits in edout submodule bus control select output ?p-?p force i/o pin edge detect 16-bit register bsl mode1 mode0 il1 output buffer tbbb tbba f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 7-4 ctm reference single action submodule (sasm) 7 7.2.2 input capture (ic) mode in ic mode, the 16-bit counter value on the selected time base bus is ?aptured when a triggering event occurs on the channel s input pin. triggering of the input capture circuitry is done by a rising or falling edge on the input pin; the polarity of the triggering edge is selected by the edout bit. the logic level on the input pin can be read by software via the in bit in the channel s sic register. note: in ic mode, the input pin is schmitt triggered and the input signal is synchronized to the system clock (f sys ). the in bit re?cts the state present on the input pin (after being schmitt triggered and synchronized). when an input capture occurs, the count value on the selected time base bus is latched into the channel s 16-bit data register. at the same time, the flag bit in the sic register is set to indicate that an input capture has occurred. the flag bit must be reset by software (see section 7.2.1). if the interrupt is serviced, the flag bit should be cleared by the servicing routine before returning from that routine. if a subsequent input capture event occurs while the flag bit is set, the new captured counter value is latched, and the flag bit remains unchanged. note: in ic mode, the value of the edout bit is permanently transferred to the output ?p-?p. this value will be output on the pin when the mode is changed to one of the output modes. 7.2.3 output compare (oc) mode in oc mode, the state of an output pin is changed when a successful output compare occurs; an interrupt may also be generated. the output compare circuitry performs a comparison between the 16-bit register and the selected time base bus. when a match is found, the edout bit value is transferred to the output ?p-?p. at the same time, the flag bit is set to indicate to the processor that a match has occurred. depending on the state of the ien bit, an interrupt can be generated when the flag bit is set. the flag bit must be reset by software (see section 7.2.1). if the interrupt is serviced, the flag bit should be cleared by the servicing routine before returning from that routine. if a subsequent output compare occurs while the flag bit is set, the output compare function occurs normally, and the flag bit remains set. an output compare match can be simulated in software by writing a one to the force bit. setting the force bit forces the edout bit value onto the pin as if an output compare had occurred. in this case, the flag bit is not affected. only if a genuine output compare occurs while doing a force, will the flag bit be set to signify that the compare has occurred. note: in oc mode, the in bit value re?cts the logic state on the output of the output ?p-?p. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 7-5 single action submodule (sasm) 7 7.2.4 output compare and toggle (oct) mode in oct mode, the state of an output pin is toggled each time a successful output compare occurs; an interrupt may also be generated. the output compare circuitry performs a comparison between the 16-bit register and the selected time base bus. when a match is found, the output ?p-?p is toggled to the opposite state. at the same time, the flag bit is set to indicate to the processor that the output compare has occurred. depending on the state of the ien bit, an interrupt can be generated when the flag bit is set. the flag bit must be reset by software (see section 7.2.1). if the interrupt is serviced, the flag bit should be cleared by the servicing routine before returning from that routine. if a subsequent output compare occurs while the flag bit is set, the output toggles, and the flag bit remains set. an output compare match can be simulated in software by writing a one to the force bit. setting the force bit forces the output ?p ?p to toggle as if an output compare had occurred. in this case, the flag bit is not affected. only if a genuine output compare occurs while doing a force, will the flag bit be set to signify that the compare has occurred. note: in oct mode, the in bit re?cts the logic state on the output of the output ?p-?p. 7.2.5 output port (op) mode in op mode the channel s input/output pin is used as a single output port pin. the output compare function is still available, but for internal operation only, and does not affect the state of the output pin. an interrupt may also be generated when a compare occurs. the state of the output pin always re?cts the value of the edout bit in the channel s sic register. reading the edout bit returns the last value written to it. the internal compare feature compares the 16-bit register with the selected time base bus. the output compare circuitry performs a comparison between the 16-bit register and the selected time base bus. when a match is found, the flag bit is set to indicate to the processor that the output compare has occurred. depending on the state of the ien bit, an interrupt can be generated when the flag bit is set. the flag bit must be reset by software (see section 7.2.1). if the interrupt is serviced, the flag bit should be cleared by the servicing routine before returning from that routine. if a subsequent output compare occurs while the flag bit is set, the internal output compare functions normally, and the flag bit remains set. note: in op mode, the in bit value re?cts the logic state on the output of the output ?p-?p. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 7-6 ctm reference single action submodule (sasm) 7 7.3 sasm interrupts each channel in the dual-channel sasm has separately enabled and initiated interrupts and they each have their own unique vector number and address. however, they are both assigned to the same interrupt level and arbitration priority by the il[2:0] and iarb3 bits in the sica register. a valid sasm interrupt is recognized when the flag bit is set, the corresponding ien bit is set and the interrupt level de?ed by bits il[2:0] is not equal to zero. the flag bit is a status bit that indicates, when set, that an input capture or output compare has occurred on the corresponding single action channel. the relative priority of these sources of interrupt is ?ed and channel a has a higher priority than channel b. 7.4 freeze action on the sasm when the imb freeze signal is recognized, the sasm input capture and output compare functions are halted. as soon as the freeze signal is negated, sasm actions resume as if nothing had happened. during freeze, the in bits of the sic registers (sica and sicb) are readable and return the levels present at the input pins if an input mode is in operation, or the output value if an output mode is in operation (see section 7.5.1 and section 7.5.3). when one of the output modes is in operation, the force output function remains available, allowing the software to output the desired level (a useful feature for debugging). all sasm registers are accessible during freeze. 7.5 sasm registers the sasm register map comprises eight 16-bit register locations. as shown in table 7-1, the register block contains two sasm registers for each channel and four reserved registers. all unused bits and reserved address locations return zero when read by the software. writing to unused bits and reserved address locations has no meaning nor effect. all register addresses in this section are speci?d as offsets from the base address of the sasm. in ctm implementations featuring multiple sasms, each sasm has its own set of registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 7-7 single action submodule (sasm) 7 7.5.1 sica ?sasm status/interrupt/control register a this register contains the control, interrupt enable and status bits for sasm channel a. it also contains the interrupt priority level bits il[2:0] and the arbitration priority bit iarb3 for the whole sasm (i.e. common to channels a and b). flag ?event ?g bit the flag bit is set whenever an input capture or output compare event occurs. this ?g bit is set only by the hardware and cleared only by the software or by a system reset. if the il ?ld is non-zero, and the ien bit is set, an interrupt request is generated when the flag bit is set. 1 (set) an input capture or output compare event has occurred. 0 (clear) an input capture or output compare event has not occurred. in ic mode, if a subsequent input capture event occurs while the flag bit is set, the new value is latched and the flag bit remains set. in oc mode, if a subsequent output compare event occurs while the flag bit is set, the compare occurs normally and the flag bit remains set. in oct mode, if a subsequent output compare event occurs while the flag bit is set, the toggle of the output signal occurs as normal and the flag bit remains set. in op mode, if a subsequent internal compare event occurs while the flag bit is set, the compare occurs normally and the flag bit remains set. (1) offset from the base address of the sasm submodule. (1) offset from the base address of the sasm submodule. table 7-1 sasm register map address (1) 15 8 7 0 $00 sasm status/interrupt/control register a (sica) $02 sasm data register a (sdata) $04 sasm status/interrupt/control register b (sicb) $06 sasm data register a (sdatb) $08 $0a $0c $0e bit: 15 14 13 12 11 10 9876543210 sica $00 (1) flag il2 il1 il0 iarb3 ien bsl in force edout mode1 mode0 reset: 00000000u0000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 7-8 ctm reference single action submodule (sasm) 7 to clear the ?g, the software must ?st read the bit (as ?ne? then write a ?ero to the bit. note: the ?g clearing mechanism will work only if no ?g setting event occurs between the read and write operations; if a flag setting event occurs between the read and write operations, the flag bit will not be cleared. il[2:0] ?interrupt level bits the three interrupt level bits are read/write control bits that select the priority level of interrupt requests made by the sasm. these bits can be read or written at any time and are cleared by reset. note: these bits affect both sasm channels, not just channel a. iarb3 ?interrupt arbitration bit 3 the read/write iarb3 bit works in conjunction with the iarb[2:0] ?ld in the biusm module con?uration register. each module that generates interrupt requests on the imb must have a unique value in the arbitration ?ld (iarb). this interrupt arbitration identi?ation number is used to arbitrate for the imb when modules generate simultaneous interrupts of the same priority (see section 3). the iarb3 bit is cleared by reset. note: this bit affects both sasm channels, not just channel a. ien ?interrupt enable bit this control bit enables interrupts on channel a when the flag bit is set and the il[2:0] ?ld is non-zero. this bit is cleared by reset. 1 (set) interrupts enabled. 0 (clear) interrupts disabled. il2 il1 il0 selected level 0 0 0 interrupt disabled 0 0 1 interrupt level 1 (lowest) 0 1 0 interrupt level 2 0 1 1 interrupt level 3 1 0 0 interrupt level 4 1 0 1 interrupt level 5 1 1 0 interrupt level 6 1 1 1 interrupt level 7 (highest) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 7-9 single action submodule (sasm) 7 bsl ?time base bus select bit this control bit selects the time base bus to be connected to sasm channel a. this bit is cleared by reset. 1 (set) time base bus b selected. 0 (clear) time base bus a selected. in ?input pin status bit in input mode (ic), the in bit re?cts the logic state present on the corresponding input pin (after being schmitt triggered and synchronized). in the output modes (oc, oct and op), the in bit value re?cts the state of the output of the output ?p-?p. the in bit is a read-only bit; writing to it has no effect. reset has no effect on this bit. force ?force compare control bit in the ic and op modes, the force bit is not used and writing to it has no effect. in the oc and oct modes, the force bit is used by the software to cause the output ?p-?p (and the output pin) to behave as though an output compare had occurred. in oc mode, setting the force bit causes the value of edout to be transferred to the output of the output ?p-?p; in oct mode, setting the force bit causes the output ?p-?p to toggle. internal synchronization ensures that the correct level appears on the output pin when a new value is written to edout and force is set at the same time. 1 (set) force output ?p-?p to behave as if an output compare has just occurred. 0 (clear) no action. the force bit is cleared by reset and always reads as zero. note: the flag bit is not affected by the use of the force bit. edout ?edge detect and output level bit in ic mode, the edout bit is used to select the edge that will trigger the input capture circuitry. 1 (set) input capture on rising edge. 0 (clear) input capture on falling edge. in oc mode, the edout bit is used to latch the value to be output to the pin on the next output compare match or when the force bit is set. internal synchronization ensures that the correct level appears on the output pin when a new value is written to edout and force is set at the same time. reading edout returns the previous value written. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 7-10 ctm reference single action submodule (sasm) 7 in oct mode, the edout bit has no effect. however, the force function is still available and will force the value of the edout bit to appear on the output pin. in op mode, the value of the edout bit is output to the corresponding pin. reading edout returns the previous value written. the edout bit is cleared by reset. mode1, mode0 ?sasm operating mode select bits these control bits select the mode of operation of the sasm channel, as shown in the following table. mode1 and mode0 are cleared by reset. 7.5.2 sdata ?sasm data register a sdata is the 16-bit read-write register associated with channel a. in ic mode, sdata contains the last captured value. in the oc, oct and op modes, it is loaded with the value of the next output compare. sdata is not affected by reset. 7.5.3 sicb ?sasm status/interrupt/control register b this register contains the control and status bits for sasm channel b. the bits it contains are identical to those in sica, with the exception of the il[2:0], iarb3 and ien which apply to both (1) offset from the base address of the sasm submodule. mode1 mode0 sasm channel operating mode 0 0 input capture (ic) 0 1 output port (op) 1 0 output compare (oc) 1 1 output compare and toggle (oct) bit: 15 14 13 12 11 10 9876543210 sdata $02 (1) msb lsb reset: uuuuuuuuuuuuuuuu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 7-11 single action submodule (sasm) 7 channels simultaneously and which are included only in sica. for descriptions of the bits, please refer to section 7.5.1). 7.5.4 sdatb ?sasm data register b sdatb is the 16-bit read-write register associated with channel a. in the ic mode, sdatb contains the last captured value. in the oc, oct and op modes, it is loaded with the value of the next output compare. sdatb is not affected by reset. (1) offset from the base address of the sasm submodule. (1) offset from the base address of the sasm submodule. bit: 15 14 13 12 11 10 9876543210 sicb $04 (1) flag bsl in force edout mode1 mode0 reset: 0000000000000000 bit: 15 14 13 12 11 10 9876543210 sdatb $06 (1) msb lsb reset: uuuuuuuuuuuuuuuu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 7-12 ctm reference single action submodule (sasm) this page intentionally left blank 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 8-1 double action submodule (dasm) 8 8 double action submodule (dasm) figure 8-1 dasm block diagram 16-bit comparator a il2 il0 iarb3 flag 2 time base buses interrupt bus control register bits control register bits in forcb submodule bus control select output ?p-?p forca i/o pin edge detect 16-bit register a bsl mode3 mode2 il1 output buffer tbbb tbba 16-bit register b1 16-bit register b2 mode1 mode0 16-bit comparator b wor edpol register b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 8-2 ctm reference double action submodule (dasm) 8 8.1 dasm description the dasm is a timer submodule designed speci?ally to be integrated into ctm systems used in motorola s m68300 and m68hc16 family mcus. it contains two timing channels a and b associated with the same input/output pin. the dual action submodule is so called because its timing channel con?uration allows two events (input capture or output compare) to occur before some software intervention is required. six operating modes allow the software to use the dasm s input capture and output compare functions to perform pulse width measurement, period measurement, single pulse generation and continuous pulse width generation, as well as standard input capture and output compare. the dasm can also work as a single i/o pin (see table 8-1). the dasm is composed of two timing channels (a and b), an output ?p-?p, an input edge detector, some control logic and an interrupt section (see figure 8-1). all control and status bits are contained in the dasmsic register. channel a comprises one 16-bit data register and one 16-bit comparator. channel b also appears to the user to consist of one 16-bit data register and one 16-bit comparator, however, internally, channel b has two data registers b1 and b2, and the operating mode determines which register is accessed by the software: in the input capture modes (ipwm, ipm and ic), registers a and b2 are used to hold the captured values; in these modes, the b1 register is used as a temporary latch for channel b. in the output compare modes (oca and ocab), registers a and b2 are used to de?e the output pulse; register b1 is not used in these modes. in the output pulse width modulation mode (opwm), registers a and b1 are used as primary registers and hidden register b2 is used as a double buffer for channel b. register contents are always transferred automatically at the correct time so that the minimum pulse (measurement or generation) is just one time base bus count. the a and b data registers are always read/write registers, accessible via the ctm s submodule bus. in the input capture modes, the edge detect circuitry triggers a capture whenever a rising or falling edge (as de?ed by the edpol bit) is applied to the input pin. the signal on the input pin is schmitt triggered and synchronized with the system clock (f sys ). in the disabled mode (dis) and in the input modes, the in bit re?cts the state present on the input pin (after being schmitt triggered and synchronized). in the output modes the in bit re?cts the value present at the output of the output ?p-?p. the output ?p-?p is used in output modes to hold the logic level applied to the output pin. the time base bus selector is common to all input and output functions; it connects the dasm to time base bus a or b and is controlled in software by the bus select bit bsl in the dasmsic register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 8-3 double action submodule (dasm) 8 8.2 32-bit coherent access in the ipwm and ipm modes, 32-bit coherent access of the data registers is supported (see section 1.3.4). a 32-bit coherent access consists of doing a long word aligned access of data register a. in this case, register a is accessed ?st, immediately followed (on the next cycle) by a register b access. during this time, any ?g setting or data transfer from the hidden b register is deferred until coherent access has ended. when the 32-bit access has ended, the dasm ?ishes any pending b action and resumes normal operation. 8.3 dasm modes of operation the mode of operation of the dasm is determined by the mode select bits mode[3:0] in the dasmsic register (see table 8-1). warning: to avoid spurious interrupts, and to make sure that the flag bit is set according to the newly selected mode, the following sequence of operations should be adopted when changing mode: 1. disable dasm interrupts 2. change mode 3. reset the corresponding flag bit 4. re-enable dasm interrupts (if desired) note: when changing between output modes (op, oc or oct), it is not necessary to follow this procedure, as in these modes the flag bit merely indicates to the software that the compare value can be updated. table 8-1 dasm modes of operation mode[3:0] mode description of mode 0000 dis disabled ?input pin is high impedance; in gives state of the input pin. 0001 ipwm input pulse width measurement ?capture on the leading edge and the trailing edge of an input pulse. 0010 ipm input period measurement ?capture two consecutive rising/falling edges. 0011 ic input capture ?capture when the designated edge is detected. 0100 ocb output compare, ?g set on b compare ?generate leading and trailing edges of an output pulse and set the ?g. 0101 ocab output compare, ?g on a and b compare ?generate leading and trailing edges of an output pulse and set the ?g. 1xxx opwm output pulse width modulation ?generate continuous pwm output with 7, 9, 11, 12, 13, 14, 15 or 16 bits of resolution. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 8-4 ctm reference double action submodule (dasm) 8 8.3.1 disable (dis) mode dis mode is selected by making mode[3:0] = 0000. in this mode, all input capture and output compare functions of the dasm are disabled and the flag bit is maintained in its reset state, but the input port pin function remains available. the associated pin becomes a high impedance input and the input level on this pin is re?cted by the state of the in bit in the dasmsic register. all control and interrupt bits remain accessible, allowing the software to prepare for future mode selection. data registers a and b are accessible at consecutive addresses. writing to data register b stores the same value in registers b1 and b2. warning: when changing modes, it is imperative to go through the dis mode in order to reset the dasm s internal functions properly. failure to do this could lead to invalid and unexpected output compare or input capture results, and to flags being set incorrectly. 8.3.2 input pulse width measurement (ipwm) mode ipwm mode is selected by making mode[3:0] = 0001. this mode allows the width of a positive or negative pulse to be determined by capturing the leading edge of the pulse on channel b and the trailing edge of the pulse on channel a; successive captures are done on consecutive edges of opposite polarity. the edge sensitivity is selected by the edpol bit in the dasmsic register. this mode also allows the software to determine the logic level on the input pin at any time by reading the in bit in the dasmsic register. the channel a input capture function remains disabled until the ?st rising edge triggers the ?st input capture on channel b. when this rising edge is detected, the count value of the time base bus selected by the bsl bit is latched in the 16-bit data register b1; the flag bit is not affected. when the next falling edge is detected, the count value of the time base bus is latched into the 16-bit data register a and, at the same time, the flag bit is set and the contents of register b1 are transferred to register b2. reading data register b returns the value in register b2. if subsequent input capture events occur while the flag bit is set, data registers a and b will be updated with the latest captured values and the flag bit will remain set. if a 32-bit coherent operation is in progress when the falling edge is detected, the transfer from b1 to b2 is deferred until the coherent operation is completed. operation of the dasm then continues on channels b and a as previously described. the input pulse width is calculated by subtracting the value in data register b from the value in data register a. figure 8-2 provides an example of how the dasm can be used for input pulse width measurement. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 8-5 double action submodule (dasm) 8 8.3.3 input period measurement (ipm) mode ipm mode is selected by making mode[3:0] = 0010. this mode allows the period of an input signal to be determined by capturing two consecutive rising edges or two consecutive falling edges; successive input captures are done on consecutive edges of the same polarity. the edge polarity is de?ed by the edpol bit in the dasmsic register. this mode also allows the software to determine the logic level on the input pin at any time by reading the in bit in the dasmsic register. when the ?st edge having the selected polarity is detected, the time base bus value is latched into the 16-bit data register a, the data in register b1 is transferred to data register b2 and ?ally the data in register a is transferred to register b1. on this ?st capture the flag bit is not set. on the second and subsequent captures, the flag bit is set immediately before the data in register a is transferred to register b1. when the second edge of the same polarity is detected, the time base bus value is latched into data register a, the data in register b1 is transferred to data register b2, the flag bit is set to signify that the beginning and end points of a complete period have been captured, and ?ally data register a is transferred to register b1. this sequence of events is repeated for each subsequent capture. reading data register b returns the value in register b2. if a 32-bit coherent operation is in progress when an edge is detected, the transfer of data from b1 to b2 is deferred until the coherent operation is completed. at any time, the input level present on the input pin can be read on the in bit. figure 8-2 input pulse width measurement example time base bus $0500 $1000 $1100 $1250 $1525 $16a0 flag bit dasma captured value 1 b1 captured value 2 b2 value 1 $xxxx $1000 $1000 $1250 $1250 $16a0 $xxxx $xxxx $1100 $1100 $1525 $1525 $xxxx $xxxx $1000 $1000 $1250 $1250 input signal mode selection; edpol = 1 flag reset by software flag reset by software babab 1. these values are accessible to the software. 2. these values are internal and are not accessible. notes: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 8-6 ctm reference double action submodule (dasm) 8 the input pulse period is calculated by subtracting the value in data register b from the value in data register a. figure 8-3 provides an example of how the dasm can be used for input period measurement. figure 8-3 input period measurement example time base bus $0500 $1000 $1100 $1250 $1525 $16a0 flag bit dasma captured value 1 b1 value 2 b2 value 1 $xxxx $1000 $1250 $16a0 $xxxx $1000 $1250 $16a0 $xxxx $xxxx $1000 $1250 input signal mode selection; edpol = 0 flag reset by software flag reset by software aaa 1. these values are accessible to the software. 2. these values are internal and are not accessible. notes: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 8-7 double action submodule (dasm) 8 8.3.4 input capture (ic) mode ic mode is selected by making mode[3:0] = 0011. this mode is identical to the input period measurement mode (ipm) described above, with the exception that the flag bit is also set at the occurrence of the ?st detected edge of the selected polarity. in this mode the dasm functions as a standard input capture function in a similar way to the m68hc11 family timers. in this case the value latched in channel b can be ignored. figure 8-4 provides an example of how the dasm can be used for input capture. 8.3.5 output compare (ocb and ocab) modes oc mode is selected by making mode[3:0] = 010x. the mode0 bit controls the setting criteria for the flag bit, i.e. when a compare occurs only on channel b or when a compare occurs on either channel (see section 8.6.1). this mode allows the dasm to perform four different output functions: single-shot output pulse (two edges), with flag set on the second edge. single-shot output pulse (two edges), with flag set on both edges. single-shot output transition (one edge). output port pin, with output compare function disabled. in this mode the leading and trailing edges of variable width output pulses are generated by calculated output compare events occurring on channels a and b, respectively. oc mode may also figure 8-4 dasm input capture example time base bus $0500 $1000 $1100 $1250 $1525 $16a0 flag bit dasma captured value 1 b1 value 2 b2 value 1 $xxxx $1000 $1250 $16a0 $xxxx $1000 $1250 $16a0 $xxxx $xxxx $1000 $1250 input signal mode selection; edpol = 0 flag reset by software flag reset by software aaa flag reset by software 1. these values are accessible to the software. 2. these values are internal and are not accessible. notes: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 8-8 ctm reference double action submodule (dasm) 8 be used to perform a single output compare function, similar to the m68hc11 timer, or may be used as an output port bit. in this mode, channel b is accessed via register b2. register b1 is not used and is not accessible to the user. both channels work together to generate one ?ingle shot output pulse signal. channel a de?es the leading edge of the output pulse, while channel b de?es the trailing edge of the pulse. flag setting can be done when a compare occurs on channel b only or when a compare occurs on either channel (as de?ed by the mode0 bit in the dasmsic register). when this mode is ?st selected, both comparators are disabled. each comparator is enabled by writing to its data register; it remains enabled until the next successful comparison is made on that channel, whereupon it is disabled. the values stored in registers a and b are compared with the count value on the selected time base bus when their corresponding comparators are enabled. the output ?p-?p is set when a match occurs on channel a. the output ?p-?p is reset when a match occurs on channel b. the polarity of the output signal is selected by the edpol bit. the output ?p-?p level can be obtained at any time by reading the in bit. if subsequent enabled output compares occur on channels a and b, the output pulses continue to be output, regardless of the state of the flag bit. at any time, the forca and forcb bits allow the software to force the output ?p-?p to the level corresponding to a comparison on channel a or b, respectively. note that the flag bit is not affected by these ?orce operations. totem pole or open-drain output circuit con?urations can be selected using the wor bit in the dasmsic register. warning: there is no hardware protection to disable comparator b while comparator a is enabled. it is the user s responsibility to load data registers a and b with the values needed to produce the desired output pulse. note: if both channels are loaded with the same value they will try to force different levels on the output ?p-?p. hardware protection circuitry ensures that no contention occurs and the output ?p-?p provides a logic zero level output. 8.3.5.1 single shot output pulse operation the single shot output pulse operation is selected by writing the leading edge value of the desired pulse to data register a and the trailing edge value to data register b. a single pulse will be output at the desired time, thereby disabling the comparators until new values are written to the data registers. note: in this mode, registers a and b2 are accessible to the user software (at consecutive addresses). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 8-9 double action submodule (dasm) 8 figure 8-5 provides an example of how the dasm can be used to generate a single output pulse. 8.3.5.2 single output compare operation the single output compare operation is selected by writing to only one of the two data registers (a or b), thus enabling only one of the comparators. following the ?st successful match on the enabled channel, the output level is ?ed and remains at the same level inde?itely with no further software intervention being required. note: in this mode, registers a and b2 are accessible to the user software (at consecutive addresses). figure 8-6 provides an example of how the dasm can be used to perform a single output compare. 8.3.5.3 output port bit operation the output port bit operation is selected by leaving both channels disabled, i.e. by writing to neither register a nor b. the edpol bit alone controls the output value.the same result can be achieved by keeping edpol at zero and using the forca and forcb bits to obtain the desired output level. figure 8-5 single-shot output pulse example time base bus $0500 $1000 $1100 $0000 $1000 $1100 flag bit dasma value 1 b2 value 1 $xxxx $1100 $1100 $xxxx $1000 $1000 output signal mode selection; mode0 = 0 flag reset by software ab write to a and b 1. these values are accessible to the software. note: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 8-10 ctm reference double action submodule (dasm) 8 8.3.6 output pulse width modulation (opwm) mode opwm mode is selected by making mode[3:0] = 1xxx. the mode[2:0] bits allow some of the comparator bits to be masked. this mode allows pulse width modulated output waveforms to be generated, with eight selectable frequencies (for a given time base). both channels (a and b) are used to generate one pwm output signal on the dasm pin. channel b is accessed via register b1. register b2 is not accessible to the user. channels a and b de?e the leading and trailing edges, respectively, of the pwm output pulse. the value in register b1 is continuously transferred to register b2 in the time between each trailing edge and the following leading edge. the value loaded in register a is continuously compared with the value on the time base bus. when a match on a occurs, the flag bit is set and the output ?p-?p is set. the value loaded in register b2 is continually compared with the value on the time base bus. when a match occurs on b, the output ?p-?p is reset. the polarity of the pwm output signal is selected by the edpol bit. the output ?p-?p level can be obtained at any time by reading the in bit. if subsequent compares occur on channels a and b, the pwm pulses continue to be output, regardless of the state of the flag bit. at any time, the forca and forcb bits allow the software to force the output ?p-?p to the level corresponding to comparison on a or b respectively. note that the flag bit is not affected by the forca and forcb operations. figure 8-6 single shot output transition example time base bus $0500 $1000 $1100 $1000 $1100 $1000 flag bit dasma value 1 b2 value 1 $xxxx $xxxx $1100 $1100 $xxxx $1000 $1000 $1000 input signal mode selection; mode0 = 1 flag reset by software flag reset by software ab write to b write to a 1. these values are accessible to the software. note: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 8-11 double action submodule (dasm) 8 warning: there is no hardware protection to disable comparator b while comparator a is enabled. it is the user s responsibility to load data registers a and b with the values needed to produce the desired pwm output pulse. note: if both channels are loaded with the same value they will try to force different levels on the output ?p-?p. hardware protection circuitry ensures that no contention occurs and the output ?p-?p provides a logic zero level output. figure 8-7 provides an example of how the dasm can be used for pulse width modulation. to generate pwm output pulses of different frequencies, the 16-bit comparator can have some of its bits masked. this is controlled by bits mode2, mode1 and mode0. the frequency of the pwm output (f pwm ) is given by the following equation (assuming the dasm is connected to a free running counter): [1] where n cpsm is the overall cpsm clock divide ratio ( ? 2 to ? 512 or ? 3 to ? 768) and n dasm is the dasm divide ratio. a few examples of frequencies and resolutions that can be obtained are shown in table 8-2. figure 8-7 dasm output pulse width modulation example time base bus $1000 $1100 $0000 $1000 $1500 $1700 flag bit dasma value 1 b1 value 1 b2 value 2 $xxxx $1500 $1500 $1700 $1700 $1000 $1000 $1000 $1000 $1000 $xxxx $xxxx $1500 $1700 $1700 pwm output edpol = 0 flag reset by software flag reset by software b2 comparison write a comparison b2 comparison matches matches matches b1 = $1700 write b1 = $1500 a comparison matches $1000 $1700 $1700 1. these values are accessible to the software. 2. these values are internal and are not accessible. notes: f pwm f sys n cpsm n dasm ---------------------------------------- = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 8-12 ctm reference double action submodule (dasm) 8 when using 16 bits of resolution on the comparator (mode[2:0] = 000), the output can vary from a 0% duty cycle up to a duty cycle of 65535/65536. in this case it is not possible to have a 100% duty cycle. in cases where 16-bit resolution is not needed, it is possible to have a duty cycle ranging from 0% to 100%. setting bit 15 of the value stored in register b to one results in the output being ?lways set? clearing bit 15 (to zero) allows normal comparisons to occur and the normal output waveform is obtained. changes to and from the 100% duty cycle are done synchronously, as are all other width changes. in the opwm mode, the wor bit selects whether the output is totem pole driven or open-drain. 8.4 dasm interrupts when the flag bit is set, an interrupt request is generated on one of eight levels as de?ed by the interrupt level bits (il[2:0]) in the dasmsic register. if the interrupt level is set to zero, interrupts are disabled. (1) this table is valid only if the dasm is connected to a free-running counter. table 8-2 dasm pwm example output frequencies/resolutions at f sys = 16 mhz n cpsm n dasm (1) pwm output frequency (hz) resolution (bits) 512 65536 0.48 16 2 65536 122.07 16 512 32768 0.95 15 2 32768 244.14 15 512 16384 1.91 14 2 16384 488.28 14 512 8192 3.81 13 2 8192 976.56 13 512 4096 7.63 12 2 4096 1953.13 12 512 2048 15.26 11 2 2048 3906.25 11 512 512 31.04 9 2 512 15625.00 9 512 128 244.14 7 2 128 62500.00 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 8-13 double action submodule (dasm) 8 8.5 freeze action on the dasm when the imb freeze signal is recognized, the dasm captures and compares functions are halted. as soon as the freeze signal is negated, dasm actions resume as if nothing had happened. during freeze, the in bit of the dasmsic register is readable and returns the level present at the input pin if an input mode is selected, or the output value if an output mode is in operation. when one of the output modes is in operation, the force output function remains available, allowing the software to output the desired level and simplifying debugging. all dasm registers are accessible during freeze. 8.6 dasm registers the dasm register map comprises four 16-bit register locations. as shown in table 8-3, the register block contains three dasm registers and one reserved register. all unused bits and reserved address locations return zero when read by the software. writing to unused bits and reserved address locations has no meaning nor effect. all register addresses in this section are speci?d as offsets from the base address of the dasm. in ctm implementations featuring multiple dasms, each dasm has its own set of registers. (1) offset from the base address of the dasm submodule. table 8-3 dasm register map address (1) 15 8 7 0 $00 dasm status/interrupt/control register (dasmsic) $02 dasm register a (dasma) $04 dasm register b (dasmb) $06 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 8-14 ctm reference double action submodule (dasm) 8 8.6.1 dasmsic ?dasm status/interrupt/control register flag ?flag status bit this status bit indicates whether or not an input capture or output compare event has occurred. if the il ?ld is non-zero, an interrupt request is generated when the flag bit is set. 1 (set) an input capture or output compare event has occurred. 0 (clear) an input capture or output compare event has not occurred. in the dis mode, the flag bit is cleared. in the ipwm mode, the flag bit is set each time there is a capture on channel a. in the ipm mode, the flag bit is set each time there is a capture on channel a, except for the ?st time. in the ic mode, the flag bit is set each time there is a capture on channel a. in the ocb mode (i.e. when mode0 = 0), the flag bit is only set each time there is a successful comparison on channel b. in the ocab mode (i.e. when mode0 = 1), the flag bit is set each time there is a successful comparison on either channel a or b. in the opwm mode, the flag bit is set whenever there is a successful comparison on channel a. this ?g bit is set only by the hardware and is cleared only by the software or by a system reset. the software can clear the flag bit either by writing a zero to it, having ?st read the bit as a one, or by selecting the dis mode. to clear the ?g, the software must ?st read the bit (as ?ne? then write a ?ero to the bit. note: the ?g clearing mechanism will work only if no ?g setting event occurs between the read and write operations; if a flag setting event occurs between the read and write operations, the flag bit will not be cleared. (1) offset from the base address of the dasm submodule. bit: 15 14 13 12 11 10 9876543210 dasmsic $00 (1) flag il2 il1 il0 iarb3 wor bsl in forca forcb edpol mode3 mode2 mode1 mode0 reset: 0000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 8-15 double action submodule (dasm) 8 il[2:0] ?interrupt level bits the three interrupt level bits are read/write control bits that select the priority level of interrupt requests made by the dasm. these bits can be read or written at any time and are cleared by reset. iarb3 ?interrupt arbitration bit 3 the read/write iarb3 bit works in conjunction with the iarb[2:0] ?ld in the biusm module con?uration register. each module that generates interrupt requests on the imb must have a unique value in the arbitration ?ld (iarb). this interrupt arbitration identi?ation number is used to arbitrate for the imb when modules generate simultaneous interrupts of the same priority (see section 3). the iarb3 bit is cleared by reset. wor ?wired-or bit in the dis, ipwm, ipm and ic modes, the wor bit is not used; reading this bit returns the value that was previously written. in the ocb, ocab and opwm modes, the wor bit selects whether the output buffer is con?ured for open-drain or totem pole operation. 1 (set) output buffer is open-drain. 0 (clear) output buffer is totem pole. the wor bit is cleared by reset. bsl ?bus select bit this control bit selects the time base bus to be connected to the dasm. 1 (set) the dasm is connected to time base bus b. 0 (clear) the dasm is connected to time base bus a. note: the time base bus con?urations (a and b) are speci? to each ctm implementation (eg. ctm2). please refer to the appropriate appendix for details. il2 il1 il0 selected level 0 0 0 interrupt disabled 0 0 1 interrupt level 1 (lowest) 0 1 0 interrupt level 2 0 1 1 interrupt level 3 1 0 0 interrupt level 4 1 0 1 interrupt level 5 1 1 0 interrupt level 6 1 1 1 interrupt level 7 (highest) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 8-16 ctm reference double action submodule (dasm) 8 in ?input pin status bit in the dis, ipwm, ipm and ic modes, this read-only status bit re?cts the logic level on the input pin. in the ocb, ocab and opwm modes, reading this bit returns the value latched on the output ?p-?p, after edpol polarity selection. writing to this bit has no effect. forca ?force a bit in the ocb, ocab and opwm modes, the forca bit allows the software to force the output ?p-?p to behave as if a successful comparison had occurred on channel a (except that the flag bit is not set). writing a one to forca sets the output ?p-?p; writing a zero to it has no effect. in the dis, ipwm, ipm and ic modes, the forca bit is not used and writing to it has no effect. forca is cleared by reset and always reads as zero. note: writing a one to both forca and forcb simultaneously resets the output ?p-?p. forcb ?force b bit in the ocb, ocab and opwm modes, the forcb bit allows the software to force the output ?p-?p to behave as if a successful comparison had occurred on channel b (except that the flag bit is not set). writing a one to forcb resets the output ?p-?p; writing a zero to it has no effect. in the dis, ipwm, ipm and ic modes, the forcb bit is not used and writing to it has no effect. forcb is cleared by reset and always reads as zero. note: writing a one to both forca and forcb simultaneously resets the output ?p-?p. edpol ?edge polarity bit in the dis mode, this bit is not used; reading it returns the last value written. in the ipwm mode, this bit is used to select the capture edge sensitivity of channels a and b. 1 (set) channel a captures on a falling edge. channel b captures on a rising edge. 0 (clear) channel a captures on a rising edge. channel b captures on a falling edge. in the ipm and ic modes, the edpol bit is used to select the input capture edge sensitivity of channel a. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 8-17 double action submodule (dasm) 8 1 (set) channel a captures on a falling edge. 0 (clear) channel a captures on a rising edge. in the ocb, ocab and opwm modes, the edpol bit is used to select the voltage level on the output pin. 1 (set) the complement of the output ?p-?p logic level appears on the output pin: a compare on channel a resets the output pin; a compare on channel b sets the output pin. 0 (clear) the output ?p-?p logic level appears on the output pin: a compare on channel a sets the output pin, a compare on channel b resets the output pin. the edpol bit is cleared by reset. mode[3:0] ?mode select bits the four mode select bits select the mode of operation of the dasm. to avoid spurious interrupts, it is recommended that dasm interrupts are disabled before changing the operating mode. the mode select bits are cleared by reset. dasm control register bits bits of resolution time base bits ignored dasm mode of operation mod3 mod2 mod1 mod0 0000 dis ?disabled 0001 16 ipwm ?input pulse width measurement 0010 16 ipm ?input period measurement 0011 16 ic input capture 0100 16 ocb ?output compare, ?g on b compare 0101 16 ocab ?output compare, ?g on a and b compare 0110 0111 1000 16 opwm ?output pulse width modulation 1001 15 15 opwm ?output pulse width modulation 1010 14 15, 14 opwm ?output pulse width modulation 1011 13 15-13 opwm ?output pulse width modulation 1100 12 15-12 opwm ?output pulse width modulation 1101 11 15-11 opwm ?output pulse width modulation 1110 9 15-9 opwm ?output pulse width modulation 1111 7 15-7 opwm ?output pulse width modulation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 8-18 ctm reference double action submodule (dasm) 8 8.6.2 dasma ?dasm data register a dasma is the data register associated with channel a; its use varies with the different modes of operation: in the dis mode, dasma can be accessed to prepare a value for a subsequent mode selection. in the ipwm mode, dasma contains the captured value corresponding to the trailing edge of the measured pulse. in the ipm and ic modes, dasma contains the captured value corresponding to the most recently detected dedicated edge (rising or falling edge). in the ocb and ocab modes, dasma is loaded with the value corresponding to the leading edge of the pulse to be generated. writing to dasma in the ocb and ocab modes also enables the corresponding channel a comparator until the next successful comparison. in the opwm mode, dasma is loaded with the value corresponding to the leading edge of the pwm pulse to be generated. 8.6.3 dasmb ?dasm data register b dasmb is the data register associated with channel b; its use varies with the different modes of operation. depending on the mode selected, software access is to register b1 or register b2. in the dis mode, dasmb can be accessed to prepare a value for a subsequent mode selection. in this mode, register b1 is accessed in order to prepare a value for the opwm mode. unused register b2 is hidden and cannot be read, but is written with the same value when register b1 is written. in the ipwm mode, dasmb contains the captured value corresponding to the leading edge of the measured pulse. in this mode, register b2 is accessed; buffer register b1 is hidden and cannot be accessed. (1) offset from the base address of the dasm submodule. (1) offset from the base address of the dasm submodule. bit: 15 14 13 12 11 10 9876543210 dasma $02 (1) msb lsb reset: uuuuuuuuuuuuuuuu bit: 15 14 13 12 11 10 9876543210 dasmb $04 (1) msb lsb reset: uuuuuuuuuuuuuuuu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 8-19 double action submodule (dasm) 8 in the ipm and ic modes, dasmb contains the captured value corresponding to the most recently detected period edge (rising or falling edge). in this mode, register b2 is accessed; buffer register b1 is hidden and cannot be accessed. in the ocb and ocab modes, dasmb is loaded with the value corresponding to the trailing edge of the pulse to be generated. writing to dasmb in the ocb and ocab modes also enables the corresponding channel b comparator until the next successful comparison. in this mode, register b2 is accessed; buffer register b1 is hidden and cannot be accessed. in the opwm mode, dasmb is loaded with the value corresponding to the trailing edge of the pwm pulse to be generated. in this mode, register b1 is accessed; buffer register b2 is hidden and cannot be accessed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 8-20 ctm reference double action submodule (dasm) 8 8.7 dasm examples 8.7.1 ic mode example **************************************************************************** * * dasm_ic (for cpu16 based devices) * * demonstration of the dasm ctm sub-module operating in ic mode. * the dasm is configured to capture the first falling input edge, * then generate an interrupt. * * timings assume 16.777mhz system clock * **************************************************************************** * set up the bus interface unit sub-module, biusm ldd #$0c01 ; ctm not stopped, ignore freeze, std biumcr ; vector base =$4x, iarb2-0=4, bus b displayed * set up the counter prescaler module, cpsm ldd #$0008 ; set prun to start prescaler and set std cpcr ; pclk dividers to /2 /4 /8 /16 /32 and /64 * set up the free running counter module, fcsm ldd #$0905 ; no interrupts, arb3=1, timebase b driven std fcsm25sic ; clock using pclk6 (/64 clock, 3.8147 m s) ldd #$0900 ; mode = %0000 = dis std dasm10sic ; disable dasm module before re-configuring * ensure that cpu will respond to a level 1 interrupt andp #$ff1f ; and ccr with $ff1f to clear interrupt mask * dasm ic mode initialization ldd #$1913 ; mode = %0011 select ic mode ; edpol = 1 capture -ve edge ; bsl = 1 use time base bus b ; iarb3 = 1 ; il = %001 lowest priority interrupt std dasm10sic loop bra loop ; hang here (until interrupt) *********************************************************************** * * ic1 interrupt routine. * the interrupt vector for the dasm module should * contain the entry address ctm reference motorola 8-21 double action submodule (dasm) 8 8.7.2 ipm mode example **************************************************************************** * * dasm_ipm (for cpu16 based devices) * * demonstration of the dasm ctm sub-module operating in ipm mode. * the dasm is configured to measure periods between input falling * edges. an interrupt is generated after each measured period. * the interrupt routine motorola 8-22 ctm reference double action submodule (dasm) 8 8.7.3 ocb mode example **************************************************************************** * * dasm_ocb (for cpu16 based devices) * * demonstration of the dasm ctm sub-module operating in ocb mode. * direct read of time-base and flag polling also used. * * pin a b a b.. * forced ________________ ________________ * low | | | | * xxxxx | | | | * |___________| |__________| |_.. * +----------> $200 +----------> $200 * $100* +----------------> $100 +----------------> * * the pin is initially forced low by selecting ocb mode with the edpol * clear. the current timebase value is then read from biutbr. the rising * edge (a) is scheduled $100 counts from this value, and the falling * edge is scheduled $200 counts after the rising edge. * the pulse train is maintained continuously by polling the dasm flag * bit. when it has been by a b compare another two compares are * scheduled. * * * the time between forcing the pin low and the first rising edge is * slightly less than $100 counts. this is because of the software delay * between forcing the the pin low (by selecting ocb mode in dasmsic) and * reading biutbr. * * timings assume 16.777mhz system clock * **************************************************************************** * set up the bus interface unit sub-module, biusm ldd #$0c01 ; ctm not stopped, ignore freeze, std biumcr ; vector base =$4x, iarb2-0=4, bus b displayed * set up the counter prescaler module, cpsm ldd #$0008 ; set prun to start prescaler and set std cpcr ; pclk dividers to /2 /4 /8 /16 /32 and /64 * set up the free running counter module, fcsm ldd #$0905 ; no interrupts, arb3=1, timebase b driven std fcsm25sic ; clock using pclk6 (/64 clock, 3.8147 m s) * dasm ocb mode initialization ldd #$0900 ; mode = %0000 = dis std dasm10sic ; disable dasm module before re-configuring ldd #$0904 ; mode = %0100 select ocb mode ; edpol = 0 generate positive pulse ; forca,b = 0 don't force pin now ; bsl = 1 use time base bus b ; wor = 0 totem pole output ; iarb3 = 1 ; il = %000 interrupts disabled std dasm10sic bset biumcr+1,#1 ; allow timebase bus 2 to be read f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 8-23 double action submodule (dasm) 8 ldd biutbr ; read current timer count addd #$100 std dasm10a ; set rising edge $100 counts later addd #$200 std dasm10b ; set falling edge $200 after rising edge loop brclr dasm10sic,#$80,loop; wait for dasm flag to be set... bclr dasm10sic,#$80 ; then clear ldd dasm10b ; get previous falling edge time addd #$100 std dasm10a ; set rising edge $100 counts later addd #$200 std dasm10b ; set falling edge $200 after rising edge bra loop ; ..and wait for flag again f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 8-24 ctm reference double action submodule (dasm) 8 8.7.4 pwm mode example **************************************************************************** * * dasm_pwm (for cpu16 based devices) * * demonstration of the dasm ctm sub-module operating in 7-bit pwm mode. * data shown for generating pwm duty cycles from 0% to 100% * * timings assume 16.777mhz system clock * **************************************************************************** * set up the bus interface unit sub-module, biusm ldd #$0c01 ; ctm not stopped, ignore freeze, std biumcr ; vector base =$4x, iarb2-0=4, bus b displayed * set up the counter prescaler module, cpsm ldd #$0008 ; set prun to start prescaler and set std cpcr ; pclk dividers to /2 /4 /8 /16 /32 and /64 * set up the free running counter module, fcsm ldd #$0905 ; no interrupts, arb3=1, timebase b driven std fcsm25sic ; clock using pclk6 (/64 clock, 3.8147 m s) * dasm pwm mode initialization ldd #$0900 ; mode = %0000 = dis std dasm10sic ; disable dasm module before re-configuring ldd #$090f ; mode = %1111 select 7-bit opwm mode ; edpol = 0 generate positive pulse ; forca,b = 0 don't force pin now ; bsl = 1 use time base bus b ; wor = 0 totem pole output ; iarb3 = 1 ; il = %000 interrupts disabled std dasm10sic ldd #$0000 ; a edge at $0000 std dasm10a ldd #$0040 ; b edge at $0040, 64/128 = 50% duty cycle * ; other example pwm values: * ldd #$0000 ; b edge at $0000, 0/128 = 0% duty cycle * ldd #$0001 ; b edge at $0001, 1/128 = 0.78% duty cycle * ldd #$007f ; b edge at $007f, 127/128 = 99.2% duty cycle * ldd #$8000 ; special case, bit 15 set = 1002% duty cycle std dasm10b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 9-1 pulse width modulation submodule (pwmsm) 9 9 pulse width modulation submodule (pwmsm) the pwmsm is one of a family of submodules designed speci?ally for use in ctm systems in motorola s m68300 and m68hc16 family microcontrollers. 9.1 pwmsm features output pulse width modulated (pwm) signal generation with no software involvement pulse width value provided by software: double-buffered for glitch-free pulse width changes 2-cycle minimum pulse width (e.g. 119 ns, for a 16.78 mhz mcu clock) up to 16-bit resolution on pulse width pwm period value provided by software: double-buffered for glitch-free period changes wide range of periods (e.g. 238 ns to 3 seconds, for a 16.67 mhz mcu clock) maximum 50% duty cycle output frequency of 4.19 mhz (for a 16.78 mhz mcu clock) 0% and 100% duty cycles selected by software optional interrupt after each pulse output pulse polarity selected by software output pin status can be read by software output pins may be used as standard output port pins when pwm is not required f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 9-2 ctm reference pulse width modulation submodule (pwmsm) 9 9.2 pwmsm description the pwmsm allows pulse width modulated signals to be generated over a wide range of frequencies, independently of other ctm output signals. the output pulse width can vary from 0% to 100%, with 16 bits of resolution. the minimum pulse width is twice the minimum mcu system clock period (i.e., the minimum pulse width is 119 ns when using a 16.78 mhz clock). the pwmsm is composed of: an output ?p-?p with output polarity control, clock prescaler and selection logic, a 16-bit up-counter, two registers to hold the current and next pulse width values, two registers to hold the current and next pulse period values, a pulse width comparator, a system state sequencer, logic to create 0% and 100% pulses, interrupt logic, a status, interrupt and control register, and a submodule bus interface section. the pwmsm includes its own time base counter and does not use the ctm time base buses, however the pwmsm does use the prescaled clock signal pclk1 generated in the cpsm (see section 4). a block diagram of the pwmsm is shown in figure 9-1. 9.2.1 output ?p-?p and pin the output ?p-?p is the basic output mechanism of the pwmsm. except when the required pulse width is 0% or 100%, the output ?p-?p is set at the beginning of each period and is cleared at the end of the designated pulse width. the polarity of the output pulse can be selected in software. the output of the pwmsm is connected to an external, output-only pin. when the pwmsm is not required, and is disabled by clearing the en bit in the pwmsic register, this pin serves as a digital output-only port pin. when the pwmsm is disabled, the pol bit in the sic register serves as an output port bit. 9.2.2 clock selection the pwmsm contains an 8-bit prescaler that is clocked by the pclk1 signal from the cpsm (i.e. the mcu system clock divided by 2 or by 3). a 3-bit ?ld (clk[2:0]) in the pwmsm status, interrupt and control register (pwmsic) allows the software to select which of the 8 prescaler outputs drives the pwmsm counter. the prescaler outputs are the main mcu clock divided by: 2, 4, 8, 16, 32, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 9-3 pulse width modulation submodule (pwmsm) 9 64, 128 and 512 (or 3, 6, 12, 24, 48, 96, 192 and 768, if the divide-by-3 option is used in the cpsm to generate pclk1). 9.2.3 the pwmsm counter (pwmc) the 16-bit up-counter in the pwmsm provides the time base for the pwm output signal. the counter is held in the $0001 state on reset or when the pwmsm is disabled. when the pwmsm is enabled, the counter begins counting at the rate de?ed by the clock selection. each time the counter matches the contents of the period register, the counter is preset to $0001 and starts to count from that value. the counter can be read at any time without affecting its value. writing to the counter has no effect. figure 9-1 pulse width modulation submodule block diagram 16-bit up counter il2 il1 il0 iarb3 il1 state / 256 prescaler clk1 clk0 clk2 output set submodule bus sequencer buffer (n count ) zero detect control register bits pin 16-bit comparator period register next period register pwma1 pwma2 clock select 16-bit comparator pulse width register next pulse width register pwmb1 pwmb2 output ?p-?p interrupt control flag pol load en clear clear all zeros match match load enable pclk1 output pin pwmc pwma pwmb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 9-4 ctm reference pulse width modulation submodule (pwmsm) 9 9.2.4 pwmsm period registers and comparator the period section of the pwmsm consists of two 16-bit period registers (pwma1 and pwma2) and one 16-bit comparator. pwma2 holds the current pwm period value and pwma1 holds the next pwm period value. the software establishes the next period of the output pwm signal by writing a value into pwma1. pwma2 acts as a double buffer of pwma1, allowing the contents of pwma1 to be changed at any time without affecting the current period of the output signal; it cannot be accessed directly by the software. pwma1 can be read or written at any time. the new value in the pwma1 register is transferred to pwma2 on the next full cycle of the output or when a ? is written to the load bit in the pwmsic register. the comparator continuously compares the contents of the pwma2 register with the value in the pwmsm counter. when a match occurs, the state sequencer sets the output ?p-?p and resets the counter to $0001. period values $0000 and $0001 are special cases. when pwma2 contains $0000, an output period of 65536 pwm clock periods is generated. when pwma2 contains $0001, a period match occurs on every pwm clock period: the counter never increments beyond $0001 and the output level never changes. note: a value of $0002 in the period register and a value of $0001 in the pulse register are the conditions necessary to obtain the maximum possible output frequency for a given pwm clock period. 9.2.5 pwmsm pulse width registers and comparator the pulse width section of the pwmsm consists of two 16-bit pulse width registers (pwmb1 and pwmb2) and one 16-bit comparator. pwmb2 holds the current pwm pulse width value and pwmb1 holds the next pwm pulse width value. the software establishes the next pulse width of the output pwm signal by writing a value into pwmb1. software may write a new pulse width value into pwmb1 at any time and this new value will take effect at the start of the next pwm period (or when the load bit in the pwmsic register is written to a ??. the pwmsm hardware does not modify the contents of pwmb1 at any time. pwmb2 acts as a double buffer of pwmb1, allowing the contents of pwmb1 to be changed at any time without affecting the current pulse width of the output signal; it cannot be accessed directly by the software. pwmb1 can be read or written at any time. the new value in the pwmb1 register is transferred to pwmb2 on the next full cycle of the output or when a ? is written to the load bit in the pwm sic register . the pulse width comparator is a 16-bit ?nes-equality comparator that compares the contents of the pwmb2 register with the 16-bit pwm counter. when the counter reaches the value in pwmb2, a match occurs and the output ?p-?p is cleared. this pulse width match completes the pulse width; it does not affect the counter. since a ?nes-equality comparator is used, subsequent f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 9-5 pulse width modulation submodule (pwmsm) 9 comparisons can occur, but will have no effect on the output signal as the output ?p-?p has already been cleared. the pwm output pulse may be as short as one pwm clock period (pwmb2 = $0001). it may be as long as one pwm clock period less than the pwm period; for example, the pulse width equal to 65535 pwm clock periods can be obtained by setting pwmb2 = $ffff and pwma2 = $0000. 9.2.5.1 0% and 100% ?ulses the 0% and 100% ?ulses are special limiting cases (zero width and in?ite width) that are de?ed by the ?lways clear and ?lways set states of the output ?p-?p. the 0% pulse is generated by making the pulse width value in pwmb2 equal to $0000. the output is a true steady state signal with no glitches. the 100% pulse is created by making the pulse width value in pwmb2 equal to or greater than the period value in pwma2. the output is a true steady state signal with no glitches. note: it is not possible to have a 100% duty cycle when the output period is selected to be 65536 pwm clock periods (by setting pwmb2 = $0000); in this case the maximum duty cycle is 99.998% (100 x 65535/65536). when using the pwm output signal to generate analog levels, the 0% and 100% pulses provide the full scale values. note: even when 0% or 100% pulses are being generated, the 16-bit pwm counter continues to count and output changes to or from these limit values are done synchronously with the selected period. 9.2.6 pwmsm coherency byte access of registers is discussed in section 1.3.1, however, it should be noted that byte writes to the double buffered registers pwma1 and pwmb1 are not recommended as the transfer from the primary registers to the secondary registers is done on a word basis. for most pwmsm operations, 16-bit accesses are suf?ient and long word accesses are treated as two word accesses, with one exception ?a long word write to the period/pulse width registers. in this case, if the long word write is done within the pwm period, there is no visible effect on the output signal and the new values are stored in pwma1 and pwmb1 ready to be loaded into the buffer registers at the start of the next period. if, however, the long word write coincides with the end of the period, then the transfer of values from the primary registers to the secondary registers is suppressed until the end of the next pwm period; during this period, the current values in the secondary registers are used for the period and the pulse width. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 9-6 ctm reference pulse width modulation submodule (pwmsm) 9 9.2.7 pwmsm interrupts the flag bit in the pwmsic register is set when a new period begins and indicates that the period and pulse width registers (pwma1 and pwmb1) may be updated with values for the next output period and pulse width. when the flag bit is set, an interrupt request is generated on one of eight levels as de?ed by the interrupt level bits (il[2:0]) in the pwmsic register. if the interrupt level is set to zero, interrupts are disabled. 9.2.8 freeze action on the pwmsm when the imb freeze signal is recognized, the pwmsm counter stops incrementing and remains set at its last value. when the freeze signal is negated, the counter starts incrementing from its last value, as if nothing had happened. 9.3 pwm frequency, pulse width and resolution table 9-1 and table 9-2 shows the pulse widths and frequencies that can be achieved using the /2 and /3 options and a clock frequency of 16.78 mhz. table 9-1 pwm pulse and frequency ranges (in hz) using /2 option (16.78 mhz) minimum pulse width bits of resolution 16151413121110987654321 0.119 m s/2 128 256 512 1024 2048 4096 8192 16384 32768 65.5k 131k 262k 524k 1049k 2097k 4195kk 0.238 m s/4 64 128 256 512 1024 2048 4096 8192 16384 32768 65.5k 131k 262k 524k 1049k 2097k 0.477 m s/8 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65.5k 131k 262k 524k 1049k 0.954 m s /16 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65.5k 131k 262k 524k 1.91 m s /32 8.0 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65.5k 131k 262k 3.81 m s /64 4.0 8.0 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65.5k 131k 7.63 m s /128 2.0 4.0 8.0 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65.5k 30.5 m s /512 0.5 1.0 2.0 4.0 8.0 16 32 64 128 256 512 1024 2048 4096 8192 16384 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 9-7 pulse width modulation submodule (pwmsm) 9 9.3.1 pwm frequency the relationship between the pwm output frequency (f pwmo ) and the mcu system clock frequency (f sys ) is given by equation 1. [1] where n clock is the cpsm clock divide ratio (2 or 3) and n counter is the pwmsm counter divide ratio. 9.3.2 pwm pulse width the minimum output pulse width (t pwmin ) and the mcu system clock frequency (f sys ) is given by equation 2. [2] table 9-2 pwm pulse and frequency ranges (in hz) using /3 option (16.78 mhz) minimum pulse width bits of resolution 16151413121110987654321 0.179 m s/3 85.33 170.7 341.3 682.7 1365 2731 5461 10923 21845 43.69k 87.38k 174.8k 349.5k 699.1k 1398k 2796k 0.358 m s/6 42.67 85.33 170.7 341.3 682.7 1365 2731 5461 10923 21845 43.69k 87.38k 174.8k 349.5k 699.1k 1398k 0.715 m s /12 21.33 42.67 85.33 170.7 341.3 682.7 1365 2731 5461 10923 21845 43.69k 87.38k 174.8k 349.5k 699.1k 1.431 m s /24 10.67 21.33 42.67 85.33 170.7 341.3 682.7 1365 2731 5461 10923 21845 43.69k 87.38k 174.8k 349.5k 2.861 m s /48 5.333 10.67 21.33 42.67 85.33 170.7 341.3 682.7 1365 2731 5461 10923 21845 43.69k 87.38k 174.8k 5.722 m s /96 2.667 5.333 10.67 21.33 42.67 85.33 170.7 341.3 682.7 1365 2731 5461 10923 21845 43.69k 87.38k 11.44 m s /192 1.333 2.667 5.333 10.67 21.33 42.67 85.33 170.7 341.3 682.7 1365 2731 5461 10923 21845 43.69k 45.78 m s /768 0.333 0.667 1.333 2.667 5.333 10.67 21.33 42.67 85.33 170.7 341.3 682.7 1365 2731 5461 10923 f pwmo f sys n clock n counter ---------------------------------------------------- = t pwmin n clock f sys ------------------- - = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 9-8 ctm reference pulse width modulation submodule (pwmsm) 9 9.3.3 pwm period and pulse width register values the value to be loaded into the pwm period register (pwma1) to obtain a given period is given by equation 3. [3] the value to be loaded into the pwm pulse width register (pwmb1) to obtain a given period is given by equation 4. [4] where t (pwmo) is the actual output pulse width. pwma1 f sys n clock f pwmo ------------------------------------------- - = pwmb1 t pwmo t pwmin ----------------- duty cycle % 100 -------------------------------- pwma1 == f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 9-9 pulse width modulation submodule (pwmsm) 9 9.4 pwmsm register map and registers the pwmsm register map comprises four 16-bit registers as shown in table 9-3. all unused bits and reserved address locations return zero when read by the software. writing to unused bits and reserved address locations has no meaning nor effect. all register addresses in this section are speci?d as offsets from the base address of the pwmsm. 9.4.1 pwmsic ?status, interrupt and control register the pwmsic register contains status, interrupt enable and control bits for the pwmsm. it also contains interrupt level and arbitration bits. flag ?period completion status bit the flag bit is a status bit that indicates when the pwm output period has been completed. 1 (set) pwm period completed. 0 (clear) pwm period not completed. the flag bit is set by the hardware each time a pwm period is completed. whenever the pwm is enabled, the flag bit is set immediately to indicate that the contents of the buffer registers pwma2 and pwmb2 have been updated, and that the period using these new values has started. it also indicates that the user accessible period and pulse width registers pwma1 and pwmb1 can be loaded with values for the next pwm period. once set, the flag bit will remain set and will not be affected by any subsequent period completions, until it is cleared by the software. (1) offset from the base address of the pwmsm submodule. (1) offset from the base address of the pwmsm submodule. table 9-3 pwmsm register map address (1) 15 8 7 0 $00 status, interrupt and control register (pwmsic) $02 pwm period register(pwma) $04 pwm pulse width register (pwmb) $06 pwm counter register (pwmc) bit: 15 14 13 12 11 10 9876543210 pwmsic $00 (1) flag il2 il1 il0 iarb3 pin load pol en clk2 clk1 clk0 reset: 0000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 9-10 ctm reference pulse width modulation submodule (pwmsm) 9 the flag bit can only be cleared by software. to clear the ?g, the software must ?st read the bit (as ?ne? then write a ?ero to the bit. writing a one to the flag bit has no effect. when the pwm is disabled the flag bit remains in the cleared state. note: the ?g clearing mechanism will work only if no ?g setting event occurs between the read and write operations; if a flag setting event occurs between the read and write operations, the flag bit will not be cleared. when the interrupt level set by the interrupt level bit il[2:0] is not equal to zero, an interrupt request is generated when the flag bit is set. before returning from the interrupt service routine, the flag bit should be cleared by software to prevent the pwmsm from immediately generating another interrupt request on the imb. il[2:0] ?interrupt level bits the three interrupt level bits select the interrupt level of requests made by the pwmsm. iarb3 ?interrupt arbitration bit 3 the read/write iarb3 bit works in conjunction with the iarb[2:0] ?ld in the biusm module con?uration register. each module that generates interrupt requests on the imb must have a unique value in the arbitration ?ld (iarb). this interrupt arbitration identi?ation number is used to arbitrate for the imb when modules generate simultaneous interrupts of the same priority (see section 3). the iarb3 bit is cleared by reset. pin ?output pin status bit the pin bit is a status bit that indicates the logic state present on the output pin. 1 (set) logic one state present on the output pin. 0 (clear) logic zero state present on the output pin. the software can thus monitor the waveform being created on the output pin. pin is a read-only bit; writing to it has no effect. il2 il1 il0 selected level 0 0 0 interrupt disabled 0 0 1 interrupt level 1 (lowest) 0 1 0 interrupt level 2 0 1 1 interrupt level 3 1 0 0 interrupt level 4 1 0 1 interrupt level 5 1 1 0 interrupt level 6 1 1 1 interrupt level 7 (highest) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 9-11 pulse width modulation submodule (pwmsm) 9 load ?period and pulse width register load control bit the load bit is a control bit that allows the software to reinitialize the pwmsm and start a new pwm period without causing a glitch on the pwm output signal. 1 (set) load period and pulse width registers. 0 (clear) no action. this bit is always read as a zero. writing a one to this bit results in the following immediate actions: the contents of pwma1 (period value) are transferred to pwma2, the contents of pwmb1 (pulse width value) are transferred to pwmb2, the counter register (pwmc) is initialized to $0001, the control logic and state sequencer are reset, the flag bit is set, and the output ?p-?p is set if the new value in pwmb2 is different from $0000. note: writing a one to the load bit when the en bit = 0, i.e. when the pwmsm is disabled, has no effect. pol ?output pin polarity control bit the pol bit is a control bit that allows the software to set the polarity of the pwm output signal. it works in conjunction with the en bit and controls whether the pwmsm drives the output pin with the true or inverted value of the output ?p-?p (see table 9-4). table 9-4 pwmsm output pin polarity selection control bits output pin state periodic edge variable edge optional interrupt on pol en 0 0 always low 1 0 always high 0 1 high pulse rising edge falling edge rising edge 1 1 low pulse falling edge rising edge falling edge f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 9-12 ctm reference pulse width modulation submodule (pwmsm) 9 en ?pwmsm enable control bit the en bit is a control bit that allows the software to enable and disable the pwmsm as required. 1 (set) enable the pwmsm and start generation of pwm output pulses. 0 (clear) disable the pwmsm and stop generation of pwm output pulses. while the pwmsm is disabled (en = 0): the output ?p-?p is held reset and the level on the output pin is set to one or zero according to the state of the pol bit, the pwmsm s divide-by-256 prescaler is held in reset, the counter stops incrementing and is held equal to $0001, the comparators are disabled, and the pwma1 and pwmb1 registers permanently transfer their contents to the buffer registers (pwma2 and pwmb2, respectively). when the en bit is changed from zero to one: the output ?p-?p is set to start the ?st pulse, the pwmsm s divide-by-256 prescaler is released, the counter is released and starts to increment from $0001, and the flag bit is set (to indicate that pwma1 and pwmb1 can be updated with new values of period and pulse width. while en is set, the pwmsm generates continuously a pulse width modulated output signal based on the data in pwma2 and pwmb2 (which are updated via pwma1 and pwmb2 each time a period is completed). note: to prevent unwanted glitches on the output waveform when disabling the pwmsm, the en bit should not be cleared by the software until one period has been output as a 0% pulse (pwmb2 = $0000). clk[2:0] ?clock rate selection bits the clk bits are control bits that allow the software to select one of the eight counter clock sources coming from the pwmsm prescaler. these bits can be changed by the software at any time. table 9-5 shows the counter clock sources and rates in detail. 9.4.2 pwma ?pwm period register the pwma register contains the period value for the next cycle of the pwm output waveform. in normal usage, with the pwmsm enabled, the software writes a period value into pwma1 and this value is then loaded into the pwma2 register at the end of the current period. if the pwmsm is f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 9-13 pulse width modulation submodule (pwmsm) 9 disabled, a period value written to pwma1 is loaded into pwma2 on the next tic (of the mcu system clock). pwma2 is a temporary register that is used for smoothly updating the pwm period value; it cannot be read or written directly by software. software may write a new period value into pwma1 at any time and this new value will take effect at the start of the next pwm period (or when the load bit in the pwmsic register is written to a ??. the pwmsm hardware does not modify the contents of pwma1 at any time. 9.4.3 pwmb ?pwm pulse width register the pwmb register contains the pulse width value for the next cycle of the pwm output waveform. in normal usage, with the pwmsm enabled, the software writes a pulse width value into pwmb1 and this value is then loaded into the pwmb2 register at the end of the current period. if the pwmsm is disabled, a pulse width value written to pwmb1 is loaded into pwmb2 on the next tic (of the mcu system clock). pwmb2 is a temporary register that is used for smoothly updating the pwm pulse width value; it cannot be read or written directly by software. (1) offset from the base address of the pwmsm submodule. table 9-5 pwmsm clock rate selection pwmsm clk bits cpsm bit div23 pwmsm clock clock source clk2 clk1 clk0 000 0 f sys / 2 pclk1 001 0 f sys / 4 prescaler (/2) 010 0 f sys / 8 prescaler (/4) 011 0 f sys / 16 prescaler (/8) 100 0 f sys / 32 prescaler (/16) 101 0 f sys / 64 prescaler (/32) 110 0 f sys / 128 prescaler (/64) 111 0 f sys / 512 prescaler (/256) 000 1 f sys / 3 pclk1 001 1 f sys / 6 prescaler (/2) 010 1 f sys / 12 prescaler (/4) 011 1 f sys / 24 prescaler (/8) 100 1 f sys / 48 prescaler (/16) 101 1 f sys / 96 prescaler (/32) 110 1 f sys / 192 prescaler (/64) 111 1 f sys / 768 prescaler (/256) bit: 15 14 13 12 11 10 9876543210 pwma $02 (1) msb lsb reset: uuuuuuuuuuuuuuuu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 9-14 ctm reference pulse width modulation submodule (pwmsm) 9 software may write a new pulse width value into pwmb at any time and this new value will take effect at the start of the next pwm period (or when the load bit in the pwmsic register is written to a ??. the pwmsm hardware does not modify the contents of pwmb1 at any time. 9.4.4 pwmc ?pwm counter register the counter (register pwmc) is read-only: software may read the counter register at any time; writing to it has no effect. pwmc is loaded with the value $0001 on reset and is set to that value and held whenever the pwmsm is disabled (en = 0). (1) offset from the base address of the pwmsm submodule. (1) offset from the base address of the pwmsm submodule. bit: 15 14 13 12 11 10 9876543210 pwmb $04 (1) msb lsb reset: uuuuuuuuuuuuuuuu bit: 15 14 13 12 11 10 9876543210 pwmc $06 (1) msb lsb reset: 0000000000000001 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 10-1 electrical specifications 10 10 electrical specifications 10.1 fcsm and mcsm timing information (1) value applies when using external clock. (2) value applies when using internal clock. minimum counter resolution depends on prescaler divide ratio selection. table 10-1 fcsm timing characteristics (v dd = 5.0vdc 10%, vss = 0vdc, t a = t l to t h ) characteristic symbol min max unit system operating frequency f clk 0 16.67 mhz input pin frequency (1) f pcntr 0f clk /4 mhz input pin low time (1) t pinl 2.0/f clk m s input pin high time (1) t pinh 2.0/f clk m s clock pin to counter increment t pinc 4.5/f clk 6.5/f clk m s clock pin to new tbb value t ptbb 5.0/f clk 7.0/f clk m s clock pin to cof set ($ffff) t pcof 4.5/f clk 6.5/f clk m s pin to in bit delay t pinb 1.5/f clk 2.5/f clk m s flag to imb interrupt request t firq 1.0/f clk 1.0/f clk m s counter resolution (2) t cres 2.0/f clk m s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 10-2 ctm reference electrical specifications 10 (1) value applies when using external clock. (2) value applies when using internal clock. minimum counter resolution depends on prescaler divide ratio selection. table 10-2 mcsm timing characteristics (v dd = 5.0vdc 10%, vss = 0vdc, t a = t l to t h ) characteristic symbol min max unit system operating frequency f clk 0 16.67 mhz input pin frequency (1) f pcntr 0f clk /4 mhz input pin low time (1) t pinl 2.0/f clk m s input pin high time (1) t pinh 2.0/f clk m s clock pin to counter increment t pinc 4.5/f clk 6.5/f clk m s clock pin to new tbb value t ptbb 5.0/f clk 7.0/f clk m s clock pin to cof set ($ffff) t pcof 4.5/f clk 6.5/f clk m s load pin to new counter value t pload 2.5/f clk 3.5/f clk m s pin to in bit delay t pinb 1.5/f clk 2.5/f clk m s flag to imb interrupt request t firq 1.0/f clk 1.0/f clk m s counter resolution (2) t cres 2.0/f clk m s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 10-3 electrical specifications 10 figure 10-1 fcsm and mcsm time base timing diagram example not writing to counter register: clock counter register time base bus $1025 $1026 $1027 $1028 $1025 $1026 $1027 $1028 clock counter register time base bus $1025 $1026 $5001 $5002 $1025 $1026 $5001 $5002 writing to counter register: $5000 write $5000 to counter register here clock counter register time base bus $1025 $5000 $5001 $5002 $1025 $5000 $5001 $5002 write $5000 to counter register here f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 10-4 ctm reference electrical specifications 10 figure 10-2 fcsm and mcsm clock pin to counter timing diagram figure 10-3 mcsm load pin to counter timing diagram clock clock pin counter t pinc cof bit tbbx t pcof t ptbb register clock load pin counter t pload register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 10-5 electrical specifications 10 figure 10-4 fcsm and mcsm pin to in bit timing diagram figure 10-5 fcsm and mcsm cof bit to interrupt request timing diagram clock input pin in bit t pinb clock cof bit smb irqx t firq imb irqx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 10-6 ctm reference electrical specifications 10 10.2 sasm timing information (1) minimum resolution depends on counter and prescaler divide ratio selection (2) time given from when new value is stable on time base bus table 10-3 sasm timing characteristics (v dd = 5.0vdc 10%, vss = 0vdc, t a = t l to t h ) characteristic symbol min max unit system operating frequency f clk 0 16.67 mhz input capture mode: input pin low time t pinl 2.0/f clk m s input pin high time t pinh 2.0/f clk m s input capture resolution (1) t resca 2.0/f clk m s pin to input capture delay t pcapt 2.5/f clk 4.5/f clk m s pin to flag set t pflag 2.5/f clk 4.5/f clk m s pin to in bit delay t pinb 1.5/f clk 2.5/f clk m s output compare mode: oct output pulse t oct 2.0/f clk m s compare resolution (1) t rescm 2.0/f clk m s tbb change to flag set t cflag 1.5/f clk 1.5/f clk m s tbb change to pin change (2) t cpin 1.5/f clk 1.5/f clk m s flag to imb interrupt request 2 t firq 1.0/f clk 1.0/f clk m s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 10-7 electrical specifications 10 figure 10-6 sasm input capture timing diagram figure 10-7 sasm pin to in bit timing diagram clock input pin capture t pcapt flag bit t pflag register clock input pin in bit t pinb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 10-8 ctm reference electrical specifications 10 figure 10-8 sasm output compare timing diagram figure 10-9 sasm flag bit to interrupt request timing diagram clock input pin flag bit t cflag output pin t cpin clock flag bit smb irqx t firq imb irqx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 10-9 electrical specifications 10 10.3 dasm timing information (1) minimum resolution depends on counter and prescaler divide ratio selection. (2) time given from when new value is stable on time base bus. table 10-4 dasm timing characteristics (v dd = 5.0vdc 10%, vss = 0vdc, t a = t l to t h ) characteristic symbol min max unit system operating frequency f clk 16.67 mhz input modes: (iplm, ipm, ic): input pin low time t pinl 2.0/f clk m s input pin high time t pinh 2.0/f clk m s input capture resolution (1) t resca 2.0/f clk m s pin to input capture delay t pcapt 2.5/f clk 4.5/f clk m s pin to flag set t pflag 2.5/f clk 4.5/f clk m s pin to in bit delay t pinb 1.5/f clk 2.5f clk m s output modes: (oc, opwm): oct output pulse t oct 2.0/f clk m s compare resolution (1) t rescm 2.0/f clk m s tbb change to flag set t cflag 1.5/f clk 1.5/f clk m s tbb change to pin change (2) t cpin 1.5/f clk 1.5/f clk m s flag to imb interrupt request (2) t firq 1.0/f clk 1.0/f clk m s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 10-10 ctm reference electrical specifications 10 figure 10-10 dasm input capture timing diagram figure 10-11 dasm pin to in bit timing diagram clock input pin capture t pcapt flag bit t pflag register clock input pin in bit t pinb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 10-11 electrical specifications 10 figure 10-12 dasm output compare timing diagram figure 10-13 dasm flag bit to interrupt request timing diagram clock input pin flag bit t cflag output pin t cpin clock flag bit smb irqx t firq imb irqx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 10-12 ctm reference electrical specifications 10 10.4 pwmsm timing information (1) minimum output resolution depends on counter and prescaler divide ratio selection. (2) excluding the case where the output is always zero. (3) with pwmsm enabled before enabling cpsm and div23 = 0. (4) with pwmsm enabled before enabling cpsm and div23 = 1. (5) with cpsm enabled before enabling pwmsm and div23 = 0. (6) with cpsm enabled before enabling pwmsm and div23 = 1. table 10-5 pwmsm timing characteristics (v dd = 5.0vdc 10%, vss = 0vdc, t a = t l to t h ) characteristic symbol min max unit system operating frequency f clk 0 16.67 mhz pwmsm output resolution (1) t pwmr 2.0/f clk m s pwmsm output pulse (2) t pwmo 2.0/f clk m s cpsm enable to output set t pwmp (3) 3.5/f clk m s t pwmp (4) 6.5/f clk m s pwm enable to output set t pwme (5) 3.5/f clk 4.5/f clk m s t pwme (6) 5.5/f clk 6.5/f clk m s flag to imb interrupt request t firq 1.0/f clk m s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola 10-13 electrical specifications 10 figure 10-14 pwmsm minimum output pulse example timing diagram figure 10-15 pwmsm cpsm enable to pwm output set timing diagram clock output pin t pw min clock cpsm output pin t pwmp enable bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola 10-14 ctm reference electrical specifications 10 figure 10-16 pwmsm enable to output set timing diagram figure 10-17 pwmsm flag bit to interrupt request timing diagram clock pwmsm output pin t pwme enable bit clock flag bit smb irqx t firq imb irqx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola a-1 register and bit summary a a register and bit summary a.1 biusm registers and bits a.1.1 biumcr ?biusm module con?uration register a.1.1.1 stop ?stop enable 1 (set) stops operation of the ctm. 0 (clear) allows operation of the ctm. a.1.1.2 frz ?freeze enable 1 (set) halts the ctm sub module when the freeze signal appears on the imb. 0 (clear) ignores the freeze signal on the imb. (1) offset from the base address of the ctm. bit: 15 14 13 12 11 10 9876543210 biumcr $00 (1) stop frz vect7 vect6 iarb2 iarb1 iarb0 tbrs1 tbrs0 reset: 0001100000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola a-2 ctm reference register and bit summary a a.1.1.3 vect7, vect6 ?interrupt vector base number bits a.1.1.4 iarb[2:0] ?interrupt arbitration identi?ation bits the interrupt arbitration bit ?ld (iarb), composed of iarb[2:0] in the biumcr and the iarb3 bit within each submodule, provides ?teen different arbitration identi?ation numbers that can be used to arbitrate between interrupt requests occurring on the imb with the same interrupt priority level. a.1.1.5 tbrs1, tbrs0 ?time base register bus select bits a.1.2 biutest ?biusm test con?uration register reserved for factory testing of the ctm. a.1.3 biutbr ?biusm time base register (1) offset from the base address of the ctm. vect7 vect6 resulting vector base number 0 0 $00 0 1 $40 1 0 $80 1 1 $c0 tbrs1 tbrs0 time base bus 0 0 tbb1 0 1 tbb2 1 0 tbb3 1 1 tbb4 bit: 15 14 13 12 11 10 9876543210 biutbr $04 (1) msb lsb reset: 0000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola a-3 register and bit summary a a.2 cpsm registers and bits a.2.1 cpcr ?cpsm control register a.2.1.1 prun ?prescaler running bit 1 (set) prescaler is running. 0 (clear) prescaler divider is held in reset and is not running. a.2.1.2 div23 ?divide by 2 or divide by 3 bit 1 (set) first prescaler stage divides by 3. 0 (clear) first prescaler stage divides by 2. a.2.1.3 psel1, psel0 ?prescaler division ratio select bits a.2.2 cptr ?cpsm test register reserved for factory testing of the cpsm. (1) offset from the base address of the ctm. bit: 15 14 13 12 11 10 9876543210 cpcr $08 (1) prun div23 psel1 psel0 reset: 0000000000000000 prescaler control register bits prescaler division ratio prun div23 psel1 psel0 pclk1 pclk2 pclk3 pclk4 pclk5 pclk6 0xxx000000 1000248163264 10012481632128 10102481632256 10112481632512 11003612244896 110136122448192 111036122448384 111136122448768 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola a-4 ctm reference register and bit summary a a.3 fcsm registers and bits a.3.1 fcsmsic ?fcsm status/interrupt/control register a.3.1.1 cof ?counter over?w ?g bit 1 (set) counter over?w has occurred. 0 (clear) counter over?w has not occurred. a.3.1.2 il[2:0] ?interrupt level bits a.3.1.3 iarb3 ?interrupt arbitration bit 3 the read/write iarb3 bit works in conjunction with the iarb[2:0] ?ld in the biusm module con?uration register. (1) offset from the base address of the fcsm submodule. bit: 15 14 13 12 11 10 9876543210 fcsmsic $00 (1) cof il2 il1 il0 iarb3 drva drvb in clk2 clk1 clk0 reset: 00000000u0000000 il2 il1 il0 selected level 0 0 0 interrupt disabled 0 0 1 interrupt level 1 (lowest) 0 1 0 interrupt level 2 0 1 1 interrupt level 3 1 0 0 interrupt level 4 1 0 1 interrupt level 5 1 1 0 interrupt level 6 1 1 1 interrupt level 7 (highest) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola a-5 register and bit summary a a.3.1.4 drva, drvb ?drive time base bus bits warning: it is not recommended that the two time base buses be driven at the same time. a.3.1.5 in ?input pin status bit this read-only status bit re?cts the logic state of the fcsm input pin ctmc a.3.1.6 clk[2:0] ?counter clock select bits a.3.2 fcsmcnt ?fcsm counter register (1) offset from the base address of the fcsm submodule. drva drvb bus selected 0 0 neither time base bus a nor time base bus b is driven 0 1 time base bus b is driven 1 0 time base bus a is driven 1 1 both time base bus a and time base bus b are driven clk2 clk1 clk0 free running counter clock source 0 0 0 prescaler output 1 ( ? 2 or ? 3) 0 0 1 prescaler output 2 ( ? 4 or ? 6) 0 1 0 prescaler output 3 ( ? 8 or ? 12) 0 1 1 prescaler output 4 ( ? 16 or ? 24) 1 0 0 prescaler output 5 ( ? 32 or ? 48) 1 0 1 prescaler output 6 ( ? 64 to ? 768) 1 1 0 ctmc pin input, negative edge 1 1 1 ctmc pin input, positive edge bit: 15 14 13 12 11 10 9876543210 fcsmcnt $02 (1) msb lsb reset: 0000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola a-6 ctm reference register and bit summary a a.4 mcsm registers and bits a.4.1 mcsmsic ?mcsm status/interrupt/control register a.4.1.1 cof ?counter over?w ?g bit 1 (set) counter over?w has occurred. 0 (clear) counter over?w has not occurred. a.4.1.2 il[2:0] ?interrupt level bits a.4.1.3 iarb3 ?interrupt arbitration bit 3 the read/write iarb3 bit works in conjunction with the iarb[2:0] ?ld in the biusm module con?uration register. (1) offset from the base address of the mcsm submodule. bit: 15 14 13 12 11 10 9876543210 mcsmsic $00 (1) cof il2 il1 il0 iarb3 drva drvb in2 in1 edgen edgep clk2 clk1 clk0 reset: 00000000uu000000 il2 il1 il0 selected level 0 0 0 interrupt disabled 0 0 1 interrupt level 1 (lowest) 0 1 0 interrupt level 2 0 1 1 interrupt level 3 1 0 0 interrupt level 4 1 0 1 interrupt level 5 1 1 0 interrupt level 6 1 1 1 interrupt level 7 (highest) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola a-7 register and bit summary a a.4.1.4 drva, drvb ?drive time base bus bits warning: it is not recommended that the two time base buses be driven at the same time. a.4.1.5 in2 ?clock input pin status bit this read-only status bit re?cts the logic state of the mcsm clock input pin ctmc. a.4.1.6 in1 ?modulus load input pin status bit this read-only status bit re?cts the logic state of the mcsm modulus load input pin ctml. a.4.1.7 edgen, edgep ?modulus load edge sensitivity bits a.4.1.8 clk[2:0] ?counter clock select bits drva drvb bus selected 0 0 neither time base bus a nor time base bus b is driven 0 1 time base bus b is driven 1 0 time base bus a is driven 1 1 both time base bus a and time base bus b are driven edgen edgep in1 edge detector sensitivity 0 0 none 0 1 positive edge only 1 0 negative edge only 1 1 positive and negative edge clk2 clk1 clk0 free running counter clock source 0 0 0 prescaler output 1 ( ? 2 or ? 3) 0 0 1 prescaler output 2 ( ? 4 or ? 6) 0 1 0 prescaler output 3 ( ? 8 or ? 12) 0 1 1 prescaler output 4 ( ? 16 or ? 24) 1 0 0 prescaler output 5 ( ? 32 or ? 48) 1 0 1 prescaler output 6 ( ? 64 to ? 768) 1 1 0 ctmc pin input, negative edge 1 1 1 ctmc pin input, positive edge f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola a-8 ctm reference register and bit summary a a.4.2 mcsmcnt ?mcsm counter register a.4.3 mcsmml ?mcsm modulus latch register (1) offset from the base address of the mcsm submodule. (1) offset from the base address of the mcsm submodule. bit: 15 14 13 12 11 10 9876543210 mcsmcnt $02 (1) msb lsb reset: 0000000000000000 bit: 15 14 13 12 11 10 9876543210 mcsmml $04 (1) msb lsb reset: 0000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola a-9 register and bit summary a a.5 sasm registers and bits a.5.1 sica ?sasm status/interrupt/control register a a.5.1.1 flag ?event ?g bit 1 (set) an input capture or output compare event has occurred. 0 (clear) an input capture or output compare event has not occurred. a.5.1.2 il[2:0] ?interrupt level bits a.5.1.3 iarb3 ?interrupt arbitration bit 3 the read/write iarb3 bit works in conjunction with the iarb[2:0] ?ld in the biusm module con?uration register. a.5.1.4 ien ?interrupt enable bit 1 (set) interrupts enabled. 0 (clear) interrupts disabled. (1) offset from the base address of the sasm submodule. bit: 15 14 13 12 11 10 9876543210 sica $00 (1) flag il2 il1 il0 iarb3 ien bsl in force edout mode1 mode0 reset: 0000000000000000 il2 il1 il0 selected level 0 0 0 interrupt disabled 0 0 1 interrupt level 1 (lowest) 0 1 0 interrupt level 2 0 1 1 interrupt level 3 1 0 0 interrupt level 4 1 0 1 interrupt level 5 1 1 0 interrupt level 6 1 1 1 interrupt level 7 (highest) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola a-10 ctm reference register and bit summary a a.5.1.5 bsl ?time base bus select bit 1 (set) time base bus b selected. 0 (clear) time base bus a selected. a.5.1.6 in ?input pin status bit in input mode (ic), the in bit re?cts the logic state present on the corresponding input pin (after being schmitt triggered and synchronized). in the output modes (oc, oct and op), the in bit value re?cts the state of the output of the output ?p-?p. a.5.1.7 force ?force compare control bit 1 (set) force output ?p-?p to behave as if an output compare has just occurred. 0 (clear) no action. a.5.1.8 edout ?edge detect and output level bit in ic mode: 1 (set) input capture on rising edge. 0 (clear) input capture on falling edge. in oc and op modes: 1 (set) output a logic one on the next output compare on channel a. 0 (clear) output a logic zero on the next output compare on channel a. a.5.1.9 mode1, mode0 ?sasm operating mode select bits mode1 mode0 sasm channel operating mode 0 0 input capture (ic) 0 1 output port (op) 1 0 output compare (oc) 1 1 output compare and toggle (oct) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola a-11 register and bit summary a a.5.2 sdata ?sasm data register a a.5.3 sicb ?sasm status/interrupt/control register b a.5.3.1 flag ?event ?g bit 1 (set) an input capture or output compare event has occurred on channel b. 0 (clear) an input capture or output compare event has not occurred on channel b. a.5.3.2 bsl ?time base bus select bit 1 (set) time base bus b selected. 0 (clear) time base bus a selected. a.5.3.3 in ?input pin status bit in input mode (ic), the in bit re?cts the logic state present on the corresponding input pin (after being schmitt triggered and synchronized). in the output modes (oc, oct and op), the in bit value re?cts the state of the output of the output ?p-?p. (1) offset from the base address of the sasm submodule. (1) offset from the base address of the sasm submodule. bit: 15 14 13 12 11 10 9876543210 sdata $02 (1) msb lsb reset: uuuuuuuuuuuuuuuu bit: 15 14 13 12 11 10 9876543210 sicb $04 (1) flag bsl in force edout mode1 mode0 reset: 0000000000000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola a-12 ctm reference register and bit summary a a.5.3.4 force ?force compare control bit 1 (set) force output ?p-?p to behave as if an output compare has just occurred on channel b. 0 (clear) no action. a.5.3.5 edout ?edge detect and output level bit in ic mode: 1 (set) input capture on rising edge. 0 (clear) input capture on falling edge. in oc and op modes: 1 (set) output a logic one on the next output compare on channel b. 0 (clear) output a logic zero on the next output compare on channel b. a.5.3.6 mode1, mode0 ?sasm operating mode select bits a.5.4 sdatb ?sasm data register b (1) offset from the base address of the sasm submodule. mode1 mode0 sasm channel operating mode 0 0 input capture (ic) 0 1 output port (op) 1 0 output compare (oc) 1 1 output compare and toggle (oct) bit: 15 14 13 12 11 10 9876543210 sdatb $06 (1) msb lsb reset: uuuuuuuuuuuuuuuu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola a-13 register and bit summary a a.6 dasm registers and bits a.6.1 dasmsic ?dasm status/interrupt/control register a.6.1.1 flag ?flag status bit 1 (set) an input capture or output compare event has occurred. 0 (clear) an input capture or output compare event has not occurred. a.6.1.2 il[2:0] ?interrupt level bits a.6.1.3 iarb3 ?interrupt arbitration bit 3 the read/write iarb3 bit works in conjunction with the iarb[2:0] ?ld in the biusm module con?uration register. a.6.1.4 wor ?wired-or bit 1 (set) output buffer is open-drain. 0 (clear) output buffer is totem pole. (1) offset from the base address of the dasm submodule. bit: 15 14 13 12 11 10 9876543210 dasmsic $00 (1) flag il2 il1 il0 iarb3 wor bsl in forca forcb edpol mode3 mode2 mode1 mode0 reset: 0000000000000000 il2 il1 il0 selected level 0 0 0 interrupt disabled 0 0 1 interrupt level 1 (lowest) 0 1 0 interrupt level 2 0 1 1 interrupt level 3 1 0 0 interrupt level 4 1 0 1 interrupt level 5 1 1 0 interrupt level 6 1 1 1 interrupt level 7 (highest) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola a-14 ctm reference register and bit summary a a.6.1.5 bsl ?bus select bit 1 (set) the dasm is connected to time base bus b. 0 (clear) the dasm is connected to time base bus a. a.6.1.6 in ?input pin status bit in the dis, ipwm, ipm and ic modes, this read-only status bit re?cts the logic level on the input pin. in the ocb, ocab and opwm modes, reading this bit returns the value latched on the output ?p-?p, after edpol polarity selection. a.6.1.7 forca ?force a bit 1 (set) force output ?p-?p to behave as if an output compare has just occurred on channel a. 0 (clear) no action. a.6.1.8 forcb ?force b bit 1 (set) force output ?p-?p to behave as if an output compare has just occurred on channel b. 0 (clear) no action. a.6.1.9 edpol ?edge polarity bit in the ipwm mode: 1 (set) channel a captures on a falling edge. channel b captures on a rising edge. 0 (clear) channel a captures on a rising edge. channel b captures on a falling edge. in the ipm and ic modes: 1 (set) channel a captures on a falling edge. 0 (clear) channel a captures on a rising edge. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola a-15 register and bit summary a in the ocb, ocab and opwm modes: 1 (set) the complement of the output ?p-?p logic level appears on the output pin: a compare on channel a resets the output pin; a compare on channel b sets the output pin. 0 (clear) the output ?p-?p logic level appears on the output pin: a compare on channel a sets the output pin, a compare on channel b resets the output pin. a.6.1.10 mode[3:0] ?mode select bits a.6.2 dasma ?dasm data register a (1) offset from the base address of the dasm submodule. dasm control register bits bits of resolution time base bits ignored dasm mode of operation mod3 mod2 mod1 mod0 0000 dis ?disabled 0001 16 ipwm ?input pulse width measurement 0010 16 ipm ?input period measurement 0011 16 ic input capture 0100 16 ocb ?output compare, ?g on b compare 0101 16 ocab ?output compare, ?g on a and b compare 0110 0111 1000 16 opwm ?output pulse width modulation 1001 15 15 opwm ?output pulse width modulation 1010 14 15, 14 opwm ?output pulse width modulation 1011 13 15-13 opwm ?output pulse width modulation 1100 12 15-12 opwm ?output pulse width modulation 1101 11 15-11 opwm ?output pulse width modulation 1110 9 15-9 opwm ?output pulse width modulation 1111 7 15-7 opwm ?output pulse width modulation bit: 15 14 13 12 11 10 9876543210 dasma $02 (1) msb lsb reset: uuuuuuuuuuuuuuuu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola a-16 ctm reference register and bit summary a a.6.3 dasmb ?dasm data register b (1) offset from the base address of the dasm submodule. bit: 15 14 13 12 11 10 9876543210 dasmb $04 (1) msb lsb reset: uuuuuuuuuuuuuuuu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola a-17 register and bit summary a a.7 pwmsm registers and bits a.7.1 pwmsic ?pwmsm status, interrupt and control register a.7.1.1 flag ?period completion status bit 1 (set) pwm period completed. 0 (clear) pwm period not completed. a.7.1.2 il[2:0] ?interrupt level bits a.7.1.3 iarb3 ?interrupt arbitration bit 3 the read/write iarb3 bit works in conjunction with the iarb[2:0] ?ld in the biusm module con?uration register. a.7.1.4 pin ?output pin status bit 1 (set) logic one state present on the pwmsm output pin. 0 (clear) logic zero state present on the pwmsm output pin. (1) offset from the base address of the pwmsm submodule. bit: 15 14 13 12 11 10 9876543210 pwmsic $00 (1) flag il2 il1 il0 iarb3 pin load pol en clk2 clk1 clk0 reset: 0000000000000000 il2 il1 il0 selected level 0 0 0 interrupt disabled 0 0 1 interrupt level 1 (lowest) 0 1 0 interrupt level 2 0 1 1 interrupt level 3 1 0 0 interrupt level 4 1 0 1 interrupt level 5 1 1 0 interrupt level 6 1 1 1 interrupt level 7 (highest) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola a-18 ctm reference register and bit summary a a.7.1.5 load ?period and pulse width register load control bit 1 (set) load pwmsm period and pulse width registers. 0 (clear) no action. a.7.1.6 pol ?output pin polarity control bit a.7.1.7 en ?pwmsm enable control bit 1 (set) enable the pwmsm and start generation of pwm output pulses. 0 (clear) disable the pwmsm and stop generation of pwm output pulses. control bits output pin state periodic edge variable edge optional interrupt on pol en 0 0 always low 1 0 always high 0 1 high pulse rising edge falling edge rising edge 1 1 low pulse falling edge rising edge falling edge f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola a-19 register and bit summary a a.7.1.8 clk[2:0] ?clock rate selection bits a.7.2 pwma ?pwm period register a.7.3 pwmb ?pwm pulse width register (1) offset from the base address of the pwmsm submodule. (1) offset from the base address of the pwmsm submodule. pwmsm clk bits cpsm bit div23 pwmsm clock clock source clk2 clk1 clk0 000 0 f sys ? 2 pclk1 001 0 f sys ? 4 prescaler ( ? 2) 010 0 f sys ? 8 prescaler ( ? 4) 011 0 f sys ? 16 prescaler ( ? 8) 100 0 f sys ? 32 prescaler ( ? 16) 101 0 f sys ? 64 prescaler ( ? 32) 1100f sys ? 128 prescaler ( ? 64) 1110f sys ? 512 prescaler ( ? 256) 000 1 f sys ? 3 pclk1 001 1 f sys ? 6 prescaler ( ? 2) 010 1 f sys ? 12 prescaler ( ? 4) 011 1 f sys ? 24 prescaler ( ? 8) 100 1 f sys ? 48 prescaler ( ? 16) 101 1 f sys ? 96 prescaler ( ? 32) 1101f sys ? 192 prescaler ( ? 64) 1111f sys ? 768 prescaler ( ? 256) bit: 15 14 13 12 11 10 9876543210 pwma $02 (1) msb lsb reset: uuuuuuuuuuuuuuuu bit: 15 14 13 12 11 10 9876543210 pwmb $04 (1) msb lsb reset: uuuuuuuuuuuuuuuu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola a-20 ctm reference register and bit summary a a.7.4 pwmc ?pwm counter register (1) offset from the base address of the pwmsm submodule. bit: 15 14 13 12 11 10 9876543210 pwmc $06 (1) msb lsb reset: 0000000000000001 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola b-1 ctm example ?ctm2 b b ctm example ?ctm2 ctm2 is an example of a typical ctm module implementation. a block diagram of ctm2 is shown in figure b-1; it comprises the following submodules: a bus interface unit submodule (biusm), a clock prescaler submodule (cpsm), a free-running counter submodule (fcsm), two modulus counter submodules (mcsm) and 10 double action submodules (dasm). note: ctm2 does not contain any single action submodules (sasm) nor any pulse width modulation submodules (pwmsm). figure b-1 shows how the time base buses interconnect the counters and the channels in ctm2. time base buses 2 and 3 are connected together to form one global time base bus (tbbb) that is accessible to every submodule. time base buses 1 and 4 are not connected together but are known collectively as time base bus a (tbba). each submodule has access to two time base buses, tbbb and either tbb1 or tbb4 (see table b-1). table b-2 shows how the ctm2 interrupt priority and vectors are structured. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola b-2 ctm reference ctm example ?ctm2 b figure b-1 con?urable timer module 2 (ctm2) table b-1 time base bus allocation submodule local/global time base bus allocation global bus a (tbba) global bus b (tbbb) mcsm 2 tbb4 tbb2 dasm 10, 11, 12, 13 tbb4 tbb2 dasm 14, 15, 16, 17, 18, 19 tbb1 tbb2 mcsm 24 tbb1 tbb2 fcsm 25 tbb1 tbb2 bus interface intermodule bus (imb) 16-bit time base bus 4 (tbb4/tbba) 16-bit time base bus 2 (tbb2/tbbb) clock prescaler submodule 16-bit time base bus 1 (tbb1/tbba) submodule bus (smb) external 6-line prescaler bus double action submodule (dasm10) ctm2c ctm2l modulus channel i/o pins double action submodule (dasm11) double action submodule (dasm12) double-action submodule (dasm) double action submodule (dasm13) double action submodule (dasm14) double action submodule (dasm15) double action submodule (dasm16) double action submodule (dasm17) double action submodule (dasm18) double action submodule (dasm19) ctd10 ctd11 ctd12 ctd13 ctd14 ctd15 ctd16 ctd17 ctd18 ctd19 free-running counter modulus counter modulus counter submodule (mcsm2) f clk clock pin load pin unit submodule /2 to /512, or /3 to /768 submodule (mcsm24) submodule (fcsm25) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola b-3 ctm example ?ctm2 b table b-2 also shows how the i/o pins are allocated in ctm2. note: in ctm2 all three counter submodules share one external clock input pin, ctm2c. (1) z represents the high address bits de?ing the ctm2 base address. (2) xx are the two interrupt vector base number bits vect7 and vect6 contained in the biusm. (3) interrupt arbitration #2 is highest priority, arbitration #25 is lowest priority. table b-2 ctm2 interrupt priority, vector allocation and pin allocation submodule name submodule binary base address (1) submodule binary vector number (2) submodule interrupt arbitration sequence number (3) corresponding pin name biusm z00000000 none none none cpsm z00001000 none none none mcsm2 z00010000 xx000010 2 ctm2c, ctm2l dasm 10 z01010000 xx001010 10 ctd10 dasm 11 z01011000 xx001011 11 ctd11 dasm 12 z01100000 xx001100 12 ctd12 dasm 13 z01101000 xx001101 13 ctd13 dasm 14 z01110000 xx001110 14 ctd14 dasm 15 z01111000 xx001111 15 ctd15 dasm 16 z10000000 xx010000 16 ctd16 dasm 17 z10001000 xx010001 17 ctd17 dasm 18 z10010000 xx010010 18 ctd18 dasm 19 z10011000 xx010011 19 ctd19 mcsm 24 z11000000 xx011000 24 ctm2c, ctm2l fcsm 25 z11001000 xx011001 25 ctm2c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola b-4 ctm reference ctm example ?ctm2 b b.1 ctm2 registers table b-3 ctm2 register map address 15 8 7 0 $yff400 $yff407 biusm registers $yff408 $yff40f cpsm registers $yff410 $yff417 mcsm 2 registers $yff418 $yff44f $yff450 $yff457 dasm 10 registers $yff458 $yff45f dasm 11 registers $yff460 $yff467 dasm 12 registers $yff468 $yff46f dasm 13 registers $yff470 $yff477 dasm 14 registers $yff478 $yff47f dasm 15 registers $yff480 $yff487 dasm 16 registers $yff488 $yff48f dasm 17 registers $yff490 $yff497 dasm 18 registers $yff498 $yff49f dasm 19 registers $yff4a0 $yff4bf $yff4c0 $yff4c7 mcsm 24 registers $yff4c8 $yff4cf fcsm 25 registers $yff4d0 $yff4ff reserved registers always return zeros when read. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola b-5 ctm example ?ctm2 b b.1.1 ctm2 bus interface unit submodule registers b.1.2 ctm2 counter prescaler submodule registers b.1.3 ctm2 free-running counter submodule registers b.1.4 ctm2 modulus counter submodule registers (1) offset from the base address of the mcsm. table b-4 biusm register map address 15 8 7 0 $yff400 module con?uration register (mcr) $yff402 biusm test register (tcr) $yff404 time base register (tbr) $yff406 table b-5 cpsm register map address 15 8 7 0 $yff408 cpsm control register (cpcr) $yff40a cpsm test register (cptr) $yff40c $yff40e table b-6 fcsm register map address 15 8 7 0 $yff4c8 fcsm status/interrupt/control register (fcsmsic) $yff4ca fcsm counter (fcsmcnt) $yff4cc $yff4ce table b-7 mcsm register map address (1) 15 8 7 0 $00 mcsm status/interrupt/control register (mcsmsic) $02 mcsm counter (mcsmcnt) $04 mcsm modulus latch (mcsmml) $06 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola b-6 ctm reference ctm example ?ctm2 b b.1.5 ctm2 double action submodule registers (1) offset from the base address of the dasm. table b-8 dasm register map address (1) 15 8 7 0 $00 dasm status/interrupt/control register (dasmsic) $02 dasm register a (dasma) $04 dasm register b (dasmb) $06 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola c-1 glossary c c glossary this section contains abbreviations and specialist words used in this data sheet and throughout the industry. $xxxx the digits following the ? are in hexadecimal format. %xxxx the digits following the ? are in binary format. a/d , adc analog-to-digital (converter). assert an asserted signal is driven to its active or true state, irrespective of that state being represented by a high or low voltage level. biu bus interface unit; in a module, the interface between the imb and the internal circuitry of the module. biusm bus interface unit submodule; in a module, the submodule that allows the module to be connected to the imb. all information transfer between the imb and the smb is handled by the biusm. bootstrap mode in this mode the device automatically loads its internal memory from an external source on reset and then allows this program to be executed. bus cycle a single transfer of data across the bus using the established protocols and timing. a bus cycle consists of a single byte or word transfer. byte eight bits. ccr condition codes register; an integral part of the cpu. cerquad a ceramic package type, principally used for eprom and high temperature devices. clear ? ?the logic zero state; the opposite of ?et? clock two tics; a full clock cycle. for a 16.67mhz clock, a clock cycle has a duration of 60ns. cmos complementary metal oxide semiconductor. a semiconductor technology chosen for its low power consumption and good noise immunity. coherency the caability of a system to handle data as if its data bus were the same width as the data block. cop computer operating properly. aka ?atchdog? this circuit is used to detect device runaway and provide a means for restoring correct operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola c-2 ctm reference glossary c cpsm counter prescaler submodule. cpu central processing unit. cpu16 motorola s 16-bit cpu core for imb based devices. cpu32 motorola s 32-bit cpu core for imb based devices. ctm con?urable timer module. d/a, dac digital-to-analog (converter). daisy chain in the ctm, a hardware priority system whereby the relative priorities of a number of interrupt sources is determined by their position in the chain. dasm double action submodule. ebi external bus interface; a module responsible for interfacing the imb with the external bus. the external bus includes those generalized lines needed for system operation and external transactions, but does not include the lines speci? to a module. ebis will differ from chip to chip depending upon the need for handling interrupts, external bus mastership, bus errors, etc. eeprom electrically erasable programmable read only memory. aka ?erom? eprom erasable programmable read only memory. this type of memory requires exposure to ultra-violet wavelengths in order to erase previous data. aka ?rom? esd electrostatic discharge. expanded mode in this mode the internal address and data bus lines are connected to external pins. this enables the device to be used in much more complex systems, where there is a need for external memory for example. evs evaluation system. one of the range of platforms provided by motorola for evaluation and emulation of their devices. fcsm free-running counter submodule. hcmos high-density complementary metal oxide semiconductor. a semiconductor technology chosen for its low power consumption and good noise immunity. i/o input/output; used to describe a bidirectional pin or function. imb inter module bus; the 68300 series standard internal bus. it allows exchange of data between master and slave modules. ic input capture; a function provided by the timing system, whereby an external event is ?aptured by storing the value of a counter at the instant the event is detected. interrupt an asynchronous external event handled by the mcu. the external event is detected by the mcu and causes a predetermined action to occur. irq interrupt request. (the overline indicates that this is an active-low signal format.) kbyte a kilo-byte (of memory); 1024 bytes. lcd liquid crystal display. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola c-3 glossary c lsb least signi?ant byte. master the module that initiates a bus request and controls the bus transaction with a slave module. mcsm modulus counter submodule. mcu microcontroller unit. module a functional block compatible with the motorola modular microcontroller family (mmf) that connects to the imb. msb most signi?ant byte. negate a negated signal is driven to its inactive or false state, irrespective of that state being represented by a high or low voltage level. nibble half a byte; four bits. nrz non-return to zero. opcode the opcode is a byte which identi?s the particular instruction and operating mode to the cpu. see also: prebyte, operand. operand the operand is a byte containing information the cpu needs to execute a particular instruction. there may be from 0 to 3 operands associated with an opcode. see also: opcode, prebyte. oc output compare; a function provided by the timing system, whereby an external event is generated when an internal counter value matches a prede?ed value. plcc plastic leaded chip carrier package. pll phase-locked loop circuit. this provides a method of frequency multiplication, to enable the use of a low frequency crystal in a high frequency circuit. prebyte this byte is sometimes required to qualify an opcode, in order to fully specify a particular instruction. see also: opcode, operand. pull-down, pull-up these terms refer to resistors, sometimes internal to the device, which are permanently connected to either ground or v dd . pwm pulse width modulation; a technique where the width of the high and low periods of a waveform is varied, usually to enable a representation of an analog value. qfp quad ?t pack package. ram random access memory. fast read and write, but contents are lost when the power is removed. rfi radio frequency interference. rti real-time interrupt. rom read-only memory. this type of memory is programmed during device manufacture and cannot subsequently be altered. rs-232c a standard serial communications protocol. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola c-4 ctm reference glossary c sar successive approximation register. sasm single action submodule. sci serial communications interface. set ? ?the logic one state; the opposite of ?lear? silicon glen an area in the central belt of scotland, so called because of the concentration of semiconductor manufacturers and users found there. sim system integration module; a module on an imb device that reduces the need for external glue logic by providing an external interface and a variety of other system related functions. single chip mode in this mode the device functions as a self contained unit, requiring only i/o devices to complete a system. slave the module that responds to a master's request. smb submodule bus; the internal ctm bus that allows exchange of information between submodules. spi serial peripheral interface. state subunit of the bus cycle in which speci? events occur. each state has a duration of one clock tic, and represents a single state within the controlling microengine. for the imb, the states de?ed include b1, b2, b2*, b3, b4 and b4*. submodule a functional block that de?es a ctm function. most of the submodules can be placed several times in order to obtain the desired system. test mode this mode is intended for factory testing. tic a clock tic is de?ed as the single high or low state, irrespective of that state being represented by a high or low voltage level. for a 16.67mhz, a clock tic has a duration of 30ns. transaction the transfer of data between two modules (a master and a slave) using the imb and its established protocol. a single transaction may require multiple bus cycles. ttl transistor-transistor logic. uart universal asynchronous receiver transmitter. vco voltage controlled oscillator. watchdog see ?op? wired-or a means of connecting outputs together such that the resulting composite output state is the logical or of the state of the individual outputs. word two bytes; 16 bits. xirq non-maskable interrupt request. the overline indicates that this has an active-low signal format. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola i index d d index in this index numeric entries are placed ?st; page references in italics indicate that the reference is to a ?ure. 0% and 100% ?ulses 9-5 3-byte access 1-3 1-5 a action submodule 1-3 aligned access 1-3 1-5 arbitration 3-2 b biumcr ?biusm module configuration register 2-2 biusm biumcr ?biusm module configuration register 2-2 biutbr ?biusm time base register 2-5 biutest ?biusm test configuration register 2-4 freeze 2-1 interrupt vector base number 2-3 interrupt vector table 2-3 lpstop 2-1 reading the time base bus 2-5 register map 2-2 selecting the time base bus 2-4 stop 2-2 wait 2-2 biutbr ?biusm time base register 2-5 biutest ?biusm test configuration register 2-4 block diagrams cpsm 4-1 ctm architecture 1-2 ctm2 b-2 dasm 8-1 fcsm 5-2 gpt pulse width modulation system 1-10 input capture (concept) 1-7 mcsm 6-1 output compare (concept) 1-7 pulse accumulator (concept) 1-8 pwmsm 9-3 block diagrams - continued sasm 7-1 sasm channel a 7-3 bsl bit in dasmsic 8-15 bit in sica 7-9 bus interface unit submodule - see biusm byte access 1-3 1-5 c changing mode dasm 8-3 sasm 7-3 clearing flags 1-10 clk[2:0] bits in fcsmsic 5-6 bits in mcsmsic 6-7 bits in pwmsic 9-12 clock source module 1-3 clocks fcsm 5-2 mcsm 6-3 pclk clock generation 4-1 pwmsm 9-2 , 9-13 system clock - f sys 4-1 cof bit in fcsmsic 5-4 bit in mcsmsic 6-5 coherency dasm 8-3 8-5 general 1-3 1-5 pwmsm 9-5 counter dasm 8-11 fcsm 5-1 mcsm 6-2 counter overflow fcsm 5-1 mcsm 6-5 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola ii ctm reference index d counter overflow - continued pulse accumulator 1-8 pwm 1-9 counter prescaler 4-1 counter prescaler submodule - see cpsm cpcr ?cpsm control register 4-2 cpsm block diagram 4-1 counter prescaler 4-1 cpcr ?cpsm control register 4-2 cptr ?cpsm test register 4-3 freeze 4-2 prescaler division ratio selection 4-3 register map 4-2 cptr ?cpsm test register 4-3 ctm2 b-1 block diagram b-2 clock input pin - ctm2c b-1 interrupts b-3 pin allocation b-3 time base bus b-3 vector allocation b-3 d daisy-chain priority 3-2 dasm block diagram 8-1 changing mode 8-3 , 8-4 clock divide ratio 8-11 coherency 8-3 8-5 configuring the output buffer 8-15 counter 8-11 dasma ?dasm data register a 8-18 dasmb ?dasm data register b 8-18 dasmsic ?dasm status/interrupt/control register 8-14 disable (dis) mode 8-4 effect of reset on output flip-flop 8-8 flag clearing mechanism 8-14 forcing an output compare 8-16 freeze 8-13 input capture (ic) mode 8-7 input capture example 8-7 input period measurement (ipm) mode 8-5 input pin 8-2 input pin logic level 8-16 interrupts 8-12 minimum pulse width 8-2 modes of operation 8-3 multiple dasms 8-13 output compare (oca and ocab) modes 8-7 output frequencies and resolutions 8-12 output pin 8-2 output port bit operation 8-9 output pulse width modulation (opwm) mode 8-10 output pulse width modulation example 8-11 pulse width measurement (ipwm) mode 8-4 pulse width measurement example 8-5 dasm - continued register map 8-13 reserved register 8-13 selecting the input capture edge sensitivity 8-16 selecting the mode of operation 8-17 selecting the time base bus 8-15 single output compare 8-9 single shot output pulse 8-8 single-shot output pulse example 8-9 spurious interrupts 8-3 dasma ?dasm data register a 8-18 dasmb ?dasm data register b 8-18 dasmsic ?dasm status/interrupt/control register 8-14 data access 1-3 1-5 div23 - bit in cpcr 4-3 double action submodule - see dasm double buffer 9-4 drva, drvb bits in fcsmsic 5-5 bits in mcsmsic 6-6 duty cycle 1-9 e edgen, edgep - bits in mcsmsic 6-7 edout - bit in sica 7-9 edpol - bit in dasmsic 8-16 en - bit in pwmsic 9-12 enabling/disabling the ctm 2-3 event counter fcsm 5-2 mcsm 6-3 pulse accumulator 1-8 exception level mask 3-1 exception processing 3-1 f fcsm block diagram 5-2 clock sources 5-2 counter 5-1 counter overflow 5-4 driving the time base bus 5-5 effect of reset 5-1 event counter 5-2 fcsmsic ?fcsm status/interrupt/control reg. 5-4 flag clearing 5-4 freeze 5-3 input pin - ctmc 5-2 , 5-5 interrupts 5-2 , 5-3 maximum external clock frequency 5-3 , 5-6 register map 5-4 reserved registers 5-4 selecting the clock source 5-6 selecting the time base bus 5-3 setting the interrupt level 5-5 tpg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m ctm reference motorola iii index d fcsm - continued using multiple fcsms 5-4 fcsm - free-running counter submodule 5-1 fcsmcnt ?fcsm counter register 5-6 fcsmsic ?fcsm status/interrupt/control reg. 5-4 flag bit in dasmsic 8-14 bit in pwmsic 9-9 bit in sica 7-7 flag clearing 1-10 forca - bit in dasmsic 8-16 forcb - bit in dasmsic 8-16 force - bit in sica 7-9 free-running counter 1-6 frz - bit in biumcr 2-3 g gated mode pulse accumulator 1-8 glitches 9-12 i iack 2-4 , 3-1 iarb[2:0] - bits in biumcr 2-4 iarb3 bit in dasmsic 8-15 bit in fcsmsic 5-5 bit in mcsmsic 6-6 bit in pwmsic 9-10 bit in sica 7-8 ien - bit in sica 7-8 il[2:0] bits in dasmsic 8-15 bits in fcsmsic 5-5 bits in mcsmsic 6-6 bits in pwmsic 9-10 bits in sica 7-8 imb - intermodule bus 1-1 in bit in dasmsic 8-16 bit in fcsmsic 5-5 bit in sica 7-9 in1 - bit in mcsmsic 6-7 in2 - bit in mcsmsic 6-6 input capture concepts 1-6 example using dasm 8-20 period and pulse width measurement 1-6 sasm 7-1 sasm ic mode 7-4 input pins ctm2c (ctm2) b-1 dasm 8-2 fcsm 5-2 , 5-5 mcsm 6-3 , 6-6 , 6-7 input pins - continued sasm 7-2 interrupt acknowledge - see iack interrupt arbitration number 2-4 interrupts 3-1 ctm2 b-3 dasm 8-12 fcsm 5-2 , 5-3 mcsm 6-3 , 6-4 priority levels on the imb 3-1 pwmsm 9-6 sasm 7-4 , 7-5 , 7-6 setting the priority level 2-4 simultaneous interrupts 3-2 spurious interrupt vector 2-4 vector base number 2-3 vector table 2-3 l load - bit in pwmsic 9-11 loading the mcsm counter register 6-2 long word access 1-3 1-5 m maximum external clock frequency fcsm 5-3 , 5-6 mcsm 6-3 , 6-7 mcsm as free-running counter 6-3 block diagram 6-1 clock input pin - ctmc 6-3 , 6-6 clocks 6-3 counter 6-2 counter overflow 6-5 driving the time base bus 6-6 effect of reset 6-2 event counter 6-3 flag clearing 6-5 freeze 6-4 input pin - ctml 6-3 interrupts 6-3 , 6-4 loading the counter register 6-2 maximum external clock frequency 6-3 , 6-7 mcsmcnt ?mcsm counter register 6-7 mcsmml ?mcsm modulus latch register 6-8 mcsmsic ?mcsm status/interrupt/control register 6-5 modulus latch 6-2 modulus load input pin - ctml 6-7 register map 6-5 reserved registers 6-4 selecting ctml edge sensitivity 6-7 selecting the clock source 6-7 selecting the time base bus 6-4 setting the interrupt level 6-6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola iv ctm reference index d mcsmcnt ?mcsm counter register 6-7 mcsmml ?mcsm modulus latch register 6-8 mcsmsic ?mcsm status/interrupt/control register 6-5 minimum pulse width dasm 8-2 pwmsm 9-1 , 9-2 , 9-7 misaligned access 1-3 1-5 mode[3:0] - bits in dasmsic 8-17 mode1, mode0 - bit in sica 7-10 modes of operation dasm 8-3 dasm disable mode 8-4 dasm period measurement mode 8-5 dasm pulse width measurement mode 8-4 event counting mode 1-8 , 5-2 , 6-3 gated mode 1-8 input capture 7-4 , 8-7 output compare 7-4 , 8-7 output compare and toggle 7-5 output port 7-5 pulse accumulator concepts 1-8 pulse width modulation 8-10 stop mode 2-1 test mode 2-5 modulus counter submodule - mcsm modulus latch 6-2 multiple dasms 8-13 multiple fcsms 5-4 multiple sasms 7-6 o open-drain 8-8 , 8-12 , 8-15 output compare concepts 1-7 example using dasm 8-22 pulse and signal generation 1-7 sasm 7-1 sasm oc mode 7-4 toggling the state on a pin 1-8 output compare and toggle sasm oct mode 7-5 output flip-flop effect of reset 7-2 , 8-8 , 9-4 output latch pwm 1-9 output pins dasm 8-2 pwmsm 9-2 sasm 7-1 outputs sasm op mode 7-5 p period and pulse width measurement 1-6 period measurement example using dasm ipm mode 8-21 period register values pwmsm 9-8 pin - bit in pwmsic 9-10 pin allocation ctm2 b-3 pipelining 1-3 , 1-5 pol - bit in pwmsic 9-11 prescaler, switching on and off. 4-2 prun - bit in cpcr 4-2 psel1, psel0 - bits in cpcr 4-3 pulse accumulator concepts 1-8 counter overflow 1-8 event counting mode 1-8 gated mode 1-8 modes of operation 1-8 pulse and signal generation 1-7 pulse width modulation example using dasm 8-24 pulse width modulation (pwm) concepts 1-9 waveforms 1-9 pulse width modulation submodule - see pwmsm pwm duty cycle 1-9 pwma ?pwm period register 9-12 pwmb ?pwm pulse width register 9-13 pwmc ?pwm counter register 9-14 pwmsic ?status, interrupt and control register 9-9 pwmsm block diagram 9-3 clock rate selection 9-13 clock selection 9-2 coherency 9-5 comparators 9-4 counter 9-3 effect of reset on counter 9-3 effect of reset on output flip-flop 9-4 enabling and disabling the pwmsm 9-12 features 9-1 freeze 9-6 frequency 9-6 , 9-7 interrupts 9-6 maximum duty cycle 9-5 maximum output frequency 9-1 minimum pulse width 9-1 , 9-2 , 9-7 output flip-flop 9-2 , 9-5 output pin 9-2 output pulse width 9-5 period registers 9-4 pulse width 9-6 , 9-7 pulse width register values 9-8 pulse width registers 9-4 pwma ?pwm period register 9-12 pwmb ?pwm pulse width register 9-13 pwmc ?pwm counter register 9-14 pwmsic ?status, interrupt and control register 9-9 register map 9-9 reinitialization 9-11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola v ctm reference index d pwmsm - continued resolution 9-6 selecting the counter clock source 9-12 selecting the output pin polarity 9-11 setting the polarity of the output signal 9-11 r register maps biusm 2-2 cpsm 4-2 ctm2 b-4 dasm 8-13 fcsm 5-4 mcsm 6-5 pwmsm 9-9 sasm 7-7 resets effect on fcsm counter 5-1 effect on mcsm 6-2 effect on output flip-flop 9-4 effect on pwmsm counter 9-3 s sasm block diagram 7-1 capturing the time base bus value 7-4 changing mode 7-3 channel a block diagram 7-3 channel interrupt priority 7-6 clearing flags 7-4 , 7-5 effect of reset on output flip-flop 7-2 enabling interrupts 7-8 flag clearing 7-2 , 7-8 forcing an output compare 7-4 , 7-9 freeze 7-6 ic mode 7-4 input pin 7-2 interrupts 7-4 , 7-5 , 7-6 modes of operation 7-2 multiple sasms 7-6 oc mode 7-4 oct mode 7-5 op mode 7-5 output flip-flop 7-2 , 7-4 , 7-5 output pin 7-1 register map 7-7 sdata ?sasm data register a 7-10 sdatb ?sasm data register b 7-11 selecting input capture edge sensitivity 7-9 selecting the mode of operation 7-10 selecting the time base bus 7-9 setting the interrupt level 7-8 sica ?sasm status/interrupt/control register a 7-7 sicb ?sasm status/interrupt/control register b 7-10 simultaneous interrupts 7-8 sasm - continued spurious interrupts 7-3 time base bus 7-5 vectors, vector numbers 7-6 sdata ?sasm data register a 7-10 sdatb ?sasm data register b 7-11 sica ?sasm status/interrupt/control register a 7-7 sicb ?sasm status/interrupt/control register b 7-10 single action submodule - see sasm smb - submodule bus 1-2 stop - bit in biumcr 2-3 synchronization of counters 5-1 synchronization of submodules 4-3 t tbrs1, tbrs0 - bits in biumcr 2-4 time base bus 1-2 , 1-5 ctm2 b-3 dasm 8-15 fcsm 5-3 mcsm 6-4 reading 2-5 sasm 7-4 , 7-5 selecting 2-4 , 5-3 , 6-4 , 7-9 , 8-15 toggle 7-5 totem pole 8-8 totem pole 8-12 , 8-15 v vect7, vect6 - bits in biumcr 2-3 vector address 3-3 vector allocation ctm2 b-3 vector number 3-3 w wired-or 1-5 wired-or 8-15 wor - bit in dasmsic 8-15 word access 1-3 1-5 z zero detector pwm 1-9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m motorola vi ctm reference index this page intentionally left blank d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m customer feedback questionnaire (CTMRM) motorola wishes to continue to improve the quality of its documentation. we would welcome your feedback on the publication you have just received. having used the document, please complete this card (or a photocopy of it, if you prefer). 1. how would you rate the quality of the document? check one box in each category. excellent poor excellent poor organization tables readability table of contents understandability index accuracy page size/binding illustrations overall impression comments: 2. what is your intended use for this document? if more than one option applies, please rank them (1, 2, 3). selection of device for new application other please specify: system design training purposes 3. how well does this manual enable you to perform the task(s) outlined in question 2? completely not at all comments: 4. how easy is it to ?d the information you are looking for? easy dif?ult comments: 5. is the level of technical detail in the following sections suf?ient to allow you to understand how the device functions? too little detail too much detail comments: 6. have you found any errors? if so, please comment: 7. from your point of view, is anything missing from the document? if so, please say what: ?cut along this line to remove table of contents/list of figures/list of tables section 1 functional overview section 2 bus interface unit submodule (biusm) section 3 interrupts section 4 counter prescaler submodule (cpsm) section 5 free-running counter submodule (fcsm) section 6 modulus counter submodule (mcsm) section 7 single action submodule (sasm) section 8 double action submodule (dasm) section 9 pulse width modulation submodule (pwmsm) section 10 electrical specifications appendix a register summary appendix b ctm example ?ctm2 appendix c glossary appendix d index f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m 13. currently there is some discussion in the semiconductor industry regarding a move towards providing data sheets in electron ic form. if you have any opinion on this subject, please comment. 14. we would be grateful if you would supply the following information (at your discretion), or attach your card. name: phone no: position: fax no: department: company: address: thank you for helping us improve our documentation, graham livey, technical publications manager, motorola ltd., scotland . ?cut along this line to remove ?second fold back along this line ?third fold back along this line ?last tuck this edge into opposite ?p 8. how could we improve this document? 9. how would you rate motorola s documentation? excellent poor ?in general ?against other semiconductor suppliers 10. which semiconductor manufacturer provides the best technical documentation? 11. which company (in any ?ld) provides the best technical documentation? 12. how many years have you worked with microprocessors? less than 1 year 1? years 3? years more than 5 years by air mail par avion ne pas affranchir ibrs number phq-b/207/g ccri numero phq-b/207/g reponse payee grande-bretagne motorola ltd., colvilles road, kelvin industrial estate, east kilbride, g75 8br. great britain. f.a.o. technical publications manager (re: CTMRM/d) no stamp required ?first fold back along this line ! motorola ltd. semiconductor products sector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m 1 2 3 4 5 6 7 8 9 10 a b c d functional overview bus interface unit submodule (biusm) interrupts counter prescaler submodule (cpsm) free-running counter submodule (fcsm) modulus counter submodule (mcsm) single action submodule (sasm) double action submodule (dasm) pulse width modulation submodule (pwmsm) electrical specifications register summary ctm example ?ctm2 glossary index f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m 1 2 3 4 5 6 7 8 9 10 a b c d functional overview bus interface unit submodule (biusm) interrupts counter prescaler submodule (cpsm) free-running counter submodule (fcsm) modulus counter submodule (mcsm) single action submodule (sasm) double action submodule (dasm) pulse width modulation submodule (pwmsm) electrical specifications register summary ctm example ?ctm2 glossary index f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 literature distribution centres: europe: motorola ltd., european literature centre, 88 tanners drive, blakelands, milton keynes, mk14 5bp, england. asia pacific: motorola semiconductors (h.k.) ltd., silicon harbour center, no. 2, dai king street, tai po industrial estate, tai po, n.t., hong kong. japan: nippon motorola ltd., 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141, japan. usa: motorola literature distribution, p.o. box 20912, phoenix, arizona 85036. !motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i n c . . . freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m |
Price & Availability of CTMRM
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |