1 addendum to the SYM53C860 data manual version 2.0 december, 1997 this addendum contains new and changed information for the and SYM53C860 data manual version 2.0, published in june 1996. the information will be added to the next version of the manual. the changes are listed in the order in which their appropriate chapters appear in the data manual. the power management features of the SYM53C860e enable it to comply with microsofts pc 97 hardware design guide. this addendum applies to both devices, SYM53C860 and SYM53C860e, except where noted. chapter 2, functional description figure 2-4, determining the synchronous transfer rate, was inadvertently omitted. see the reference to this figure under the main heading synchronous operation. the drawing appears below. scf2 scf1 scf0 scf divisor 001 1 0 1 0 1.5 011 2 100 3 000 3 101 4 tp2 tp1 tp0 xferp divisor 000 4 001 5 010 6 011 7 100 8 101 9 11010 11111 sclk scf divider ccf divider this point must not exceed 80 mhz synchronous divider asynchronous scsi logic divide by 4 receive clock send clock (to scsi bus) cf2 ccf1 ccf0 scsi clock (mhz) 0 0 0 50.1-66.00 0 0 1 16.67-25.00 0 1 0 25.01-37.50 0 1 1 37.51-50.00 1 0 0 50.01-66.00 1 0 1 75.01-80.00 example: sclk= 80 mhz, scf = 1(/1), xferp = 0(/4), ccf = 5(75.01-80.00mhz) synchronous send rate = (sclk/scf)/xferp = (80/1)/4=20mb/s synchronous receive rate = (sclk/scf)/4 = (80/1)/4=20mb/s figure 2-4: determining the synchronous transfer rate
2 power management the SYM53C860e complies with the pci bus power management interface specification, revision 1.0. the pci function power states are defined in that specification: d0, d1, d2, and d3. d0 and d3 are required by specification and d1 and d2 are optional. d0 is the maximum powered state, and d3 is the minimum powered state. power state d3 is further categorized as d3hot or d3cold. a function that is powered off is said to be in the d3cold power state. the power states for the scsi function are independently controlled through two power state bits that are located in the pci configuration space register 44h. the bits are encoded as: 00b C power state d0, 01b C reserved, 10b - reserved, and 11b - power state d3. the pci function power states--d0 and d3--are described below. power states d1 and d2 are not implemented for this device. power state d0 power state d0 is the maximum power state and is the power-up default state for each function. power state d3 power state d3 is the minimum power state, which includes subsettings called d3hot and d3cold. the devices are considered to be in power state d3cold when power is removed from them. d3cold can transition to d0 by applying vcc and resetting the device. d3hot allows the device to transition to d0 via software. to obtain power reduction in d3hot, the scsi clock and the scsi clock doubler phase lock loop (pll) are disabled. furthermore, soft reset is continually asserted while in power state d3hot, which clears all pending interrupts and tristates the scsi bus. in addition, the functions pci command register is cleared.
3 chapter 3, pci functional description configuration registers figure 3-1 : pci configuration register map 31 16 15 0 device id vendor id = 1000h 00h status command 04h class code rev id 08h not supported header type latency timer cache line size 0ch base address zero (i/o), scsi operating registers 10h base address one (memory), scsi operating registers 14h base address two (memory) scripts ram 18h not supported 1ch not supported 20h not supported 24h reserved 28h subsystem id subsystem vendor id 2ch expansion rom base address 30h reserved capabilities pointer 34h reserved 38h max_lat min_gnt interrupt pin interrupt line 3ch power management capabilities next item pointer capability id 40h data bridge support ext pwr. mgmt. control/status register 44h note: shaded areas are reserved or represent the SYM53C860e capabilities.
4 configuration register changes for SYM53C860e register 2ch subsystem vendor id (ssvid) read only svid svid svid svid 15-12 11-8 7-4 3-0 default>>> 1 0 0 0 this register supports subsystem identification, which has a default value of 1000h in the SYM53C860e. register 2eh subsystem id (ssid) read only sid sid sid sid 15-12 11-8 7-4 3-0 default>>> 1 0 0 0 this register supports subsystem identification, which has a default value of 1000h in the SYM53C860e. register 06h status read/write dpe sse rma rta res dt dpr res nc res 15 14 13 12 11 10-9 8 7-5 4 3-0 default >>> 00 0000001 0 reads to this register behave normally. writes are slightly different in that bits can be cleared, but not set. a bit is reset whenever the register is written and the data in the corresponding bit location is a one. for instance, to clear bit 15 and not affect any other bits, write the value 8000h to the register. please note the following changes to register 06h bits 7-0. bits 7-5 reserved bit 4 new capabilities (nc) this bit is set to indicate the presence of a list of extended capabilities such as pci power management. this bit is read only. bits 3-0 reserved
5 register 08h revision id read only rid rid rid rid rid rid rid rid 76543210 default >>> 00 010011 this field specifies device and revision identifiers. the value of this register is 13h. register 34h capability pointer read only cp cp cp cp cp cp cp cp 76543210 default >>> 01 000000 this register provides an offset into the functions pci configuration space for the location of the first item in the capabilities linked list. this register is set by the device to 40h. register 40h capability id read only cid cid cid cid cid cid cid cid 76543210 default >>> 00 000001 this register indicates the type of the current data structure (linked list item). this register is set by the device to a value of 01h, indicating the power management data structure. register 41h next item pointer read only np np np np np np np np 76543210 default >>> 00 000000 this register describes the location of the next item in the functions capability list. this register is set by the device to a value of 00h, indicating that power management is the last capability in the linked list of extended capabilities.
6 register 42h power management capabilities read only pmes d2s d1s res dsi aps pmec ver 15-11 10 9 8-6 5 4 3 2-0 default >>> 00 000001 this register indicates the power management capabilities. bits 15-11 pme support (pmes) this field always returns a zero value because the devices do not provide a pme signal. bit 10 d2 support (d2s) this device does not support the d2 power management state. bit 9 d1 support (d1s) this device does not support the d1 power management state. bits 8-6 reserved bit 5 device specific initialization (dsi) this bit is set to 0 to indicate that the device requires no special initialization before the generic class device driver is able to use it. bit 4 auxiliary power source (aps) because the device does not provide a pme signal, this bit always returns a 0. this indicates that no auxiliary power source is required to support the pme signal in the d3cold power management state. bit 3 pme clock (pmec) this bit always returns a 0b value because the SYM53C860e does not provide a pme signal. bits 2-0 version (ver) this field is set to 001b to indicate that the device complies with revision 1.0 of the pci power management interface specification. register 44h power management control/status read/write pst dscl dslt pen res pws 15 14-13 12-9 8 7-2 1-0 default >>> 00 0000 this register indicates the power management control and status descriptions.
7 bit 15 pme status (pst) the device always returns a 0 for this bit, indicating that pme signal generation is not sup- ported from d3cold. bits 14-13 data scale (dscl) the device does not support the data register, therefore this field is always set to 00b. bits 12-9 data select (dslt) the device does not support the data register, therefore this field is always set to 0000b . bit 8 pme enable (pen) the device always returns a 0 for this bit to indicate that pme assertion is disabled. bits 7-2 reserved bits 1-0 power state (pws) this two bit field determines the current power state for the function and is used to set the function to a new power state. the definitions of the field values are: 00b - d0 01b - reserved 10b - reserved 11b - d3hot register 46h pmcsr bse read only bse bse bse bse bse bse bse bse 76543210 default >>> 00 000000 this register can support pci bridge specific functionality if required. the default value always returns 00h. register 47h data read only this register provides an optional mechanism for the function to report state-dependent operating data. the default value is 00h. this is currently not implemented for these devices.
8 chapter 5, operating registers on page 5-12, the formula given to calculate the synchronous send and receive rates is incorrect. the correct formula is: synchronous send rate = (sclk/scf)/xferp synchronous receive rate = (sclk/scf)/4 key: sclk = scsi clock scf = synchronous clock conversion factor, scntl3 bits 6-4 xferp = transfer period, sxfer register bits 7-5 appendix c, external memory interface diagrams this appendix was mistakenly included in some copies of the SYM53C860 data manual version 2.0. if you received this chapter in your copy, please disregard it. the SYM53C860 does not have an external memory interface.
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