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preliminary rev. 0.41 6/09 copyright ? 2009 by silicon laboratories si5368 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. si5368 a ny -r ate p recision c lock m ultiplier /j itter a ttenuator description the si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. the si5368 accepts four clock inputs ranging from 2 khz to 710 mhz and generates five clock outputs ranging from 2 khz to 945 mhz and select frequencies to 1.4 ghz. the device provides virtually any frequency translation combination across this operating range. the outputs are divided down separately from a common source. the si5368 input clock frequency and clo ck multiplication ratio are programmable through an i 2 c or spi interface. the si5368 is based on silicon laboratori es' third-generation dspll ? technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated pll solution that eliminates the need for exte rnal vcxo and loop filter components. the dspll loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. operatin g from a single 1.8, 2.5 ,or 3.3 v supply, the si5368 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. applications ? sonet/sdh oc-48/stm-16/o c-192/stm-64 line cards ? gbe/10gbe, 1/2/4/8/ 10g fc line cards ? itu g.709 and custom fec line cards ? wireless basestations ? data converter clocking ? otn/wdm muxponder, mspp, roadm line cards ? sonet/sdh + pdh clock synthesis ? test and measurement ? synchronous ethernet ? broadcast video features ? generates any frequency from 2 khz to 945 mhz and select frequencies to 1.4 ghz from an input frequency of 2 khz to 710 mhz ? ultra-low jitter clock outputs with jitter generation as low as 300 fs rms (50 khz?80 mhz) ? integrated loop filter with selectable loop bandwidth (60hz to 8.4khz) ? meets oc-192 gr-253-cor e jitter specifications ? four clock inputs with manual or automatically controlled hitless switching and phase build-out ? supports holdover and freerun modes of operation ? five clock outputs with selectable signal format (lvpecl, lvds, cml, cmos) ? sonet frame sync switching and regeneration ? support for itu g.709 and custom fec ratios (253/226, 239/237, 255/238, 255/237, 255/236) ? lol, los, fos alarm outputs ? digitally-controlled ou tput phase adjust ? i 2 c or spi programmable settings ? on-chip voltage regulator for 1.8 v 5%, 2.5 v 10%, or 3.3 v 10% operation ? small size: 14 x 14 mm 100-pin tqfp ? pb-free, rohs compliant p reliminary d ata s heet rate select i 2 c/spi port clock select xtal or refclock ckout2 ckin1 ckout1 ckin2 control skew control ckin3/fsync1 ckin4 ckout4 ckout5/fs_out input clock 3 input clock 4 output clock 2 vdd (1.8, 2.5, or 3.3 v) gnd n32 n31 dspll ? n2 ckout3 n33 n34 device interrupt lol/los/fos alarms fsync realignment n1_hs nc1_ls nc2_ls nc3_ls nc4_ls nc5_ls
si5368 2 preliminary rev. 0.41
si5368 preliminary rev. 0.41 3 t able of c ontents section page 1. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.1. external reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2. further documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2. pin descriptions: si5368 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6. package outline: 100- pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7. recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
si5368 4 preliminary rev. 0.41 table 1. performance specifications (v dd = 1.8 5%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit temperature range t a ?40 25 85 oc supply voltage v dd see note 3. 2.97 3.3 3.63 v 2.25 2.5 2.75 v 1.71 1.8 1.89 v supply current (supply current is independent of v dd ) i dd f out = 622.08 mhz all ckouts enabled lvpecl format output ? 394 435 ma only ckout1 enabled ? 253 284 ma f out = 19.44 mhz all ckouts enabled cmos format output ? 278 321 ma only ckout1 enabled ? 229 261 ma sleep mode ? 165 ma input clock frequency (ckin1, ckin2, ckin3, ckin4) ck f input frequency and clock multiplication ratio determined by programming device pll dividers. consult silicon laboratories configuration software dspll sim or any- rate precision clock family reference manual at www.silabs.com/timing (click on documentation) to determine pll divider settings for a given input frequency/clock multiplication ratio combination. 0.002 ? 710 mhz input clock frequency (ckin3, ckin4 used as fsync inputs) ck f 0.002 ? 0.512 mhz output clock frequency (ckout1, ckout2, ckout3, ckout4, ckout5 used as fifth high-speed out- put) ck of 0.002 970 1213 ? ? ? 945 1134 1400 mhz ckout5 used as frame sync output (fs_out) ck of 0.002 ? 710 mhz 3-level input pins input mid current i imm see note 2. ?2 ? 2 a input clocks (ckin1, ckin2, ckin3, ckin4) differential voltage swing ckn dpp 0.25 ? ? v pp notes: 1. for a more comprehensive listing of device specifications , please consult the silicon laboratories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing (click on documentation) . 2. this is the amount of leakage that the 3-level input can tolerate from an external driver. see the family reference manual. in most designs, an external resistor voltage divider is recommended. 3. the lvpecl and cmos output formats draw more current than either lvds or cml; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the tqfp devices is limited when they are operated at 3.3 v. w hen there are four enabled lvpecl or cmos outputs, the fifth output must be disabled. when there are five enabled outputs, there can be no more than three outputs that are either lvpecl or cmos.
si5368 preliminary rev. 0.41 5 input voltage level limits ckn vin 0?v dd v common mode voltage ckn vcm 1.8 v 5% 0.9 ? 1.4 v 2.5 v 10% 1.0 ? 1.7 v 3.3 v 10% 1.1 ? 1.95 v rise/fall time ckn trf 20?80% ? ? 11 ns duty cycle (minimum pulse width) ckn dc whichever is smaller 40 ? 60 % 2??ns output clocks (ckout1, ckout2 , ckout3, ckout4, ckout5/fs_out) common mode v ocm lvpecl 100 ? load line-to-line v dd ?1.42 ? v dd ?1.25 v differential output swing v od 1.1 ? 1.9 v dd single ended output swing v se 0.5 ? 0.93 vpp pll performance jitter generation j gen f in = f out = 622.08 mhz, lvpecl output format 50 khz?80 mhz ? 300 420 fs rms 12 khz?20 mhz ? 300 410 fs rms jitter peaking j pk f in = f out = 622.08 mhz ? 0.05 0.1 db phase noise cko pn f in = f out = 622.08 mhz 100 hz offset ? ?65 ?50 dbc/hz 1 khz offset ? ?95 ?87 dbc/hz 10 khz offset ? ?110 ?100 dbc/hz 100 khz offset ? ?117 ?110 dbc/hz 1 mhz offset ? ?130 ?125 dbc/hz subharmonic noise sp subh phase noise @ 100 khz offset ? ?90 ?85 dbc spurious noise sp spur max spur @ n x f3 (n > 1, n x f3 < 100 mhz) ? ?98 ?75 dbc table 1. performance specifications (continued) (v dd = 1.8 5%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit notes: 1. for a more comprehensive listing of device specifications , please consult the silicon laboratories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing (click on documentation) . 2. this is the amount of leakage that the 3-level input can tolerate from an external driver. see the family reference manual. in most designs, an external resistor voltage divider is recommended. 3. the lvpecl and cmos output formats draw more current than either lvds or cml; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the tqfp devices is limited when they are operated at 3.3 v. w hen there are four enabled lvpecl or cmos outputs, the fifth output must be disabled. when there are five enabled outputs, there can be no more than three outputs that are either lvpecl or cmos.
si5368 6 preliminary rev. 0.41 package thermal resistance junction to ambient ? ja still air ? 40 ? oc/w table 2. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 3.63 v lvcmos input voltage v dig ?0.3 to (v dd + 0.3) v junction temperature t jct ?55 to 150 oc storage temperature range t stg ?55 to 150 oc esd hbm tolerance (100 pf, 1.5 k ? ); all pins except ckin+/ckin? 2 kv esd mm tolerance; all pins except ckin+/ckin? 200 v esd hbm tolerance (100 pf, 1.5 k ? ); ckin+/ckin? 700 v esd mm tolerance; ckin+/ckin? 150 v latch-up tolerance jesd78 compliant note: permanent device damage may occur if the absolute maxi mum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operation se ctions of this data sheet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. table 1. performance specifications (continued) (v dd = 1.8 5%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit notes: 1. for a more comprehensive listing of device specifications , please consult the silicon laboratories any-rate precision clock family reference manual. this document can be downloaded from www.silabs.com/timing (click on documentation) . 2. this is the amount of leakage that the 3-level input can tolerate from an external driver. see the family reference manual. in most designs, an external resistor voltage divider is recommended. 3. the lvpecl and cmos output formats draw more current than either lvds or cml; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipation for the tqfp devices is limited when they are operated at 3.3 v. w hen there are four enabled lvpecl or cmos outputs, the fifth output must be disabled. when there are five enabled outputs, there can be no more than three outputs that are either lvpecl or cmos.
si5368 preliminary rev. 0.41 7 figure 1. typical phase noise plot jitter band jitter, rms brick wall, 100 hz to 100 mhz 1,279 fs sonet_oc48, 12 khz to 20 mhz 315 fs sonet_oc192_a, 20 khz to 80 mhz 335 fs sonet_oc192_b, 4 to 80 mhz 194 fs sonet_oc192_c, 50 khz to 80 mhz 318 fs brick wall, 800 hz to 80 mhz 343 fs 155.52 mhz in, 622.08 mhz out -160 -140 -120 -100 -80 -60 -40 -20 0 100 1000 10000 100000 1000000 10000000 100000000 offset frequency (hz) phase noise (dbc/hz )
si5368 8 preliminary rev. 0.41 figure 2. si5368 typical application circuit (i 2 c control mode) figure 3. si5368 typical application circuit (spi control mode) si5368 ckin1+ ckin1? int_alm cnb lol rst ckout1+ ckout1? vdd gnd ferrite bead system power supply c 10 c 1?9 input clock sources* reset interrupt/alarm output indicator ckinn invalid indicator (n = 1 to 3) pll loss of lock indicator clock outputs cmode control mode (l) ckout4+ ckout4? fs_out+ fs_out? ckin4+ ckin4? assumes differential lvpecl termination (3.3 v) on clock inputs. *note: serial data serial clock sda scl i 2 c interface serial port address a[2:0] 0.1 f 1 f 0.1 f 100 ? 0.1 f + ? 0.1 f 100 ? 0.1 f + ? 0.1 f 100 ? 0.1 f + ? 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v xa xb crystal xa xb ext. refclk 0.1 f option 1: option 2: 0.1 f rate[1:0] rate inc inc dec dec si5368 ckin1+ ckin1? int_alm cnb lol rst ckout1+ ckout1? input clock sources* reset interrupt/alarm output indicator ckinn invalid indicator (n = 1 to 3) pll loss of lock indicator clock outputs cmode control mode (h) ckout4+ ckout4? fs_out+ fs_out? ckin4+ ckin4? 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v spi interface serial data out serial data in sdo sdi serial clock scl slave select ss vdd gnd ferrite bead system power supply c 10 c 1?9 0.1 f 1 f assumes differential lvpecl termination (3.3 v) on clock inputs. *note: 0.1 f 100 ? 0.1 f + ? 0.1 f 100 ? 0.1 f + ? 0.1 f 100 ? 0.1 f + ? xa xb crystal xa xb ext. refclk 0.1 f option 1: option 2: 0.1 f rate[1:0] rate inc inc dec dec
si5368 preliminary rev. 0.41 9 1. functional description the si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. the si5368 accepts four clock inputs ranging from 2 khz to 710 mhz and generates five clock outputs ranging from 2 khz to 945 mhz and select frequencies to 1.4 ghz. the device provides virtually any frequency translation combination across this operating range. independent dividers are available for every input clock and output clock, so the si5368 can accept input clocks at different frequencies and it can generate output clocks at different frequencies. the si5368 input clock frequency and clock multiplication ratio are programmable through an i 2 c or spi interface. optionally, the fifth clock output can be configured as a 2 to 512 khz sonet/sdh frame synchronization output that is phase aligned with one of the high-speed output clocks. silicon laboratories offers a pc-based software utility, dspll sim , that can be used to determine the optimum pll divider settings for a given input frequency/clock multiplication ratio combination that minimizes phase noise and power consumption. this utility can be downloaded from http://www.silabs.com/timing (click on documentation) . the si5368 is based on silicon laboratories' 3rd- generation dspll ? technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the si5368 pll loop bandwidth is digitally programmable and supports a range from 60 hz to 8.4 khz. the dspll sim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. the si5368 supports hitless switching between input clocks in compliance with gr-253-core and gr-1244- core that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (<200 ps typ). manual, automatic revertive and non-revertive input clock switching options are available. the si5368 monitors the four input clocks for loss-of- signal and provides a los alarm when it detects missing pulses on any of the four input clocks. the device monitors the lock status of the pll. the lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. the si5368 monitors the frequency of ckin1, ckin2, ckin3, and ckin4 with respect to a selected reference frequency and generates a frequency offset alarm (fos) if the threshold is exceeded. this fos feature is available for sonet applications in which both the monitored frequency on ckin1, ckin3, and ckin4 and the reference frequency are integer multiples of 19.44 mhz. both stratum 3/3e and sonet minimum clock (smc) fos thresholds are supported. the si5368 provides a digital hold capability that allows the device to continue generation of a stable output clock when the selected input reference is lost. during digital hold, the dspll generates an output frequency based on a historical average that existed a fixed amount of time before the error event occurred, eliminating the effects of phase and frequency transients that may occur immediately preceding digital hold. fine phase adjustment is available and is set using the flat register bits. the nominal range and resolution of the flat[14:0] latency adjustment word are: 110 ps and 3 ps, respectively. the si5368 has five differential clock outputs. the electrical format of the clock outputs is programmable to support lvpecl, lvds, cml, or cmos loads. if not required, unused clock outputs can be powered down to minimize power consumption. the phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. in addition, the phase of one output clock may be adjusted in relation to the phase of the other output clock. the resolution varies from 800 ps to 2.2 ns depending on the pll divider settings. consult the dspll sim configuration software to determine the phase offset resolution for a given input clock/clock multiplication ratio combination. for system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal dspll. the device is powered by a single 1.8 or 2.5 v supply. 1.1. external reference an external, 38.88 mhz clock or a low-cost 114.285 mhz 3rd overtone crystal is used as part of a fixed-frequency oscillator within the dspll. this external reference is required for the device to operate. silicon laboratories recommends using a high-quality crystal. specific recommendations may be found in the family reference manual. an external clock from a high-quality ocxo or tcxo can also be used as a reference for the device. in digital hold, the dspll remains locked to this external reference. any changes in the frequency of this reference when the dspll is in digital hold, will be tracked by the output of the device. note that crystals can have temperature sensitivities. 1.2. further documentation consult the silicon laborato ries any-rate precision clock family reference ma nual (frm) for detailed information about the si5368. additional design support is available from silicon laboratories through your distributor. silicon laboratories has developed a pc-based software utility called dspll sim to simplify device configuration, including frequency planning and loop bandwidth selection. the frm and this utility can be downloaded from http://www.silabs.com/timing ; click on documentation.
si5368 10 preliminary rev. 0.41 2. pin descriptions: si5368 table 3. si5368 pin descriptions pin # pin name i/o signal level description 1, 2, 4, 20, 22, 23, 24, 25, 37, 47, 48, 50, 51, 52, 53, 56, 66, 67, 72, 73, 74, 75, 80, 85, 95 nc no connect. these pins must be left unc onnected for normal operation. 3 rst ilvcmos external reset. active low input that performs external hardware reset of device. resets all inte rnal logic to a known state and forces the device registers to their default value. clock outputs are dis- abled during reset. the part must be programmed after a reset or power-on to get a clock ou tput. see family reference man- ual for details. this pin has a weak pull-up. note: internal register names are indicated by underlined italics, e.g. int_pin . see si5368 register map. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45444342 41 40 39 38 37 36 35 3433 31 3029 2827 26 32 64 61 62 63 57 58 59 60 50 51 52 53 54 55 56 49 nc fs_align c2b gnd c1b c3b xa xb vdd ckin3+ ckin3? rate0 ckin1+ ckin1? ckin2+ ckin2? rate1 ckin4+ ckin4? lol sdi nc nc a1 a0 gnd vdd sda_sdo scl c2a c1a cs1_c4a nc dec inc ckout3+ cmode ckout3? nc ckout1+ ckout1? fs_out+ fs_out? vdd ckout2+ ckout2? nc ckout4+ nc ckout4? 17 20 19 18 24 23 22 21 25 74 73 72 71 70 69 68 67 66 65 75 100 89 9091 929394 95 9697 98 99 7677 78 79 8081 828384 85 8687 88 rst nc nc vdd gnd cs0_c3a gnd gnd gnd nc nc nc gnd vdd gnd gnd gnd gnd gnd gnd gnd gnd vdd a2_ss gnd nc vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd nc nc nc nc nc vdd nc nc nc nc nc nc nc si5368 gnd pad int_alm
si5368 preliminary rev. 0.41 11 5, 6, 15, 27, 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100 v dd vdd supply v dd . the device operates from a 1.8, 2.5, or 3.3 v supply. bypass capacitors should be as sociated with the following v dd pins: pins bypass cap 5, 6 0.1 f 15 0.1 f 27 0.1 f 62, 63 0.1 f 76, 79 1.0 f 81, 84 0.1 f 86, 89 0.1 f 91, 94 0.1 f 96, 99, 100 0.1 f 7, 8, 14, 18, 19, 26, 28, 31, 33, 36, 38, 41, 43, 46, 64, 65 gnd gnd supply ground. this pin must be connected to system ground. minimize the ground path impedance for optimal performance. 9c1bol vcmos ckin1 invalid indicator. this pin performs the ck1_bad function if ck1_bad_pin =1 and is tristated if ck1_bad_pin = 0. active polarity is con- trolled by ck_bad_pol . 0 = no alarm on ckin1. 1 = alarm on ckin1. 10 c2b o lvcmos ckin2 invalid indicator. this pin performs the ck2_bad function if ck2_bad_pin =1 and is tristated if ck2_bad_pin = 0. active polarity is con- trolled by ck_bad_pol . 0 = no alarm on ckin2. 1 = alarm on ckin2. 11 c3b o lvcmos ckin3 invalid indicator. this pin performs the ck3_bad function if ck3_bad_pin =1 and is tristated if ck3_bad_pin = 0. active polarity is con- trolled by ck_bad_pol . 0 = no alarm on ckin3. 1 = alarm on ckin3. 12 int_alm o lvcmos interrupt/alarm output indicator. this pin functions as a maskabl e interrupt output with active polarity controlled by the int_pol register bit. the int output function can be turned off by setting int_pin = 0. if the alr- mout function is desired instead on this pin, set alrmout_pin = 1 and int_pin =0. 0= alrmout not active. 1= alrmout active. the active polarity is controlled by ck_bad_pol . if no function is selected, the pin tristates. table 3. si5368 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g. int_pin . see si5368 register map.
si5368 12 preliminary rev. 0.41 13 57 cs0_c3a cs1_c4a i/o lvcmos input clock select/ckin3 or ckin4 active clock indicator. input : if manual clock select ion is chosen, and if cksel_pin = 1, the cksel pins control clock selection and the cksel_reg bits are ignored. if cksel_pin =0, the cksel_reg register bits control this function and these inputs tristate. if configured as inputs, these pins must not float. output: if auto clock selection is enabled, then they serve as the ckin_n active clock indicator. 0 = ckin3 (ckin4) is not the active input clock 1 = ckin3 (ckin4) is currently the active input to the pll the ckn_actv_reg bit always reflects the active clock status for ckin_n. if ckn_actv_pin = 1, this status will also be reflected on the cna pin with active polarity controlled by the ck_actv_pol bit. if ckn_actv_pin = 0, this output tristates. 16 17 xa xb ianalog external crystal or reference clock. external crystal should be connected to these pins to use inter- nal oscillator ba sed reference. refer to family reference man- ual for interfacing to an external reference. external reference must be from a high-quality cl ock source (tcxo, ocxo). fre- quency of crystal or external clock is set by the rate pins. 21 fs_align i lvcmos fsync alignment control. if fsync_align_pin = 1 and ck_config = 1, a logic high on this pin causes the fs_out phase to be realigned to the ris- ing edge of the currently active input sync (ckin_3 or ckin_4). if fsync_align_pin = 0, this pin is ignored and the fsync_align_reg bit performs this function. 0 = no realignment. 1 = realign. this pin has a weak pull-down. 29 30 ckin4+ ckin4? imulti clock input 4. differential clock input. this inpu t can also be driven with a sin- gle-ended signal. ckin4 serves as the frame sync input associ- ated with the ckin2 clock when ck_config_reg =1. 32 42 rate0 rate1 i 3-level external crystal or reference clock rate. three level inputs that select the type and rate of external crys- tal or reference clock to be applied to the xa/xb port. refer to the family reference manual for settings. these pins have both a weak pull-up and a weak pull-down; they default to m. table 3. si5368 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g. int_pin . see si5368 register map. cs[1:0] active input clock 00 ckin1 01 ckin2 10 ckin3 11 ckin4
si5368 preliminary rev. 0.41 13 34 35 ckin2+ ckin2? imulti clock input 2. differential input clock. this inpu t can also be driven with a sin- gle-ended signal. 39 40 ckin3+ ckin3? imulti clock input 3. differential clock input. this inpu t can also be driven with a sin- gle-ended signal. ckin3 serves as the frame sync input associ- ated with the ckin1 clock when ck_config_reg =1. 44 45 ckin1+ ckin1? imulti clock input 1. differential clock input. this inpu t can also be driven with a sin- gle-ended signal. 49 lol o lvcmos pll loss of lock indicator. this pin functions as the active high pll loss of lock indicator if the lol_pin register bit is set to one. 0 = pll locked. 1 = pll unlocked. if lol_pin = 0, this pin will tristate. active polarity is controlled by the lol_pol bit. the pll lock status will always be reflected in the lol_int read only register bit. 54 dec i lvcmos coarse latency decrement. a pulse on this pin decreases the input to output device latency by 1/fosc (approximately 200 ps). detailed operations and tim- ing characteristics for this pin may be found in the any-rate precision clock family reference manual. there is no limit on the range of latency adjustment by this method. pin control is enabled by setting incdec_pin = 1 (default). if incdec_pin = 0, this pin is ignored and coarse output latency is controlled via the clat register. if both inc and dec are tied high, phase buildout is disabled and the device maintains a fixed-phase relationship between the selected input clock and the output clock during an input clock switch. detailed operations and timing characteristics for these pins may be found in the any-rate precision clock fam- ily reference manual. this pin has a weak pull-down. table 3. si5368 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g. int_pin . see si5368 register map.
si5368 14 preliminary rev. 0.41 55 inc i lvcmos coarse latency increment. a pulse on this pin increases the input to output device latency by 1/fosc (approximately 200 ps). detailed operations, restric- tions, and timing characteristics for this pin may be found in the any-rate precision clock family reference manual. there is no limit on the range of laten cy adjustment by th is method. pin control is enabled by setting incdec_pin = 1 (default). note: inc does not increase latency if ni_hs = 4. if incdec_pin = 0, this pin is ignored and coarse output latency is controlled via the clat register. if both inc and dec are tied high, phase buildout is disabled and the device maintains a fixed-phase relationship between the selected input clock and the output clock during an input clock switch. detailed operations and timing characteristics for these pins may be found in the any-rate precision clock fam- ily reference manual. this pin has a weak pull-down. 58 c1a o lvcmos ckin1 active cl ock indicator. this pin serves as the ckin1 active clock indicator. the ck1_actv_reg bit always reflects the active clock status for ckin1. if ck1_actv_pin = 1, this status will also be reflected on the c1a pin with active polarity controlled by the ck_actv_pol bit. if ck1_actv_pin = 0, this output tristates. 59 c2a o lvcmos ckin2 active cl ock indicator. this pin serves as the ckin2 active clock indicator. the ck2_actv_reg bit always reflects the active clock status for ckin_2. if ck2_actv_pin = 1, this status will also be reflected on the c2a pin with active polarity controlled by the ck_actv_pol bit. if ck2_actv_pin = 0, this output tristates. 60 scl i lvcmos serial clock. this pin functions as the serial port clock input for both spi and i 2 c modes. this pin has a weak pull-down. 61 sda_sdo i/o lvcmos serial data. in i 2 c microprocessor control mode (cmode = 0), this pin func- tions as the bidirectional serial data port. in spi microprocessor control mode (cmode = 1), this pi n functions as the serial data output. 68 69 a0 a1 ilvcmos serial port address. in i 2 c microprocessor control mode (cmode = 0), these pins function as hardware controlled address bits. the i 2 c address is 1101 [a2] [a1] [a0]. in spi microprocessor control mode (cmode = 1), these pins are ignored. this pin has a weak pull-down. 70 a2_ss ilvcmos serial port addr ess/slave select . in i 2 c microprocessor control mode (cmode = 0), this pin func- tions as a hardware controlled address bit [a2]. in spi microprocessor control mode (cmode = 1), this pin functions as the slave select input. this pin has a weak pull-down. table 3. si5368 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g. int_pin . see si5368 register map.
si5368 preliminary rev. 0.41 15 71 sdi i lvcmos serial data in. in spi microprocessor control mode (cmode = 1), this pin functions as the se rial data input. in i 2 c microprocessor control mode (cmode = 0), this pin is ignored. this pin has a weak pull-down. 77 78 ckout3+ ckout3? omulti clock output 3. differential clock output. output signal format is selected by sfout3_reg register bits. output is differential for lvpecl, lvds, and cml compatible modes. for cmos format, both output pins drive identical single-ended clock outputs. 82 83 ckout1? ckout1+ omulti clock output 1. differential clock output. output signal format is selected by sfout1_reg register bits. output is differential for lvpecl, lvds, and cml compatible modes. for cmos format, both output pins drive identical single-ended clock outputs. 87 88 fs_out? fs_out+ omulti frame sync output. differential frame sync output or fifth high-speed clock output. output signal format is selected by sfout_fsync_reg reg- ister bits. output is different ial for lvpecl, lvds, and cml compatible modes. for cmos form at, both output pins drive identical single-ended clock out puts. duty cycle and active polarity are controlled by fsync_pw and fsync_pol bits, respectively. detailed operations and timing characteristics for these pins may be found in the any-rate precision clock fam- ily reference manual. 90 cmode i lvcmos control mode. selects i 2 c or spi control mode for the device. 0=i 2 c control mode. 1 = spi control mode. this pin must be tied high or low. 92 93 ckout2+ ckout2? omulti clock output 2. differential clock output. output signal format is selected by sfout2_reg register bits. output is differential for lvpecl, lvds, and cml compatible modes. for cmos format, both output pins drive identical single-ended clock outputs. 97 98 ckout4? ckout4+ omulti clock output 4. differential clock output. output signal format is selected by sfout4_reg register bits. output is differential for lvpecl, lvds, and cml compatible modes. for cmos format, both output pins drive identical single-ended clock outputs. gnd pad gnd pad gnd supply ground pad. the ground pad must provide a low thermal and electrical impedance to a ground plane. table 3. si5368 pin descriptions (continued) pin # pin name i/o signal level description note: internal register names are indicated by underlined italics, e.g. int_pin . see si5368 register map.
si5368 16 preliminary rev. 0.41 3. register map all register bits that are not defined in this map shou ld always be written with the specified reset values. the writing to these bits of values other than the specif ied reset values may result in undefined device behavior. registers not listed, such as register 64, should never be written to. register d7 d6 d5 d4 d3 d2 d1 d0 0 free_run ckout_ always_ on ck_config _reg bypass_ reg 1 ck_prior4 [1:0] ck_pr ior3 [1:0] ck_prior2 [1:0] ck_prior1 [1:0] 2 bwsel_reg [3:0] 3 cksel_reg [1:0] dhold sq_ical 4 autosel_reg [1:0] hist_del [4:0] 5 icmos [1:0] sfout2_reg [2:0] sfout1_reg [2:0] 6 sleep sfout4_reg [2:0] sfout3_reg [2:0] 7 sfout5_reg [2:0] fosrefsel [2:0] 8 hlog_4 [1:0] hlog_3 [1:0] h log_2 [1:0] hlog_1 [1:0] 9 hist_avg [4:0] hlog_5 [1:0] 10 dsbl5_ reg dsbl4_ reg dsbl3_ reg dsbl2_ reg dsbl1_ reg 11 align_thr [2:0] pd_ck4 pd_ck3 pd_ck2 pd_ck1 12 fpw_valid fsync_ align_reg fsync_ align_ mode fsync_ swtch_ reg fskew_ valid fsync_ skew [16:16] fsync_pw [9:8] 13 fsync_pw [7:0] 14 fsync_skew [15:8] 15 fsync_skew [7:0] 16 clat [7:0] 17 flat_valid flat [14:8] 18 flat [7:0] 19 fos_en fos_thr [1:0] val time [1:0] lockt [2:0] 20 alrmout_ pin ck3_bad_ pin ck2_bad_ pin ck1_bad_ pin lol_pin int_pin 21 incdec_ pin fsync_ align_pin ck4_actv_ pin ck3_actv_ pin ck2_actv_ pin ck1_actv_ pin cksel_pin 22 fsync_ align_pol fsync_ pol fsyncout _pol ck_actv_ pol ck_bad_ pol lol_pol int_pol
si5368 preliminary rev. 0.41 17 23 los4_msk los3_msk los2_msk los1_msk losx_msk 24 align_msk fos4_msk fos3_msk fos2_msk fos1_msk lol_msk 25 n1_hs [2:0] nc1_ls [19:16] 26 nc1_ls [15:8] 27 nc1_ls [7:0] 28 nc2_ls [19:16] 29 nc2_ls [15:8] 30 nc2_ls [7:0] 31 nc3_ls [19:16] 32 nc3_ls [15:8] 33 nc3_ls [7:0] 34 nc4_ls [19:16] 35 nc4_ls [15:8] 36 nc4_ls [7:0] 37 nc5_ls [19:16] 38 nc5_ls [15:8] 39 nc5_ls [7:0] 40 n2_hs [2:0] n2_ls [19:16] 41 n2_ls [15:8] 42 n2_ls [7:0] 43 n31_ [18:16] 44 n31_[15:8] 45 n31_ [7:0] 46 n32_ [18:16] 47 n31_ [15:8] 48 n32_[7:0] 49 n33_[18:16] 50 n33_[15:8] 51 n33_[7:0] 52 n34_[18:16] 53 n34_[15:8] register d7 d6 d5 d4 d3 d2 d1 d0
si5368 18 preliminary rev. 0.41 54 n34_[7:0] 55 clkin2rate_[2:0] clkin1rate[2:0] 56 clkin4rate_[2:0] clkin3rate[2:0] 128 ck4_actv_ reg ck3_actv_ reg ck2_actv_ reg ck1_actv_ reg 129 los4_int los3_int los2 _int los1_int losx_int 130 clat- progress dighold- valid align_int fos4_int fos3_int fos2_int fos1_int lol_int 131 los4_flg los3_flg los2_flg los1_flg losx_flg 132 align_flg fos4_flg fos3_flg fos2_flg fos1_flg lol_flg aign_err [8:8] 133 align_err [7:0] 134 partnum_ro [11:4] 135 partnum_ro [3:0] revid_ro [3:0] 136 rst_reg ical grade_ro [1:0] 138 los4_en [1:1] los3_en [1:1] los2_en [1:1] los1_en [1:1] 139 los4_en [0:0] los3_en [0:0] los2_en [0:0] los1_en [0:0] fos4_en fos3_en fos2_en fos1_en 140 independentskew1 [7:0] 141 independentskew2 [7:0] 142 independentskew3 [7:0] 143 independentskew4 [7:0] 144 independentskew5 [7:0] 185 nvm_revid [7:0] register d7 d6 d5 d4 d3 d2 d1 d0
si5368 preliminary rev. 0.41 19 4. register descriptions reset value = 0001 0100 register 0. bitd7d6d5d4d3d2d1d0 name free_ run ckout_ always_ on ck_ config_ reg bypass_ reg type rr/wr/wrr/wrr/wr bit name function 7 reserved reserved. 6free_run free run. internal to the device, route xa/ xb to ckin2. this allows the device to lock to its external reference. 0: disable free run 1: enable 5ckout_ always_on ckout always on. this will bypass the sq_ical func tion. output will be availabl e even if sq_ical is on and ical is not complete or successful. see table 4. 0: squelch output until pa rt is calibrated (ical). 1: provide an output. note: the frequency ma y be significantly off until the part is calibrated. 4 reserved reserved. 3 ck_config_ reg ck_config_reg. this bit controls the input clock configuratio n for either normal clkin function or fsync operation. whenever ck_config_reg = 1, fsync_align_mode mu st not be set to 1. 0: ckin_1, 2, 3, 4 inputs do not have a synch ronized relationship. clkout5 is an inde- pendent output. there is no fsyncout. 1: ckin_1, 3 and ckin_2, 4 clock/fsync pair s. ckout5 is configured as the fsync output. 2 reserved reserved. 1 bypass_ reg bypass register. this bit enables or disables the pll bypass mode. use is only valid when the part is in digital hold or before the first ical. 0: normal operation 1: bypass mode. selected input clock is c onnected to ckout buffers, bypassing pll. 0 reserved reserved.
si5368 20 preliminary rev. 0.41 reset value = 1110 0100 register 1. bitd7d6d5d4d3d2d1d0 name ck_prior4 [1:0] ck_prior3 [1:0] c k_prior2 [1:0] ck_prior1 [1:0] type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7:6 ck_prior4 [1:0] selects which of the input clocks will be 4th priority in the autose lection state machine. 00: ckin0 is 4th priority 01: ckin1 is 4th priority 10: ckin2 is 4th priority 11: ckin3 is 4th priority 5:4 ck_prior3 [1:0] selects which of the input clocks will be 3rd priority in the autoselection state machine. 00: ckin0 is 3rd priority 01: ckin1 is 3rd priority 10: ckin2 is 3rd priority 11: ckin3 is 3rd priority 3:2 ck_prior2 [1:0] ck_prior 2. selects which of the input clocks will be 2nd priority in the autose lection state machine. 00: ckin1 is 2nd priority 01: ckin2 is 2nd priority 10: ckin3 is 2nd priority 11: ckin4 is 2nd priority 1:0 ck_prior1 [1:0] ck_prior 1. selects which of the input clocks will be 1st priority in the autose lection state machine. 00: ckin0 is 1st priority 01: ckin1 is 1st priority 10: ckin2 is 1st priority 11: ckin3 is 1st priority
si5368 preliminary rev. 0.41 21 reset value = 0100 0010 reset value = 0000 0101 register 2. bitd7d6d5d4d3d2d1d0 name bwsel_reg [3:0] reserved type r/w r bit name function 7:4 bwsel_reg [3:0] bwsel_reg. selects nominal f3db bandwidth for pll. see the dspllsim for settings. after bwsel_reg is written with a new value, an ical is required for the change to take effect. 3:0 reserved reserved. register 3. bitd7d6d5d4d3d2d1d0 name cksel_reg [1:0] dho ld sq_ical reserved type r/w r/w r/w r bit name function 7:6 cksel_reg [1:0] cksel_reg. if the device is operating in manua l register-based clock selection mode (autosel_reg = 00), and cksel_pin = 0, then these bits select which input clock will be the active input clock. if cksel_pin = 1, the cksel[1:0] input pins continue to control clock selection and ckse l_reg is of no consequence. 00: ckin_1 selected. 01: ckin_2 selected. 10: ckin_3 selected. 11: ckin_4 selected. 5 dhold dhold. forces the part into digital hold. this bit overrides all other manual and automatic clock selection controls. 0: normal operation. 1: force digital hold mode. over rides all other settings and ignores the quality of all of the input clocks.
si5368 22 preliminary rev. 0.41 reset value = 0001 0010 reset value = 1110 1101 4 sq_ical sq_ical. this bit determines if the output clocks will remain enabled or be squelched (disabled) during an internal calibration. see table 4. 0: output clocks enabled during ical. 1: output clocks disabled during ical. 3:0 reserved reserved. register 4. bitd7d6d5d4d3d2d1d0 name autosel_reg [1:0] res erved hist_del [4:0] type r/w r r/w bit name function 7:6 autosel_ reg [1:0] autosel_reg [1:0]. selects method of input clock selection to be used. 00: manual (either register or pin controlled. see cksel_pin). 01: automatic non-revertive 10: automatic revertive 11: reserved 5 reserved reserved. 4:0 hist_del [4:0] hist_del [4:0]. selects amount of delay to be used in generating the history information mhist, the value of m used dur ing digital hold. register 5. bitd7d6d5d4d3d2d1d0 name icmos [1:0] sfout2_reg [2:0] sfout1_reg [2:0] type r/w r/w r/w
si5368 preliminary rev. 0.41 23 bit name function 7:6 icmos [1:0] icmos [1:0]. when the output buffer is set to cmos mode, these bits determine the output buffer drive strength. the first number below refers to 3.3 v operation; the second to 1.8 v operation. these values assume ckout+ is tied to ckout-. 00: 8ma/2ma 01: 16ma/4ma 10: 24ma/6ma 11: 32ma (3.3 v operation)/8ma (1.8 v operation) 5:3 sfout2_ reg [2:0] sfout2_reg [2:0] controls output signal format and disable fo r ckout2 output buffer. the lvpecl and cmos output formats draw more current than either lvds or cml; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipa- tion for the tqfp devices is limited when they are operated at 3.3 v. when there are four enabled lvpecl or cmos outputs, the fifth ou tput must be disabled. when there are five enabled ou tputs, there can be no more than three outputs that are either lvpecl or cmos. 000: reserved 001: disable 010: cmos 011: low swing lvds 100: reserved 101: lvpecl 110: cml 111: lvds 2:0 sfout1_ reg [2:0] sfout1_reg [2:0] controls output signal format and disable fo r ckout1 output buffer. the lvpecl and cmos output formats draw more current than either lvds or cml; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipa- tion for the tqfp devices is limited when they are operated at 3.3 v. when there are four enabled lvpecl or cmos outputs, the fifth ou tput must be disabled. when there are five enabled ou tputs, there can be no more than three outputs that are either lvpecl or cmos. 000: reserved 001: disable 010: cmos 011: low swing lvds 100: reserved 101: lvpecl 110: cml 111: lvds
si5368 24 preliminary rev. 0.41 reset value = 0010 1100 register 6. bitd7d6d5d4d3d2d1d0 name reserved sleep sfout4_reg [2:0] sfout3_reg [2:0] type rr/w r/w r/w bit name function 7 reserved reserved. 6sleep sleep. in sleep mode, the clock outputs are disabled and the maximum amount of internal circuitry is powered down to reduce powe r dissipation and noise generation. this bit overrides the sfoutn_reg[2:0] output signal format settings. note: output skew is random coming out of sleep until a successful ical is completed. 0: normal operation 1: sleep mode 5:3 sfout4_ reg [2:0] sfout4_reg [2:0]. controls output signal format and disable fo r ckout4 output buffer. the lvpecl and cmos output formats draw more current than either lvds or cml; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipa- tion for the tqfp devices is limited when they are operated at 3.3 v. when there are four enabled lvpecl or cmos outputs, the fifth ou tput must be disabled. when there are five enabled ou tputs, there can be no more than three outputs that are either lvpecl or cmos. 000: reserved 001: disable 010: cmos 011: low swing lvds 100: reserved 101: lvpecl 110: cml 111: lvds
si5368 preliminary rev. 0.41 25 reset value = 0010 1010 2:0 sfout3_ reg [2:0] sfout3_reg [2:0]. controls output signal format and disable fo r ckout3 output buffer. the lvpecl and cmos output formats draw more current than either lvds or cml; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipa- tion for the tqfp devices is limited when they are operated at 3.3 v. when there are four enabled lvpecl or cmos outputs, the fifth ou tput must be disabled. when there are five enabled ou tputs, there can be no more than three outputs that are either lvpecl or cmos. 000: reserved 001: disable 010: cmos 011: low swing lvds 100: reserved 101: lvpecl 110: cml 111: lvds register 7. bitd7d6d5d4d3d2d1d0 name reserved sfout5_reg [2 :0] fosrefsel [2:0] type rr/w r/w bit name function 7:6 reserved. reserved.
si5368 26 preliminary rev. 0.41 reset value = 0000 0000 5:3 sfout5_ reg [2:0] sfout5_reg [2:0] controls output signal format and disable fo r ckout5 output buffer. the lvpecl and cmos output formats draw more current than either lvds or cml; however, there are restrictions in the allowed output format pin settings so that the maximum power dissipa- tion for the tqfp devices is limited when they are operated at 3.3 v. when there are four enabled lvpecl or cmos outputs, the fifth ou tput must be disabled. when there are five enabled ou tputs, there can be no more than three outputs that are either lvpecl or cmos. 000: reserved 001: disable 010: cmos 011: low swing lvds 100: reserved 101: lvpecl 110: cml 111: lvds 2:0 fosrefsel [2:0] fosrefsel [2:0]. selects which input clock is used as the reference frequency fo r frequency off-set (fos) alarms. 000: xa/xb (external reference) 001: ckin1 010: ckin2 011: ckin3 100: ckin4 101: reserved 110: reserved 111: reserved register 8. bitd7d6d5d4d3d2d1d0 name hlog_4[1:0] hlog_3[1:0] hlog_2[1:0] hlog_1[1:0] type r/w r/w r/w r/w bit name function 7:6 hlog_4 [1:0] hlog_4 [1:0]. 00: normal operation 01: holds ckout4 output at st atic logic 0. entrance and ex it from this state will occur without glitches or runt pulses. 10: holds ckout4 output at st atic logic 1. entrance and ex it from this state will occur without glitches or runt pulses. 11: reserved
si5368 preliminary rev. 0.41 27 reset value = 1100 0000 5:4 hlog_3 [1:0] hlog_3 [1:0]. 00: normal operation 01: holds ckout3 output at st atic logic 0. entrance and ex it from this state will occur without glitches or runt pulses. 10: holds ckout3 output at st atic logic 1. entrance and ex it from this state will occur without glitches or runt pulses. 11: reserved. 3:2 hlog_2 [1:0] hlog_2 [1:0]. 00: normal operation 01: holds ckout2 output at st atic logic 0. entrance and ex it from this state will occur without glitches or runt pulses. 10: holds ckout2 output at st atic logic 1. entrance and ex it from this state will occur without glitches or runt pulses. 11: reserved. 1:0 hlog_1 [1:0] hlog_1 [1:0]. 00: normal operation 01: holds ckout1 output at st atic logic 0. entrance and ex it from this state will occur without glitches or runt pulses. 10: holds ckout1 output at st atic logic 1. entrance and ex it from this state will occur without glitches or runt pulses. 11: reserved register 9. bitd7d6d5d4d3d2d1d0 name hist_avg [4:0] reserved hlog_5 [1:0] type r/w r r/w bit name function 7:3 hist_avg [4:0] hist_avg [4:0]. selects amount of averaging time to be used in generating mhist, the value of m used during digital hold. see family reference manual for settings. 2 reserved reserved. 1:0 hlog_5 [1:0] hlog_5 [1:0]. 00: normal operation 01: holds ckout5 output at st atic logic 0. entrance and ex it from this state will occur without glitches or runt pulses. 10: holds ckout5 output at static logic 1. entrance and exit from this state will occur without glitches or runt pulses. 11: reserved
si5368 28 preliminary rev. 0.41 reset value = 0000 0000 register 10. bitd7d6d5d4d3d2d1d0 name reserved dsbl5_ reg reserved dsbl4_ reg dsbl3_ reg dsbl2_ reg dsbl1_ reg type rr/wrr/wr/wrr bit name function 7:6 reserved reserved. 5dsbl5_ reg dsbl5_reg. this bit controls the powerdown and disable of the ckout5 output buffer. if disable mode is selected, the nc5_ls output divider is also powered down. 0: ckout5 enabled. 1: ckout5 disabled. 4 reserved reserved. 3dsbl4_ reg dsbl4_reg. this bit controls the powerdown and disable of the ckout4 output buffer. if disable mode is selected, the nc4 output divider is also powered down. 0'b=ckout4 enabled 1'b=ckout4 disabled 2 dsbl3_reg dsbl3_reg. this bit controls the powerdown and disable of the ckout3 output buffer. if disable mode is selected, the nc3 output divider is also powered down. 0: ckout3 enabled 1: ckout3 disabled 1 dsbl2_reg dsbl2_reg. this bit controls the powerdown and disable of the ckout2 output buffer. if disable mode is selected, the nc2 output divider is also powered down. 0: ckout2 enabled 1: ckout2 disabled 0 dsbl1_reg dsbl1_reg. this bit controls the powerdown and disable of the ckout1 output buffer. if disable mode is selected, the nc1 output divider is also powered down. 0: ckout1 enabled 1: ckout1 disabled
si5368 preliminary rev. 0.41 29 reset value = 0100 0000 register 11. bitd7d6d5d4d3d2d1d0 name align_thr [2:0] reserved pd_ck4 pd_ck3 pd_ck2 pd_ck1 type r/w r/w r/w r r/w r/w r/w r/w bit name function 7:5 align_thr [2:0] align_thr [2:0]. these bits control the threshold for the alignment error alarm. input to output sync phase skews that deviate more than the alignment threshold from the ideal value (set by fsync_skew[16:0]) in either the leading or lagging direction trigger the alignmenta- larm. value is in units of tclkout2. 000: 4 001: 8 010: 16 011: 32 100: 48 101: 64 110: 96 111: 128 4 reserved reserved. 3pd_ck4 pd_ck4. this bit controls the powerdown of the ckin4 input buffer. 0: ckin4 enabled 1: ckin4 disabled 2pd_ck3 pd_ck3. this bit controls the powerdown of the ckin3 input buffer. 0: ckin3 enabled 1: ckin3 disabled 1pd_ck2 pd_ck2. this bit controls the powerdown of the ckin2 input buffer. 0: ckin2 enabled 1: ckin2 disabled 0pd_ck1 pd_ck1. this bit controls the powerdown of the ckin1 input buffer. 0: ckin1 enabled 1: ckin1 disabled
si5368 30 preliminary rev. 0.41 reset value = 1000 1000 register 12. bitd7d6d5d4d3d2d1d0 name fpw_ valid fsync_ align_ reg fsync_ align_ mode fsync_ swtch_ reg fskew_ valid fsync_ skew [16:16] fsync_pw [9:8] type r/w bit name function 7 fpw_valid fpw_valid. when in frame sync mode (ck_config_reg=1), befor e writing either a new fsync_pw[9:0] or nc5_ls [19:0] value, this bit must be set to zero. this causes the existing fsync_pw [9:0] or nc5_ls[19:0] value to be held by the internal state machine for use while the new values are wr itten. once the new fsync_pw [9:0] or nc5_ls [19:0] values are completely written, set fpw_valid = 1 to enable their use. 0: memorize existing fsync_pw[9:0] and nc5_ls [19:0] values and ignore intermediate register values during writ e of new fsync_pw [9:0] and nc5_ls [19:0] values. 1: use fsync_pw[9:0] value directly from registers 6 fsync_ align_reg fsync_align_reg. if fsync_align_pin=0, this bit controls re alignment of fsyncout to the active sync input (ckin_3 or ckin_4). if fsync_alig n_pin=1, the fsync_align pin controls this function. 0: no realignment 1: active 5 fsync_ align_ mode fsync_align_mode. this bit must be set to 1 when in fr ame sync mode (when ck_config_reg = 1). 4 fsync_ swtch_reg fsync_swtch_reg. enables or disables the use of the ckin3 and ckin4 loss-of-signal indi cators as inputs to the automatic clock selection state machine fo r the clock configuration mode supporting frame sync switching (ck_conf ig=1 or ck_config_reg=1). 0: ckin3 and ckin4 status not used in clock selection 1: ckin3 and ckin4 status used in clock selection 3 fskew_ valid fskew_valid. before writing a new fsync_skew[16:0] value, this bit must be set to zero, which causes the existing fsync_skew[16:0] valu e to be held internally by the skew alignment state machine for use while the new value is being written. once the new fsync_skew[16:0] is comple tely written, set fskew_valid=1 to enable its use. 0: memorize existing fsync_skew[16:0] value and ignore intermediate register values during write of ne w fsync_skew value. 1: use fsync_skew[[16:0] valu e directly from registers.
si5368 preliminary rev. 0.41 31 reset value = 0000 0001 reset value = 0000 0000 2 fsync_ skew [16:0] fsync_skew [16:0]. phase skew control for fsyncout. the resolu tion of the skew control is 1/fckout2. entered values should be less than the fsyncout period. 0 0000 0000 0000 0000=zero phase skew. 0 0000 0000 0000 0001=delay of 1 period of clkout_2. 1 0010 1111 1011 1111=delay of 77,759 periods of ckout2. if ckout2=622.08 mhz and fsyncout=8 khz, this delay equals 125 ms - 1/fckout2 and is the maximum value that should be entered. 1 1111 1111 1111 1111=delay of 131,071 periods of ckout2. 1:0 fsync_ pw [9:0] fsync_pw [9:0]. these bits control the pulse width of the f syncout signal. the resolution of the pulse width control is 1/fckout2. 0000000000=50% duty cycle. 0000000001=1 period of ckout2. 0000000010=2 periods of ckout2. 1111111111=1023 periods of ckout2. register 13. bitd7d6d5d4d3d2d1d0 name fsync_pw [7:0] type r/w bit name function 7:0 fsync_pw [7:0] fsync_pw [7:0]. see register 12. register 14. bitd7d6d5d4d3d2d1d0 name fsync_skew [15:8] type r/w bit name function 7:0 fsync_ skew [15:8] fsync_skew [15:8]. see register 12.
si5368 32 preliminary rev. 0.41 reset value = 0000 0000 reset value = 0000 0000 register 15. bitd7d6d5d4d3d2d1d0 name fsync_skew [7:0] type r/w bit name function 7:0 fsync_ skew [7:0] fsync_skew [7:0]. see register 12. register 16. bitd7d6d5d4d3d2d1d0 name clat [7:0] type r/w bit name function 7:0 clat [7:0] clat [7:0]. with incdec_pin=0, this register sets the phase delay for ckout_n in units of n1_hs/fosc. note: this can take as long as 20 seconds. 01111111: +127 x 1/fosc (2s compliment) 00000000: 0 1000000: ?128 x 1/fosc (2s compliment)
si5368 preliminary rev. 0.41 33 reset value = 1000 0000 reset value = 0000 0000 register 17. bitd7d6d5d4d3d2d1d0 name flat_ valid flat [14:8] type r/w r/w bit name function 7flat_vaild flat_vaild. before writing a new flat[14:0] value, this bit must be set to zero, which causes the existing flat[14:0] value to be held interna lly for use while the new value is being writ- ten. once the new flat[14:0] value is comple tely written, set flat_valid = 1 to enable its use. 0: memorize existing flat[14:0] value and ignore intermediate register values during write of new flat[14:0] value. 1: use flat[14:0] value directly from registers. 6:0 flat [14:0] flat [14:0]. fine resolution control for overall device latency from input clocks to output clocks. positive values increase the skew. see dspllsim for details. register 18. bitd7d6d5d4d3d2d1d0 name flat [7:0] type r/w bit name function 7:0 flat [7:0] flat [7:0]. see register 17.
si5368 34 preliminary rev. 0.41 reset value = 0010 1100 register 19. bitd7d6d5d4d3d2d1d0 name fos_en fos_thr [1:0] valtime [1:0] lockt [2:0] type r/w r/w r/w r/w bit name function 7fos_en fos_en. frequency offset enable globally disables fos. see the individual fos enables (fosx_en, register 139). 00: fos disable 01: fos enabled by fosx_en 6:5 fos_thr [1:0] fos_thr [1:0]. frequency offset at which fos is declared: 00: 11 to 12 ppm stratum 3/3e compliant, with a stratum 3/3e used for refclk. 01: 48 to 49 ppm (smc). 10: 30 ppm sonet minimum clock (smc), with a stratum 3/3e used for refclk. 11: 200 ppm 4:3 valtime [1:0] valtime [1:0]. sets amount of time for input clock to be valid before the associated alarm is removed. 00: 2 ms 01: 100 ms 10: 200 ms 11: 13 seconds 2:0 lockt [2:0] lockt [2:0]. sets retrigger interval for one shot monitori ng phase detector output. one shot is trig- gered by phase slip in dspll. refer to t he family reference manual for more details. 000: 106 ms 001: 53 ms 010: 26.5 ms 011: 13.3 ms 100: 6.6 ms 101: 3.3 ms 110: 1.66 ms 111: 833 us
si5368 preliminary rev. 0.41 35 reset value = 0011 1100 register 20. bitd7d6d5d4d3d2d1d0 name reserved alrmout _pin ck3_bad_ pin ck2_bad_ pin ck1_bad_ pin lol_pin int_pin type r r/wr/wr/wr/wr/wr/w bit name function 7:6 reserved reserved. 5alrmout_ pin alrmout_pin. the alrmout status can be reflected on the alrmout output pin. the request to reflect the interrupt status on this pin (i nt_pin=1) overrides the alrmout_pin request. 0: alrmout not reflected on output pi n. output pin disabled if int_pin=0. 1: alrmout reflected to output pin if in t_pin=0. if int_pin=1, interrupt status appears on the output pin and alrmout is not available on an output pin. 4 ck3_bad_ pin ck3_bad_pin. the ck3_bad status can be reflected on the c3b output pin. 0: c3b output pin tristated 1: c3b status reflected to output pin 3 ck2_bad_ pin ck2_bad_pin. the ck2_bad status can be reflected on the c2b output pin. 0: c2b output pin tristated 1: c2b status reflected to output pin 2 ck1_bad_ pin ck1_bad_pin. the ck1_bad status can be reflected on the c1b output pin. 0: c1b output pin tristated 1: c1b status reflected to output pin 1 lol_pin lol_pin. the lol_int status bit can be reflected on the lol output pin. 0: lol output pin tristated 1: lol_int status reflected to output pin 0int_pin int_pin. reflects the interrupt status on the int output pin. 0: interrupt status not displayed on int outp ut pin. if alrmout_pin = 0, output pin is tristated. 1: interrupt status reflected to output pin. alrmout_pin ignored.
si5368 36 preliminary rev. 0.41 reset value = 1111 1111 register 21. bitd7d6d5d4d3d2d1d0 name incdec_ pin reserved fsync_ align_pin ck4_actv _pin ck3_actv _pin ck2_actv _pin ck1_actv _pin cksel_ pin type r/w force 1 r/w r/w r/w r/w r/w r/w bit name function 7 incdec_pin incdec_pin. determines how coarse skew adjustments can be made. the adjustments can be made via hardware using the inc/dec pins or with software via the clat register. 0: inc and dec inputs ignored; use clat register to adjust skew. 1: inc and dec inputs control out put phase increment/decrement. 6 reserved reserved. 5 fsync_ align_pin fsync_align_pin. realignment of fsyncout can be controlled by the fsync_align input pin instead of the fsync_align_reg register bit. 0: fsync_align pin ignored. fsy nc_align_reg register bit controls fsyncout realignment. 1: fsync_align pin contro ls fsyncout realignment. 4 ck4_actv_ pin ck4_actv_pin. if the cksel[1]/ck4_actv pin is func tioning as the ck4_actv output (see cksel[1]/ck4_actv pin description on ck4_a ctv), the ck4_actv_reg status bit can be reflected to the ck4_actv output pin using the ck4_actv_pin enable function. 0: ck4_actv output pin tristated 1: ck4_actv status reflected to output pin. 3 ck3_actv_ pin ck3_actv_pin. if the cksel[0]/ck3_actv pin is func tioning as the ck3_actv output (see cksel[0]/ck3_actv pin description on ck3_a ctv), the ck3_actv_reg status bit can be reflected to the ck3_actv output pin using the ck3_actv_pin enable function. 0: ck3_actv output pin tristated. 1: ck3_actv status reflected to output pin. 2 ck2_actv_ pin ck2_actv_pin. the ck2_actv_reg status bit can be reflected to the ck2_actv output pin using the ck2_actv_pin enable function. 0: ck2_actv output pin tristated. 1: ck2_actv status reflected to output pin.
si5368 preliminary rev. 0.41 37 reset value = 1101 1111 1 ck1_actv_ pin ck1_actv_pin. the ck1_actv_reg status bit can be reflected to the ck1_actv output pin using the ck1_actv_pin enable function. 0: ck1_actv output pin tristated. 1: ck1_actv status reflected to output pin. 0 cksel_pin cksel_pin. if manual clock selection is being used, clock selection can be controlled via the cksel_reg[1:0] register bits or the cksel[1:0] input pins. 0: cksel pins ignored. ckse l_reg[1:0] register bits control clock selection. 1: cksel[1:0] input pins controls clock selection. register 22. bitd7d6d5 d4 d3d2d1d0 name fsync_ align_ pol fsync_ pol reserved fsyncout _pol ck_actv_ pol ck_bad_ pol lol_pol int_pol type r/w r/w r r/w r/w r/w r/w r/w bit name function 7 fsync_ align_ pol fsync_align_pol. sets the active polarity or edg e for the fsync_align input pin. 0: active low (falling edge). 1: active high (rising edge). 6 fsync_ pol fsync_pol. sets the active polarity and edge for the ckin_3 and ckin_4 inputs when used as frame sync inputs. 0: active low (falling edge). 1: active high (rising edge). 5 reserved reserved. 4 fsyncout_ pol fsyncout_pol. controls active polarity of fsyncout. 0: active low 1: active high 3 ck_actv_ pol ck_actv_pol. sets the active polarity for the ck1_actv, ck2_actv, ck3_actv, and ck4_actv signals when reflected on an output pin. 0: active low 1: active high
si5368 38 preliminary rev. 0.41 reset value = 0001 1111 2 ck_bad_ pol ck_bad_pol. sets the active polarity fo r the c1b, c2b, c3b, and alrmout signals when reflected on output pins. 0: active low 1: active high 1 lol_pol lol_pol. sets the active polarity for the lol status when reflected on an output pin. 0: active low 1: active high 0int_pol int_pol. sets the active polarity for the interrupt status when reflected on the int_alm output pin. 0: active low 1: active high register 23. bitd7d6d5d4d3d2d1d0 name reserved reserved reserved los4_ msk los3_ msk los2_ msk los1_ msk losx_ msk type r r r r/wr/wr/wr/wr/w bit name function 7:5 reserved reserved. 4los4_msk los4_msk. determines if a los on ckin4 (los4_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the los4_flg register. 0: los4 alarm triggers active inte rrupt on int output (if int_pin=1). 1: los4_flg ignored in generating interrupt output. 3los3_msk los3_msk. determines if a los on ckin3 (los3_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the los3_flg register. 0: los3 alarm triggers active inte rrupt on int output (if int_pin=1). 1: los3_flg ignored in generating interrupt output. 2los2_msk los2_msk. determines if a los on ckin2 (los2_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the los2_flg register. 0: los2 alarm triggers active inte rrupt on int output (if int_pin=1). 1: los2_flg ignored in generating interrupt output.
si5368 preliminary rev. 0.41 39 reset value = 0011 1111 1los1_msk los1_msk. determines if a los on ckin1 (los1_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the los1_flg register. 0: los1 alarm triggers active inte rrupt on int output (if int_pin=1). 1: los1_flg ignored in generating interrupt output. 0losx_msk losx_msk. determines if a los on xa/xb(losx_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the losx_flg register. 0: losx alarm triggers active interr upt on int output (if int_pin=1). 1: losx_flg ignored in generating interrupt output. register 24. bitd7d6d5d4d3d2d1d0 name reserved align_ msk fos4_ msk fos3_ msk fos2_ msk fos1_ msk lol_msk type r r/wr/wr/wr/wr/wr/w bit name function 7:6 reserved reserved. 5align_ msk align_msk. determines if an alignment alarm (align_flg) is used in the generation of an interrupt. writes to this register do not change the value held in the align_flg register. 0: fsync alignment alarm triggers active interrupt on int output (if int_pin=1). 1: align_flg ignored in generating interrupt output. 4fos4_ msk fos4_msk. determines if the fos4 _flg is used to in the generation of an interrupt. writes to this register do not change the value held in the fos4_flg register. 0: fos4 alarm triggers active inte rrupt on intoutput (if int_pin=1). 1: fos4_flg ignored in generating interrupt output. 3fos3_ msk fos3_msk. determines if the fos3 _flg is used in the generation of an interrupt. writes to this register do not change the value held in the fos3_flg register. 0: fos3 alarm triggers active inte rrupt on int output (if int_pin=1). 1: fos3_flg ignored in generating interrupt output. 2 fos2_msk fos2_msk. determines if the fos2_flg is used in the gen eration of an interrupt. writes to this reg- ister do not change the value held in the fos2_flg register. 0: fos2 alarm triggers active inte rrupt on int output (if int_pin=1). 1: fos2_flg ignored in generating interrupt output.
si5368 40 preliminary rev. 0.41 reset value = 0010 0000 1 fos1_msk fos1_msk. determines if the fos1_flg is used in the gen eration of an interrupt. writes to this reg- ister do not change the value held in the fos1_flg register. 0: fos1 alarm triggers active inte rrupt on int output (if int_pin=1). 1: fos1_flg ignored in generating interrupt output. 0lol_msk lol_msk. determines if the lol_flg is used in the generation of an interrupt. writes to this regis- ter do not change the value held in the lol_flg register. 0: lol alarm triggers active interr upt on int output (if int_pin=1). 1: lol_flg ignored in generating interrupt output. register 25. bitd7d6d5d4d3d2d1d0 name n1_hs [2:0] reserved nc1_ls [19:16] type r/w r r/w bit name function 7:5 n1_hs [2:0] n1_hs [2:0]. sets value for n1 high speed divider which dr ives ncn_ls (n = 1 to 4) low-speed divider. 000: n1= 4 note: changing the coarse skew vi a the inc pin is disabled for this value. 001: n1= 5 010: n1=6 011: n1= 7 100: n1= 8 101: n1= 9 110: n1= 10 111: n1= 11 4 reserved reserved. 3:0 nc1_ls [19:16] nc1_ls [19:0]. sets value for nc1 low-speed divider, which drives ckout1 output. must be 0 or odd. 00000000000000000000=1 00000000000000000001=2 00000000000000000011=4 00000000000000000101=6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20].
si5368 preliminary rev. 0.41 41 reset value = 0000 0000 reset value = 0011 0001 register 26. bitd7d6d5d4d3d2d1d0 name nc1_ls [15:8] type r/w bit name function 7:0 nc1_ls [15:8] nc1_ls [15:8]. see register 25. register 27. bitd7d6d5d4d3d2d1d0 name nc1_ls [7:0] type r/w bit name function 7:0 nc1_ls [7:0] nc1_ls [7:0]. see register 25.
si5368 42 preliminary rev. 0.41 reset value = 0000 0000 reset value = 0000 0000 register 28. bitd7d6d5d4d3d2d1d0 name reserved nc2_ls [19:16] type rr/w bit name function 7:4 reserved reserved. 3:0 nc1_ls [19:0] nc2_ls [19:16]. sets value for nc2 low-speed divider, which drives ckout2 output. must be 0 or odd. 00000000000000000000=1 00000000000000000001=2 00000000000000000011=4 00000000000000000101=6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20] register 29. bitd7d6d5d4d3d2d1d0 name nc2_ls [15:8] type r/w bit name function 7:0 nc2_ls [15:8] nc2_ls [15:8]. see register 28.
si5368 preliminary rev. 0.41 43 reset value = 0011 0001 reset value = 0000 0000 register 30. bitd7d6d5d4d3d2d1d0 name nc2_ls [7:0] type r/w bit name function 7:0 nc2_ls [7:0] nc2_ls [7:0]. see register 28. register 31. bitd7d6d5d4d3d2d1d0 name reserved nc3_ls [19:16] type rr/w bit name function 7:4 reserved reserved. 3:0 nc3_ls [19:0] nc3_ls [19:0. sets value for nc3 low-speed divider, which drives ckout3 output. must be 0 or odd. 00000000000000000000=1 00000000000000000001=2 000000000000000000011=4 000000000000000000101=6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20].
si5368 44 preliminary rev. 0.41 reset value = 0000 0000 reset value = 0011 0001 register 32. bitd7d6d5d4d3d2d1d0 name nc3_ls [15:8] type r/w bit name function 7:0 nc3_ls [15:8] nc3_ls [15:8]. see register 31. register 33. bitd7d6d5d4d3d2d1d0 name nc3_ls [7:0] type r/w bit name function 7:0 nc3_ls [7:0] nc3_ls [7:0]. see register 31.
si5368 preliminary rev. 0.41 45 reset value = 0000 0000 reset value = 0000 0000 register 34. bitd7d6d5d4d3d2d1d0 name reserved nc4_ls [19:16] type rr/w bit name function 7:4 reserved reserved. 3:0 nc4_ls [19:0] nc4_ls [19:0]. sets value for nc4 low-speed divider, which drives ckout4 output. must be 0 or odd. 00000000000000000000=1 00000000000000000001=2 000000000000000000011=4 000000000000000000101=6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20]. register 35. bitd7d6d5d4d3d2d1d0 name nc4_ls [15:8] type r/w bit name function 7:0 nc4_ls [15:8] nc4_ls [15:8]. see register 34.
si5368 46 preliminary rev. 0.41 reset value = 0011 0001 reset value = 0000 0000 register 36. bitd7d6d5d4d3d2d1d0 name nc4_ls [7:0] type r/w bit name function 7:0 nc4_ls [7:0] nc4_ls [7:0]. see register 34. register 37. bitd7d6d5d4d3d2d1d0 name reserved nc5_ls [19:16] type rr/w bit name function 7:4 reserved reserved. 3:0 nc5_ls [19:0] nc5_ls [19:0]. sets value for nc5 low-speed divider, which drives ckout5 output. must be 0 or odd. when ck_config=0: 00000000000000000000=1 00000000000000000001=2 000000000000000000011=4 000000000000000000101=6 ... 11111111111111111111=2^20 valid divider values=[1, 2, 4, 6, ..., 2^20]. when ck_config=1, maximum value limited to 2^19.: 00000000000000000000=1 00000000000000000001=2 000000000000000000011=4 000000000000000000101=6 ... 01111111111111111111=2^19 valid divider values=[1, 2, 4, 6, ..., 2^19].
si5368 preliminary rev. 0.41 47 reset value = 0000 0000 reset value = 0011 0001 register 38. bitd7d6d5d4d3d2d1d0 name nc5_ls [15:8] type r/w bit name function 7:0 nc5_ls [15:8] nc5_ls [15:8]. see register 37. register 39. bitd7d6d5d4d3d2d1d0 name nc5_ls [7:0] type r/w bit name function 7:0 nc5_ls [7:0] nc5_ls [7:0]. see register 37.
si5368 48 preliminary rev. 0.41 reset value = 1100 0000 reset value = 0000 0000 register 40. bitd7d6d5d4d3d2d1d0 name n2_hs [2:0] reserved n2_ls [19:16] type r/w r r/w bit name function 7:5 n2_hs [2:0] n2_hs [2:0]. sets value for n2 high speed divider which dr ives ncn_ls (n = 1 to 4) low-speed divider. 000:4 001:5 010:6 011:7 100:8 101:9 110:10 111:11. 4 reserved reserved. 3:0 n2_ls [19:16] nc2_ls [19:0]. sets value for n2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 000000000000000000011 = 4 000000000000000000101 = 6 ... 11111111111111111111 = 2^20 valid divider values = [2, 4, 6, ..., 2^20]. register 41. bitd7d6d5d4d3d2d1d0 name n2_ls [15:8] type r/w bit name function 7:0 n2_ls [15:8] n2_ls [15:8]. see register 40.
si5368 preliminary rev. 0.41 49 reset value = 1111 1001 reset value = 0000 0000 register 42. bitd7d6d5d4d3d2d1d0 name n2_ls [7:0] type r/w bit name function 7:0 n2_ls [7:0] n2_ls [7:0]. see register 40. register 43. bitd7d6d5d4d3d2d1d0 name reserved n31 [18:16] type rr/w bit name function 7:3 reserved reserved. 2:0 n31 [18:0] n31 [18:0]. sets value for input divider for ckin1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 valid divider values=[1, 2, 3, ..., 2^19].
si5368 50 preliminary rev. 0.41 reset value = 0000 0000 reset value = 0000 1001 register 44. bitd7d6d5d4d3d2d1d0 name n31 [15:8] type r/w bit name function 7:0 n31 [15:8] n31 [15:8]. see register 43. register 45. bitd7d6d5d4d3d2d1d0 name n31 [7:0] type r/w bit name function 7:0 n31 [7:0] n31 [7:0]. see register 43.
si5368 preliminary rev. 0.41 51 reset value = 0000 0000 reset value = 0000 0000 register 46. bitd7d6d5d4d3d2d1d0 name reserved n32_[18:16] type rr/w bit name function 7:3 reserved reserved. 2:0 n32_[18:0] n32_[18:0]. sets value for input divider for ckin2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 valid divider values=[1, 2, 3, ..., 2^19]. register 47. bitd7d6d5d4d3d2d1d0 name n32_[15:8] type r/w bit name function 7:0 n32_[15:8] n32_[15:8]. see register 46.
si5368 52 preliminary rev. 0.41 reset value = 0000 1001 reset value = 0000 0000 register 48. bitd7d6d5d4d3d2d1d0 name n32_[7:0] type r/w bit name function 7:0 n32_[7:0] n32_[7:0]. see register 46. register 49. bitd7d6d5d4d3d2d1d0 name reserved n33_[18:0] type rr/w bit name function 18:0 n33_[18:0] n33_[18:0]. sets value for input divider for ckin3. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 valid divider values=[1, 2, 3, ..., 2^19].
si5368 preliminary rev. 0.41 53 reset value = 0000 0000 reset value = 0000 1001 register 50. bitd7d6d5d4d3d2d1d0 name n33_[15:8] type r/w bit name function 7:0 n33_[15:8] n33_[15:8]. see register 49. register 51. bitd7d6d5d4d3d2d1d0 name n33_[7:0] type r/w bit name function 7:0 n33_[7:0] n33_[7:0]. see register 49.
si5368 54 preliminary rev. 0.41 reset value = 0000 0000 reset value = 0000 0000 register 52. bitd7d6d5d4d3d2d1d0 name reserved n34_[18:16] type rr/w bit name function 7:0 n34_[18:0] n34_[18:0]. sets value for input divider for ckin4. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 valid divider values=[1, 2, 3, ..., 2^19]. register 53. bitd7d6d5d4d3d2d1d0 name n34_[15:8] type r/w bit name function 7:0 n34_[15:8] n34_[15:8]. see register 52.
si5368 preliminary rev. 0.41 55 reset value = 0000 1001 reset value = 0000 0000 register 54. bitd7d6d5d4d3d2d1d0 name n34_[7:0] type r/w bit name function 7:0 n34_[15:8] n34_[7:0]. see register 52. register 55. bitd7d6d5d4d3d2d1d0 name reserved clkin2rate_[ 2:0] clkin1rate[2:0] type rr/w r/w bit name function 7:6 reserved reserved. 5:3 clkin2rate [2:0] clkin2rate[2:0]. ckinn frequency selection for fos alarm monitoring. 000: 10 - 27 mhz 001: 25 - 54 mhz 002: 50 - 105 mhz 003: 95 - 215 mhz 004: 190 - 435 mhz 005: 375 - 710 mhz 006: reserved 007: reserved 2:0 clkin1rate [2:0] clkin1rate[2:0]. ckinn frequency selection for fos alarm monitoring. 000: 10 - 27 mhz 001: 25 - 54 mhz 002: 50 - 105 mhz 003: 95 - 215 mhz 004: 190 - 435 mhz 005: 375 - 710 mhz 006: reserved 007: reserved
si5368 56 preliminary rev. 0.41 reset value = 0000 0000 register 56. bitd7d6d5d4d3d2d1d0 name reserved clkin4rate_[ 2:0] clkin3rate[2:0] type rr/w r/w bit name function 7:6 reserved reserved. 5:3 clkin4rate [2:0] clkin4rate[2:0]. ckinn frequency selection for fos alarm monitoring. 000: 10 - 27 mhz 001: 25 - 54 mhz 002: 50 - 105 mhz 003: 95 - 215 mhz 004: 190 - 435 mhz 005: 375 - 710 mhz 006: reserved 007: reserved 2:0 clkin3rate [2:0] clkin3rate[2:0]. ckinn frequency selection for fos alarm monitoring. 000: 10 - 27 mhz 001: 25 - 54 mhz 002: 50 - 105 mhz 003: 95 - 215 mhz 004: 190 - 435 mhz 005: 375 - 710 mhz 006: reserved 007: reserved
si5368 preliminary rev. 0.41 57 reset value = 0010 0000 register 128. bitd7d6d5d4d3d2d1d0 name reserved ck4_actv _reg ck3_actv _reg ck2_actv _reg ck1_actv _reg type rr r r r bit name function 7:4 reserved reserved. 3 ck4_actv_ reg ck4_actv_reg. indicates if ckin4 is currently th e active clock for the pll input. 0: ckin4 is not the active input clock. eith er it is not selected or los4_int is 1. 1: ckin_4 is the active input clock. 2 ck3_actv_ reg ck3_actv_reg. indicates if ckin3 is currently th e active clock for the pll input. 0: ckin3 is not the active input clock - eith er it is not selected or los3_int is 1. 1: ckin3 is the active input clock. 1 ck2_actv_ reg ck2_actv_reg. indicates if ckin2 is currently th e active clock for the pll input. 0: ckin2 is not the active input clock. eith er it is not selected or los2_int is 1. 1: ckin2 is the active input clock. 0 ck1_actv_ reg ck1_actv_reg. indicates if ckin1 is currently th e active clock for the pll input. 0: ckin1 is not the active input clock. eith er it is not selected or los1_int is 1. 1: ckin1 is the active input clock.
si5368 58 preliminary rev. 0.41 reset value = 0001 1110 register 129. bitd7d6d5d4d3d2d1d0 name reserved los4_int los3_int los2_int los1_int losx_int type r rrrrr bit name function 7:5 reserved reserved. 4 los4_int los4_int. indicates the los status on ckin4. 0: normal operation. 1: internal loss-of-signal alarm on ckin4 input. 3 los3_int los3_int. indicates the los status on ckin3. 0: normal operation. 1: internal loss-of-signal alarm on ckin3 input. 2 los2_int los2_int. indicates the los status on ckin2. 0: normal operation. 1: internal loss-of-signal alarm on ckin2 input. 1 los1_int los1_int. indicates the los status on ckin1. 0: normal operation. 1: internal loss-of-signal alarm on ckin1 input. 0 losx_int losx_int. indicates the los status of the exte rnal reference on the xa/xb pins. 0: normal operation. 1: internal loss-of-signal alarm on xa/xb reference clock input.
si5368 preliminary rev. 0.41 59 reset value = 0000 0001 register 130. bitd7 d6 d5d4d3 d2 d1 d0 name clat- progress dighold- valid align_ int fos4_int fos3_int fos2_int fos1_int lol_int type rrrrrrrr bit name function 7clat- progress clat progress. indicates if the last change in the clat register has been processed. 0: coarse skew adjustment not in progress. 1: coarse skew adjustment in progress. 6dighold- valid digital hold valid. indicates if the digital hold circuit has enough samples of a valid clock to meet digital hold specifications. 0: indicates digital filter has not been filled. the digital hol d output freque ncy (from the filter) is not valid. 1: indicates digital hold filter has been filled. the digital ho ld output freq uency is valid. 5 align_int align_int. alignment alarm status. 0: normal operation. 1: alignment alarm between input and output frame sync signals. 4fos4_int fos4_int. ckin4 frequency offset status. 0: normal operation. 1: internal frequency offset alarm on ckin4 input. 3fos3_int fos3_int. ckin3 frequency offset status. 0: normal operation. 1: internal frequency offset alarm on ckin3 input. 2fos2_int fos2_int. ckin2 frequency offset status. 0: normal operation. 1: internal frequency offset alarm on ckin2 input. 1fos1_int fos1_int. ckin1 frequency offset status. 0: normal operation. 1: internal frequency offset alarm on ckin1 input. 0lol_int lol_int. pll loss of lock status. 0: pll locked. 1: pll unlocked.
si5368 60 preliminary rev. 0.41 reset value = 0001 1111 register 131. bitd7 d6 d5d4d3 d2 d1 d0 name reserved los4_ flg los3_ flg los2_ flg los1_ flg losx_ flg type r r/w r/w r/w r/w r/w bit name function 7:5 reserved reserved. 4los4_flg los4_flg. ckin4 loss-of-signal flag. 0: normal operation. 1: held version of los4_int. generates active output interrupt if output interrupt pin is enabled (int_pin=1) and if not masked by los4_msk bit. flag cleared by writing location to 0. 3los3_flg los3_flg. ckin3 loss-of-signal flag. 0: normal operation. 1: held version of los3_int. generates active output interrupt if output interrupt pin is enabled (int_pin=1) and if not masked by los3_msk bit. flag cleared by writing location to 0. 2los2_flg los2_flg. ckin2 loss-of-signal flag. 0: normal operation. 1: held version of los2_int. generates active output interrupt if output interrupt pin is enabled (int_pin=1) and if not masked by los2_msk bit. flag cleared by writing location to 0. 1los1_flg los1_flg. ckin1 loss-of-signal flag. 0: normal operation. 1: held version of los1_int. generates active output interrupt if output interrupt pin is enabled (int_pin=1) and if not masked by los1_msk bit. flag cleared by writing location to 0. 0 losx_flg losx_flg. external reference (signal on pins xa/xb) loss-of-signal flag. 0: normal operation. 1: held version of losx_int. ge nerates active output interrupt if output interrupt pin is enabled (int_pin=1) and if not masked by losx_msk bit. flag cleared by writing location to 0.
si5368 preliminary rev. 0.41 61 reset value = 0000 0010 register 132. bitd7d6d5d4d3d2d1d0 name reserved align_ flg fos4_flg fos3_flg fos2_flg fos1_flg lol_flg align_ err [8,8] type r r/wr/wr/wr/wr/wr/w r bit name function 7 reserved reserved. 6 align_flg align_flg. alignment alarm flag. 0: normal operation. 1: held version of align_int. generates active output interrupt if output interrupt pin is enabled (int_pin=1) and if not masked by align_msk bit. flag cleared by writing location to 0. 5fos4_flg fos4_flg. clkin_4 frequency offset flag. 0: normal operation. 1: held version of fos4_int. generates active output interrupt if output interrupt pin is enabled (int_pin=1) and if not masked by fos4_msk bit. flag cleared by writing location to 0. 4fos3_flg fos3_flg. clkin_3 frequency offset flag. 0: normal operation. 1: held version of fos3_int. generates active output interrupt if output interrupt pin is enabled (int_pin=1) and if not masked by fos3_msk bit. flag cleared by writing location to 0. 3fos2_flg fos2_flg. clkin_2 frequency offset flag. 0: normal operation. 1: held version of fos2_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by fos2_msk bit. flag cleared by writing location to 0. 2fos1_flg fos1_flg. clkin_1 frequency offset flag. 0: normal operation. 1: held version of fos1_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by fos1_msk bit. flag cleared by writing location to 0.
si5368 62 preliminary rev. 0.41 reset value = 0000 0000 1lol_flg lol_flg. pll loss of lock flag. 0: pll locked 1: held version of lol_int. generates active output interrupt if output interrupt pin is enabled (int_pin = 1) and if not masked by lol_msk bit. flag cleared by writing location to 0. 0 align_err [8,8] align_err [8:0]. indicates the magnitude of the deviation of the input to output frame sync phase alignment from the ideal valu e set in the fsync_skew[16:0] registers. the alignment error is given in units of tckout_2. if the alignment error exceeds 255 fckout_2 clock cycles, align_err[7:0] limits to its maximum value (11111111). the polarity of the phase deviation (leading or lagging) is given by the align_err[8] bit. 00000000=0 11111111=255 register 133. bitd7d6d5d4d3d2d1d0 name align_err [7:0] type r bit name function 7:0 align_err [7:0] align_err [7:0]. see register 132.
si5368 preliminary rev. 0.41 63 reset value = 0000 0100 reset value = 0100 0010 register 134. bitd7d6d5d4d3d2d1d0 name partnum_ro [11:4] type r bit name function 7:0 partnum_ ro [11:0] partnum_ro [11:0]. device id: 0000 0100 0100'b=si5368 register 135. bitd7d6d5d4d3d2d1d0 name partnum_ro [3:0 ] revid_ro [3:0] type rr bit name function 7:4 partnum_ ro [3:0] partnum_ro [3:0]. see register 134. 3:0 revid_ro [3:0] revid_ro [3:0]. indicates revision number of device. 0000: revision a 0001: revision b 0010: revision c other codes: reserved
si5368 64 preliminary rev. 0.41 reset value = 0000 0000 register 136. bitd7d6d5d4d3d2d1d0 name rst_reg ical reserved grade_ro [1:0] type r/w r/w r r bit name function 7 rst_reg rst_reg. internal reset. 0: normal operation. 1: reset of all internal logic. outputs tristated or disabled during reset. 6ical ical. start an internal calibration sequence. for proper operation, the device must go through an internal calibration sequence. ical is a self-clearing bit. writing a one to this location initiates an ic al. the calibration is complete once the lol alarm goes low. a valid stable clock (within 100 ppm) must be present to begin ical. note: any divider, clkinn_rate or bwsel_reg changes require an ical to take effect. changes in sfoutn_reg, pd_ckn, or dsbln_reg will cause a random change in skew until an ical is completed. 0: normal operation. 1: writing a "1" initiates inte rnal self-calibration. upon co mpletion of internal self- calibration, ical is inte rnally reset to zero. 5:2 reserved reserved. 1:0 grade_ro [1:0] grade_ro [1:0]. indicates maximum clock output frequency of this device. limits the range of the n1_hs divider. 00: n1_hs x ncn_ls > 4. maximum clock output frequency = 1.4175 ghz. 01: n1_hs x ncn_ls > 6. maximum clock output frequency = 808 mhz. 10: n1_hs x ncn_ls > 14. maximum clock output frequency = 346 mhz. 11: n1_hs x ncn_ls > 20. maximum clock output frequency = 243 mhz.
si5368 preliminary rev. 0.41 65 reset value = 0000 1111 register 138. bitd7d6d5d4d3d2d1d0 name reserved los4_en [1:1] los3_en [1:1] los2_en [1:1] los1_en [1:1] type rr/wr/wr/wr/w bit name function 7:4 reserved reserved. 3los4_en [1:0] los4_en [1:0]. note: los1_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive version of los. see the family reference manual for details. 2los3_en [1:0] los3_en [1:0]. note: los1_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive version of los. see the family reference manual for details. 1los2_en [1:0] los2_en [1:0]. note: los1_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive version of los. see the family reference manual for details. 0los1_en [1:0] los1_en [1:0]. note: los1_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive version of los. see the family reference manual for details.
si5368 66 preliminary rev. 0.41 reset value = 1111 1111 register 139. bitd7d6d5d4d3d2d1d0 name los4_en [0:0] los3_en [0:0] los2_en [0:0] los1_en [0:0] fos4_en fos3_en fos2_en fos1_en type r/w r/w r/w r/w r/w r/w r/w r/w bit name function 7los4_en [0:0] los4_en [0:0]. enable ckin1 los monitoring on the specified input (1 of 2). note: los1_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive version of los. see the family reference manual for details. 6los3_en [0:0] los3_en [0:0]. enable ckin1 los monitoring on the specified input (1 of 2). note: los1_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive version of los. see the family reference manual for details. 5los2_en [0:0] los2_en. enable ckin1 los monitoring on the specified input (1 of 2). note: los1_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive version of los. see the family reference manual for details. 4los1_en [0:0] los1_en [0:0]. enable ckin1 los monitoring on the specified input (1 of 2). note: los1_en is split between two registers. 00: disable los monitoring. 01: reserved. 10: enable losa monitoring. 11: enable los monitoring. losa is a slower and less sensitive version of los. see the family reference manual for details.
si5368 preliminary rev. 0.41 67 reset value = 0000 0000 3fos4_en fos4_en. enables fos on a per channel basis. 0: disable fos monitoring. 1: enable fos monitoring. 2fos3_en fos3_en. enables fos on a per channel basis. 0: disable fos monitoring. 1: enable fos monitoring. 1fos2_en fos2_en. enables fos on a per channel basis. 0: disable fos monitoring. 1: enable fos monitoring. 0fos1_en fos1_en. enables fos on a per channel basis. 0: disable fos monitoring. 1: enable fos monitoring. register 140. bitd7d6d5d4d3d2d1d0 name independentskew1 [7:0] type r/w bit name function 7:0 independ- entskew1 [7:0] independentskew1 [7:0]. 8 bit field that represents a twos complement of the phase offset in terms of clocks from the high speed output divider.
si5368 68 preliminary rev. 0.41 reset value = 0000 0001 reset value = 0000 0000 reset value = 0000 0000 register 141. bitd7d6d5d4d3d2d1d0 name independentskew2 [7:0] type r/w bit name function 7:0 independ- entskew2 [7:0] independentskew2 [7:0]. 8 bit field that represents a twos complement of the phase offset in terms of clocks from the high speed output divider. register 142. bitd7d6d5d4d3d2d1d0 name independentskew3 [7:0] type r/w bit name function 7:0 independ- entskew3 [7:0] independentskew3 [7:0]. 8 bit field that represents a twos complement of the phase offset in terms of clocks from the high speed output divider. register 143. bitd7d6d5d4d3d2d1d0 name independentskew4 [7:0] type r/w bit name function 7:0 independ- entskew4 [7:0] independentskew4 [7:0]. 8 bit field that represents a twos complement of the phase offset in terms of clocks from the high speed output divider.
si5368 preliminary rev. 0.41 69 reset value = 0000 0000 reset value = 0001 0011 register 144. bitd7d6d5d4d3d2d1d0 name independentskew5 [7:0] type r/w bit name function 7:0 independ- entskew5 [7:0] independentskew5 [7:0]. 8 bit field that represents a twos complement of the phase offset in terms of clocks from the high speed output divider when ck_config =0. register 185. bitd7d6d5d4d3d2d1d0 name nvm_revid [7:0] type r bit name function 7:0 nvm_revid [7:0] nvm_revid [7:0].
si5368 70 preliminary rev. 0.41 table 5 lists all of the register locations that should be followed by an ical after their contents are changed. table 4. ckout_always_on and sqical truth table ckout_always_on sqical result s output to output skew preserved? 0 0 ckout off until after the first ical n 0 1 ckout off until after the first successful ical (i.e., when lol is low) y 1 0 ckout always on, including during an ical n 1 1 ckout always on, including during an ical y table 5. register locations requiring ical addr register 0 bypass_reg 0 ckout_always_on 1 ck_prior4 1 ck_prior3 1 ck_prior2 1 ck_prior1 2 bwsel_reg 4h i s t _ d e l 5i c m o s 7 fosrefsel 9h i s t _ a v g 10 dsbl5_reg 10 dsbl4_reg 10 dsbl3_reg 10 dsbl2_reg 10 dsbl1_reg 11 pd_ck2 11 pd_ck1 19 fos_en 19 fos_thr 19 valtime 19 lockt 21 incdec_pin 25 n1_hs 26 nc1_ls 28 nc2_ls 31 nc3_ls
si5368 preliminary rev. 0.41 71 34 nc4_ls 37 nc5_ls 40 n2_hs 40 n2_ls 43 n31 46 n32 49 n33 51 n34 55 clkin2rate 55 clkin1rate 56 clkin4rate 56 clkin3rate table 5. register locations requiring ical addr register
si5368 72 preliminary rev. 0.41 5. ordering guide ordering part number output clock frequency range package rohs6, pb-free temperature range si5368a-c-gq 2 khz?945 mhz 970?1134 mhz 1.213?1.417 ghz 100-pin 14 x 14 mm tqfp yes ?40 to 85 c si5368b-c-gq 2 khz?808 mhz 100-pin 14 x 14 mm tqfp yes ?40 to 85 c si5368c-c-gq 2 khz?346 mhz 100-pin 14 x 14 mm tqfp yes ?40 to 85 c note: add an r at the end of the device to denote tape and reel options (for example, si5368-c-gmr).
si5368 preliminary rev. 0.41 73 6. package outl ine: 100-pin tqfp figure 4 illustrates the package details for the si5368. table 6 lis ts the values for the di mensions shown in the illustration. figure 4. 100-pin thin quad flat package (tqfp) table 6. 100-pin package diagram dimensions dimension min nom max dimension min nom max a ? ? 1.20 e 16.00 bsc. a1 0.05 ? 0.15 e1 14.00 bsc. a2 0.95 1.00 1.05 e2 3.85 4.00 4.15 b 0.17 0.22 0.27 l 0.45 0.60 0.75 c 0.09 ? 0.20 aaa ? ? 0.20 d 16.00 bsc. bbb ? ? 0.20 d1 14.00 bsc. ccc ? ? 0.08 d2 3.85 4.00 4.15 ddd ? ? 0.08 e0 . 5 0 b s c . ? 0o 3.5o 7o notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec ms-026, variant aed-hd. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specification for small body components.
si5368 74 preliminary rev. 0.41 7. recommended pcb layout figure 5. pcb land pattern diagram
si5368 preliminary rev. 0.41 75 table 7. pcb land pattern dimensions dimension min max e0 . 5 0 b s c . e 15.40 ref. d 15.40 ref. e2 3.90 4.10 d2 3.90 4.10 ge 13.90 ? gd 13.90 ? x ? 0.30 y1 . 5 0 r e f . ze ? 16.90 zd ? 16.90 r1 0.15 ref r2 ? 1.00 notes (general): 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes (solder mask design): 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes (stencil design): 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness shou ld be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. notes (card assembly): 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si5368 76 preliminary rev. 0.41 d ocument c hange list revision 0.1 to revision 0.2 ? changed lvttl to lvcmos in table 2, ?absolute maximum ratings,? on page 6. ? updated figure 2 and figure 3 on page 8. ? updated ?2. pin descriptions: si5368?. ?? added rate0 to pin description. by changing rate[1:0] the part can emulate a si5367. ?? changed xa/xb pin description to support both differential and single ended external refclk. revision 0.2 to revision 0.3 ? added figure 1, ?typical phase noise plot,? on page 7. ? updated figure 2, ?si53 68 typical application circuit (i 2 c control mode),? and figure 3, ?si5368 typical application circuit (spi control mode),? on page 8 to show inc and dec. ? updated ?2. pin descriptions: si5368?. ?? changed font of register names to underlined italics . ? updated "5. ordering guide" on page 72. ? added ?7. recommended pcb layout?. revision 0.3 to revision 0.4 ? changed v dd specification for 1.8 v. ? updated table 1 on page 4. ? updated table 2 on page 6. ? added table under figure 1 on page 7. ? updated "1. functional description" on page 9. ? clarified "2. pin descriptions: si5368" on page 10 including correcting pin assignments for rate0 and rate1. revision 0.4 to revision 0.41 ? added register map. ? added 3.3 v operation. ? removed some tbds from the ac specifications.
si5368 preliminary rev. 0.41 77 n otes :
si5368 78 preliminary rev. 0.41 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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