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1/38 ? semiconductor MSM7718-01 ? semiconductor MSM7718-01 echo canceler with adpcm codec general description the msm7718, developed for phs (personal handyphone system) applications, is a cmos lsi device and contains a line echo canceler and a single channel full-duplex adpcm transcoder that performs interconversion between voice-band analog signal and 32 kbps adpcm data. this device includes dtmf tone and several types of tone generation, transmit/receive data mute and gain control, and vox function and is best suited for master telephones in phs applications. features ? single 3 v power supply v dd : 2.7 v to 3.6 v ? adpcm : itu-t recommendations g.726 (32 kbps) ? full-duplex single channel operation ? transmit/receive synchronous mode ? pcm interface coding format : m -law ? built-in line echo canceler echo attenuation : 30 db (typ.) cancelable echo delay time : normal speech mode : 23 ms (max.) line echo canceler expansion mode : 54 ms (max.) ? serial pcm/adpcm transmission data rate : 64 kbps to 2048 kbps ? low power consumption operating mode : typically 66 mw (v dd = 3.0 v) power-down mode : typically 0.3 mw (v dd = 3.0 v) ? two analog input gain adjustable amplifier stages ? analog output stage : push-pull drive, (direct drive of 350 w + 120 nf) ? master clock frequency : 9.600/19.200 mhz ? transmit/receive mute, transmit/receive programmable gain control ? built-in dtmf tone generator and various ringing tones generator ? dtmf tone and call progress tone detection ? serial mcu interface control ? built-in vox control transmit side : voice/silence detect receive side : background noise generation at the absence of voice signal ? built-in 2100 hz tone detection (bidirectional) ? package: 100-pin plastic tqfp (tqfp100-1414-0.50-k) (product name : MSM7718-01ts-k) e2u0052-18-86 this version: aug. 1998
2/38 ? semiconductor MSM7718-01 block diagram voxo sgr sgt ain1C ain1+ gsx1 ain2 gsx2 vfro pwi aoutC aout+ v ddd1,2,3 v dda dg1,2,3 ag den exck din dout int pcmpci pcmpco pcmlni pcmlno pcmaci pcmaco pcmadi pcmado syncp bclkp mcksl mck pdn / rst pdwn tsti1-4 voxi tone generator (dtmf etc.) atttgrx attsl attrx gainl attrl line echo canceler pcm codec flash memory controller (reserved) adpcm coder adpcm decoder adpcm transcoder + atttgtx atttx center clip sinl routl voice detect vref 1.2 k w 1.2 k w C1 C + C + C + l/ m l/ m bpf adc rc lpf rc lpf dac lpf p/s s/p test interface clock gen. mcu interface p/s&s/p timing gen. m /l m /l l/ m m /l rinl power detect noise gen. line adapive fir filter (laff) coeff.l0 coeff.l1 power calc. howling detector double talk detector soutl tone detector (dtmf etc.) mlv0 mlv1 mlv2 mute d7-0 a20-0 we oe cs1 cs2 is bclka synca ir C tsto rp mute 2100 hz detect
3/38 ? semiconductor MSM7718-01 75 1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 nc a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 nc a15 a16 a17 a18 a19 a20 dg1 v dda ain2 gsx2 nc nc cs1 oe we rp pdwn v ddd3 tsti1 bclka synca ir bclkp nc pcmpci pcmlni pcmaci pcmadi dout is pcmpco pcmlno dg3 pcmaco pcmado nc nc 74 cs2 73 int 72 tsto 71 voxo 70 voxi 69 mlv0 68 mlv1 67 mlv2 66 mute 65 dg2 64 d7 63 nc 62 d6 61 d5 60 d4 59 d3 58 d2 57 d1 56 d0 55 a0 54 a1 53 a2 52 v ddd2 51 nc 2 tsti2 3 pdn / rst 4 din 5 exck 6 den 7 v ddd1 8 syncp 9 tsti4 10 tsti3 11 mck 12 mcksl 13 gnda 14 vfro 15 pwi 16 aoutC 17 aout+ 18 sgt 19 sgr 20 nc 21 nc 22 ain1C 23 gsx1 24 ain1+ 25 nc nc nc: no-connect pin 100-pin plastic tqfp
4/38 ? semiconductor MSM7718-01 pin functional description ain1+, ain1C, ain2, gsx1, gsx2 transmit analog inputs and the outputs for transmit gain adjustment. ain1C (ain2) connects to inverting input of the internal transmit amplifier. ain1+ connects to non- inverting input of the internal transmit amplifier. gsx1 (gsx2) connects to the internal transmit amplifier output. refer to fig.1 for gain adjustment. vfro, aout+, aoutC, pwi receive analog outputs and the output for receive gain adjustment. vfro is the receive filter output. aout+ and aoutC are differential analog signal outputs which can directly drive z l (= 350 w + 120 nf) or a 1.2 k w load. refer to fig.1 for gain adjustment. however, these outputs are in high impedance state during power-down. figure 1 analog interface transmit gain: v gsx2 /vi = (r2/r1) (r4/r3) ain1C gsx1 r2 c1 to encoder r1 from decoder differential analog output receive gain: v o /v vfro = 2 (r5/r6) z l =120 nf + 350 w ain2 gsx2 r4 c2 r3 aoutC pwi r5 vfro r6 aout+ ain1+ C1 C + C + C + c1 r1 r2 vref sgt + C differential analog input v1 v o
5/38 ? semiconductor MSM7718-01 sgt, sgr outputs of the analog signal ground voltage. sgt outputs the analog signal ground voltage of the transmit system, and sgr outputs the analog signal ground voltage for the receive system. the output voltage is approximately 1.4 v. connect bypass capacitors of 10 m f and 0.1 m f (ceramic type) between these pins and the ag pin. however to reduce the response time of the receiver power-on, it is recommended to apply bypass capacitors of 1 m f and 0.1 m f. during power-down, the output changes to 0 v. ag analog ground. dg1, 2, 3 digital ground. v dda +3 v power supply for analog circuits. v ddd1, 2, 3 +3 v power supply for digital circuits. pdn / rst power-down reset control input. a logic 0 makes the lsi device enter a power-down state. at the same time, all control register data is reset to the initial state. set this pin to a logic 1 during normal operating mode. since the pdn / rst pin is ored with cr0-b5 of the control register, set cr0-b5 to digital 0 when using this pin. pdwn power-down control input. when set to a logic 0, the device changes to the power-down state, but each bit of control register and internal variables of control register are retained. during normal operation, set this pin to logic 1. since the pdwn pin is ored with cr0-b6 of the control register, set cr0-b6 to logic 0 when using this pin. mck master clock input. the frequency must be 9.6 mhz or 19.2 mhz. the master clock signal is allowed to be asynchronous with syncp, synca, bclkp, and bclka.
6/38 ? semiconductor MSM7718-01 mcksl master clock selection input. set mcksl to logic 0 when the master clock frequency is 9.6 mhz, and to logic 1 when it is 19.2 mhz. pcmpco pcm data output of the pcm codec. pcm is output from msb, synchronizing with the rising edge of bclkp and syncp. this pin is in a high impedance state except during 8-bit pcm output. (it is also in a high impedance state during power-down mode.) a pull-up resistor must be connected to this pin because its output is configured as an open drain. pcmpci pcm data input of the pcm codec. pcm is shifted in at the falling edge of the bclkp signal. the start of the pcm data (m sb) is identified at the rising edge of syncp. pcmado pcm data output of the adpcm transcoder. pcm is the output data after adpcm decoder processing and is serially output from msb in synchronization with the rising edge of bclkp and syncp. however, this signal timing can be controlled at pcm multiplexing by the control register cr1-b5. (the time slot 1 or 2 can be selected. refer to figs. 2-4.) this pin is in a high impedance state except during 8-bit pcm output. (it is also in an high impedance state during power-down mode.) a pull-up resistor must be connected to this pin because its output is configured as an open drain. pcmadi pcm data input of the adpcm transcoder. pcm is shifted in at a falling edge of the bclkp signal and input from msb. the start of the pcm data (msb) is identified at the rising edge of syncp. however, this signal timing can be controlled at pcm multiplexing by the control register cr1-b5. (the time slot 1 or 2 can be selected. refer to figs. 2-4.) pcmlno pcm receive data output of the line echo canceler. pcm is output from msb in a sequential order, synchronizing with the rising edge of bclkp and syncp. however, this signal timing can be controlled at pcm multiplexing by the control register cr2-b3 to b5. (the time slot of 1 to 7 can be selected. refer to figs. 2-4.) this pin is in a high impedance state except during 8-bit pcm output. (it is also in a high impedance state during power-down mode.) a pull-up resistor must be connected to this pin because its output is configured as an open drain.
7/38 ? semiconductor MSM7718-01 pcmlni pcm transmit data input of the line echo canceler. pcm is shifted in at a falling edge of the bclkp signal and input from msb. the start of the pcm data (msb) is identified at the rising edge of syncp. however, this signal timing can be controlled at pcm mutiplexing by the control register cr2-b3 to b5. (one of the time slots 1 to 7 can be selected. refer to figs. 2-4.) pcmaco pcm transmit data output of the line echo canceler. pcm is output from msb in a sequential order, synchronizing with the rising edge of bclkp and syncp. however, this signal timing can be controlled at pcm multiplexing by the control register cr2-b0 to b2. (the time slot 1 to 7 can be selected. refer to figs. 2 - 4.) this pin is in a high impedance state except during 8-bit pcm output. (it is also in a high impedance sate during power down mode.) a pull-up resistor must be connected to this pin because its output is configured as an open drain. pcmaci pcm receive data input of the line echo canceler. pcm is shifted in at a falling edge of bclkp and input from msb. the start of the pcm data (msb) is identified at the rising edge of syncp. however, this signal timing can be controlled at pcm multiplexing by the control register cr2-b0 to b2. (one of the time slots 1 to 7 can be selected. refer to figs. 2-4.) bclkp syncp pcm multiple time slot 1 time slot 2 time slot 3 time slot 7 note : the pcm signals (pcmpci and pcmpco) of the pcm codec are always assigned to time slot 1. the pcm signals (pcmadi and pcmado) of the adpcm transcoder can be assigned to time slot 1 or 2. the pcm signals (pcmlni, pcmlno, pcm aci, pcmaco) of the line echo canceler can be assigned to one of the time slots 1 to 7. (m ultiple timing is controlled by cr1 and cr2.) figure 2 pcm multiple timing
8/38 ? semiconductor MSM7718-01 note : in this connection, pcmlni, pcmlno, pcmaci, and pcmaco should all be assigned to time slot 1 for their output timing (the output timing for the pcm codec is always assigned to time slot 1). turn on the line echo canceler and establish a route between the slave telephone and the line. figure 3 pcm signal connection example 1 line echo canceler pcm codec pcmlni pcmpco pcmpci adpcm transcoder pcmlno pcmaci pcmaco pcmadi pcmado msm7718 line slave telephone
9/38 ? semiconductor MSM7718-01 line echo canceler pcm codec pcmlni pcmpco pcmpci adpcm codec pcmlno pcmaci pcmaco pcmadi pcmado msm7718 line slave telephone pcm codec microphone and speaker of the master telephone notes : the pcm signals of the adpcm transcoder are assigned to time slot 2. (the pcm signals of the pcm codec are always assigned to time slot 1.) the pcm signals of an external pcm codec are assigned to time slot 3. route between the line and the slave telephone pcmlni and pcmlno are assigned to time slot 1 and pcmaci and pcmaco are assigned to time slot 2. turn on the line echo canceler, and establish the route between the line and the slave telephone. route between the master telephone's microphone/speaker (handsfree) and the slave telephone pcmlni and pcmlno are assigned to time slot 3 and pcmaci and pcmaco are assigned to time slot 2. turn on the line echo canceler, and establish the route between the microphone/ speaker of the master telephone and the slave telephone. route between the line and the master telephone's microphone/speaker (handsfree) pcmlni and pcmlno are assigned to time slot 1 and pcmaci and pcmaco are assigned to time slot 3. put the line echo canceler into through mode, and establish the route between the line and the microphone/speaker of the master telephone. various routing can be implemented providing extension of external pcm codecs. figure 4 pcm signal connection example 2
10/38 ? semiconductor MSM7718-01 bclkp shift clock input for the pcm data (pcmpco, pcmpci, pcmado, pcmadi, pcmlno, pcmlni, pcmaco, pcmaci). the frequency is set in the range of 64 khz to 2048 khz. this signal must be synchronized with the syncp signal. (refer to fig. 2.) syncp 8 khz synchronous signal input for transmit and receive pcm data. this signal must be synchronized with the bclkp signal. (refer to fig. 2.) is transmit adpcm data output. this data is the output data after adpcm encoding, and is serially output from msb in synchroniza- tion with the rising edge of bclka and synca. this pin is an open drain output which remains in a high impedance state during power-down, and requires a pull-up resistor. ir receive adpcm data input. adpcm is shifted in on the rising edge of bclka in synchronization with synca and input orderly from msb. bclka shift clock input for the adpcm data (is, ir). the frequency is from 64 khz to 2048 khz. this signal must be synchronized with the synca signal. synca 8 khz synchronous signal input for transmit and receive adpcm data. synchronize this data with bclka signal. synca is used for indicating the msb of the serial adpcm data stream. den, exck, din, dout, int serial control ports for mcu interface. reading and writing data is performed by an external mcu through these pins. 17-byte control registers are provided in this device. den is the enable control signal input, exck is the data shift clock input, din is the address and data input, and dout is the data output. input/output timing is shown in fig. 5. int goes to logic 0 when any change has been found in the tone detection results in the tone detection mode (change in the control register bits cr7-b3, b2), and goes to logic 1 when the data of control register cr7 is read out.
11/38 ? semiconductor MSM7718-01 figure 5 mcu interface input/output timing voxo signal output for transmit vox function. the vox function recognizes the presence or absence of the transmit voice signal by detecting the level of the transmit signal to the line echo canceler . 1 and 0 levels set to this pin correspond to the presence and the absence of voice, respectively. this result appears also at the register data cr7-b7. the signal energy detect threshold is set by the control register data cr6-b6, b5. the timiging diagram of the vox function is shown in fig 6. the transmit signal to the line echo canceler refers to the signal input to the pcmlni pin. voxi signal input for receive vox function. the 1 level at voxi indicates the presence of a voice signal, the decoder block processes normal receive signal, and the voice signal on the pcmaci pin goes through. the 0 level indicates the absence of a voice signal and the background noise generated in this device is output to the line echo canceler. the background noise amplitude is set by the control register cr6. because this signal is ored with the register data cr6-b3, set the control register data cr6-b3 to logic 0. high impedance high impedance (a) data write timing (b) data read timing den w exck din a2 dout a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 r a2a1a0 b7 den exck din dout a3 a3 a4 a4 b6 b5 b4 b3 b2 b1 b0
12/38 ? semiconductor MSM7718-01 voice input gsx2 voxo voxi voice output vfro t vxon voice detect t vxoff silence detect (hangover time) normal voice signal decoded time period background noise (a) transmit vox function timing diagram (for analog input) (b) receive vox function (cr6-b3: lo g ic 0) timin g dia g ram (for analo g in p ut) voice voice voice silence silence voice note: the vox function is valid when cr6-b7 is set to logic 1. figure 6 vox function mute this pin is used to enable the receive side voice path mute level. to set the mute level, set this pin to 1. mlv0, mlv1, mlv2 these pins are used to set the receive side voice path mute level. for the control method, refer to the control register description (cr1). since these pins are ored with cr1-b2, b1, and b0 internally, set the bits of the register to 0 before using this pin.
13/38 ? semiconductor MSM7718-01 d7 to d0 (reserved for external memory i/f) output of write data, and input-output of read data. a20 to a0 (reserved for external memory i/f) external memory address output. we (reserved for external memory i/f) output for write control . oe (reserved for external memory i/f) output for read control. cs1 , cs2 (reserved for external memory i/f) chip select output. rp (reserved for external memory i/f) reset/power-down control output for external memory. tsti1, tsti2, tsti3, tsti4 input for test. normally fix these pins to logic 0. tsti4 input for mode select. fix this pin to logic 0 for normal speech mode. fix this pin to logic 1 for line echo canceler expansion mode. refer to the explanation of cr0 for the operation mode. tsto output for test.
14/38 ? semiconductor MSM7718-01 (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) parameter power supply voltage operating temperature input high voltage input low voltage digital input rise time digital input fall time master clock frequency master clock duty ratio bit clock frequency synchronous pulse frequency clock duty cycle transmit sync pulse setting time receive sync pulse setting time receive sync pulse setting time pcm, adpcm setup time pcm, adpcm hold time symbol v dd ta v ih v il t ir t if f mck d c f bck f sync d ck t xs t sx t rs t sr t ws t ds t dh condition all digital inputs all digital inputs all digital inputs all digital inputs mck mck bclkp, bclka syncp, synca bclkp, bclka, exck bclkp to syncp, bclka to synca syncp to bclkp, synca to bclka bclkp to syncp, bclka to synca syncp to bclkp, synca to bclka syncp, synca unit v c v v ns ns mhz % khz khz % ns ns ns ns m s ns ns max. 3.6 +70 0.16 50 50 +100ppm 60 2048 +1000ppm 60 100 v dd typ. +25 19.2/9.6 50 8.0 50 min. 2.7 C25 0.45 v dd 0 C 100ppm 40 64 C 1000ppm 40 100 100 100 100 1 bclk 100 100 t ro syncp to bclkp, synca to bclka ns 100 t xo syncp to bclkp, synca to bclka ns 100 absolute maximum ratings parameter power supply voltage analog input voltage digital input voltage storage temperature symbol v dd v ain v din t stg condition rating C0.3 to +5 C 0.3 to v dd + 0.3 C0.3 to v dd + 0.3 C55 to +150 unit v v v c recommended operating conditions note: if syncp and synca are generated from different clocks, do not change the relative timing of the rising edge of syncp and that of synca (that is, which rising edge is earlier) after the reset state has been released.
15/38 ? semiconductor MSM7718-01 electrical characteristics dc characteristics analog interface characteristics parameter symbol condition min. typ max. unit input resistance output load resistance output load capacitance r in r l1 r l2 r l3 c l1 c l2 v o3 ain+, ainC, ain2, pwi gsx1, gsx2, vfro aout+ aoutC gsx1, gsx2, vfro aout+ 10m w 20k w 1.2 k w 1.2 k w 100 pf 100 pf 1.3 v pp (v dd = 2.7 to 3.6 v, ta= C25 to +70c) pf v pp v pp mv mv v k w k w output voltage level (*1) offset voltage sgt, sgr output voltage sgt output impedance sgr output impedance c l3 aoutC 100 v o1 gsx1, gsx2, vfro (r l =20k w ) 1.3 v o2 aout+ (r l =1.2 k w ) 1.3 v ofgx v ofgx v sg r sgt r sgr aoutC (r l =1.2 k w ) vfro vfro sgt, sgr sgt sgr C100 +100 C20 +20 1.4 4080 4 8 parameter symbol condition min. typ. max. unit power supply current 1 power supply current 2 input leakage current high level digital output voltage low level digital output voltage digital output leakage current input capacitance i dd1 i dd2 i ih i il v oh1 v oh2 v ol i o c in operating mode, no signal (only the master clock is input) power down mode (only the master clock is input) v i =v dd v i = 0 v i oh = 0.4 ma i oh = 1 m a 1lsttl, pull-up resistance : 500 w is 2240ma 0.2 1 ma 2 m a 0.5 m a 0.5 v dd v dd v 0.8 v dd v dd v 0 0.2 0.4 v 10 m a 5pf (v dd = 2.7 to 3.6 v, ta= C25 to +70c) *1 C7.7 dbm (600 w ) = 0 dbm0, +3.14 dbm0=1.30 v pp
16/38 ? semiconductor MSM7718-01 digital interface characteristics pcm/adpcm output timing 123456 78910 123456 78910 0 t xd1 t xd2 t ws t sx t xs t sdx msb lsb t xs t sx t xd1 t xd2 msb lsb t xd3 t xd3 t sdx bclkp syncp pcmpco pcmado pcmlno pcmaco bclka synca is 0 t xo t xo note : the timing for pcmado, pcmlno, and pcmaco shown above reperesents the timing when time slot 1 is selected. parameter symbol condition min. typ. max. unit digital output delay time pcm, adpcm interface serial port digital input/output setting time t sdx , t sdr t xd1 , t rd1 t xd2 , t rd2 t xd3 , t rd3 t m1 t m2 t m7 1lsttl+100 pf pull-up resistance : 500 w values in parentheses apply when cload = 10 pf, pull-up resistance : 2 k w cload=100 pf 0 200 (100) ns 0 200 (100) ns 0 200 (100) ns 0 200 (100) ns 50 ns 20 ns 50 (v dd = 2.7 to 3.6 v, ta= C25 to +70c) ns mhz shift clock frequency t m3 20 t m6 50 t m8 t m9 f eck exck 0 50 10 50 100 ns t m10 50 ns ns ns ns ns ns t m4 t m5 t m11 t m12 ns ns 100 0
17/38 ? semiconductor MSM7718-01 pcm/adpcm input timing 123456 789 t ws t sr t rs bclka synca msb lsb ir t dh t ds 0 10 t ro 123456 789 t sr t rs bclkp syncp msb pcmpci pcmadi pcmlni pcmaci t dh t ds 0 10 t ro lsb note : the timing for pcmadi, pcmlni, and pcmaci shown above represents the timing when time slot 1 is selected. serial port timing for microcontroller interface t m1 t m3 t m4 t m2 123567 t m6 t m7 t m5 13 14 t m10 t m11 w/r a4 a1 a0 b7 t m8 b1 b0 b1 b0 t m9 den exck din dout t m12 b7 15
18/38 ? semiconductor MSM7718-01 ac characteristics *2. p-message weighted filter used *3. pcmpci input code: 11111111 ( m -law) *4. 0.320 vrms=0 dbm0=C7.7 dbm note : all adpcm coder and decoder characteristics fully comply with itu-t recommenda tions g.726. parameter symbol condition freq.(hz) level (dbm0) others min. typ. max. unit 0-60 transmit frequency response l oss t1 0 300-3k l oss t2 1020 l oss t3 3300 l oss t4 3400 l oss t5 3968.75 l oss t6 25 C0.15 +0.2 reference C0.15 +0.8 0 0.8 13 C0.15 +0.2 reference C0.15 +0.8 0 0.8 13 35 35 35 28 23 35 35 35 28 23 C0.2 +0.2 reference C0.2 +0.2 C0.5 +0.5 C1.2 +1.2 C0.2 +0.2 reference C0.2 +0.2 C0.5 +0.5 C1.2 +1.2 C68 (C75.7) C72 0.285 0.32(*4) 0.359 0.285 0.32(*4) 0.359 30 30 (79.7) db db db db db db dbm0p (dbmp) dbm0p (dbmp) vrms vrms db db 0 0 C30 (*2) 0 3 C40 C45 (*2) (*2) (*2) gsx2 vfro 3 0 C30 C40 C45 3 C10 C40 C50 C55 3 C10 C40 C50 C55 ain=sg (*3) 0 noise level: 50 mvpp l oss r1 l oss r2 l oss r3 l oss r4 l oss r5 sd t1 sd t2 sd t3 sd t4 sd t5 sd r1 sd r2 sd r3 sd r4 sd r5 gt t1 gt t2 gt t3 gt t4 gt t5 gt r1 gt r2 gt r3 gt r4 gt r5 n idlt n idlr a vt a vr p srrt p srrr receive frequency response transmit signal to distortion receive signal to distortion transmit gain tracking receive gain tracking idle channel noise absolute signal amplitude power supply noise rejection ratio 0-3000 1020 3300 3400 3968.75 1020 1020 1020 1020 1020 noise freq.: 0 to 50 khz (v dd = 2.7 to 3.6 v, ta = C25 to +70c)
19/38 ? semiconductor MSM7718-01 ac characteristics (dtmf and other tones) *5 not including programmable gain set values ac characteristics (gain settings) ac characteristics (vox function) parameter symbol condition min. typ. max. unit frequence deviation relative value of dtmf tones tone reference output level (*5) df t1 df t2 v tl v th v rl v rh r dtmf dtmf tones other various tones transmit side tone (gain set value:0db) C1.5 +1.5 % C1.5 +1.5 % C10 C8 C6 dbm0 C8 C6 C4 dbm0 C10 C8 C6 dbm0 C8 C6 C4 dbm0 123db recieve side tone (gain set value:0db) dtmf (low group) dtmf (high group), others v th /v tl, v rh /v rl dtmf (high group), others dtmf (low group) (v dd = 2.7 to 3.6 v, ta = C25 to +70c) parameter symbol condition min. typ. max. unit d g for all gain set values C1 0 +1 db transmit/recieve gain setting accurancy (v dd = 2.7 to 3.6 v, ta = C25 to +70c) parameter symbol condition min. typ. max. unit t vxon silence ? voice 5 ms transmit vox detection time voice signal on/off detect time (v dd = 2.7 to 3.6 v, ta = C25 to +70c) t vxoff d vx transmit vox detection level accuracy (voice detection level) voxo pin:see fig.6 voice/silence differential:10 db 140/300 160/320 180/340 ms C2.5 0 +2.5 db voice ? silence for detection level set values by crm6-b6,b5
20/38 ? semiconductor MSM7718-01 ac characteristics (tone detect function) parameter symbol condition min. (v dd = 2.7 to 3.6 v, ta = C25 to +70c) typ. max. unit cpt detection frequency f detcp 350 640 hz cpt non-detection frequency f rejcp 700 hz 250 hz cpt detection level v detcp input frequency: 350 to 640 hz C39 0 dbm0 cpt non-detection level v rejcp C49 dbm0 t detcp 55 ms t rejcp 30 ms cpt detection delay time t dlycp 30 45 55 ms cpt detection hold time t holcp 71624ms dtmf detection frequency f detdt 1.5 % dtmf non-detection frequency 3.8 % dtmf detection level C39 0 dbm0 dtmf non-detection level C47 dbm0 dtmf input signal continuation time 38 ms 16 ms dtmf detection delay time 16 38 ms dtmf detection hold time 14 25 ms ans detection frequency 2079 2100 2121 hz ans non-detection frequency 2350 hz 1900 hz ans detection level C31 0 dbm0 ans non-detection level C35 dbm0 ans input signal continuation time 480 ms 420 ms ans detection delay time 420 450 480 ms ans detection hold time 71217ms f rejdt v detdt v rejdt t detdt t rejdt t dlydt t holdt f detan f rejan v detan v rejan t detan t rejan t dlyan t holan cpt detected cpt not detected at nominal frequency at nominal frequency input frequency:nominal frequency 1.5% cpt detected cpt not detected input frequency: 2079 to 2121 hz cpt detected cpt not detected cpt input signal continuation time note : in the case of call progress tone, dtmf tone, and 2100 hz tone, xx refers to cp, dt, and an respectively. input signal detecpt: cr7-b3 detdtmf: cr7-b2 det21l: cr7-b1 det21l: cr7-b1 int pin int: cr7-b4 (positive logic) t dlyxx t holxx t rejxx t detxx the state of the int pin is changed by reading the contents of cr7. it is retained when cr7 is not read.
21/38 ? semiconductor MSM7718-01 functional description control registers table 1 control register map reg name address a3 a1 contents r/w b7 cr0 0 0 0 a2 a0 0 b6 b5 b4 b3 b2 b1 b0 pdn/ rst ope mode3 ope mode2 ope mode1 ope mode0 r/w cr1 0 0 01 pcm ad sel tx mute rx mute rx mlv2 rx mlv1 rx mlv0 r/w cr2 0 1 00 pcm ln sel2 pcm ln sel1 pcm ln sel0 pcm ac sel2 pcm ac sel1 pcm ac sel0 r/w cr3 0 1 01 tx gain1 tx gain0 rx gain3 rx gain2 rx gain1 rx gain0 r/w cr4 0 0 10 r/w cr5 0 0 11 tone4 rx tone send r/w cr6 0 1 10 on lvl0 off time vox in rx. noise level sel rx. noise lvl1 rx. noise lvl0 r/w cr7 0 1 11 silence level 0 r cr8 1 0 00 lecclr1 r/w cr9 1 0 01 r/w cr10 1 1 00 r/w cr11 1 1 01 r/w cr12 1 0 10 r/w cr13 1 0 11 r/w pdwn adpcm mode adpcm reset pcm pco mute pcm pci mute tx gain3 tx gain2 tx tone gain3 tx tone gain2 dtmf/others sel tx tone send tone3 tone2 tone1 tone0 vox on/off on lvl1 vox out silence level 1 det dtmf busy/ det21l rpm/ det21a lecclr2 lechd aecclr aechd cmd3 cmd2 cmd1 cmd0 * r/w : read/write enable r : read only register a4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tx tone gain1 tx tone gain0 rx tone gain3 rx tone gain2 rx tone gain1 rx tone gain0 int det cpt lecthr (hcl)* leccclp (nlp)* lechld (adp)* lecatt (att)* lecgc (gc)* aecthr (hcl)* aeccclp (nlp)* aechld (apd)* aecatt (att)* aecgc (gc)* adpcm mode1 adpcm mode0 send/ rec mem sel st5/ a5 st4/ a4 st3/ a3 st2/ a2 st1/ a1 st0/ a0 st7/ a7 st6/ a6 st13/ a13 st12/ a12 st11/ a11 st10/ a10 st9/ a9 st8/ a8 st15/ a15 st14/ a14 st20/ a20 st19/ a19 st18/ a18 st17/ a17 st16/ a16 cr14 1 1 10 r/w sp3 sp2 sp1 sp0 0 sp4 sp5 sp6 sp7 cr15 1 1 11 r/w sp11 sp10 sp9 sp8 0 sp12 sp13 sp14 sp15 cr16 0 0 00 r/w sp19 sp18 sp17 sp16 1 sp20 cr17 0 0 01 r/w d3/ca3 d2/ca2 d1/ca1 d0/ca0 1 d4/ca4 d5/ca5 d6/ca6 d7/ca7 d tone3/ wa3 d tone2/ wa2 d tone1/ wa1 d tone0/ wa0 wa4 wa5 wa6 wa7 cr18 0 1 00 r/w 1 : these are the s y mbols of control p ins used in the msm7602 ( echo canceler lsi device ) .
22/38 ? semiconductor MSM7718-01 (1)cr0 (basic operating mode settings) * : indicates the value to be set when a resetting is made through the pdn / rst pin. (also when reset by bit 5 (b5, pdn/rst), the other bits of cr0 are reset to initial values.) b7 ... not used b6 ... power-down (entire system) 0: power-on 1: power-down ored with the inverted external power-down signals set the pdwn pin to 1 when this data is used. the control registers and their internal variables are not reset. b5 ... power-down reset (entire system) 0: power-on 1: power-down reset ored with the inverted external power-down reset signals set the pdn / rst pin to 1 when this data is used . b4 ... not used b3, 2, 1, 0 ...... selection of an operating mode (0, 0, 0, 0) : initial mode this mode enables a change (see figure 15-1, 2) in memory that contains internal default values such as tone generation frequencies. in this mode, the pcm output pin acts to output idle patterns and the pcm input pin acts to input idle patterns. when a reset or power-down occurs or when power down is released, the device enters the initial mode about 200 ms after that. (0, 0, 0, 1) : reserved (0, 0, 1, 0) : normal speech mode (see figure 7-1) this mode enables call services between a slave telephone and a line (including tone generation) and detection of a dtmf tone and a call progress tone. the internal process enables the tone detector. the adpcm encoder/decoder, the tone generator, and the line echo canceler become operative and can be controlled by the contents of the control registers. (0, 0, 1, 1) to (0, 1, 0, 0) : reserved (0, 1, 0, 1) : line echo canceler expansion mode (see figure 7-2) this mode can expand the delay time of the line echo canceler up to 54 ms. concerning the internal processing, the adpcm encoder/decoder, the line echo canceler, and the tone generator become operative and can be controlled by the contents of the control registers. in addition, 2100 hz tone of pcmlni and pcmaci (bidirectional) can be detected. (0, 1, 1, 0) to (1, 1, 1, 1) : reserved cr0 initial value * b7 b6 b5 b4 b3 b2 b1 b0 pdwn pdn/rst ope mode3 ope mode2 ope mode1 ope mode0 00000000
23/38 ? semiconductor MSM7718-01 figure 7-1 normal speech mode figure 7-2 line echo canceler expansion mode note : ? when the msm7718 is used in line echo canceler expansion mode, set the tsti4 pin to digital 1. ? in line echo canceler expansion mode, the tone detector can detect not only call progress tone and dtmf tone by pmlni input but also 2100 hz tone by pcmlni and pcmaci input (bidirectional). ? the pcm codec does not operate in this mode. a capacitor is required between sgt and ground and between sgr and ground (see application circuit). note : ? when the msm7718 is used in normal speech mode, set the tsti4 pin to 0. ? in normal speech mode, the tone detector can detect call progress tone and dtmf tone by pmlni input. tone generator tone detector 23 ms line echo canceler adpcm decoder pcm codec msm7718 tone generator adpcm decoder msm7718 adpcm coder adpcm coder tone detector 54 ms line echo canceler pcm codec
24/38 ? semiconductor MSM7718-01 (2) cr1 (setting of adpcm operating mode and pcm i/o signals) cr1 initial value b7 b6 b5 b4 b3 b2 b1 b0 rx mute rx mlv2 rx mlv1 rx mlv0 00000000 adpcm mode adpcm reset pcm ad sel tx mute b7 ... adpcm algorithm 0: 32 kbps (g.726) 1: reserved b6 ... transmitter/receiver adpcm resetting (conforming to g.726) 1: reset b5 ... pcm i/o multiple timing control (pcmadi and pcmado pins) of the adpcm codec 0: time slot 1 1: time slot 2 b4 ... muting of transmitter adpcm data 1: mute b3 ... muting of receiver adpcm data 1: muting specified by bits b2, b1, and b0 is enabled. this bit is valid when the mute pin is 0. b2, b1, b0 ... setting of a receiver voice path mute level (mlv2, mlv1, mlv0) = (0, 0, 0) : through (0, 0, 1) : C 6 db (0, 1, 0) : C12 db (0, 1, 1) : C18 db (1, 0, 0) : C24 db (1, 0, 1) : C30 db (1, 1, 0) : C36 db (1, 1, 1) : mute
25/38 ? semiconductor MSM7718-01 (3) cr2 (setting of pcm i/o multiple control) cr2 initial value b7 b6 b5 b4 b3 b2 b1 b0 pcm ln sel0 pcm ac sel2 pcm ac sel1 pcm ac sel0 00000000 pcm pco mute pcm pci mute pcm ln sel2 pcm ln sel1 b7 ... on or off of the pcm signal of the transmitter side of the pcm codec (pcmpco pin) 0: on 1: off when this bit is 1 (off), the pcmpco pin transmits a pcm idle pattern. b6 ... on or off of the pcm signal of the receiver side of the pcm codec (pcmpci pin) 0: on 1: off when this bit is 1 (off), the pcmpci pin receives a pcm idle pattern. b5, 4, 3 .... pcm i/o multiple timing control (pcmlni and pcmlno pins) of the line echo canceler (see table 2) b2, 1, 0 .... pcm i/o multiple timing control (pcmaci and pcmaco pins) of the line echo canceler (see table 2) b5 b4 b3 0 0 0 none 001 1 010 2 011 3 corresponding time slot b2 b1 b0 () 100 4 101 5 110 6 111 7 table 2 pcm multiple timing control table note : w hen bits b5 to b3 or b2 to b0 are all zeros, the internal process inputs a pcm idle pattern. in this case, the outputs are all in high impedance state for all time slots.
26/38 ? semiconductor MSM7718-01 (4) cr3 (transmit/receive gain adjustment) b7, 6, 5, 4 ...... adjustment of the transmit signal gain [atttx] (see table 3) b3, 2, 1, 0 ...... adjustment of the receive signal gain [attrx] (see table 3) cr3 initial value b7 b6 b5 b4 b3 b2 b1 b0 rx gain3 rx gain2 rx gain1 rx gain0 00000000 tx gain3 tx gain2 tx gain1 tx gain0 b6 b5 b4 000 001 010 011 100 101 110 111 transmit signal gain C16 db C14 db C12 db C10 db C8 db C6 db C4 db C2 db b2 b1 b0 000 001 010 011 100 101 110 111 b7 1 1 1 1 1 1 1 1 b3 1 1 1 1 1 1 1 1 receive signal gain C16 db C14 db C12 db C10 db C8 db C6 db C4 db C2 db 000 0 db 000 0 0 0 db 001 +2 db 001 0 0 +2 db 010 +4 db 010 0 0 +4 db 011 +6 db 011 0 0 +6 db 100 +8 db 100 0 0 +8 db 1 0 1 +10 db 1 0 1 0 0 +10 db 1 1 0 +12 db 1 1 0 0 0 +12 db 1 1 1 +14 db 1 1 1 0 0 +14 db table 3 transmit/receive signal gain setting this table is for gains of transmit/receive voice signals.
27/38 ? semiconductor MSM7718-01 (5) cr4 (adjustment of tone generator gain) cr4 initial value b7 b6 b5 b4 b3 b2 b1 b0 rx tone gain3 rx tone gain2 rx tone gain1 rx tone gain0 00000000 tx tone gain3 tx tone gain2 tx tone gain1 tx tone gain0 b7, 6, 5, 4 ...... transmit side gain adjustment for the tone generator [atttgtx] (see table 4) b3, 2, 1, 0 ...... receive side gain adjustment for the tone generator [atttgrx] (see table 5) b7 b6 b5 b4 0000 0001 0010 0011 0100 0101 0110 0111 tone generator gain C36 db C34 db C32 db C30 db C28 db C26 db C24 db C22 db tone generator gain C20 db C18 db C16 db C14 db C12 db C10 db C8 db C6 db b7 b6 b5 b4 1000 1001 1010 1011 1100 1101 1110 1111 table 4 setting of transmit side gain of tone generator table 5 setting of receive side gain of tone generator b3 b2 b1 b0 0000 0001 0010 0011 0100 0101 0110 0111 tone generator gain C36 db C34 db C32 db C30 db C28 db C26 db C24 db C22 db tone generator gain C20 db C18 db C16 db C14 db C12 db C10 db C8 db C6 db b3 b2 b1 b0 1000 1001 1010 1011 1100 1101 1110 1111 settings of table 5 are made in relation to the following tone levels: dtmf tone (low frequency group) : C2 dbm0 dtmf tone (high frequency group) and other tone : 0 dbm0 for example, when bits b3, b2, b1, and b0 are set to 1, 1, 1, 1 (C6 db), the pcmlno pin outputs a tone of the following levels: dtmf tone (low frequency group) : C8 dbm0 dtmf tone (high frequency group) and other tone : C6 dbm0 the default value change command enables the gain adjustment by C1 db step. writing 13cah into the address 00d8h adds a gain of C1 db to the values in the above table. the default value is 1634h.
28/38 ? semiconductor MSM7718-01 (6) cr5 (setting of tone generator operating mode and tone frequency) cr5 initial value b7 b6 b5 b4 b3 b2 b1 b0 tone3 tone2 tone1 tone0 00000000 dtmf/others sel tx tone send rx tone send tone4 b7 ... selection of dtmf signal or others (s, f, or r tone) 0: others 1: dtmf signal b6 ... transmission of transmit side tone 0: not transmit 1: transmit b5 ... transmission of receive side tone 0: not transmit 1: transmit b4, 3, 2, 1, 0 ... setting of a tone frequency (see table 6) b4 b3 b1 b0 *0 00 *0 01 *0 10 *0 11 *0 00 *0 01 *0 10 *0 11 b2 0 0 0 0 1 1 1 1 description 697 hz + 1209 hz (1) 697 hz + 1336 hz (2) 697 hz + 1477 hz (3) 697 hz + 1633 hz (a) 770 hz + 1209 hz (4) 770 hz + 1336 hz (5) 770 hz + 1477 hz (6) 770 hz + 1633 hz (b) b4 b3 b1 b0 *1 00 *1 01 *1 10 *1 11 *1 00 *1 01 *1 10 *1 11 b2 0 0 0 0 1 1 1 1 description 852 hz + 1209 hz (7) 852 hz + 1336 hz (8) 852 hz + 1477 hz (9) 852 hz + 1633 hz (c) 941 hz + 1209 hz (*) 941 hz + 1336 hz (0) 941 hz + 1477 hz (#) 941 hz + 1633 hz (d) (b) when b7 = 0 (others) the table below lists default frequencies. 00000 to 00011 (b4, b3, b2, b1, b0) are tones, which are m odulated by sinewave. 01000 to 01011 are wamble tones, and 10000 to 10111 are single tones. for procedures to change frequencies, see the next page. table 6 setting of tone generator frequencies (a) when b7 = 1 (dtmf tone) description 400/0h C 16 hz sine wave modulation 3000/0h C 16 hz sine wave modulation 2700/0h C 16 hz sine wave modulation */*h C 16 hz sine wave modulation 513/636 hz 12 hz wamble 800/1000 hz 8 hz wamble 2000/2667 hz 8 hz wamble */*hz *hz wamble description 400 hz single tone 1000 hz single tone 2000 hz single tone 2667 hz single tone 1300 hz single tone 2080 hz single tone *hz single tone *hz single tone b4 b3 b2 b1 b0 100 00 100 01 100 01 100 11 101 00 101 01 101 10 101 11 110 00 110 01 110 10 110 11 111 00 111 01 111 10 111 11 b4 b3 b2 b1 b0 000 00 000 00 000 10 000 11 001 00 001 01 001 10 001 11 010 00 010 01 010 10 010 11 011 00 011 01 011 10 011 11
29/38 ? semiconductor MSM7718-01 frequencies of tones (other than dtmf signals) to be generated by the tone generator can be changed. tone frequencies can be changed in the initial mode. see figure 15-1 for procedures to change tone frequencies. the related subaddresses are shown below. subaddress 1 (frequency 1) *1 subaddress 2 (frequency 2) *1 subaddress 3 (time 1) *2 subaddress 4 (time 2) *2 168h 16ch 170h 174h 169h 16dh 171h 175h 16ah 16eh 172h 176h 16bh 16fh 173h 177h wamble subaddress 1 (frequency 1) *1 164h 165h 166h 167h modulation by 16 hz sine wave modulation by 16 hz sine wave subaddress 1 (frequency 1) *1 178h 179h 17ah 17bh single tone 17ch 17dh 17eh 17fh 8 hz wamble tone transmit single tone 62.5 ms time 1 62.5 ms time 2 62.5 ms b4 b3 b2 b1 b0 1000 0 1000 1 1001 0 1001 1 1010 0 1010 1 1011 0 1011 1 b4 b3 b2 b1 b0 0100 0 0100 1 0101 0 0101 1 b4 b3 b2 b1 b0 0000 0 0000 1 0001 0 0001 1 *1 transmitted tone frequency = a 8.192 (a = frequency) ex. when frequency = 1000 hz, 1000 8.192 = 9011.2 = 9011d (eliminate after the decimal point) = 2333h *2 wamble frequency (tone transmit time) = (a/b)/2 C 1 (a = transmitted tone frequency, b = wamble frequency) ex. when wamble frequency is 8 hz, tone frequency = 2667 hz. (2667/8)/2 C 1 = 166.69 = 166d (eliminate after the decimal point) = a6h
30/38 ? semiconductor MSM7718-01 (7)cr6 (vox function control) cr6 initial value b7 b6 b5 b4 b3 b2 b1 b0 vox in rx. noise level sel rx. noise lvl1 rx. noise lvl0 00000000 vox on/off on lvl1 on lvl0 off time b7 ... turns on or off the vox function. 0: off, 1: on b6, 5 ... setting of transmit side voice or silence detection level (0, 0) : C20 dbm0 (0, 1) : C25 dbm0 (1, 0) : C30 dbm0 (1, 1) : C35 dbm0 note: ? the detection level is changeable by inserting the pad of C1 db to C5 db in addition to the above values. ? write 16384 10 (Ca/20) at address "175h". (a=pad) example: when C1 db pad is inserted, 16384 10 (C (C1)/20) =18383.15=18383d (eliminate after the decimal point)=47cfh b4 ... setting of hangover time (t vxoff ) (see figure 6) 0: 160 ms 1: 320 ms b3 ... vox input signal (receiver side) 0: transmits an internal background noise. 1: transmits a voice reception signal. set the voxi pin to 0 to use this data. b2 ... setting of a receiver side background noise level 0: automatic internal setting 1: reserved b1, 0 ... externally-set background noise level (0, 0) : no noise (0, 1) : C55 dbm0 (1, 0) : C45 dbm0 (1, 1) : C35 dbm0 (8) cr7 (detection register : read-only) b7 ... detection of transmit side voice or noise 0: silence 1: voice b6, 5 ... transmit side silence level (indicator) (0, 0) : C10 db or less with respect to the detection level defined by cr6-b6, b5. (0, 1) : C5 to C10 db with respect to the detection level defined by cr6-b6, b5. (1, 0) : 0 to C5 db with respect to the detection level defined by cr6-b6, b5. (1, 1) : 0 db or more. refer to the detection level defined by cr6-b6, b5. note : the above outputs are valid only when the vox function is enabled by bit 7 of cr6. b4 ... external interrupt signal goes to a logic 0 when any change has been found in the tone detection results for call progress tone, dtmf tone, and 2100 hz tone. goes to a logic 1 when the cr7 control register is read out . the inverted state of this bit (b4) is output to the int pin. cr7 initial value b7 b6 b5 b4 b3 b2 b1 b0 det cpt 00000000 vox out silence level 1 silence level 0 int det dtmf busy/ det21l prm/ det21a
31/38 ? semiconductor MSM7718-01 b3 ... detection of a call progress tone 1: detected 0: not detected b2 ... detection of a dtmf tone 1: detected 0: not detected b1 ... pcmlni input 2100 hz tone detection (det21l: valid only in the line echo canceler expansion mode) 1: detected 0: not detected b0 ... pcmaci input 2100 hz tone detection (det21a: valid only in the line echo canceler expansion mode) 1: detected 0: not detected (9) cr8 (setting of line echo canceler operating mode) *1 names of control pins used in the msm7602 b7 ... through mode control bit for the line echo canceler. in the through m ode, rinl and sinl data is output directly to routl and soutl respec tively. 1: through mode 0: normal mode (echo cancellation) b6 ... selects whether or not to clear the coefficient 1 of the adaptive fir filter (laff) used by the line echo canceler. 1: resets the coefficient 0: normal operation b5 ... selects whether or not to clear the coefficient 2 of the adaptive fir filter (laff) used by the line echo canceler. 1: resets the coefficient 0: normal operation b4 ... howling detector (hd) on/off control 1: on 0: off b3 ... turns on or off the center clip function which forcibly sets the soutl output of the line echo canceler to minimum positive value when it is C57 dbm0 or less. 1: center clip function on 0: center clip function off b2 ... selects whether or not to update the coefficient of the adaptive fir filter (laff) for the line echo canceler. 1: coefficient fixed mode 0: normal mode (updates the coefficient) b1 ... turns on or off the att function which prevents howling from occurring by means of attenuators attsl and attrl provided for the rinl input and the soutl output of the line echo canceler. when a signal is input to rinl only, the attenuator attsl of the soutl output is activated. when a signal is input to sinl only or to both sinl and rinl, the attenuator attrl of the rinl input is activated. their att values are both about 6 db. 1: att off 0: att on b0 ... turns on or off the gain control function which controls the rinl input level and prevents howling from occurring by the gain controller (gainl) for the rinl input of the line echo canceler. the gain controller adjusts the rin level when it is C24 dbm0 or above, and it has the control range of 0 to C8.5 db. 1: gain control on 0: gain control off cr8 initial value b7 b6 b5 b4 b3 b2 b1 b0 lechld (adp)*1 10 000000 lecthr (hcl)*1 lecatt (att)*1 lecgc (gc)*1 leccclp (nlp)*1 lecclr1 lecclr2 lechd
32/38 ? semiconductor MSM7718-01 (10) cr9 : reserved (setting of acoustic echo canceler operating mode) cr9 initial value b7 b6 b5 b4 b3 b2 b1 b0 aechld (adp)*1 10000000 aecthr (hcl)*1 aecatt (att)*1 aecgc (gc)*1 aeccclp (nlp)*1 aecclr aechd *1 names of control pins used in the msm7602 b7 ... acoustic echo canceler through-mode control bit in this mode, rina data and sina data are through-output to routl and soutl respectively. 1: through mode 0: normal mode (echo cancellation) b6 ... not used b5 ... selects whether or not to clear the coefficient of the adaptive fir filter (aaff) for the acoustic echo canceler. 1: resets the coefficient 0: normal operation b4 ... howling detector (hd) on/off control 1: on 0: off b3 ... turns on or off the center clip function which forcibly sets the sout output of the acoustic echo canceler to a minimum positive value when it is C57 dbm0 or less. 1: center clip function on 2: center clip function off b2 ... selects whether or not to update the coefficient of the adaptive fir filter (aaff) for the acoustic echo canceler. 1: coefficient fixed mode 0: normal mode (updates the coefficient.) b1 ... turns on or off the att function which prevents howling from occurring by means of attenuators attra and attsa provided for the rina input and the souta output of the acoustic echo canceler. when a signal is input to rina only, the attenuator attsa of the souta output is activated. when a signal is input to sina only or to both sina and rina, the attenuator attra of the rina input is activated. their att values are both about 6 db. 1: att off 0: att on b0 ... turns on or off the gain control function which controls the rina input level and prevents howling from occurring by the gain controller (gaina) for the rina input of the acoustic echo canceler. the gain controller starts controlling when the rin level is C24 dbm0 or above and has the control range of 0 to C8.5 db. 1: gain control on 0: gain control off
33/38 ? semiconductor MSM7718-01 cr10 initial value b7 b6 b5 b4 b3 b2 b1 b0 00000000 send/ rec cmd3 mem sel adpcm mode1 adpcm mode0 cmd2 cmd1 cmd0 (11) cr10 (external memory (flash memory) interface control) b7 ... reserved (connection to the recording interface) b6 ... reserved (selection of external memory) b5, 4 ... reserved (selection of recording/playback adpcm compression mode) b3, 2, 1, 0 ... reserved (memory interface command) (0, 0, 0, 0) : nop (0, 0, 0, 1) : reserved (0, 0, 1, 0) : reserved (0, 0, 1, 1) : reserved (0, 1, 0, 0) : reserved (0, 1, 0, 1) : reserved (0, 1, 1, 0) : reserved (0, 1, 1, 1) : reserved (1, 0, 0, 0) : reserved (1, 0, 0, 1) : reserved (1, 0, 1, 0) : reserved (1, 0, 1, 1) : reserved (1, 1, 0, 0) : reserved (1, 1, 0, 1) : mdwr (change default) writes the data of cr17 (d0 to d7) and cr16 (d8 to d15) in the lower byte of default storage memory. the address is specified by a0 to a7 of cr11 and a8 to a15 of cr12. (1, 1, 1, 0) : reserved (1, 1, 1, 1) : reserved
34/38 ? semiconductor MSM7718-01 (12) cr11, 12, 13 (memory address register 1) cr11 initial value b7 b6 b5 b4 b3 b2 b1 b0 st7/ a7 st6/ a6 st5/ a5 st4/ a4 st3/ a3 st2/ a2 st1/ a1 st0/ a0 cr12 initial value b7 b6 b5 b4 b3 b2 b1 b0 st15/ a15 st14/ a14 st13/ a13 st12/ a12 st11/ a11 st10/ a10 st9/ a9 st8/ a8 cr13 initial value b7 b6 b5 b4 b3 b2 b1 b0 st20/ a20 st19/ a19 st18/ a18 st17/ a17 st16/ a16 cr11 to 13 : registers storing an address (a0 to a20) required for the default value change command since cr13 is assigned 0h, no setting is requited for it. (13) cr14, 15, 16 (memory address register 2) cr14 initial value b7 b6 b5 b4 b3 b2 b1 b0 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 cr15 initial value b7 b6 b5 b4 b3 b2 b1 b0 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 cr16 initial value b7 b6 b5 b4 b3 b2 b1 b0 sp20 sp19 sp18 sp17 sp16 cr14 to 16: when the default value change command is used, the bit 7 to bit 0 of cr16 corre- spond to the d15 to d8 of write data. note : cr14 and cr15 are the reserved registers.
35/38 ? semiconductor MSM7718-01 (14) cr17 (memory data register) cr17 initial value b7 b6 b5 b4 b3 b2 b1 b0 d7/ca7 d6/ca6 d5/ca5 d4/ca4 d3/ca3 d2/ca2 d1/ca1 d0/ca0 cr17 is the register to store the data used by the default value store command. (15) cr18 (setting of tone detection frequency, memory address register 3) d tone3 to 0: valid only when the tone generator is operating (except for the initial mode) b7, 6, 5, 4 ... not used b3, 2, 1, 0 ... setting of a tone frequency (see table 7) table 7 setting of tone detector frequencies frequency 697 hz + 1209 hz (1) 770 hz + 1209 hz (4) 852 hz + 1209 hz (7) 941 hz + 1209 hz (*) 697 hz + 1336 hz (2) 770 hz + 1336 hz (5) 852 hz +1336 hz (8) 941 hz + 1336 hz (0) frequency 697 hz + 1477 hz (3) 770 hz + 1477 hz (6) 852 hz + 1477 hz (9) 941 hz + 1477 hz (#) 697 hz + 1633 hz (a) 770 hz + 1633 hz (b) 852 hz + 1633 hz (c) 941 hz + 1633 hz (d) b3 b2 b1 b0 0000 0001 0010 0011 0100 0101 0110 0111 b3 b2 b1 b0 1000 1001 1010 1011 1100 1101 1110 1111 cr18 initial value b7 b6 b5 b4 b3 b2 b1 b0 00000 wa7 wa6 wa5 wa4 d tone3/ wa3 d tone2/ wa2 d tone1/ wa1 d tone0/ wa0
36/38 ? semiconductor MSM7718-01 direct access to default store memory (see figs.8-1, 8-2) the contents of the default store memory can be changed (e.g., to change tone detection levels and tone generation frequencies) in the initial mode (cr0-b3 to cr0-b0="0000"). refer to the following procedure: 1.set the default value store memory address (cr11, cr12). set the write data into cr16 and cr17. 2.when writing data to the upper byte, set the dmwr (change default) command (cr10-b3 to cr10-b0="1101"). default value store memory direct access set address. set write data. (1) cr12, cr11 cr16, cr17 set command to write in upper byte (dmwr) (2) cr10 end continue to write? yes no figure 8-1 flow chart of default value store memory direct access default value store memory data (cr16, cr17) address (cr11, cr12) figure 8-2 memory map for default value store memory direct access
37/38 ? semiconductor MSM7718-01 application circuit voice analog input (v i ) 1 m f 10 m f 1 m f 10 m f + C 1 m f 1 m fr1 r2 1 m fr3 r4 r5 r6 transmit gain (v gsx2 /v i ) = (r2/r1) (r4/r3) receive gain (v o /v vfro ) = 2 r5/r6 receiver output v o v dda sgt sgr ag dg1,2,3 ain1+ ain1C gsx1 ain2 gsx2 vfro pwi aout+ mck pdn / rst pdwn exck den din dout aoutC basic controller synca voxo voxi pcmpci pcmpco pcmlni pcmlno pcmaci pcmaco pcmadi pcmado a20-19 blkp syncp adpcm receive data pcm control msm7718 z l = 120 nf + 350 w v ddd1,2,3 bclka adpcm control adpcm transmit data ir is int + C a18-0 d7-0 we oe rp cs1 cs2
38/38 ? semiconductor MSM7718-01 notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tqfp100-p-1414-0.50-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.55 typ. mirror finish (unit : mm) package dimensions

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