View HM62W256LT-8SL_1936214.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hm62w256 series 256 k sram (32-kword 8-bit) ade-203-084h (z) rev. 8.0 nov. 1997 features low voltage operation sram operating supply voltage: 3.0 v to 3.6 v 0.8 m m hi-cmos process high speed access time: 55/70/85 ns (max) low power standby: 0.33 m w (typ) completely static memory no clock or timing strobe required directly lvttl compatible: all inputs and outputs ordering information type no. access time package hm62w256lfp-7t 70 ns 450 mil 28-pin plastic sop (fp-28da) hm62w256lfp-5slt hm62w256lfp-7slt hm62w256lfp-8slt 55 ns 70 ns 85 ns hm62w256lfp-7ult 70 ns hm62w256lt-7 70 ns 8 mm 14 mm 32-pin tsop (normal type) (tfp-32da) hm62w256lt-7sl HM62W256LT-8SL 70 ns 85 ns hm62w256ltm-7 70 ns 8 mm 13.4 mm 28-pin tsop (normal type) (tfp-28da) hm62w256ltm-5sl hm62w256ltm-7sl hm62w256ltm-8sl 55 ns 70 ns 85 ns hm62w256ltm-7ul 70 ns
hm62w256 series 2 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ss a10 cs nc i/o7 i/o6 i/o5 i/o4 i/o3 v i/o2 i/o1 i/o0 a0 nc a1 a2 oe a11 nc a9 a8 a13 we v a14 a12 a7 a6 a5 nc a4 a3 cc 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ss a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 v i/o2 i/o1 i/o0 a0 a1 a2 oe a11 a9 a8 a13 we v a14 a12 a7 a6 a5 a4 a3 cc hm62w256lfpseries hm62w256lt series hm62w256ltm series (top view) (top view) (top view) pin description pin name function a0 C a14 address inputs i/o0 C i/o7 input/output cs chip select we write enable oe output enable nc no connection v cc power supply v ss ground
hm62w256 series 3 block diagram ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a12 a5 a3 (msb) (lsb) a14 a13 a4 a8 a7 a6 i/o0 i/o7 cs we oe a2 a1 a0 a10 a11 (lsb) (msb) a9 v v cc ss row decoder memory matrix 512 512 column i/o column decoder input data control timing pulse generator read/write control
hm62w256 series 4 function table we cs oe mode v cc current i/o pin ref. cycle x h x not selected i sb , i sb1 high-z h l h output disable i cc high-z h l l read i cc dout read cycle (1)C(3) l l h write i cc din write cycle (1) l l l write i cc din write cycle (2) note: x: h or l absolute maximum ratings parameter symbol value unit power supply voltage *1 v cc C0.5 to 4.6 v terminal voltage *1 v t C0.5 *2 to v cc + 0.5 *3 v power dissipation p t 1.0 w operating temperature topr 0 to + 70 c storage temperature tstg C55 to +125 c storage temperature under bias tbias C10 to +85 c notes: 1. relative to v ss 2. v t min: C3.0 v for pulse half-width 50 ns 3. maximum voltage is 4.6 v recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit supply voltage v cc 3.0 3.3 3.6 v v ss 00 0v input high(logic 1) voltage v ih 2.0 v cc +0.3 v input low(logic 0) voltage v il C0.3 *1 0.8 v note: 1. v il min: C3.0 v for pulse half-width 50 ns
hm62w256 series 5 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) parameter symbol min typ *1 max unit test conditions input leakage current |i li |1 m av ss vin v cc output leakage current |i lo | 1 m a cs = v ih or oe = v ih or we = v il , v ss v i/o v cc operating power supply current (dc) i ccdc1 15 ma cs = v il , others = v ih / v il i i/o = 0 ma i ccdc2 10 ma cs 0.2 v, v ih 3 v cc C 0.2 v, v il 0.2 v, i i/o = 0 ma average operating power supply current hm62w256-5 i ccac1 30 ma min cycle, duty = 100 %, cs = v il , others = v ih /v il i i/o = 0 ma hm62w256-7 i ccac1 30 hm62w256-8 i ccac1 27 i ccac2 15 ma cycle time 3 1 m s, duty = 100% i i/o = 0 ma, cs 0.2 v, v ih 3 v cc C 0.2 v, v il 0.2 v standby power supply current i sb 0.1 1 ma cs = v ih i sb1 0.1 50 m a vin 3 0 v, cs 3 v cc C 0.2 v, 0.1 10 *2 0.1 5 *3 output low voltage v ol 0.4 v i ol = 2.0 ma 0.2 v i ol = 100 m a output high voltage v oh v cc C 0.2 v i oh = C100 m a 2.4 v i oh = C2.0 ma notes: 1. typical values are at v cc = 3.3 v, ta = +25 c and not guaranteed. 2. this characteristic is guaranteed only for l-sl version. 3. this characteristic is guaranteed only for l-ul version. capacitance (ta = 25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions input capacitance *1 cin 5 pf vin = 0 v input/output capacitance *1 c i/o 8 pfv i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
hm62w256 series 6 ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, unless otherwise noted.) test conditions input pulse levels: 0.4 v to 2.4 v input rise and fall time: 5 ns input reference level: 1.4 v output timing reference level: hm62w256-5: 1.4 v hm62w256-7/8: 0.8 v/2.0 v dout 500 w 1.4 v 50 pf* output load (including scope & jig) read cycle hm62w256 -5 -7 -8 parameter symbol min max min max min max unit notes read cycle time t rc 557085ns address access time t aa 55 70 85ns chip select access time t acs 55 70 85ns output enable to output valid t oe 30 35 45ns chip selection to output in low-z t clz 5 1010ns2 output enable to output in low-z t olz 555 ns2 chip deselection to output in high-z t chz 0 20 0 25 0 30 ns 1, 2 output disable to output in high-z t ohz 0 20 0 25 0 30 ns 1, 2 output hold from address change t oh 101010ns notes: 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested.
hm62w256 series 7 read timing waveform (1) ( we = v ih ) t t t t t rc aa acs oe olz t oh t ohz t chz valid data address cs oe dout high impedance valid address read timing waveform (2) ( we = v ih , cs = v il , oe = v il ) address t t rc t oh t oh valid data dout aa valid address read timing waveform (3) ( we = v ih , oe = v il ) *1 t acs dout valid data t chz cs t clz high impedance note: 1. address must be valid prior to or simultaneously with cs going low.
hm62w256 series 8 write cycle hm62w256 -5 -7 -8 parameter symbol min max min max min max unit notes write cycle time t wc 557085ns chip selection to end of write t cw 456075ns4 address setup time t as 000 ns5 address valid to end of write t aw 456075ns write pulse width t wp 40 50 55 ns 3, 8 write recovery time t wr 000 ns6 write to output in high-z t whz 0 25 0 25 0 30 ns 1, 2, 7 data to write time overlap t dw 303035ns data hold from write time t dh 000 ns output active from end of write t ow 101010ns2 output disable to output in high-z t ohz 0 20 0 25 0 30 ns 1, 2, 7 notes: 1. t ohz and t whz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is samples and not 100% tested. 3. a write occurs during the overlap (t wp ) of a low cs and a low we . a write begins at the later transition of cs going low or we going low. a write ends at the earlier transition of cs going high or we going high. t wp is measured from the beginning of write to the end of write. 4. t cw is measured from cs going low to the end of write. 5. t as is measured from the address valid to the beginning of write. 6. t wr is measured from the earlier of we or cs going high to the end of write cycle. 7. during this period, i/o pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. in the write cycle with oe low fixed, t wp must satisfy the following equation to avoid a problem of data bus contention, t wp 3 t whz max + t dw min.
hm62w256 series 9 write timing waveform (1) ( oe clock) t wc t cw t wp t as t ohz t dw t dh t aw t wr *1 address oe cs we dout din valid data valid address high impedance high impedance notes: 1. if cs goes low simultaneously with we going low or after we going low, the outputs remain in the high impedance state.
hm62w256 series 10 write timing waveform (2) ( oe low fixed) address we dout din t wc t cw t wp t whz t dw t dh *1 t as cs t aw *2 *4 *3 t oh t ow t wr valid data valid address high impedance notes: 1. if cs goes low simultaneously with we going low or after we going low, the outputs remain in the high impedance state. 2. dout is the same phase of the write data of this write cycle. 3. dout is the read data of next address. 4. if cs is low during this period, i/o pins are in the output state. therefore, the input signals of the opposite phase to the output must not be applied to them.
hm62w256 series 11 low v cc data retention characteristics (ta = 0 to +70 c) parameter symbol min typ * 1 max unit test conditions *6 v cc for data retention v dr 2.0 3.6 v cs 3 v cc C 0.2 v, vin 3 0 v data retention current i ccdr 0.05 30 *2 m av cc = 3.0 v, vin 3 0 v cs 3 v cc C 0.2 v, 0.05 8 *3 0.05 3 *4 chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r t rc *5 ns notes: 1. typical values are at v cc = 3.0 v, ta = 25 c and not guaranteed. 2. 10 m a max. at ta = 0 to +40 c. 3. this characteristics guaranteed for only l-sl version. 2.5 m a max. at ta = 0 to +40 c. 4. this characteristics guaranteed for only l-ul version. 0.6 m a max. at ta = 0 to +40 c. 5. t rc = read cycle time. 6. cs controls address buffer, we buffer, oe buffer, and din buffer. if cs controls data retention mode, other input levels (address, we , oe , i/o) can be in the high impedance state. low v cc data retention timing waveform cc v 3.0 v 2.0 v 0 v cs t cdr t r cs v ?0.2 v cc > dr v data retention mode
hm62w256 series 12 package dimensions hm62w256lfp series (fp-28da) 0.17 0.05 3.00 max 8.40 18.00 18.75 max 1.12 max 28 15 1 14 11.80 0.30 0 ?8 1.00 0.20 1.70 0.20 0.15 m 0.40 0.08 hitachi code jedec eiaj weight (reference value) fp-28da conforms conforms 0.82 g 1.27 0.38 0.06 + 0.15 ?0.10 0.20 0.15 0.04 unit: mm dimension including the plating thickness base material dimension
hm62w256 series 13 package dimensions hm62w256lt series (tfp-32da) hitachi code jedec eiaj weight (reference value) tfp-32da conforms conforms 0.26 g 0.10 0.08 m 0.50 8.00 0.22 0.08 14.00 0.20 1.20 max 12.40 32 116 17 0.17 0.05 0.13 0.05 0 ?5 8.20 max 0.45 max 0.50 0.10 0.80 0.20 0.06 0.125 0.04 unit: mm dimension including the plating thickness base material dimension
hm62w256 series 14 package dimensions hm62w256ltm series (tfp-28da) 0.10 m 0.55 8.00 0.22 0.05 13.40 0.30 0.05 1.20 max 11.80 0 ?5 21 22 7 8 8.20 max 0.10 +0.10 ?.05 0.50 0.10 0.80 0.63 max hitachi code jedec eiaj weight (reference value) tfp-28da ? ? 0.22 g 1 28 0.20 0.04 0.125 0.04 0.145 0.05 unit: mm dimension including the plating thickness base material dimension
hm62w256 series 15 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca. 94005-1897 u s a tel: 800-285-1601 fax:303-297-0447 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm62w256 series 16 revision record rev. date contents of modification drawn by approved by 0.0 mar. 27, 1992 initial issue y. saito y. kawashima 1.0 dec. 20, 1992 full specification y. saito y. kawashima 2.0 feb. 25, 1993 addition of hm62w256lt series y. saito y. kawashima 3.0 apr. 1, 1993 operation supply voltage: 3.0v C 3.6 v to single 3.3 v supply f = 2 mhz to f = 1 mhz function table not selected to standby absolute maximum rating relative to v cc to relative to v ss dc characteristics i ccac2 cycle time: 500 ns to 1 m s low v cc data retention timing waveforms change of notes k. imato t. matumoto 4.0 sep. 10, 1993 absolute maximum rating v t = C0.5 to v cc + 0.5 v to C0.5 to v cc + 0.3 v dc characteristics i ccdc1 (max): 5.0 ma to 15 ma i ccdc2 (max): 2.5 ma to 10 ma ac characteristics tdw (min): 30/40 ns to 30/35 ns addition of notes for low v cc data retention timing waveform y. saito k. yoshizaki 5.0 mar. 18, 1994 dc characteristics i ccac2 (max): 10 ma to 15 ma y. saito k. yashizaki 6.0 oct. 31, 1994 addition of hm62w256ltm series (tfp-28da) addition of block diagram ac characteristics addition of note 12 low v cc data retention characteristics i ccdr (typ): / m a to 0.2/0.2 m a note 2: 20 m a max at ta = 0 to 40 c to 10 m a max at ta = 0 to 40 c y. saito k. yoshizaki 7.0 jun. 19, 1995 feature low power (standby): 0.66 m w to 0.33 m w deletion of hm62w256lfp-8t deletion of hm62w256lt-8 deletion of hm62w256ltm-8 addition of hm62w256lfp-5slt/7ult addition of hm62w256ltm-5slt/7ult change of block diagram absolute maximum ratings terminal voltage v t : C0.5 to v cc + 0.3 v to C0.5 to v cc + 0.5 v m. higuchi k. yoshizaki
hm62w256 series 17 revision record (cont) rev. date contents of modification drawn by approved by 7.0 jun. 19, 1995 dc characteristics addition of note 3. i ccac1 (max): 30/27 ma to 30/30/27 ma i sb1 (typ): 0.2/0.2/ m a to 0.1/0.1/0.1 m a i sb1 (max): 50/10 m a to 50/10/5 m a capacitance cin (max): 8 pf to 5 pf c i/o (max): 10 pf to 8 pf ac characteristics addition of output timing reference level: hm62w256-5: 1.4 v change order of notes t rc (min): 70/85 ns to 55/70/85 ns t aa (max): 70/85 ns to 55/70/85 ns t acs (max): 70/85 ns to 55/70/85 ns t oe (max): 35/45 ns to 30/35/45 ns t clz (min): 10/10 ns to 5/10/10 ns t olz (min): 5/5 ns to 5/5/5 ns t chz (max): 25/30 ns to 20/25/30 ns t ohz (max): 25/30 ns to 20/25/30 ns t oh (min): 10/10 ns to 10/10/10 ns t wc (min): 70/85 ns to 55/70/85 ns t cw (min): 60/75 ns to 45/60/75 ns t aw (min): 60/75 ns to 45/60/75 ns t wp (min): 50/55 ns to 40/50/55 ns t whz (max): 25/30 ns to 25/25/30 ns t dw (min): 30/35 ns to 30/30/35 ns t ow (min): 10/10 ns to 10/10/10 ns low vcc data retantion characteristics i ccdr (typ): 0.2/0.2 m a to 0.05/0.05/0.05 m a i ccdr (max): 30/8 m a to 30/8/3 m a m. higuchi k. yoshizaki 8.0 nov. 1997 change of format change of subtitle

▲Up To Search▲

Price & Availability of HM62W256LT-8SL

	To Download HM62W256LT-8SL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .