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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com CS7665 digital color-space processor for ccd cameras features l itu-601 compliant image formatting l itu-656 and smpte-125/m transport l provides separate href and vref (or alternately vsync) signals l i 2 c control interface l limited secondary i 2 c bus master l automatic white balance l programmable gamma correction l 4:5 square-pixel interpolation l advanced color anti-aliasing filter l programmable luma gain and saturation control l fully programmable color separation matrix coefficients l supports images up to 1024 pixels wide, with no limitation on vertical size description the CS7665 is a low-power digital color-space proces- sor for ccd cameras. it provides all necessary digital image processing for standard four-color interline trans- fer ccd imagers. the CS7665 processes the mycg ccd imager data into ycrcb formatted component dig- ital video. internal processing includes color separation, automatic white balance, user programmable gamma correction curves, square pixel interpolation, and output formatting. the CS7665 employes an advanced color anti-aliasing filter which prevents both incorrect color and color noise that can undermine compression based systems. the CS7665 digital output is itu-601 compliant and supports both itu-656 and smpte- 125/m transport. additionally, href and vref (or vsync) output pins are provided to support older ana- log video encoders and the current zv-port definition. the CS7665 can support horizontal line widths of up to 1024 pixels. it has no limitations on the number of lines it can support in the vertical direction. the CS7665 is designed to work directly with the cs7615 ccd imager analog processor. ordering information CS7665-kq 0 to +70 c 64-pin tqfp (10 mm x 10 mm x 1.4 mm) i ccd data socondary deformatter i 2 c color separation i 2 c bus vref/vsync ycrcb i 2 c bus gamma correction white clock square pixel interpolation output formatter register interface block driver balance awb control master clocks href data may 97 ds232pp5
CS7665 2 ds232pp5 digital characteristics: (test conditions: t a =25 c ; v dd =5v; output load=30pf; input lev- els: logic 0=0v, logic 1=v dd .) switching characteristics: (test conditions: t a =25c ; v dd =5v; output load=30pf; input levels: logic 0=0v, logic 1=v dd .) notes: 1. clkin, f clk , is f clk2x /2 in non-interpolated mode and f clk2x *2/5 in interpolated mode. parameter symbol min typ max units ilogic inputs high-level input voltage v ih v dd -0.8 v low-level input voltage v il 0.8 v input leakage current i in 10.0 m a input pin capacitance c di 10 pf input clamp voltage -0.7 v logic outputs high-level output source current @ v oh = v dd -0.4v i oh 2ma low-level output sink current @ v ol = 0.4v i ol 2ma high-z leakage current i z 10.0 m a parameter symbol min typ max units digital input clkin2x frequency range (note 1) f clk2x 30 mhz input data setup time, di [9-0] t s1 5ns input data hold time, di [9-0] t h1 5ns digital output channel a/b digital data output clock: interleaved data parallel data f clkout 30 15 mhz mhz channel a/b output hold time t oh 0ns channel a/b output propagation delay t pd 1.9 5 ns digital output rise time with 30 pf load t r 15 ns digital output fall time with 30 pf load t f 15 ns
CS7665 ds232pp5 3 power consumption: (test conditions: t a =25 c ; v dd =5v; output load=no load; input levels: logic 0=0v, logic 1=v dd .) t s1 t h1 clkin2x clkin mosaic input data di [9-0] t h2 t s2 input timing diagram clkout t pd t oh output data do [a9-a0] do [b9-b0] output timing diagram parameter symbol min typ max units normal mode i dd 80 ma low power mode i dd 7ma
CS7665 4 ds232pp5 control port characteristics: (test conditions: t a =25 c ; v dd =5v; input levels: logic 0=0v, logic 1=v dd .) parameter symbol min typ max units scl clock frequency f scl 100 khz bus free time between transmissions t buf 4.7 m s start condition hold time t hdst 4.0 m s clock pulse width: high low t high t low 4.0 4.7 m s m s setup time for repeat start condition t sust 4.7 m s sdain hold time from scl falling t hdd 0 m s sdain setup time from scl rising t sud 0.25 m s sdaout and scl rise time t r tbd m s sdaout and scl fall time t f tbd m s setup time for stop condition t susp 4.0 m s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda s cl i 2 c timing diagram
CS7665 ds232pp5 5 recommended operating characteristics: absolute maximum ratings: note: specifications are subject to change without notice. parameter symbol min typ max units power supply voltage v dd 4.5 5.0 5.5 v ground to ground voltage differential 10 mv digital input rise/fall time 10 ns clkin level setup to clkin2x rising (non-interpolated) clkin level hold after clkin2x rising (non-interpolated) t s2 t h2 8 8 ns ns digital input voltage range 0 v dd v operating temperature range t a 070 c parameter symbol min max units power supply voltage v dd -0.3 7.0 v digital input voltage range gnd-0.3 v dd +0.3 v sustained digital output current 50 ma forced digital output voltage gnd-0.3 v dd +0.3 v output short circuit current ma operating temperature range t a 070c lead solder temperature (10sec duration) +260 c storage temperature range -65 +160 c
CS7665 6 ds232pp5 general description overview the CS7665 forms the heart of a four chip digital ccd camera. the four chips include the ccd im- ager, the cs7615 ccd digitizer, the CS7665 color space processor, and a vertical drive interface-chip for the ccd imager. most four-phase ccd imag- ers (and their associated vertical drives) can be used with the cs7615 digitizer and the CS7665 processor to form a simple and cost-effective ycrcb output format digital camera. the cs7615 and CS7665 together support imager formats rang- ing from 175x175 pixels up to 1000x1000 pixels. timing control is located in the cs7615 analog processor, while the CS7665 synchronizes itself to the cs7615 data stream by decoding the timing queues embedded in the cs7615 data stream. al- ternately, the CS7665 accepts horizontal and verti- cal timing signals on pin inputs. the block diagram in figure 1 illustrates a typical system interconnect. the CS7665 is a ccd camera color separation and color-space processor designed to process the four- color mosaic ccd imager data into itu-601 com- pliant full-motion 4:2:2 ycrcb digital component video. the CS7665 timing control is based on the main pixel clock (from the cs7615), and provides formatted component digital video compliant with smpte-125 and itu-656 transport protocols. the CS7665 provides the color separation matrix- ing of standard mycg chroma block data from in- dustry standard four-color ccd imagers, via the cs7615 quantizer. gamma correction and white balance adjustments functions are also included in the CS7665. the ycrcb (luminance and chromi- nace) data is output at the ccd pixel rate in 20-bit format, or at twice the pixel rate in 10-bit format (see discussion on digital output formats). the ycrcb output data from the CS7665 conforms to the itu-601/656 component digital video recom- mendation with embedded synchronization (see embedded eav and sav discussion). external horizontal and vertical synchronization signals are also provided to support the older transport proto- cols made popular by philips, as well as the pc- card zoom-video standard being used in notebook computers. the CS7665 incorporates an internal horizontal 4:5 scaler which may be turned on to increase the hor- izontal pixel count of the popular 512 horizontal pixel class of imagers to deliver digital video signal with 640 horizontal pixels, supporting the ubiqui- tous 640x480 image format. the cs7615 and CS7665 chip set support a wide range of imager formats up to 1000x1000 pixels, while incorporating an output format that follows ccd bias vertical drive timing cds/adc video codec +18v to +12v i 2 c bus 6 6 3 +5v CS7665 512x480 cs7615 ccd image processor 4:2:2, h.656 video i 2 c i 2 c figure 1. typical 4-chip digital ccd camera master clocks ccd data deformatter color separation white balance i2c interface register block ycrcb data clock driver i c bus 2 square pixel interpolarion secondary i c bus 2 vref/vsync href CS7665 awb control gamma correction output formatter figure 2. CS7665 block diagram
CS7665 ds232pp5 7 the itu-601 component digital video recommen- dation. the itu-601 document primarily specifies horizontal resolutions of 720 active horizontal pix- els (which is required for broadcast television com- patibility). many of todays digital video receivers are capable of operating with a wide range of video image formats. even though these digital video re- ceivers allow image formats not specified in the itu-601/656 recommendation, all of these receiv- ers expect the basic itu-601/656 protocol to be followed in terms of data sequence and timing queues. this is the case with the CS7665, where all output formats follow the itu-601/656 recommen- dation even if the image formats differ in horizontal and vertical pixel dimensions. the 640 pixel horizontal line the following discussion assumes that a 512 hori- zontal pixel class imager has been selected for the camera, and that the internal 4:5 horizontal scaler has been enabled. many other imager/scaler com- binations are possible, but the digital video format would not be significantly different than the 640x480 case described here. transmitted during each active line are 1280 mul- tiplexed luminance and chrominance values (640 luminance, 320 chrominance cr, and 320 chromi- nance cb values). eight of the remaining 280 inter- face clock intervals are used to transmit synchronizing information. the first of these 1560 interface clock intervals is designated line 0 word 0 for the purpose of reference only. the 1560 sample words per total line are therefore numbered 0 through 1559. intervals 0 through 1279, inclusive, contain video data. the interface clock intervals occurring during dig- ital blanking are designated 1280 through 1559. in- tervals 1280 through 1283 are reserved for the end- active-video (eav) timing reference. intervals 1556 through 1559 are reserved for the start-of-ac- tive-video (sav) timing reference. figure 3 indi- cates the values of the timing reference signals (f, v, h) for an entire frame of interlaced video. please note the scan lines are numbered 1 through 525 consecutively in the time domain (spatially they are interlaced). table 2 defines the 1560 samples of a single scan line of video. embedded itu-656 eav and sav timing the lines in figure 3 are numbered 1 through 525. video data is not present on lines 1 to 19 or 264 to 282, which constitute the vertical blanking periods. the vertical blanking is in full line increments, where y samples are set to 10h, while cb and cr samples are set to 80h. the interval starting with eav and ending with sav is the digital horizontal synchronization, which occurs on every line. it is implicit that the timing reference signals are contiguous with the video data and continue through the vertical blanking interval. each timing reference signal consists of the four-word sequence in table 1. the first three words are a preamble, fol- lowed by a fourth word indicating a) even field (field 2) identification, b) state of vertical blanking, and c) state of horizontal blanking. table 2 details the timing reference format. the protected bit states are dependent on the f, v, and h bits accord- ing to table 3. table 1. timing reference signal value description first byte ffh fixed second byte 00h fixed third byte 00h fixed fourth byte xyh see table 3
CS7665 8 ds232pp5 table 2. detail of scan line for 640x480 image word data content pixel notes 1280 1111 1111 640 eav 1281 0000 0000 eav 1282 0000 0000 eav 1283 1fv1 p3p2p1p0 641 eav 1284 1000 0000 642 fro pixels 642 to 777 cr = cb = 80h y = 10h 1285 0001 0000 1286 1000 0000 1287 0001 0000 643 1552 1000 0000 776 1553 0001 0000 1554 1000 0000 1555 0001 0000 777 1556 1111 1111 778 sav 1557 0000 0000 sav 1558 0000 0000 sav 1559 1fv0 p3p2p1p0 779 sav 0cb0 0 start of digital video 1y0 for vblank line 1 to 19 and 264 to 283 cr = cb = 80h y = 10h 2cr0 3y1 1 4cb2 2 5y2 6cr2 7y3 3 2n cbn n for active pixels 20 through 263 and 283 to 525 for n=even from pix- els 0 to 638 2n + 1 yn 2n + 3 crn yn+1 n+1 1272 cb636 636 1273 y636 1274 cr636 1275 y637 637 1276 cb638 638 1277 y638 1278 cr638 1279 y639 end of digital video
CS7665 ds232pp5 9 protected state bits - in table 3 and 4, h, v, and f bits provide all the necessary timing and state infor- mation. bits 0 to 3 provide error detection and cor- rection information. the protection bits allow for correction of single-bit errors and detection of two- bit errors. the f or field bit indicates which of the interlaced fields is active, the first/odd field which contains 262 lines, or the second/even field which contains 263 lines. table 3. eav and sav timing reference signal detail. vertical blanking vertical blanking horizontal blanking horizontal blanking active video field 1 active video field 2 eav h=1 sav h=0 640 779 0 639 f=1 lines 266 to 3 f=0 lines 4 to 265 lines 1 to 19 v=1 lines 20 to 263 v=0 lines 264 to 282 v=1 lines 283 to 525 v=0 figure 3. horizontal and vertical timing states bit position word 1281 and 1556 word 1281 and 1557 word 1282 and 1558 word 1283 and 1589 description 71001 fixed 6100f f = 0 during field 1/odd f = 1 during field 2/even 5100v v = 0 during active video v = 1 during vertical blanking 4100h h = 1 at end of active video h = 0 at start of active video 3100p3see protected bits state table 4 2100p2see protected bits state table 4 1100p1see protected bits state table 4 0100p0see protected bits state table 4
CS7665 10 ds232pp5 table 4. eav and sav protected bit states detail. individual timing and synchronization signals in addition to the embedded eav and sav timing signals, the CS7665 provides individual synchroni- zation output signals which are employed by many video encoder circuits. these synchronization sig- nals are typically used to interface the h.656 digital video stream to other components and subsystems. the individual synchronization signals include hrefout and vrefout. hrefout hrefout is an active-high signal indicating when active pixel data is being transmitted on do a[0-9] or do b[0-9] . hrefout is low when non-active picture data is being transmitted during horizontal blanking. depending on the mode of op- eration, the hrefout signal follows either the hrefin signal or the href defined by the eav and sav code. vrefout/vsync vrefout is an output signal that is active high when the CS7665 is putting out active video lines. the active-low portion of this signal defines the vertical blanking period. alternately, when the zv mode bit in register 06h is set, this output behaves as a vsync signal appropriate for zv ports. the vsync signal is active-high during the first six horizontal line period of every field. the transition in vsync signal lags the href signals rising edge during odd field and leads the rising edge of href during even field. digital output formats the CS7665 outputs data in a 20-bit wide format at the output pixel clock rate. alternately, the data can be multiplexed in a 10-bit format at a 2x output pix- el clock rate. figures 4 and 5 detail the clock and data relationships. the output data transitions on the falling edge of the clock, such that the rising edge of the clock can be used to latch the data into subsequent circuitry. the CS7665 delivers 4:2:2 component digital vid- eo output data in ycrcb format. the digital out- puts can be configured for 10-bit interleaved y and crcb data, or for 20-bit parallel operation. the in- terl bit of the operational control register 06h determines which output format is active. logic 0 places the CS7665 in interleave mode with output data on channel a. logic 1 places the CS7665 in non-interleaved mode where luminance data is out- put on channel a and chrominance data is output on channel b. in 20-bit wide mode, the luminance information is output on do a[0-9] and the chrominance informa- tion is output on do b[0-9] . bit 7 bit 6 (f) bit 5 (v) bit 4 (h) bit 3 (p3) bit 2 (p2) bit 1 (p1) bit 0 (p0) 10000000 10011101 10101011 10110110 11000111 11011010 11101100 11110001
CS7665 ds232pp5 11 table 5. interl controlled output formats the CS7665 supports both 8-bit and 10-bit opera- tion as per the itu h.656 recommendation. the h.656 recommendation defines the primary data path as 8-bits wide with two additional fractional bits that can be used to form a 10-bit data path. if only 8-bits of output data are used, it is very impor- tant to msb align the CS7665 and the data path. this is essential to properly pass the image data and synchronization signals to the next component. internal horizontal 4:5 scaler the internal horizontal 4:5 scaler is used to bridge between broadcast based image formats (like the common 512 horizontal pixel imagers) and com- puter based image formats (as with the 640x480 vga standard). the 4:5 data rate scaler will con- vert the standard 512 horizontal pixel width ccd imager used for cam-corders into the vga 640x480 format. the scaler is enabled/disabled via the interp pin on both the CS7665 and the cs7615 (if that device is used in the system.) the filtering done in the scaler should not generate any noticeable image artifacts. clkin and clkin2x input timing the clkin, pin 55, will always require a primary pixel rate clock source. ccd manufacturers gener- ally specify a pixel clock frequency that is compat- ible with one of the analog encoders that can be used with a given imager. if an analog encoder is used in the camera to generate an analog output, the pixel clock frequency expected by the encoder must be matched precisely. digital display sys- tems, such as those based on vga graphics adaptor cards and zoom video systems, are generally not sensitive to pixel clock frequency, and will tolerate a wide range of pixel and frame rates. specific pixel-rate clock frequencies for analog en- coders include 14.31818 mhz for 768h imagers, the primary itu-601 13.5 mhz for 720h imagers, and down to 12.272727mhz clock rates for 640h vga format imagers. the clkin2x, pin 56, will either require a 5/2x ccd pixel rate clock when the internal 4:5 scaler is enabled or a 2x times the 1x ccd pixel rate clock in non-interpolation mode. clkout clkout follows the output data rate. in the non- interleaved mode the clock output is at the output luma sample rate whereas in the interleaved mode the clock output is at 2x the output luma sample rate. parallel interl = 1 interleaved interl = 0 doa[0-9] 10-bit luminance data interleaved 10-bit luminance data and 10-bit chromi- nance data dob[0-9] 10-bit chominance data high-z clkout pixel rate 2x pixel rate
CS7665 12 ds232pp5 figure 4. 2x pixel clock, 10-bit interleaved output format for 640x480 image format. figure 5. 1x pixel clock, 20-bit parallel output for a 640x480 image. 24.5454mhz clkout do [9-0] line 3 pixel 776 to line 4 pixel 3 do [9-0] line 263 pixel 638 to line 264 pixel 645 do [9-0] line 525 pixel 638 to line 1 pixel 645 cb638 y638 cr638 y639 ffh 00h 00h 9dh 80h 10h 80h 10h 80h 10h eav ffh 00h 00h f1h 80h 10h 80h 10h 80h 10h 80h 10h 80h 10h eav ffh 00h 00h abh 80h 10h 80h 10h 80h 10h 80h 10h 80h 10h sav a a a note: eav, sav, and blanking data values are based on the 8 msb's of the output data, the two lsbs are considered fractional. 12.2727mhz clkout href do [9-0] do [9-0] 10h y0 y1 y2 y3 y4 y633 y634 y635 y636 y637 y638 y639 10h 80h cb0 cr0 cb2 cr2 cb4 cb632 cr634 cb634 cr636 cb636 cr638 cb638 80h a b note: eav, sav, and blanking data values are based on the 8 msb's of the output data, the two lsbs are considered fractional.
CS7665 ds232pp5 13 internal processing the internal operation of the CS7665 can be sepa- rated into several distinct blocks. the following section provides an overview of how these blocks operate and interact. input data format and chroma separator the CS7665 accepts up to 10-bit mycg image data from the ccd digitizer, cs7615, or other suit- able ccd analog processing unit. the CS7665 in- ternally converts the four-color ccd mycg interlaced image data into the various color space formats. these include rgb and yuv, as well as ycrcb. the individual image adjustments are per- formed in the most appropriate color space repre- sentation. ultimately the image is converted to ycrcb format for outputting data. luminance edge enhancement and color saturation control edge enhancement is performed in ycrcb color space and is a complement to the spatial anti-alias- ing filtering performed in the chroma separator. color saturation control color saturation control is via the red saturation and the blue saturation control register addresses 0ah and 0bh. white balance and gamma correction the red and blue color balances can be adjusted through the i 2 c control port. during the awb (au- tomatic white balance) sequence the red level is ad- justed to minimize the (y-r) difference component; similarly the blue level is adjusted to minimize the (y-b) color difference component. the red balance is accessed through register 08h, and the blue balance is accessed through register 09h. internal register structure and user interface the user interface describes the users external view of the CS7665 and the basic control opera- tions. these areas include digital data output modes and organization, timing and synchronization sig- nals, i 2 c interface, and miscellaneous controls. the CS7665 has two i 2 c ports: (i) a slave i 2 c port called the primary i 2 c port, and (ii) a secondary i 2 c port with limited i 2 c master capabilities. the pri- mary i 2 c port allows an external controller to con- trol the CS7665. it is assumed the external controller will also directly control any other i 2 c slave devices on the camera board. this is the nor- mal i 2 c operation mode of CS7665. the secondary i 2 c port, on the other hand, may be used to control all the other slave devices on a camera board through CS7665 only. this feature is useful when the external i 2 c controller is used to control multi- ple cameras. when used in this configuration the 4bytemode pin of CS7665 must be tied high and the device is operated in four-byte mode. operating CS7665 in normal i 2 c configuration in normal mode the CS7665 is connected as a slave device to an external i 2 c controller through the pri- mary i 2 c port. the connection is done via a two- wire serial bus. other i 2 c devices on the camera may also share the same serial bus. the external controller communicates with the i 2 c devices by sending and receiving short packets of 8-bit words in accordance with the i 2 c protocol. each device on the i 2 c bus has unique 8-bit write and 8-bit read station addresses. the two addresses of the device differ only in the lsb. the packets contain the sta- tion address of the target device, the desired regis- ter address, and data. there are three packet formats: write format, address set format, and read format. each packet is addressed to a device by the station ad- dress. the lsb of the station address is the data di- rection bit. this bit is set low in the write and address set packets, and it is set high for read packets. the receiver can read and write to non-existent registers within the selected device.
CS7665 14 ds232pp5 write operations will have no effect; read op- erations will return a value of 00h. station address the CS7665 default station address is 34h for writes and 35h for reads. the station address can be changed by writing a new base station address to internal i 2 c register ffh. write operations the write format consists of a three-byte packet. the first byte is the station address with the data di- rection bit set low to indicate a write. the second byte is the device register address (0..255). the third byte is the register data (0..255). no extra bytes should be sent. table 6. write format packet address set operation the address set format consists of a two-byte packet which sets the address of a subsequent read operation. the first byte of the station ad- dress with the lsb (data direction bit) set low to indicate a write operation. the second byte is the register address (0..255). the address set for- mat is the same as the write format, without the register data. table 7. address set format packet operation read operations the read operation consist of two or more bytes of packet. the first byte is the station address with the lsb (data direction bit) set high indicating a read operation. the addressed device then sends one or more bytes back from the register last ad- dressed by the previous write operation, or ad- dress set operation. table 8. read format packet. operating CS7665 in four-byte i 2 c config- uration in this configuration the external controller talks only to CS7665 through the primary i 2 c interface. all the other slave devices on the camera board are tied to the secondary i 2 c port of CS7665. write and read packets only are defined in four-byte mode. independent address set operation to slave devices on secondary i 2 c bus is not allowed in four-byte mode. four-byte-mode is active when the 4bytemode pin is logic high. byte sequence write format packet detail first byte station address with lsb set low second byte device register address (0..255) third byte register data (0..255) byte sequence address set format packet details first byte station address with lsb set low second byte device register address (0..255) byte sequence read format packet details first byte station address with lsb set high; source device then returns one byte of register data (0..255) second byte returned data from CS7665 external eprom secondary i 2 c primary i 2 c cs7615 CS7665 controller encoder figure 6. i 2 c configuration showing primary and secondary i 2 c busses. to other sub-systems
CS7665 ds232pp5 15 write operations in four-byte mode: all write operations from external controller, through the CS7665, to any slave device must use the four-byte mode; his includes writing to CS7665 itself. the external controller sends a four-byte write command to CS7665 which initiates a write operation to the destination slave device and sets the i2cbusy bit in status register. exter- nal controller can poll the status register to check if CS7665 has completed the command . CS7665 has a one command buffer which allows the external controller to queue one additional command while the current command is still being executed. if more than one command is sent before the i2cbusy bit is cleared CS7665 saves only the last command and executes it after the current one is completed. commands that involve writing or reading only to CS7665 registers are not put in the queue and are executed immediately without af- fecting any transactions going on in the master i 2 c interface. any attempt by the external i 2 c controller to write to CS7665 registers while CS7665 is busy initializ- ing from eprom will be ignored. however, reads from CS7665 are allowed. if during a read or write operation to a slave device CS7665 fails to receive an acknowledge bit the execution of the command is aborted and the nodev bit in the status register is set high. this bit remains set unless it is explicitly cleared by writing to it or a new command is written to CS7665. table 9. four-byte write format packet read operation the read operation in four-byte mode first re- quires a three-byte read-trigger packet to CS7665. the first byte is the station address of CS7665 with lsb set. the second byte is the target slave devices station address with the lsb (data direction bit) set high. the third byte is the regis- ter address (0..255). table 10. read-trigger packet in four-byte mode the read-trigger packet initiates a read operation by CS7665 from the target slave device on the secondary i 2 c bus. the status register on CS7665 may be checked to see if the read operation has been completed. i2cbusy bit in status register 01h is set to zero when the operation is completed. on completion of read from the target device, CS7665 places the read data in a slave data hold register at address 19h. the external controller can read this data through the primary i 2 c port. this re- quires first performing an address set opera- tion to set the address to 19h and then sending a one-byte station address indicating read to CS7665. the data from register 19h is then returned by CS7665. table 11. address set for slave data hold register in four-byte mode byte sequence write format packet detail first byte station address of CS7665 with lsb set low second byte station address of target slave device with lsb set low third byte device register address (0..255) fourth byte register data (0..255) byte sequence read-trigger format packet details first byte CS7665 station address with lsb set low second byte target device station address with lsb set high third byte device register address (0..255) byte sequence write format packet detail first byte station address of CS7665 with lsb set low second byte station address of CS7665 with lsb set low third byte slave data hold reg. address 19h
CS7665 16 ds232pp5 table 12. read format packet. initializing slave devices on secondary i 2 c bus from an eprom. an eprom may be attached to the secondary i 2 c bus for initialization purposes. a reset to CS7665 initiates a download of register values from the eprom into any of the slave devices on the sec- ondary i 2 c bus. the eprom is assumed to be at station address a0h. if during initialization, CS7665 does not receive an acknowledge bit from the eprom, all transactions with the eprom are aborted and nodev status bit is set in status reg- ister at address 01h. at the end of reset period, the CS7665 fetches three bytes from the eprom. these three bytes repre- sent destination station address, register address, and data. CS7665 then writes the data into the spec- ified register of the destination station. after com- pleting this process CS7665 reads the next three bytes from the eprom. the number of registers to be read and initialized from the eprom is loaded into a two-byte count register in CS7665. the top six bytes in the eprom must specify the num- ber of triple-bytes to be read from the eprom. the maximum number of triple-bytes allowed in the eprom space is 2 kbytes/3. while the CS7665 is downloading from the eprom, the initact bit is set in the status regis- ter of CS7665. all attempts to write to CS7665 reg- isters by the external controller will be ignored during this time. a typical map of the eprom table is shown in fig- ure 7. the only exception to this organization is data for the CS7665 gamma table. the data for the gamma table is organized as shown in figure 8. byte sequence read format packet details first byte CS7665 station address with lsb set high. second byte returned data from register 19h of CS7665 CS7665 station address[7] +w 1ah (addrs of low byte count) count value CS7665 station address[7] +w 1bh (addrs of high byte count) count value dest. station address + w dest. device address data value dest. station address + w eprom block 000 (binary) address 00h figure 7. map of eprom table for initialization of registers CS7665 station address[7] +w 0ch (gamma reg. addrs) data = select rgb ram data [gamma loc 00h] data [gamma loc 01h] data [gamma loc ffh] figure 8. map of eprom table for storing gamma ram initialization data.
CS7665 ds232pp5 17 master reset register (00h) mr0 setting bit mr0 to logic high will initiate a CS7665 master reset equivalent to executing an external reset using the reset pin. all registers will be placed in their default state, and the download of any external eprom present on the secondary i 2 c bus will be initiated. the bit is self-cleared. status register (01h) evnfld logic high indicates even field of interline-transfer ccd. logic low indicates odd field of interline- transfer ccd. this bit provides a course means of synchronizing to the field rate. nodev logic high indicates that the addressed slave device on the secondary i 2 c bus did not respond. i2cbusy logic high indicates that the CS7665 secondary i 2 c master is busy accessing the addressed slave device. initact logic high indicates the CS7665 master is busy initializing registers from the external i 2 c eprom on the secondary i 2 c bus (if present). digital gain register (03h) dg0..dg4 controls the digital gain applied to the y (luminance) signal after the rgb to ycrcb converter block. the range of gains are from 0 to 31/8 in increments of 1/8. a gain of 0, indicates no brightness. feature control register (05h) awb the automatic white balance procedure is initiated by pointing to a white scene and setting this bit high. the bit will return a logic high while the awb procedure is in progress. setting this bit low will have no effect. this bit will always be read as a 0 when the awb is not in progress. gamon the gamma correction from the gamma ram look up table is applied to the video signal in r-g-b space when this bit is set high. the gamma ram is a fully user programmable, 256 entry look up table. lumoff setting lumoff bit high disables the luma peaking filter. chroff setting the chroff bit high disables the chroma low-pass filter for minimizing color aliasing. 76543210 mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 -------w 76543210 res res res res initact i2cbusy nodev evnfld ---- rrrr 76543210 res res res dg4 dg3 dg2 dg1 dg0 - - - r/w r/w r/w r/w r/w 76543210 res res res chroff lumoff gamon awb res - - - r/w r/w r/w r/w -
CS7665 18 ds232pp5 operational control register (06h) oblu logic high causes the first line after vref of the odd field to be processed as a blue line. logic low causes the first line of the odd field to be processed as a red line. eblu logic high causes the first line after vref of the even field to be processed as a blue line. logic low causes the first line of the even field to be processed as a red line. pospix logic 1 causes the first pixel of the first line to be treated as a positive pixel in the color separation block. logic 0 causes the first pixel to be treated as a negative pixel. try toggling this bit if the colors appear reversed. oe the output enable bit operates in conjunction with the external output enable pin, as illustrated in table 13. inref logic 1 causes CS7665 to accept href input and vref input pins as the reference inputs signals. eav and sav codes in the ccd data stream are ignored. logic 0 causes the internal de-formatter to decode and follow the embedded eav and sav codes sent from the ccd digitizer (as with the cs7615). interl logic 0 places the digital outputs in interleaved mode with alternate y and crcb data on the do [a0..a9 ] 10-bit output. logic 1 places the digital outputs in parallel mode with y data on do [a0..a9 ] and crcb on the do [b0..b9] outputs. zv a logic 1 causes vrefout pin to output a vsync signal compatible with zv port specifications as well as many composite video encoders. red balance register (08h) rb0..rb7 the red balance register controls the red contribution to the r-y chrominance signal. when the reg- ister value is 00h, the red contribution is minimized; when the register value is ffh, the red contribu- tion is maximized. when the awb correction is in progress, this register value is adjusted such that the absolute magnitude of the r-y signal is minimized. 7654 3210 res zv interl inref oe pospix eblu oblu - r/w r/w r/w r/w r/w r/w r/w 76543210 rb7rb6rb5rb4rb3rb2rb1rb0 oe bit oe pin digital outputs 0 0 enabled 0 1 high-z 1 0 high-z 1 1 enabled table 13. oe pin and bit operation
CS7665 ds232pp5 19 blue balance register (09h) bb0..bb7 the blue balance register controls the blue contribution to the b-y chrominance signal. when the reg- ister value is 00h, the blue contribution is minimized; when the register value is ffh, the blue contri- bution is maximized. when the awb correction is in progress, this register value is adjusted such that the absolute magnitude of the b-y signal is minimized. red saturation register (0ah) rs0..rs7 the red saturation register value controls the amplitude of the r-y chrominance signal. when the register value is 00h, the amplitude of the r-y is minimized; when the register value is ffh, the am- plitude of the r-y is maximized. blue saturation register (0bh) bs0..bs7 the blue saturation register value controls the amplitude of the b-y chrominance signal. when the register value is 00h, the amplitude of the b-y is minimized; when the register value is ffh, the am- plitude of the b-y is maximized. gamma correction register (0ch) writing to the gamma register (0ch) selects the r, g, and/or b ram. continuing data writes without sending a stop bit after the register write results in writes to the ram locations starting with 00h and continuing to ffh. reads from register 0ch function in a similar way. note: all three gamma rams may be selected for simultaneous writes, but read should be done one ram table at a time. gc0 logic 1 selects blue gamma ram for subsequent access. gc1 logic 1 selects green gamma ram for subsequent ram access. gc2 logic 1 selects red gamma ram for subsequent ram access. gc0..gc7 provide r/w access to ram after gamma ram table has been selected. 76543210 bb7 bb6 bb5 bb4 bb3 bb2 bb1 bb0 76543210 rs7 rs6 rs5 rs4 rs3 rs2 rs1 rs0 76543210 bs7 bs6 bs5 bs4 bs3 bs2 bs1 bs0 76543210 gc7 gc6 gc5 gc4 gc3 gc2 gc1 gc0 --------
CS7665 20 ds232pp5 test control a register (0eh) test control b register (0fh) yr coefficient register (10h) color separation and color space conversion coefficient. crr coefficient register (11h) color separation and color space conversion coefficient. cbr coefficient register (12h) color separation and color space conversion coefficient. yg coefficient register (13h) color separation and color space conversion coefficient. crg coefficient register (14h) color separation and color space conversion coefficient. 76543210 tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 reserved 76543210 tcb7 tcb6 tcb5 tcb4 tcb3 tcb2 tcb1 tcb0 reserved 76543210 yr7 yr6 yr5 yr4 yr3 yr2 yr1 yr0 -------- 76543210 crr7 crr6 crr5 crr4 crr3 crr2 crr1 crr0 -------- 76543210 cbr7 cbr6 cbr5 cbr4 cbr3 cbr2 cbr1 cbr0 -------- 76543210 yg7 yg6 yg5 yg4 yg3 yg2 yg1 yg0 -------- 76543210 crg7 crg6 crg5 crg4 crg3 crg2 crg1 crg0 --------
CS7665 ds232pp5 21 cbg coefficient register (15h) color separation and color space conversion coefficient. yb coefficient register (16h) color separation and color space conversion coefficient. crb coefficient register (17h) color separation and color space conversion coefficient. cbb coefficient register (18h) color separation and color space conversion coefficient. slave data hold register (19h) when an external i 2 c controller initiates a register read from a slave device on the secondary i 2 c bus through CS7665, the returned data is placed in this register. the external controller may then read the data from the slave data hold register. eprom count low byte register (1ah) lower byte of the number of triple-bytes to be read from eprom upon reset of CS7665. eprom count high byte register (1bh) upper byte of the number of triple-bytes to be read from eprom upon reset of CS7665. 76543210 cbg7 cbg6 cbg5 cbg4 cbg3 cbg2 cbg1 cbg0 -------- 76543210 yb7 yb6 yb5 yb4 yb3 yb2 yb1 yb0 -------- 76543210 crb7 crb6 crb5 crb4 crb3 crb2 crb1 crb0 -------- 76543210 cbb7 cbb6 cbb5 cbb4 cbb3 cbb2 cbb1 cbb0 -------- 76543210 76543210 rrrrrrrr 76543210 76543210 rrrrrrrr 76543210 76543210 rrrrrrrr
CS7665 22 ds232pp5 version (major) register (1ch) the major version register in CS7665 rev. a is assigned the value ffh. with each major revision the value is de- creased by 1. version (minor) register (1dh) the minor version register in CS7665 rev. a is assigned the value 00h. with each minor revision the value is in- creased by 1. low power register (20h) pd0 setting bit pd0 to 1 will place the CS7665 in low power mode. test enable register (21h) station address register (ffh) cs7615 station address , 7 msbs (the lsb of the complete 8-bit station address is determined by the lsb which acts as a read/write direction bit) . interpolation test register (24h) 76543210 76543210 rrrrrrrr 76543210 76543210 rrrrrrrr 76543210 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 -------r/w 76543210 te7 te6 te5 te4 te3 te2 te1 te0 reserved 76543210 res sa6 sa5 sa4 sa3 sa2 sa1 sa0 r r/w r/w r/w r/w r/w r/w r/w 76543210 reserved
CS7665 ds232pp5 23 pin descriptions clkin2x clkin interp scanmode nc nc nc nc sclsec sdasec di0(lsb) di1 di2 di3 di4 vdd gnd di5 di6 di7 di8 di9(msb) reset vrefin hrefin vrefout hrefout scl sda gnd vdd dob0(lsb) 41 43 45 47 33 35 37 39 7 5 3 1 15 13 11 9 gnd vdd clkout testpinb doa0(lsb) dob9(msb) dob8 dob7 dob6 dob5 dob4 dob3 doa2 gnd vdd doa1 doa6 doa5 doa4 doa3 4bytemode doa9(msb) doa8 doa7 transp field oe scanenable gnd vdd dob2 dob1 17 19 21 23 25 27 29 31 63 61 59 57 55 53 51 49 8 6 4 2 16 14 12 10 18 20 22 24 26 28 30 32 42 44 46 48 34 36 38 40 64 62 60 58 56 54 52 50 64-pin tqfp top view
CS7665 24 ds232pp5 power supply connection vdd - power supply, pins 11, 22, 26, 41, 58. positive digital supplies. nominally +5 volts. gnd - digital ground, pins 10, 21, 27, 40, 57. digital ground supplies. input data and clocks di[0..9] - digital mosaic inputs. cmos level mosaic coded ccd input data from ccd digitizer clkin - mosaic input data clock, pin 55. main system input clock, used to strobe incoming digital ccd mosaic data. the clkin frequency is the mosaic input data rate. clkin2x - mosaic input data interpolation clock, pin 56. mosaic input data interpolation clock. twice the clkin input in normal mode (non- interpolated output data ... see interp description). twice the 5/4 output rate clock when internal 5 to 4 horizontal data rate scaler is in operation. hrefin - horizontal input timing reference, pin 32. active low horizontal input timing reference. used to synchronize the output timing signals with the incoming mosaic data and timing. when used with ccd digitizers like the cs7615 which imbed the necessary timing signals in the data stream, the hrefin signal is not needed. table 14. digital mosaic inputs pin name pin function pin number di0(lsb) digital mosaic input (lsb) 46 di1 digital mosaic input 45 di2 digital mosaic input 44 di3 digital mosaic input 43 di4 digital mosaic input 42 di5 digital mosaic input 39 di6 digital mosaic input 38 di7 digital mosaic input 37 di8 digital mosaic input 36 di9(msb) digital mosaic input (msb) 35
CS7665 ds232pp5 25 vrefin - vertical input timing reference, pin 33. active low vertical input timing reference. used to synchronize the output timing signals with the incoming mosaic data and timing. when used with ccd digitizers like the cs7615 which embed the necessary timing signals in the data stream, the vrefin signal is not needed. i 2 c serial control sda - primary i 2 c data bus, pin 28. primary i 2 c data bus. used with scl to read and write the internal register set. scl - primary i 2 c clock, pin 29. primary i 2 c clock. used with sda to read and write the internal register set. sdasec - secondary i 2 c data bus, pin 47. secondary i 2 c data bus with limited bus mastering capabilities. used with sclsec to read and write i 2 c devices located on the secondary bus. various devices can be isolated by the CS7665 from the primary i 2 c bus. the CS7665 will start reading i 2 c eprom devices at addresses a0h after reset. it will download the eprom contents into the specified registers inside the secondary bus devices as well as any CS7665 registers specified in the eprom entries. devices are typically connected to either the primary or the secondary i 2 c bus. however, the two busses may be connected together when system design requires the use of eprom initialization while at the same allowing direct access to all the camera devices from the external i 2 c controller. sclsec - secondary i 2 c clock, pin 48. secondary i 2 c clock with limited bus mastering capabilities. used with sdasec to read and write i 2 c devices located on the secondary bus. various devices can be isolated by the CS7665 from the primary i 2 c bus. the CS7665 will start reading i 2 c eprom devices at addresses a0h after reset, and download the eprom contents into the specified secondary bus registers, as well as any CS7665 registers specified in the eprom entries. devices are typically connected to either the primary or the secondary i 2 c bus. however, the two busses may be connected together when system design requires the use of eprom initialization while at the same allowing direct access to all the camera devices from the external i 2 c controller. 4bytemode - four-byte mode i 2 c operation enable, pin 1. places CS7665 in the four-byte mode for i 2 c transactions on the primary i 2 c bus. active high. digital video outputs and clocking do a[0..9] - a channel digital output bits. cmos level 10-bit digital video output channel a. either ycrcb interleaved digital video output data, or y component digital video data is available at this port according to the state of bit 5 in register 06h. do a0(lsb) is the least significant bit of channel a; do a9(msb) is the most significant bit of channel a.
CS7665 26 ds232pp5 do b[0..9] b channel digital output bits. cmos level 10-bit digital video output channel b. either logic 0 in interleaved digital video output data mode, or crcb component digital video data is available at this port according to the state of bit 5 in register 06h. do b0(lsb) is the least significant bit of channel b; do b9(msb) is the most significant bit of channel b. clkout - digital output data clock, pin 59. digital output clock for both channel a and b. output data transitions on the falling edge of clkout and can be latched on the rising edge. the clkout rate is twice the input mosaic pixel rate in the interleaved output mode with y and crcb output data both available on channel a. if the internal 4:5 horizontal scaler is enabled, the clkout rate will be 5/4 times the 2x mosaic input data rate in interleaved mode. the clkout rate is equal to the input mosaic pixel rate in the non-interleaved output mode with y output data available on channel a and crcb data available on channel b. if the internal 4:5 horizontal scaler is enabled, the clkout rate will be 5/4 times the 1x mosaic input data rate in non-interleaved mode. table 15. digital output organization pin name pin function pin number do a0(lsb) channel a lsb 13 do a1 channel a data output 12 do a2 channel a data output 9 do a3 channel a data output 8 do a4 channel a data output 7 do a5 channel a data output 6 do a6 channel a data output 5 do a7 channel a data output 4 do a8 channel a data output 3 do a9(msb) channel a msb 2 do b0(lsb) channel b lsb 25 do b1 channel b data output 24 do b2 channel b data output 23 do b3 channel b data output 20 do b4 channel b data output 19 do b5 channel b data output 18 do b6 channel b data output 17 do b7 channel b data output 16 do b8 channel b data output 15 do b9(msb) channel b msb 14
CS7665 ds232pp5 27 table 16. example 512x492 imager output options interp - digital video horizontal data rate scaler enable, pin 54. cmos input enabling the internal 4:5 horizontal data rate scaler. requires the clkin2 to be supplied with a 5/2 rate clock relative to the clkin clock input which is the incoming ccd mosaic data. this pin control is active logic high. hrefout - horizontal reference output, pin 30. cmos output providing href. vrefout - vertical reference output, pin 31. cmos output providing a vref, or alternatively vsync vertical blanking signal. field - odd/even field indicator, pin 62. cmos input providing an odd or even field indication for interlaced field imagers. the field indicator changes according to the embedded eav/sav timing data, or the input timing signals from the analog processor. typically the field indicator changes on the fourth line of every field when using the cs7615. odd fields are indicated with logic low, and even fields are indicated with logic high. output mode mosaic data rate clkin clkin2 channel ?a? channel ?b? clkout horizontal pixels interleaved, scaler disabled 9.818mhz 9.818mhz 19.63mhz ycrcb logic 0 19.63mhz 512 interleaved, scaler enabled 9.818mhz 9.818mhz 24.54mhz ycrcb logic 0 24.54mhz 640 parallel, scaler disabled 9.818mhz 9.818mhz 19.63mhz y crcb 9.818mhz 512 parallel, scaler enabled 9.818mhz 9.818mhz 24.54mhz y crcb 12.27mhz 640
CS7665 28 ds232pp5 oe - output enable, pin 63. cmos input used to place all output pins in a high-z mode. this control works in conjunction with the oe bit in the 06h internal i 2 c register. miscellaneous reset - master external reset control, pin 34. cmos input which initiates a complete power-on reset, where all registers are reset to their defaults, and the secondary i 2 c bus attempts to load any eprom configuration information. this pin operates in conjunction with the 0-bit of the 00h internal i 2 c register. reset is an active logic low input. scanmode - test pin, pin 53. test pin, connect to gnd. testpinb - test pin, pin 60. test pin, connect to vdd. transp - test pin, pin 61. test pin, connect to vdd. scanenable - test pin, pin 64. test pin, connect to gnd. nc - no connect, pins 49, 50, 51, 52. no internal connection. recommend that these pins not be connected. table 17. control of high-z mode of output pins oe bit oe pin digital outputs 0 0 enabled 0 1 high-z 1 0 high-z 1 1 enabled
CS7665 ds232pp5 29 definitions color space - a color space is a mathematical representation of a set of colors. three fundamental color models are rgb (used in color computer graphics and color television), yiq, yuv, or ycrcb (used in broadcast and television systems), and cmyk (used in color printing). rgb color space - the red, green, and blue (rgb) is widely used throughout computer graphics and imaging. red, green, and blue are three primary additive colors where the individual components are added together to form the desired color. yuv color space - the yuv color space is the basic color space used by the pal (phase alternation line), ntsc (national television system committee), and secam (sequential couleur avec memoire or sequential color with memory) composite color video standards. the format conveys intensity in the y component and color information in the u and v components. in an 8-bit system, where rgb range from code 0 to code 255, y has a range of code 0 to code 255. the u component ranges over code 0 +/-112 codes, and the v component ranges over code 0+/-157. ycrcb color space - the ycrcb color space was developed as part of recommendation itu-601 during the development of a world-wide digital component video standard. ycrcb are scaled and offset versions of yuv color space. y is defined to have a nominal range of code 16 to code 235; cr and cb are defined to have a range of code 16 to code 240, with code equal to the zero level. mycg colors - standard color ccd imagers employ integrated filter dots over the individual pixels. typically, four color filters are used, magenta, yellow, cyan, and green. chroma block - a group of four adjacent ccd pixel with integrated mycg filter dots. these four pixels are generally formed with two pixels on one horizontal scan line, and two physically just below on the next scan line. there can also be some slight horizontal shift of the pixels to smooth the image. the chroma block is generally processed using a color separator into yuv, ycrcb, or rgb color space before any image processing.
CS7665 30 ds232pp5 package dimensions 64-pin tqfp millimeters inches 64 1 dim d d e b a a l c 0.461 0.394 0.40 0.016 10.00 11.70 0.14 - 0.00 min 0.35 0.077 1.66 - max 0.26 0.70 0.177 0.006 - 0.00 min 0.014 0.003 0.068 - max 0.010 0.028 0.007 0.60 10.00 12.30 0.024 0.394 0.484 1 d d 1 e e 1 e e 0.461 0.394 10.00 11.70 10.00 12.30 0.394 0.484 1 a 1 a e b l terminal detail 1 c 1 0 12 0 12 64-pin tqfp
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