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description the ADJD-J823 is a cmos mixed-signal ic with integrated rgb photosensors designed to be the optical feedback device of an rgb led-based backlighting system. a typical system consists of an array of red, green and blue (rgb) leds, led drivers and the ADJD-J823. the device samples the light output from the rgb led array, pro - cesses the color information and adjusts the light output from the rgb leds until the target color is achieved. to achieve this, the device integrates an rgb photosensor array, an analog-to-digital converter front-end, a color data processing logic core and a high-resolution 12-bit pwm output generator. by employing a feedback system and the ADJD-J823, the light output produced by the led array maintains its color over time and temperature. in addition, using a serial interface, specifying the color of the led arrays light output is as simple as picking the target color co - ordinates from the cie color space and writing several bytes of data to the device. the sensitivity of the device to light can be adjusted through an automated process. the pwm output signals control the on-time duration of the red, green and blue leds. that duration is continually adjusted in real-time to match the light output from the rgb led array to the target color. ADJD-J823 color management controller with integrated rgb photosensor data sheet features ? integrated rgb photosensor ? integrated color management feedback controller ? serial interface ? direct interface to standard i2c eeprom ? 3-channel 12-bit pwm output C red, green and blue led channels ? built-in oscillator applications ? lcd backlighting avago technologies products and software are not specifically designed, manufactured or authorized for sale as parts, components or assemblies for the planning, construction, maintenance or direct operation of a nuclear facility or for use in medical devices or applications. customer is solely responsible, and waives all rights to make claims against avago technologies or its suppliers, for all loss, damage, expense or liability in connection with such use. esd warning: standard cmos handling precautions should be observed to avoid static discharge.
2 package dimensions bottom view note: dimensions are in millimeter (mm) pin 1 pin 15 pin 13 pin 12 pin 11 pin 14 pin 1 marker notch seating plane 0.75 0.1 0.2 ref 0.3 0.65 ref 3.2 ref 0.5 ref 3.2 ref 5.0 0.1 5.0 0.1 1.05 a
3 pin information pin name type description 1 nc no connect no connect. leave foating. 2 pwmb output pwmb is the active-high blue pulse width modulation output pin. tie it to the blue led driver channel. 3 pwmg output pwmg is the active-high green pulse width modulation output pin. tie it to the green led driver channel. 4 pwmr output pwmr is the active-high red pulse width modulation output pin. tie it to the red led driver channel. 5 dgnd ground tie to digital ground. 6 dgnd ground tie to digital ground. 7 dvdd power digital power pin. 8 agnd ground tie to analog ground. 9 clkio output clkio outputs a reference internal clock signal. 10 xrst input global, asynchronous, active low system reset. when asserted low, xrst resets all registers. minimum reset pulse low is 10us and must be provided by external circuitry. 11 sclslv input sdaslv and sclslv are the serial interface communications pins. sdaslv is the bidirectional data pin and sclslv is the interface clock. a pull-up resistor should be tied to sdaslv because it goes tri-state to output logic 1. 12 sdaslv input/output (tri-state high) 13 sclprom output an external serial i2c eeprom can be connected to the device to store calibration and confguration data. sdaprom and sclprom should be tied to the i2c data (sda) and clock (scl) pins of the eeprom. a pull-up resistor should be tied to sdaprom because it goes tri-state to output logic 1. 14 sdaprom input/output (tri-state high) 15 sleep input when sleep=1, the device goes into sleep mode. in sleep mode, all analog circuits are powered down and the clock signal is gated away from the core logic resulting in very low current consumption. 16 agnd ground tie to analog ground. 17 agnd ground tie to analog ground. 18 agnd ground tie to analog ground. 19 avdd power analog power pin. 20 nc no connect no connect. leave foating.
4 powering the device 0v t vdd_ramp v ddd / v dda no voltage must be applied to io's during power-up and power-down ramp time esd protection diode turn-on during power-up and power-down a particular power-up and power-down sequence must be used to prevent any esd diode from turning on inad - vertently. the fgure above describes the sequence. in general, avdd and dvdd should power-up and power- down together to prevent esd diodes from turning on inadvertently. during this period, no voltage should be applied to the ios for the same reason. ground connection agnd and dgnd must both be set to 0v and preferably star-connected to a central power source as shown in the application diagram. a potential diference between agnd and dgnd may cause the esd diodes to turn on inadvertently. general specifcations feature value interface 100khz serial interface input color format cie yxy output pwm frequency 6.35khz (nominal) output pwm resolution 12 bits supply 2.6v digital (nominal), 2.6v analog (nominal) block diagram photocurrent to voltage conversion red photocurrent to voltage conversion green photocurrent to voltage conversion blue analog to digital conversion device controller sdaslv sclslv sdaprom sclprom pwmr pwmg pwmb xrst sleep rgb photosensor array
5 high level description a hardware reset (by asserting xrst) should be performed before starting any operation. it is assumed that factory calibration was performed prior deployment of ADJD-J823. calibration is discussed at the end of this section. the user controls and confgures the device by program - ming a set of internal registers through a serial interface. at the start of application, the following register data must be written to it: ? frequency registers ? setup data ? calibration data ? bright and color input registers. the register data is usually gathered during a calibration process which is performed once in manufacturing. factory calibration is needed at a system level to map the integrated tri-color sensors reading (device dependent) with a standard device independent color space. once the register data is entered, the feedback operation begins; the device starts to sample the rgb sensor using the internal adc. that data is compared to a user-controlled color point target. the pwm duty factor for each channel is adjusted in response to any error signal generated by that comparison operation. thus, the actual color produced by the leds is maintained close to the target. there are three methods to operate the device. they are diferentiated by the technique in which the register data is stored and used. the three fgures below describe the methods. nvprom stands for non-volatile programmable read-only memory such as an eeprom. independent nvprom the nvprom is independent from the device. during factory calibration, the host must read the register data from the device and write it to the nvprom. at the start of application, the host must read the register data from the nvprom and write it back to the device, after which the device will wait for further instructions in normal mode. device nvprom host controller sdaslv sclslv device nvprom sdaprom sclprom host controller sdaslv sclslv device nvprom sdaprom sclprom dedicated nvprom in standalone mode a dedicated nvprom is connected to the device. during factory calibration, the host can instruct the device to upload the register data to the nvprom. the diference versus interactive mode is that, in application, the device itself will download the register data and immediately after, enter normal mode. then, it will start driving the pwm channels to achieve a default target color point. the default color point is programmed after factory calibration. a host controller is not necessary during ap - plication. the serial interface protocol between device and nvprom is hard coded. so, a standard nvprom such as a serial i2c eeprom with address 0x50 (7-bit) must be used. dedicated nvprom in interactive mode a dedicated nvprom is connected to the device. during factory calibration, the host can instruct the device to upload the register data to the nvprom. at the start of application, the host can instruct the device to download the register data from the nvprom, after which the de - vice will wait for further instructions in normal mode. the serial interface protocol between device and nvprom is hard coded. a standard nvprom such as a serial i2c eeprom with address 0x50 (7-bit) must be used.
6 open loop sensor gain self-adjustment read and store red leds data read and store green leds data read and store blue leds data compute calibration data store calibration data & other configuration data factory calibration factory calibration is needed at a system level to create a snapshot of the initial conditions of the system. the color management algorithm references the snapshot data. in efect, the calibration data trims out variation in the entire signal chain from leds to sensor to adc. the fgure below shows the calibration procedure in brief. first, the device is put into open loop mode in which the color management algorithm is turned of. second, the host controller needs to determine the optimum sensor sensitivity for the given brightness de - tection level. the sensitivity is a combination of several internal settings. searching for the optimum settings can be performed manually or through an automatic search routine which is built into the device. the host can start the routine by issuing a command to the device. the device will then turn the leds (usually at maximum duty factor) and start the search routine. next, the host needs to turn only the red leds on. an external camera must be set up to capture the cie co - ordinates of the red leds. the scaled xyz readings are then written to the device. at the same time, the host needs to instruct the device to sample the rgb sensor and store the results. this is repeated for the green and blue leds. lastly, the host needs to instruct the device to start a calibration calculator. the calculator uses the camera and sensor readings for each color to develop a map - ping matrix that maps the rgb sensor to the standard cie color space. the mapping matrix and other confguration data is the device setup data referred to in the previous section. factory calibration flow chart for details, refer to application note 5241 ADJD-J823 programming manual
7 electrical specifcations absolute maximum ratings (notes 1 & 2) parameter symbol minimum typical maximum units free air operating temperature t a 0 25 70 c digital supply voltage, dvdd to dvss v ddd 2.5 2.6 3.6 v analog supply voltage, avdd to avss v dda 2.5 2.6 3.6 v output current load high i oh 3 ma output current load low i ol 3 ma input voltage high level (note 4) v ih 0.7v ddd v ddd v input voltage low level (note 4) v il 0 0.3v ddd v power supply ramp period t vdd_ ramp 100 ms parameter symbol minimum maximum units notes storage temperature t stg_abs -40 85 c digital supply voltage, dvdd to dvss v ddd_abs -0.5 3.7 v analog supply voltage, avdd to avss v dda_abs -0.5 3.7 v input voltage v in_abs -0.5 v ddd +0.5 v all i/o pins solder refow peak temperature t l_abs 235 c human body model esd rating esd hbm_ abs 2 kv all pins, human body model per jesd22- a114-b recommended operating conditions dc electrical specifcations over recommended operating conditions (unless otherwise specifed) parameter symbol conditions minimum typical (note 3) maximum units output voltage high level (note 5) v oh i oh = 3ma v ddd -0.8 v ddd -0.4 v output voltage low level (note 6) v ol i ol = 3ma 0.2 0.4 v dynamic supply current (note 7,8) i dd_dyn (note 9) 9.4 14 ma static supply current (note 8) i dd_ static (note 9) 2.7 6 ma sleep-mode supply current (note 8) i dd_slp (note 9) 0.2 15 ua input leakage current i leak -10 10 ua ac electrical specifcations over recommended operating conditions (unless otherwise specifed) parameter symbol conditions minimum typical (note 3) maximum units internal clock frequency f clk 16 26 38 mhz
8 optical specifcations parameter symbol conditions minimum maximum units sensor operating detection range e v (note 3 &10) 800 10000 lux serial interface timing information parameter symbol minimum maximum units scl clock frequency f scl 0 100 khz (repeated) start condition hold time t hd:sta 4 - m s data hold time t hd:dat 0 (note 11) 3.45 m s scl clock low period t low 4.7 - m s scl clock high period t high 4.0 - m s repeated start condition setup time t su:sta 4.7 - m s data setup time t su:dat 250 - ns stop condition setup time t su:sto 4.0 - m s bus free time between start and stop conditions t buf 4.7 - m s figure 1. serial interface bus timing waveforms sda scl t hd:sta t low t high t su:dat t hd:dat t su:sto t buf s p s t su:sta t hd:sta sr notes: 1. the absolute maximum ratings are those values beyond which damage to the device may occur. the device should not be operated at these limits. the parametric values defned in the electrical specifcations table are not guaranteed at the absolute maximum ratings. the recom - mended operating conditions table will defne the conditions for actual device operation. 2. unless otherwise specifed, all voltages are referenced to ground. 3. specifed at room temperature (25c) and vddd = vdda = 2.6v. 4. applies to all digital input pins. 5. applies to all digital output pins and clkio pin. sdaslv and sdaprom pins go tri-state when output logic high. minimum v oh depends on the pull-up resistor value. 6. applies to all digital output and digital input-output pins. 7. dynamic testing is performed with the ic operating in a mode representative of typical operation. 8. refers to total device current consumption. 9. output and bidirectional pins are not loaded. 10. using r:g:b led light source brightness ratio of 7:13:1 to achieve white d90 color point red led (x,y) = (0.700, 0.300) green led (x,y) = (0.171, 0.715) blue led (x,y) = (0.158, 0.019) 11. a hold time of at least 300ns must be provided internally by a device for the sda signal ( with reference to the minimum vih of scl) to bridge the undefned region of the falling edge of scl.
9 system performance color accuracy chart. data obtain from 1078 units at 25 o c and v ddd & v dda at 2.6v. color set point at cie x=0.287, y=0.296 (9000k) the average duv is 0.002 with standard deviation 0.0012 and a maximum value of 0.0062. color accuracy 21.9% 34.5% 24.9% 12.9% 4.4% 1.4% 0.1% 0.0% 5.0% 10.0% 15.0% 20.0% 25.0% 30.0% 35.0% 40.0% 0 to <1 1 to <2 2 to <3 3 to <4 4 to <5 5 to <6 6 to <7 du'v' (x 10 -3 ) units sensor optical performance the integrated sensor spectral respond graph from 400 to 700nm. the color indicates the color channel of the color sensor. spectral response 0 0.2 0.4 0.6 0.8 1 400 450 500 550 600 650 700 wavelength (nm) relative sensitivity red green blue red green blue
10 calculating sampling frequency and pwm output frequency the sampling frequency, f samp , which is the frequency at which ADJD-J823 samples the tricolor photosensor, is related to the system clock frequency, f clk . the output pwm frequency, f pwm , is also related to f clk . calculation example: sampfreq x 8 f clk f samp = = 108hz(nominal) (pwmfreq + 1) x 4096 f clk f pwm = = 6.35khz(nominal) f clk = 26 mhz (nominal) sampfreq = sampling frequency register setting = concatenation of registers [0x06][0x07] pwmfreq = pwm frequency register setting = register [0x05] the internal oscillator frequency varies from part-to-part but it will not vary as signifcantly during operation. color drift over temperature data obtain from 5 units. color set point is at 9000k and v ddd & v dda at 2.6v. system consists of ADJD-J823 and rgb leds with color coordinates, red (x,y) = (0.691, 0.309), green (x,y) = (0.161, 0.704), blue (x,y) = (0.131, 0.073). the r:g:b luminance ratio is 2.6 : 3.9 : 1.0 color drift 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0 1 0 2 0 3 0 4 0 5 0 6 0 system temperature (?c) du'v' note: the starting point is at 25 o c and is zero color drift as all measurements are made relative to the starting point at 25 o c.
11 figure 2. start/stop condition s start condition p stop condition sda scl serial interface reference description the programming interface to the ADJD-J823 is a 2-wire serial bus. the bus consists of a serial clock (scl) and a serial data (sda) line. the sda line is bi-directional on ADJD-J823 and must be connected through a pull-up resistor to the positive power supply. when the bus is free, both lines are high. the 2-wire serial bus on ADJD-J823 requires one device to act as a master while all other devices must be slaves. a master is a device that initiates a data transfer on the bus, generates the clock signal and terminates the data transfer while a device addressed by the master is called a slave . slaves are identifed by unique device addresses. both master and slave can act as a transmitter or a receiver but the master controls the direction for data transfer. a transmitter is a device that sends data to the bus and a receiver is a device that receives data from the bus. the ADJD-J823 serial bus interface always operates as a slave transceiver with a data transfer rate of up to 100kbit/s. start/stop condition the master initiates and terminates all serial data transfers. to begin a serial data transfer, the master must send a unique signal to the bus called a start condition. this is defned as a high to low transition on the sda line while scl is high. the master terminates the serial data transfer by sending another unique signal to the bus called a stop condition. this is defned as a low to high transition on the sda line while scl is high. the bus is considered to be busy after a start (s) condition. it will be considered free a certain time after the stop (p) condition. the bus stays busy if a repeated start (sr) is sent instead of a stop condition. the start and repeated start conditions are functionally identical. data transfer the master initiates data transfer after a start condition. data is transferred in bits with the master generating one clock pulse for each bit sent. for a data bit to be valid, the sda data line must be stable during the high period of the scl clock line. only during the low period of the scl clock line can the sda data line change state to either high or low. figure 3. data bit transfer sda scl data valid data change
12 the scl clock line synchronizes the serial data transmission on the sda data line. it is always generated by the master. the frequency of the scl clock line may vary throughout the transmission as long as it still meets the minimum tim - ing requirements. the master by default drives the sda data line. the slave drives the sda data line only when sending an acknowledge bit after the master writes data to the slave or when the master requests the slave to send data. the sda data line driven by the master may be implemented on the negative edge of the scl clock line. the master may sample data driven by the slave on the positive edge of the scl clock line. figure 4 shows an example of a master implementation and how the scl clock line and sda data line can be synchronized. sda scl sda data sampled on the positive edge of scl sda data driven on the negative edge of scl figure 4. data bit synchronization figure 5. data byte transfer sda scl msb lsb 1 2 8 9 ack 1 2 8 9 no ack s or sr sr or p p sr start or repeated start condition stop or repeated start condition msb lsb a complete data transfer is 8-bits long or 1-byte. each byte is sent the most signifcant bit (msb) frst followed by an acknowledge or not acknowledge bit. each data transfer can send an unlimited number of bytes (depending on the data format).
13 acknowledge/not acknowledge the receiver must always acknowledge each byte sent in a data transfer. in the case of the slave-receiver and master- transmitter, if the slave-receiver does not send an acknowledge bit, the master-transmitter can either stop the transfer or generate a repeated start to start a new transfer. in the case of the master-receiver and slave-transmitter, the master generates a not acknowledge to signal the end of the data transfer to the slave-transmitter. the master can then send a stop or repeated start condition to begin a new data transfer. in all cases, the master generates the acknowledge or not acknowledge scl clock pulse. figure 6. slave-receiver acknowledge scl (master) 8 9 sda (slave-receiver) sda (master-transmitter) lsb acknowledge acknowledge clock pulse sda left high by transmitter sda pulled low by receiver figure 7. master-receiver acknowledge scl (master) 8 9 sda (slave-transmitter) sda (master-receiver) acknowledge clock pulse lsb sda left high by transmitter not acknowledge sda left high by receiver p sr stop or repeated start condition
14 addressing each slave device on the serial bus needs to have a unique address. this is the frst byte that is sent by the master- transmitter after the start condition. the address is defned as the frst seven bits of the frst byte. the eighth bit or least signifcant bit (lsb) determines the direction of data transfer. a one in the lsb of the frst byte indicates that the master will read data from the addressed slave (master-receiver and slave-transmitter). a zero in this position indicates that the master will write data to the addressed slave (master-transmitter and slave-receiver). a device whose address matches the address sent by the master will respond with an acknowledge for the frst byte and set itself up as a slave-transmitter or slave-receiver depending on the lsb of the frst byte. the slave address on ADJD-J823 is 0x58 (7-bits). figure 8. slave addressing msb lsb r/w a1 a6 a5 a4 a3 a2 a0 slave address 1 0 1 1 0 0 0 data format ADJD-J823 uses a register-based programming architecture. each register has a unique address and controls a specifc function inside the chip. to write to a register, the master frst generates a start condition. then it sends the slave address for the device it wants to communicate with. the least signifcant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then writes the new register data. once the slave acknowledges, the master generates a stop condition to end the data transfer. figure 9. register byte write protocol a6 a5 a4 a3 a2 a1 a0 w a s a p d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 master sends slave address master writes register address master writes register data master will write data start condition stop condition slave acknowledge a slave acknowledge slave acknowledge
15 to read from a register, the master frst generates a start condition. then it sends the slave address for the device it wants to communicate with. the least signifcant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then generates a repeated start condition and resends the slave address sent previously. the least signifcant bit (lsb) of the slave address must indicate that the master wants to read from the slave. the addressed device will then ac - knowledge the master. the master reads the register data sent by the slave and sends a no acknowledge signal to stop reading. the master then generates a stop condition to end the data transfer. figure 10. register byte read protocol a6 a5 a4 a3 a2 a1 a0 w a s d7 d6 d5 d4 d3 d2 d1 d0 master will write data start condition slave acknowledge a p d7 d6 d5 d4 d3 d2 d1 d0 stop condition a6 a5 a4 a3 a2 a1 a0 r sr master will read data repeated start condition slave acknowledge a master not acknowledge a slave acknowledge master sends slave address master writes register address master sends slave address master reads register data application diagrams avdd dgnd dvdd agnd xrst sleep clkio sdaslv sdaprom sclslv sclprom pwmr pwmg pwmb nc i2c serial eeprom sda scl rgb led driver enable_red enable_green enable_blue voltage regulator voltage regulator float float host system xrst sleep sda scl 10 15 12 11 19 8, 16, 17, 18 5, 6 7 2 3 4 13 14 9 1, 20 star-connected ground connect pull-up resistor to sda connect pull-up resistor to sda
16 2.18mm 0.8 mm 0.4 mm recommended refow profle it is recommended that henkel pb-free solder paste lf310 be used for soldering ADJD-J823. below is the recom - mended soldering profle. 3.19 mm 3.19 mm 5.5 mm 3.9 mm 5.5 mm 0.8 mm 0.4 mm t -peak 230 5 ?c t -reflow 218 ?c delta -flux = 2?c/sec max delta -cooling = 2?c/sec max t -max temperature t -min 120 ?c delta -ramp = 1?c/sec max t -pre = 40-60 sec max t -reflow = 20 - 40 sec max time 160 ?c 20 lead qfn recommended pcb land pad design ipc-sm-782 is used as the standard for the pcb land pad design. recommended pcb fnishing is gold plated. 20 lead qfn recommended stencil design a stencil thickness of 2.18mm (6 mils) for this qfn pack - age is recommended
17 recommendations for handling and storage of ADJD-J823 before opening the mbb (moisture barrier bag) - the sensor component must be kept sealed in a mbb (moisture barrier bag) stored at 30c and 70%rh or less at all times. - it should also be seal with a moisture absorbent material (silica gel) and an indicator card (cobalt chloride) to indicate the moisture within the bag. after opening the mbb (moisture barrier bag) - the sensor component must be kept at 30c and 60%rh or less - the sensor component should have a met (manufacturing exposure time) of 24 hours starting from the time of removal from the mbb to the soldering oven. - if unused sensor component remain, it is recommended to store them back to the mbb. - if the indicator card has turned from blue to pink or it has exceeded the recommended met (manufacturing exposure time) of 24hrs, baking treatment should be performed using the following conditions before continue to ir refow soldering. - baking treatment: 24 hours at 125c. k o b o section b-b section a- a a o 0.30 0.05 b b a a 1.75 0.10 5.50 0.05 12.00 0.10 r 0.50 typ . ? 1.55 0.05 8.00 0.10 ? 1.50 (min.) 4.00 0.10 see note #2 2.00 0.05 see note #2 a o : b o : k o : pitch: width: 5.30 5.30 2.20 8.00 12.00 notes: 1. a o and b o measured at 0.3 mm above base of pocket . 2. 10 pitches cumula tive tolerance is 0.2 mm. 3. dimensions are in millimeters (mm). package tape and reel dimensions carrier tape dimensions
reel dimensions for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countries. data subject to change. copyright ? 2007 avago technologies limited. all rights reserved. obsoletes av01-0106en av02-0492en - june 13, 2007 18.0 max.* ? 178.0 0.5 12.4 45 45 65 r10.65 r5.2 +1.5* - 0.0 ? 55.0 0.5 ? 178.0 ? 51.2 embossed ribs raised: 0.25 mm width: 1.25 mm back view notes: 1. *measured at hub area. 2. all flange edges to be rounded. avago technologies products and software are not specifically designed, manufactured or authorized for sale as parts, components or assemblies for the planning, construction, maintenance or direct operation of a nuclear facility or for use in medical devices or applications. customer is solely responsible, and waives all rights to make claims against avago technologies or its suppliers, for all loss, damage, expense or liability in connection with such use. esd warning: standard cmos handling precautions should be observed to avoid static discharge.

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