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? 2001 microchip technology inc. ds21172e-page 1 93c46b features ? single supply 5.0v operation low power cmos technology - 1 ma active current (typical) - 1 a standby current (maximum) 64 x 16 bit organization self-timed erase and write cycles (including auto-erase) automatic eral before wral power on/off data protection circuitry industry standard 3-wire serial interface device status signal during erase/write cycles sequential read function 1,000,000 e/w cycles ensured data retention > 200 years 8-pin pdip/soic and 8-pin tssop packages available for the following temperature ranges: block diagram description the microchip technology inc. 93c46b is a 1 kbit, low-voltage serial electrically erasable prom. the device memory is configured as 64 x 16 bits. advanced cmos technology makes this device ideal for low-power, nonvolatile memory applications. the 93c46b is available in standard 8-pin dip, surface mount soic, and tssop packages. the 93c46bx are only offered in a 150 mil soic package. package type - commercial (c): 0c to +70c - industrial (i): -40c to +85c - automotive (e): -40c to +125c v cc v ss di cs clk do memory array address decoder address counter data register output buffer memory decode logic clock generator 93c46b cs clk di do 1 2 3 4 8 7 6 5 v cc nc nc v ss cs clk di do v cc nc nc v ss 93c46b nc v cc cs clk nc v ss do di 93c46bx 93c46b cs clk di do 1 2 3 4 8 7 6 5 v cc nc nc v ss tssop soic soic 1 2 3 4 dip 8 7 6 5 1 2 3 4 8 7 6 5 1k 5.0v microwire ? serial eeprom microwire is a registered trademark of national semiconductor incorporated.
93c46b ds21172e-page 2 ? 2001 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings* v cc ...................................................................................7.0v all inputs and outputs w.r.t. v ss .............. -0.6v to v cc +1.0v storage temperature ..................................... -65 c to +150 c ambient temp. with power applied ................-65 c to +125 c soldering temperature of leads (10 seconds) ............. +300 c esd protection on all pins................................................4 kv *notice: stresses above those listed under ? maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended peri- ods may affect device reliability. table 1-1 pin function table name function cs chip select clk serial data clock di serial data input do serial data output v ss ground nc no connect v cc power supply table 1-2 dc and ac electrical characteristics all parameters apply over the specified operating ranges unless otherwise noted commercial (c) v cc = +4.5v to +5.5v t amb = 0c to +70c industrial (i) v cc = +4.5v to +5.5v t amb = -40c to +85c automotive (e) v cc = +4.5v to +5.5v t amb = -40c to +125c parameter symbol min. max. units conditions high level input voltage v ih 2.0 v cc +1 v (note 2) low level input voltage v il -0.3 0.8 v ? low level output voltage v ol ? 0.4 v i ol = 2.1 ma; v cc = 4.5v high level output voltage v oh 2.4 ? vi oh = -400 a; v cc = 4.5v input leakage current i li -10 10 a v in = v ss to v cc output leakage current i lo -10 10 a v out = v ss to v cc pin capacitance (all inputs/outputs) c in , c out ? 7pf v in /v out = 0 v (notes 1 & 2) t amb = +25 c, f clk = 1 mhz operating current i cc read ? 1 ma ? i cc write ? 1.5 ma ? standby current i ccs ? 1acs = v ss ; di = v ss clock frequency f clk ? 2mhzv cc = 4.5v clock high time t ckh 250 ? ns ? clock low time t ckl 250 ? ns ? chip select setup time t css 50 ? ns relative to clk chip select hold time t csh 0 ? ns relative to clk chip select low time t csl 250 ? ns ? data input setup time t dis 100 ? ns relative to clk data input hold time t dih 100 ? ns relative to clk data output delay time t pd ? 400 ns c l = 100 pf data output disable time t cz ? 100 ns c l = 100 pf (note 2) status valid time t sv ? 500 ns c l = 100 pf program cycle time t wc ? 2mserase/write mode t ec ? 6 ms eral mode t wl ? 15 ms wral mode endurance ? 1m ? cycles 25 c, v cc = 5.0v, block mode (note 3) note 1: this parameter is tested at t amb = 25 c and f clk = 1 mhz. 2: this parameter is periodically sampled and not 100% tested. 3: this application is not tested but ensured by characterization. for endurance estimates in a specific applica- tion, please consult the total endurance model which may be obtained on our website: www.microchip.com
93c46b ? 2001 microchip technology inc. ds21172e-page 3 2.0 pin description 2.1 chip select (cs) a high level selects the device; a low level deselects the device and forces it into standby mode. however, a programming cycle which is already in progress will be completed, regardless of the chip select (cs) input signal. if cs is brought low during a program cycle, the device will go into standby mode as soon as the pro- gramming cycle is completed. cs must be low for 250 ns minimum (t csl ) between consecutive instructions. if cs is low, the internal con- trol logic is held in a reset status. 2.2 serial clock (clk) the serial clock (clk) is used to synchronize the com- munication between a master device and the 93c46b. opcodes, addresses, and data bits are clocked in on the positive edge of clk. data bits are also clocked out on the positive edge of clk. clk can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (t ckh ) and clock low time (t ckl ). this gives the controlling master freedom in preparing the opcode, address, and data. clk is a ? don't care ? if cs is low (device deselected). if cs is high, but start condition has not been detected, any number of clock cycles can be received by the device, without changing its status (i.e., waiting for a start condition). clk cycles are not required during the self-timed write (i.e., auto erase/write) cycle. after detecting a start condition, the specified num- ber of clock cycles (respectively low to high transitions of clk) must be provided. these clock cycles are required to clock in all required opcodes, addresses, and data bits before an instruction is executed (table 2-1). clk and di then become don't care inputs waiting for a new start condition to be detected. 2.3 data in (di) data in (di) is used to clock in a start bit, opcode, address, and data synchronously with the clk input. 2.4 data out (do) data out (do) is used in the read mode to output data synchronously with the clk input (t pd after the positive edge of clk). this pin also provides ready/busy status informa- tion during erase and write cycles. ready/busy status information is available on the do pin if cs is brought high after being low for minimum chip select low time (t csl ) and an erase or write operation has been initiated. the status signal is not available on do, if cs is held low during the entire erase or write cycle. in this case, do is in the high-z mode. if status is checked after the erase/write cycle, the data line will be high to indicate the device is ready. note: cs must go low between consecutive instructions. table 2-1 instruction set for 93c46b instruction sb opcode address data in data out req. clk cycles erase 1 11 a5 a4 a3 a2 a1 a0 ? (rdy/bsy )9 eral 1 00 1 0xxxx ? (rdy/bsy )9 ewds 1 00 0 0xxxx ? high-z 9 ewen 1 00 1 1xxxx ? high-z 9 read 1 10 a5 a4 a3 a2 a1 a0 ? d15 - d0 25 write 1 01 a5 a4 a3 a2 a1 a0 d15 - d0 (rdy/bsy )25 wral 1 00 0 1 x x x x d15 - d0 (rdy/bsy )25
93c46b ds21172e-page 4 ? 2001 microchip technology inc. 3.0 functional description instructions, addresses and write data are clocked into the di pin on the rising edge of the clock (clk). the do pin is normally held in a high-z state except when reading data from the device, or when checking the ready/busy status during a programming operation. the ready/busy status can be verified during an erase/write operation by polling the do pin; do low indicates that programming is still in progress, while do high indicates the device is ready. the do will enter the high-z state on the falling edge of the cs. 3.1 start condition the start bit is detected by the device if cs and di are both high with respect to the positive edge of clk for the first time. before a start condition is detected, cs, clk, and di may change in any combination (except to that of a start condition), without resulting in any device oper- ation (erase, eral, ewds, ewen, read, write, and wral). as soon as cs is high, the device is no longer in the standby mode. an instruction following a start condition will only be executed if the required amount of opcodes, addresses, and data bits for any particular instruction is clocked in. after execution of an instruction (i.e., clock in or out of the last required address or data bit) clk and di become don ? t care bits until a new start condition is detected. 3.2 data in (di) and data out (do) it is possible to connect the data in (di)and data out (do) pins together. however, with this configuration, if a0 is a logic-high level, it is possible for a ? bus conflict ? to occur during the ? dummy zero ? that precedes the read operation. under such a condition, the voltage level seen at do is undefined and will depend upon the relative impedances of do and the signal source driv- ing a0. the higher the current sourcing capability of a0, the higher the voltage at the do pin. 3.3 data protection during power-up, all programming modes of operation are inhibited until vcc has reached a level greater than 3.8v. during power-down, the source data protection circuitry acts to inhibit all programming modes when vcc has fallen below 3.8v at nominal conditions. the erase/srite disable (ewds) and erase/ write enable (ewen) commands give additional protection against accidental programming during nor- mal operation. after power-up, the device is automatically in the ewds mode. therefore, an ewen instruction must be performed before any erase or write instruction can be executed. figure 3-1: synchronous data timing cs v ih v il v ih v il v ih v il v oh v ol v oh v ol clk di do (read) do (program) t css t dis t ckh t ckl t dih t pd t csh t pd t cz status valid t sv t cz note: ac test conditions: v il = 0.4v, v ih = 2.4v
93c46b ? 2001 microchip technology inc. ds21172e-page 5 3.4 erase the erase instruction forces all data bits of the spec- ified address to the logical ? 1 ? state. this cycle begins on the rising clock edge of the last address bit. the do pin indicates the ready/busy status of the device if cs is brought high after a minimum of 250 ns low (t csl ). do at logical ? 0 ? indicates that program- ming is still in progress. do at logical ? 1 ? indicates that the register at the specified address has been erased and the device is ready for another instruction. 3.5 erase all (eral) the erase all (eral) instruction will erase the entire memory array to the logical ? 1 ? state. the eral cycle is identical to the erase cycle, except for the different opcode. the eral cycle is completely self-timed and commences at the rising clock edge of the last address bit. clocking of the clk pin is not necessary after the device has entered the eral cycle. the do pin indicates the ready/busy status of the device, if cs is brought high after a minimum of 250 ns low (t csl ) and before the entire eral cycle is complete. figure 3-2: erase timing figure 3-3: eral timing cs clk di do t csl check status 1 1 1a n a n -1 a n -2 a0 t sv t cz busy ready high-z t wc high-z cs clk di do t csl check status 100 10x x t sv t cz busy ready high-z t ec high-z
93c46b ds21172e-page 6 ? 2001 microchip technology inc. 3.6 erase/write disable and enable (ewds/ewen) the device powers up in the erase/write disable (ewds) state. all programming modes must be pre- ceded by an erase/write enable (ewen) instruction. once the ewen instruction is executed, programming remains enabled until an ewds instruction is executed or vcc is removed from the device. to protect against accidental data disturbance, the ewds instruction can be used to disable all erase/write functions and should follow all programming operations. execution of a read instruction is independent of both the ewds and ewen instructions. 3.7 read the read instruction outputs the serial data of the addressed memory location on the do pin. a dummy zero bit precedes the 16-bit output string. the output data bits will toggle on the rising edge of the clk and are stable after the specified time delay (t pd ). sequen- tial read is possible when cs is held high. the memory data will automatically cycle to the next register and output sequentially. figure 3-4: ewds timing figure 3-5: ewen timing figure 3-6: read timing cs clk di 10 000x x t csl 1x cs clk di 00 1 1x t csl cs clk di do 110 an a0 high-z 0dx d0 dx d0 dx d0
93c46b ? 2001 microchip technology inc. ds21172e-page 7 3.8 write the write instruction is followed by 16 bits of data, which are written into the specified address. after the last data bit is clocked into the di pin, the self-timed auto-erase and programming cycle begins. the do pin indicates the ready/busy status of the device, if cs is brought high after a minimum of 250 ns low (t csl ) and before the entire write cycle is complete. do at logical ?0? indicates that programming is still in progress. do at logical ?1? indicates that the register at the specified address has been written with the data specified and the device is ready for another instruc- tion. 3.9 write all (wral) the write all (wral) instruction will write the entire memory array with the data specified in the command. the wral cycle is completely self-timed and com- mences at the rising clock edge of the last data bit. clocking of the clk pin is not necessary after the device has entered the wral cycle. the wral com- mand does include an automatic eral cycle for the device. therefore, the wral instruction does not require an eral instruction, but the chip must be in the ewen status. the do pin indicates the ready/busy status of the device if cs is brought high after a minimum of 250 ns low (t csl ). figure 3-7: write timing figure 3-8: wral timing cs clk di do 1 0 1an a0 dx d0 busy ready high-z high-z twc t csl t cz t sv cs clk di do high-z 1 0 0 01 x x dx d0 high-z busy ready t wl t csl t sv t cz
93c46b ds21172e-page 8 ? 2001 microchip technology inc. 93c46b product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead sm = plastic soic (208 mil body), 8-lead st = tssop, 8-lead temperature range: blank = 0 c to +70 c i =-40 c to +85 c e=-40 c to +125 c device: 93c46b = 1k microwire serial eeprom 93c46bt = 1k microwire serial eeprom tape and reel 93c46bx = 1k microwire serial eeprom in alternate pinout (sn only) 93c46bxt = 1k microwire serial eeprom in alternate pinout, tape and reel (sn only) 93c46b ? /p data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide web site (www.microchip.com)
93c46b ? 2001 microchip technology inc. ds21172e-page 9 notes:
93c46b ds21172e-page 10 ? 2001 microchip technology inc. notes:
93c46b ? 2001 microchip technology inc. ds21172e-page 11 ? all rights reserved. copyright ? 2001, microchip technology incorporated, usa. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. ? trademarks the microchip name, logo, pic, picmicro, picmaster, picstart, pro mate, k ee l oq , seeval, mplab and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. total endurance, icsp, in-circuit serial programming, filterlab, mxdev, microid, flexrom, fuzzylab, mpasm, mplink, mplib, picdem, icepic, migratable memory, fansense, economonitor, selectmode and microport are trademarks of microchip technology incorporated in the u.s.a. serialized quick term programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2001, microchip technology incorporated, printed in the u.s.a., all rights reserved. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.
information contained in this publication regarding device applications and the like is intended through suggestion only and ma y be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warrant y is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patent s or other intellectual property rights arising from such use or otherwise. use of microchip ? s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and othe r countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds21172e-page 12 ? 2001 microchip technology inc. all rights reserved. ? 2001 microchip technology incorporated. printed in the usa. 3/01 printed on recycled paper. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 austin analog product sales 8303 mopac expressway north suite a-201 austin, tx 78759 tel: 512-345-2030 fax: 512-345-6085 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 boston analog product sales unit a-8-1 millbrook tarry condominium 97 lowell road concord, ma 01742 tel: 978-371-6400 fax: 978-371-0050 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 dayton two prestige place, suite 130 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 mountain view analog product sales 1300 terra bella avenue mountain view, ca 94043-1836 tel: 650-968-9241 fax: 650-967-1590 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology beijing office unit 915 new china hong kong manhattan bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - shanghai microchip technology shanghai office room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 hong kong microchip asia pacific rm 2101, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o ? 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