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application note pd780988 subseries 8-bit single-chip microcontrollers inverter control 1991 ? printed in japan document no. u13119ej4v0an00 (4th edition) date published july 2001 j cp(k) 1997, 1999 pd780982 pd780983 pd780984 pd780986 pd780988 pd78f0988a
application note u13119ej4v0an 2 [memo]
application note u13119ej4v0an 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries.
application note u13119ej4v0an 4 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of march 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?
application note u13119ej4v0an 5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
application note u13119ej4v0an 6 major revisions in this edition page description throughout the following product name has been modified: pd78f0988 pd78f0988a p. 43 chapter 3 control figure 3-8 tm7 operation timing has been modified. p. 46 chapter 4 notes on time required for timing set interrupt proc essing the interrupt processing time has been modified accordingly under the following conditions: ? tm7 is used as an 8-bit timer. ? tm7 is used as a 10-bit timer. the mark shows major revised points.
application note u13119ej4v0an 7 introduction target readers this application note is intended for users who wish to understand the functions of the pd780988 subseries, and to design application programs using these products. this manual describes only the pd780988 hereafter. ? pd780988 subseries: pd780982, pd780983, pd780984, pd780986, pd780988, and pd78f0988a note note under development purpose the purpose of this application note is to help users understand the inverter control functions of the pd780988 subseries by using a sample application. the program and hardware configurations published here are just examples and are not intended for mass production. organization this application note is divided into the following sections: ? overview of functions ? hardware configuration ? control ? cautions ? flowcharts ? program list conventions in this application note, symbols and notation are used as follows: data significance: higher digits on the left and lower digits on the right active low representation: xxx (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary: b decimal: hexadecimal: h characters that are easily confused: 0 (zero), o (uppercase of o) 1 (one), l (lowercase of l), i (uppercase of i)
application note u13119ej4v0an 8 related documents ? ? ? ? documents related to devices document name document number pd780982, 780983, 780984, 780986, 780988, 780982(a), 780983(a), 780984(a), 780986(a), 780988(a) data sheet u12804e pd78f0988a data sheet to be prepared pd780988 subseries user's manual u13029e pd780988 subseries application note inverter control this manual 78k/0 series user's manual instruction u12326e 78k/0 series application note fundamental (i) iea-1288 78k/0, 78k/0s series application note flash memory write u14458e ? ? ? ? documents related to development tools document name document number operation u11802e language u11801e ra78k0 assembler package structured assembly language u11789e operation u11517e cc78k0 c compiler language u11518e pg-fp3 flash memory programmer u13502e ie-78k0-ns in-circuit emulator u13731e ie-78001-r-a in-circuit emulator u14142e ie-780988-ns-em4 in-circuit emulator to be prepared ep-78240 emulation probe u10332e sm78k0s, sm78k0 system simulator ver.2.10 or later windows tm based operation u14611e sm78k series system simulator ver.2.10 or later external parts user open interface specification to be prepared id78k0-ns integrated debugger ver.2.00 or later windows based operation u14379e reference u11539e id78k0 integrated debugger windows based guide u11649e ? ? ? ? documents related to embedded software (user's manuals) document name document number fundamental u11537e 78k/0 series real-time os installation u11536e 78k/0 series os mx78k0 fundamental u12257e
application note u13119ej4v0an 9 ? ? ? ? other related documents document name document number semiconductor selection guide products & packages (cd- rom) x13769x semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
application note u13119ej4v0an 10 contents chapter 1 overview of functions............................................................................... 13 1.1 pwm signal generation ............................................................................................. 13 1.2 dead time................................................................................................................. ... 14 1.3 v/f control............................................................................................................... ..... 15 1.4 inverter output setting range................................................................................... 16 1.5 frequency shifting ..................................................................................................... 17 chapter 2 hardware configuration ......................................................................... 18 2.1 system configuration................................................................................................. 18 2.2 cpu block................................................................................................................. ... 19 2.2.1 memory map ...................................................................................................... 19 2.2.2 pin mapping ....................................................................................................... 20 2.3 circuit diagram ........................................................................................................... 21 chapter 3 control ............................................................................................................ 2 2 3.1 state transition table ................................................................................................ 22 3.2 program configuration............................................................................................... 24 3.3 ram and flags ............................................................................................................ 2 6 3.4 tables.................................................................................................................... ....... 32 3.5 registers................................................................................................................. ..... 34 3.6 program description .................................................................................................. 35 3.6.1 initialization (symbol name: restart, ramclr, init) .................................. 35 3.6.2 main processing ................................................................................................. 36 3.6.3 setting pwm switching timing ............................................................................ 42 3.6.4 intp0 safety stop processing ............................................................................ 45 3.6.5 dead time input .................................................................................................. 45 chapter 4 notes on time required for timing set interrupt processing . 46 chapter 5 flowcharts..................................................................................................... 47 chapter 6 program list................................................................................................... 64 6.1 main processing ......................................................................................................... 65 6.2 interrupt processing................................................................................................... 96 6.3 table data................................................................................................................ .. 104 6.4 constant definitions................................................................................................. 113 appendix revision history ............................................................................................ 114
application note u13119ej4v0an 11 list of figures figure no. title page 1-1. use of sawtooth wave to generate pwm sine waveform ......................................................................... ......13 1-2. switching timing........................................................................................................... .....................................14 1-3. dead time ................................................................................................................ .........................................14 1-4. variation of characteristic modulation ratio with output frequency....................................................... ..........15 1-5. generation of pwm sine waveform under v/f control........................................................................ ..............15 2-1. hardware configuration ................................................................................................... ..................................18 2-2. memory map ............................................................................................................... .......................................19 3-1. program configuration.................................................................................................... ...................................25 3-2. digit switching .......................................................................................................... .........................................37 3-3. segment arrangement...................................................................................................... .................................37 3-4. 8-segment led display pattern ............................................................................................ ............................37 3-5. key input port sampling .................................................................................................. ..................................38 3-6. interrupt variable setting ............................................................................................... ....................................40 3-7. block diagram of 10-bit inverter control timer ........................................................................... ......................42 3-8. tm7 operation timing ..................................................................................................... ..................................43 3-9. sine wave table .......................................................................................................... .....................................44 3-10. v/f modulation.......................................................................................................... ..........................................44 3-11. offset revision according to v/f modulation ............................................................................... ......................44 3-12. safety stop conditions .................................................................................................. .....................................45 4-1. time required for timing set interrupt processing........................................................................ ...................46
application note u13119ej4v0an 12 list of tables table no. title page 1-1. inverter output setting range ............................................................................................ .............................. 16 2-1. pin mapping .............................................................................................................. ........................................ 20 3-1. state transition......................................................................................................... ........................................ 22 3-2. subroutines and interrupt processing..................................................................................... .......................... 24 3-3. variables used for inverter control...................................................................................... ............................. 26 3-4. flags used for inverter control .......................................................................................... ............................... 29 3-5. variables used for other than inverter control........................................................................... ..................... 29 3-6. flags used for other than inverter control............................................................................... ....................... 31 3-7. data tables.............................................................................................................. ......................................... 32 3-8. register banks........................................................................................................... ....................................... 34 3-9. registers used in interrupt processing ................................................................................... ......................... 34 3-10. segment display pattern ................................................................................................. ................................. 37 3-11. key input priority...................................................................................................... ......................................... 38 3-12. processing performed for input keys ..................................................................................... .......................... 38 3-13. setting mode state transition........................................................................................... ................................ 39 3-14. mmode set values ........................................................................................................ .................................. 39 3-15. interrupt variables and transfer buffer................................................................................. ............................ 40 3-16. wait counter set values.................................................................................................. ................................. 40 3-17. output start, stop setting .............................................................................................. ................................... 40 3-18. character codes ......................................................................................................... ...................................... 41 3-19. 8-segment led display in each mode...................................................................................... ....................... 41
application note u13119ej4v0an 13 chapter 1 overview of functions as a sample application for the real-time pulse unit (rpu) of the pd780988, this chapter introduces an application for three-phase inverter control according to pwm output. the operating environment is shown below. cpu: pd780988 operating clock: system clock 8 mhz (internal: 8 mhz) operating voltage: 5 v internal rom: 60 kbytes internal ram: 2 kbytes external expansion memory: not used 1.1 pwm signal generation as shown in figure 1-1, the pwm signal is generated by using a sawtooth (carrier) wave to modulate a sine wave. figure 1-1. use of sawtooth wave to generate pwm sine waveform v u w u+ v+ w+ remark the u?, v?, and w? phases are obtained by inverting the high and low levels of the waveforms of the u+, v+, and w+ phases.
chapter 1 overview of functions application note u13119ej4v0an 14 figure 1-2 shows the switching timing of the normal phase output. when switching occurs at the intersection of the sawtooth and sine waves, a waveform like that indicated by "a" below is generated. however, depending on the complexity of the processing and the number of settings, the sample application simulates switching at the timing indicated by "b." figure 1-2. switching timing normal phase output a normal phase output b 1.2 dead time to prevent the positive and negative transistors of each phase from going on together, dead time is inserted into the pwm output. the dead time can be set, by key input, to a value of between 1 s and 32 s, the output of the pwm signal being driven low after the elapse of the previously set delay. figure 1-3. dead time dead time dead time normal phase output inverted phase output
chapter 1 overview of functions application note u13119ej4v0an 15 1.3 v/f control to adjust the torque of the motor, v/f control is used to adjust the voltage (v) in line with the output frequency (f). figure 1-4 shows how the characteristic modulation ratio of the sample program varies with the output frequency. the modulation ratio (sine wave amplitude)/(sawtooth wave amplitude) is such that, when equal to 1, the sawtooth wave amplitude is equal to that of the sine wave. figure 1-4. variation of characteristic modulation ratio with output frequency modulation ratio 1.6 1.0 0.4 10 60 110 160 f (hz) after v/f modulation, if the sawtooth and sine waves do not intersect, as shown in figure 1-5, switching is not performed. figure 1-5. generation of pwm sine waveform under v/f control w v u u+ v+ w+ remark the u ? , v ? , and w ? phases are obtained by inverting high- and low-level waveforms of the u+, v+, and w+ phases.
chapter 1 overview of functions application note u13119ej4v0an 16 1.4 inverter output setting range table 1-1 indicates the inverter output setting range for the sample application. table 1-1. inverter output setting range carrier frequency (hz) output frequency setting range (hz) dead time setting range ( s) 200 4 to 25 400 4 to 50 600 4 to 75 800 4 to 100 1,000 4 to 120 1,200 to 3,800 1 to 32 4,000 1 to 31 4,200 1 to 29 4,400 1 to 28 4,600 1 to 27 4,800 1 to 26 5,000 1 to 25 5,200 1 to 24 5,400 1 to 23 5,600 1 to 22 5,800 1 to 21 6,000 to 6,200 1 to 20 6,400 1 to 19 6,600 to 6,800 1 to 18 7,000 to 7,200 1 to 17 7,400 to 7,800 1 to 16 8,000 to 8,200 1 to 15 8,400 to 8,800 1 to 14 9,000 to 9,600 1 to 13 9,800 to 10,400 1 to 12 10,600 to 11,200 1 to 11 11,400 to 12,400 1 to 10 12,600 to 13,800 1 to 9 14,000 to 15,600 1 to 8 15,800 to 17,800 1 to 7 18,800 to 20,000 4 to 160 1 to 6
chapter 1 overview of functions application note u13119ej4v0an 17 1.5 frequency shifting the current frequency is compared with the set frequency (target frequency) every 5 ms. when the current and target frequencies are found to differ, the output frequency is adjusted in 1-hz steps, at the specified rate of change.
application note u13119ej4v0an 18 chapter 2 hardware configuration 2.1 system configuration figure 2-1 shows the hardware configuration. figure 2-1. hardware configuration reset 5-v power supply on/off + ? changeover operating mode pd780988 driver circuit setting display output display 8 mhz pwm signal 100 vac motor 3 8 3 6 error signal output enable signal clock led dip sw key sw 8-segment led 3 add-on board air conditioner board 15
chapter 2 hardware configuration application note u13119ej4v0an 19 2.2 cpu block 2.2.1 memory map figure 2-2 shows the memory map. figure 2-2. memory map ff00h feffh fee0h fedfh fb00h faffh f800h f7ffh 0040h 003fh f400h f3ffh f000h ffffh 0000h ffffh special function registers (sfrs) general-purpose registers: 32 8 bits (3 banks used) internal ram: 1,024 8 bits (72 bytes used) reserved internal expansion ram: 1,024 8 bits reserved internal rom: 60 kbytes program: 2,756 bytes used main processing: 2,134 bytes interrupt processing: 622 bytes data table: 3,051 bytes used vector table
chapter 2 hardware configuration application note u13119ej4v0an 20 2.2.2 pin mapping table 2-1. pin mapping pin no. pin name i/o signal name a r setting pin no. pin name i/o signal name a r setting 1 p40 i/o seg led (a) output h i l 33 av ss ? (connect to v ss )??? 2 p41 i/o seg led (b) output h i l 34 p17 i changeover between 8 and 10 bits ?i i 3 p42 i/o seg led (c) output h i l 35 p16 i v/f control on/off ? i i 4 p43 i/o seg led (d) output h i l 36 p15 i ? i i 5 p44 i/o seg led (e) output h i l 37 p14 i ? i i 6 p45 i/o seg led (f) output h i l 38 p13 i tm7 count clock selection ?i i 7 p46 i/o seg led (g) output h i l 39 p12 i ? i i 8 p47 i/o seg led (h) output h i l 40 p11 i ? i i 9 p50 i/o seg led digit 3 output h i h 41 p10 i inttm7 occurrence frequency selection ?i i 10 p51 i/o seg led digit 2 output h i l 42 av ref ???? 11 p52 i/o seg led digit 1 output h i l 43 av dd ? not used (connect to v dd ) ?? ? 12 p53 i/o operation indicator led h i l 44 reset i reset input l i i 13 p54 i/o [on/off] input l i i 45 p02 i/o (connect to v ss )?ii 14 p55 i/o [+] input l i i 46 p03 i/o (connect to v ss )?ii 15 p56 i/o [?] input l i i 47 ic ? (connect to v ss )??? 16 p57 i/o [changeover] input l i i 48 x2 ? system clock ? ? ? 17 v ss0 ? ground ? ? ? 49 x1 i system clock ? i ? 18 v dd0 ? supply voltage ? ? ? 50 v ss1 ? ground ? ? ? 19 to70 o u+ output l o h 51 p00 i/o error signal input l i i 20 to71 o u? output l o h 52 p01 i/o (connect to v ss )?ii 21 to72 o v+ output l o h 53 p30 i/o ? i i 22 to73 o v? output l o h 54 p31 i/o ? i i 23 to74 o w+ output l o h 55 p32 i/o ? i i 24 to75 o w? output l o h 56 p33 i/o ? i i 25 p20 i/o l i i 57 p34 i/o ? i i 26 p21 i/o l i i 58 p35 i/o ? i i 27 p22 i/o v/f table selection l i i 59 p36 i/o ? i i 28 p23 i/o l i i 60 p37 i/o not used (connect to v dd ) ?i i 29 p24 i/o l i i 61 p64 i/o enable signal output l i h 30 p25 i/o l i i 62 p65 i/o test pin output ? i l 31 p26 i/o not used l i i 63 p66 i/o test pin output ? i l 32 v dd1 ? supply voltage ? ? ? 64 p67 i/o test pin output ? i l remark i/o: input/output (i: input, o: output) a: active level (h: high level, l: low level) r: pin status at reset (i: input, o: output) setting: setting made at initialization (i: input, h: high-level output, l: low-level output)
chapter 2 hardware configuration application note u13119ej4v0an 21 2.3 circuit diagram 8-segment led dip sw cn1 cn2 cn3 cn4 cn5 cn6 key1 key2 key3 key4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50 p51 p52 p53 p54 p55 p56 p57 v ss0 v dd0 to70 to71 to72 to73 to74 to75 p20/rxd00 p21/txd00 p22/rxd01 p23/txd01 p24/ti50/to50 p25/ti51/to51 p26/ti52/to52 v dd1 p67/astb p66/wait p65/wr p64/rd p37/rtp7 p36/rtp6 p35/rtp5 p34/rtp4 p33/rtp3 p32/rtp2 p31/rtp1 p30/rtp0 p01/intp1 p00/intp0/toff7 v ss1 x1 x2 test p03/intp3/adtrg p02/intp2 reset av dd av ref p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss test pin test pin test pin cn15 51 k ? 51 k ? pa53c 300 ? 82 ? 3 k ? pa56c pd780988 51 k ? jp1 cn16 xtal 8 mhz key5 51 k ? dip sw
application note u13119ej4v0an 22 chapter 3 control 3.1 state transition table table 3-1 lists the state transitions. during the execution of the mode handling indicated by <1> to <5> under "state," if any of the events indicated under "factor" should occur, transition to the mode having the number shown is performed. an "*" in a column indicates that mode transition is not performed. input is valid, however. a "?" in a column indicates that input is not valid. table 3-1. state transition factor note 2 state note 1 reset input on/off input + input ? input changeover input stop signal synchronous/ asynchronous input processing end <1> initialize * ? ? ? ? ? * <5> <2> output frequency change <1> <5> <4> <4> * <5> ? <3> <3> fixed output frequency <1> <5> <4> <4> * <5> ? ? <4> setting <1> #1 * * #1 <5> ? ? <5> signal output stop <1> #2 <4> <4> * * ? ? #1: transition to mode <2>, <3>, or <5> is performed depending on the output state. #2: transition to mode <2> is performed when no stop signal is input. notes 1. states initialize: initially set processing state after a reset start output frequency change: frequency change processing state, when the target frequency differs from the output frequency fixed frequency output: fixed frequency output state, when the target frequency matches the output frequency setting: setting of change pattern to be selected by key input, target frequency, carrier frequency, dead time, and rate of frequency change signal output stop: state existing when frequency output is stopped
chapter 3 control application note u13119ej4v0an 23 2. factors reset input: when key switch connected to reset pin is pressed on/off input: when [on/off] key is pressed + input: when [ + ] key is pressed ? input: when [ ? ] key is pressed changeover input: when [changeover] key is pressed stop signal: when input of the stop signal is detected dip sw input: v/f table selection setting input input to select the size (8/10 bits) of timer 7 (tm7) input to specify whether to turn v/f control on/off input to specify the tm7 count clock input to specify the inttm7 occurrence frequency processing end: when initialization ends, transition to the signal output stopped state is performed. when output frequency change processing ends, transition to fixed frequency output is performed.
chapter 3 control application note u13119ej4v0an 24 3.2 program configuration table 3-2 lists the configured subroutines and interrupt processing performed by the sample application. table 3-2. subroutines and interrupt processing symbol processing restart setting of control register and port mode ramclr ram area clear init initial setting of variables, dip sw input (setting of operating mode) mainlp set by key input setting of inverter output variable setting of leds and test pin output ledout output processing for leds and 8-segment leds keyin key input processing keyset key input setting pset determination of set value according to [on/off] key input pclr clearing of set value according to [changeover] key input pchng change of set value according to [+] or [?] key input dchng change of 8-segment led display according to [changeover] key input smchng setting mode transition processing pmset main mode transition processing invset inverter output setting processing frqcng setting of inverter output variable when changing output frequency outst setting of inverter output start waitset setting of wait when changing output frequency ledset setting of led and 8-segment led indications ladr timing set interrupt (context switching) intp0 safety stop set interrupt (vectored interrupt)
chapter 3 control application note u13119ej4v0an 25 figure 3-1 illustrates the program configuration. as shown in the figure, processing begins from restart. mloop processing is performed after the completion of restart and init processing. figure 3-1. program configuration inverter control program restart ramclr init mloop ledout keyin keyset pset pclr pchng dchng smchng pmset invset frqcng outst waitset nmistp ladr (intp0) (inttm7) ledset : interrupt : subroutine
chapter 3 control application note u13119ej4v0an 26 3.3 ram and flags tables 3-3 to 3-6 list the variables and flags used by the sample application. depending on the linker, variables and flags are allocated such that they can be relocated. to allocate 2-byte variables to an even-numbered address, however, it is necessary to specify the relocatable attribute. table 3-3. variables used for inverter control (1/2) symbol bytes use, setting, reference set value pmode 1 pwm output mode set by mode transition stop mode: 0 fixed output mode: 1 output change mode: 2 nfout 1 output frequency set by inverter output setting during output: (target frequency) example 10 hz: 0ah (10) while stopped: 0ffh rfout 1 target frequency set by key setting referenced by inverter output setting output setting: (target frequency) stop setting: 0ffh ncrry 1 carrier frequency number set by key setting referenced by inverter output setting argument at crrytbl[] reference 1 to 64h (100) ndead 1 dead time number set by key setting referenced by inverter output setting argument at deadtbl[] reference 1 to 20h (32) nchng 1 frequency change rate number set by key setting referenced by inverter output setting argument at chngtbl[] reference 0 to 3 waitcnt 2 frequency change wait counter set by inverter output setting after being set, the chngtbl[] reference value is decremented by 1 until 0 is reached. vfp 2 v/f modulation ratio pointer referenced and set by inverter output setting argument at vftbl[] reference 0 to 9dh (157) sadr 2 value added to sine wave reference phase referenced and set by inttm7 processing transfer of bsadr set value bsadr 2 transfer buffer used for sadr change set by inverter output setting value added to sine wave reference phase (output frequency) (carrier frequency) n where n = number of sine wave data items number of interrupt occurrences offset 2 offset revision determined by v/f modulation referenced and set by inttm7 processing transfer boffset set value
chapter 3 control application note u13119ej4v0an 27 table 3-3. variables used for inverter control (2/2) symbol bytes use, setting, reference set value boffset 2 transfer buffer used for offset change set by inverter output setting offset revision determined by v/f modulation bvf 2 bcm03 2 ? vf 2 v/f modulation multiplier referenced and set by inttm7 processing transfer bvf set value bvf 2 transfer buffer used for vf change set by inverter output setting v/f modulation multiplier tm7 operation clock 2 fc vftbl[ ] 80h bcm03 2 transfer buffer used for cm03 change set by inverter output setting cm03 set value tm7 operation clock 2 fc vftblno 2 v/f table address set in variable initialization referenced by inverter output setting start address of vftbl1 to vftbl8 tm7clk 1 tm7 count clock set in variable initialization referenced by inverter output setting 0 to 7 example fx/2: 1 tm7cnt 1 number of inttm7 occurrences set in variable initialization referenced by the inverter output setting 1 to 8 example one occurrence per two tm7 underflow occurrences: 2 fc: carrier frequency
chapter 3 control application note u13119ej4v0an 28 explanation of major symbols (1) vfp the argument at vftbl1[] to vftbl8[] reference is set. in vftbl1[] to vftbl8[], to describe the 157 words of the v/f modulation ratio corresponding to 4 to 160 hz, vfp can be set to a value within the range of 0 to 9dh (157). (2) sadr, bsadr the sine wave reference phase increment is set. to equally divide the sine wave table data count (512/256 words) by the carrier wave count for one sine wave cycle, calculation is performed as follows: (output frequency) (carrier frequency) (number of inttm7 interrupt occurrences) (sine wave data count) (3) vf, bvf multiplying the v/f modulation multiplier by the sintbl1[] to sintbl8[] reference value (0 to 0ffh)/sintbl1[] reference value (0 to 3ffh) gives a sine wave having an amplitude equal to that of the carrier wave multiplied by the modulation ratio. the value of vftbl1[] to vftbl8[] described in the modulation ratio table is equal to (modulation ratio) 80h. therefore, the value set for vf is as follows: 2 fc tm7 operation clock note vftbl[ ] 80h (carrier wave amplitude) (modulation ratio) = note the carrier wave amplitude is obtained by dividing the carrier wave half-cycle (1/(2 fc)) by the timer count (1/tm7 operation clock), as follows: tm7 operation clock 1/tm7 operation clock 1/(2 fc) = 2 fc (4) offset, boffset value set for offset revision determined by v/f modulation. within the v/f modulated sine wave data, because the cm3/2 data exists together with much other data, it is necessary to perform offset revision determined by v/f modulation. (a) when the v/f modulation ratio is greater than or equal to 1, the offset value is decremented. (b) when the v/f modulation ratio is less than 1, the offset value is incremented. the value set for the offset determined by v/f modulation is calculated as follows: vf 2 cm3 2 ?
chapter 3 control application note u13119ej4v0an 29 table 3-4. flags used for inverter control symbol use, setting set value _chngst interrupt variable transfer request set in inverter output setting reset by inttm7 processing reset: no transfer request set: transfer request _minit selection of mode initialization processing set/reset by mode transition processing reset: mode initialization unnecessary set: mode initialization necessary _pchng determination of output setting change set by key setting reset by inverter output setting reset: no setting change set: setting changed _bsvf transfer flag for _svf change set by inverter output setting reset: v/f modulation ratio < 1 set: v/f modulation ratio 1 _svf indicates v/f modulation ratio. set and referenced by inttm7 processing transfers _bsvf value. _10bit tm7 timer size (8/10 bits) selection set by variable initialization referenced by inverter output setting reset: tm7 is 8 bits long. set: tm7 is 10 bits long. _vfon v/f control on/off selection set by variable initialization referenced by inverter output setting reset: v/f control not exerted set: v/f control exerted table 3-5. variables used for other than inverter control (1/3) symbol bytes use, setting, reference set value dmode meaning of set value 10h target frequency 11h carrier frequency number 12h dead time number nset 1 value set by key input set and referenced by key setting 03h frequency change rate number dmode meaning of minimum value 10h target frequency 11h carrier frequency number 12h dead time number nsetmn 1 minimum nset value set and referenced by key setting 03h frequency change rate number dmode meaning of maximum value 10h target frequency 11h carrier frequency number 12h dead time number nsetmx 1 maximum nset value set and referenced by key setting 03h frequency change rate number sfout 1 buffer used for setting target frequency set by key setting referenced by inverter output setting target frequency set by key setting example 10 hz: 0ah (10)
chapter 3 control application note u13119ej4v0an 30 table 3-5. variables used for other than inverter control (2/3) symbol bytes use, setting, reference set value kin 1 key input set and referenced by key setting port (p5) input value 00h pwm output setting smode 1 key setting mode set by setting mode transition processing 01h setting off 10h display of output frequency 11h display of carrier frequency 12h display of dead time dmode 1 8-segment led display mode set and referenced by key setting 03h display of frequency change rate segbuf 3 8-segment led display buffer set and referenced by key setting character codes displayed by three 8-segment leds segcnt 1 8-segment led flash counter set and referenced by led display setting decremented ( ? 1) from 0e4h (initial value) to 1ch. seg led is lit when the most significant bit = 1. ledcnt 1 led flash counter set and referenced by led display setting decremented ( ? 1) from 0e4h (initial value) to 1ch. led is lit when the most significant bit = 1. ksmpcnt 1 key input sampling counter set and referenced by key input processing decremented ( ? 1) from 2 (initial value) to 0. koncnt 1 hold-down counter set and referenced by key input processing decremented ( ? 1) from 13h (initial value) to 0. kcode1 1 key code buffer 1 set and referenced by key input processing (key codes are listed in table 3-11 .) previously input key code 0: null 1: [changeover] 2: [ ? ] 3: [+] 4: [on/off] kcode2 1 key code buffer 2 set and referenced by key input processing input key code see above. mkake1 2 multiplicand buffer used in main processing the multiplicand data stored in the buffer is 16 bits long. mkake2 2 multiplier buffer used in main processing the multiplier data stored in the buffer is 16 bits long. mkotae 4 calculation result storage buffer used in main processing calculation result data stored in the buffer is 32 bits long. ikake1 2 multiplicand buffer used in inttm7 interrupt processing the multiplicand data stored in the buffer is 16 bits long. ikake2 2 multiplier buffer used in inttm7 interrupt processing the multiplier data stored in the buffer is 16 bits long. ikotae4 4 calculation result storage buffer used in inttm7 interrupt processing calculation result data stored in the buffer is 32 bits long. waru1 4 dividend buffer used in main processing the dividend data stored in the buffer is 32 bits long. calculation result data (quotient) stored in the buffer is 32 bits long.
chapter 3 control application note u13119ej4v0an 31 table 3-5. variables used for other than inverter control (3/3) symbol bytes use, setting, reference set value waru2 2 divider buffer used in main processing the divider data stored in the buffer is 16 bits long. amari 2 remainder storage buffer used in main processing the remainder data stored in the buffer is 16 bits long. table 3-6. flags used for other than inverter control symbol use, setting set value _ledout led output setting set/reset by led display setting reset: led not lit set: led lit
chapter 3 control application note u13119ej4v0an 32 3.4 tables table 3-7 lists the data tables used by the sample application. table 3-7. data tables symbol bytes value to be specified argument referencing sintbl[] 256 sine wave data (1 cycle) ...sin 7fh + 7fh hl of rb1 inttm7 interrupt processing sintbl1[] 512 2 sine wave data (1 cycle) ...sin 1ffh + 1ffh hl of rb1 inttm7 interrupt processing vftbl[] 4 8 v/f table address start address of vftbl1 to vftbl8 p20 to p22 variable initialization vftbl1[] 157 v/f modulation ratio (1) ...(modulation ratio) 100h (256) vfp inverter output setting vftbl2[] 157 v/f modulation ratio (2) ...(modulation ratio) 100h (256) vfp inverter output setting vftbl3[] 157 v/f modulation ratio (3) ...(modulation ratio) 100h (256) vfp inverter output setting vftbl4[] 157 v/f modulation ratio (4) ...(modulation ratio) 100h (256) vfp inverter output setting vftbl5[] 157 v/f modulation ratio (5) ...(modulation ratio) 100h (256) vfp inverter output setting vftbl6[] 157 v/f modulation ratio (6) ...(modulation ratio) 100h (256) vfp inverter output setting vftbl7[] 157 v/f modulation ratio (7) ...(modulation ratio) 100h (256) vfp inverter output setting vftbl8[] 157 v/f modulation ratio (8) ...(modulation ratio) 100h (256) vfp inverter output setting crrytbl[] 10 2 (carrier frequency) example 1,530 hz: 5fah (1530) ncrry inverter output setting fmxtbl[] 10 2 (maximum output frequency) 10 example 100 hz: 3e8h (1000) ncrry key setting dmxtbl[] 10 argument at deadtbl[] reference ncrry key setting chdsptbl[] 4 2 frequency change rate 8-segment led display data nchng led display setting chngtbl[] 4 2 frequency change rate for waitcnt setting nchng inverter output setting ledtbl[] 26 8-segment led display pattern character code led display setting tmclktbl[] 4 8 clock for tm7 operation example 8 mhz: 1200h, 007ah tm7clk inverter output setting cmntbl10[] 8 minimum carrier frequency (tm7 is 10 bits long.) example 4 khz: 14h (20) tm7clk variable initialization key setting cmntbl8[] 8 minimum carrier frequency (tm7 is 8 bits long.) example 16 khz: 50h (80) tm7clk variable initialization key setting
chapter 3 control application note u13119ej4v0an 33 explanation of major symbols (1) sine wave table sintbl[]/sintbl1[] 0 to 2 is divided by 256 or 512 to give the sine wave data for each phase. because the sine is a decimal value within the range between the minimum value ? 1 and the maximum value + 1, to enable setting as 8- and 10-bit integer data, the sine is multiplied by the values shown below for 8 and 10 bits, respectively. 0feh (+1) ? ( ? 1) = 7fh 3feh (+1) ? ( ? 1) = 1ffh also, to enable comparison based on a compare instruction, ? 1 is made to correspond to 0, and +1 is made to correspond to 0feh/3feh. therefore, the value described in the sine wave table is equal to the either of the following values for 8 and 10 bits, respectively. 7fh + 7fh sin 1ffh + 1ffh sin (2) v/f modulation ratio tables vftbl1[] to vftbl8[] the v/f modulation ratio is defined for all output frequencies (157 frequencies from 4 to 160 hz). the modulation ratio is a decimal number in the range between 0 and 1.6. to enable the setting of the modulation ratio as 8-bit integer data, the values that appear in the table are obtained by multiplying the modulation ratio by 256. each v/f modulation ratio table contains the following modulation ratios: 10 hz 60 hz 80 hz 110 hz vftbl1: 0.4 1.0 1.6 vftbl2: 0.2 1.0 1.6 vftbl3: 0.4 1.4 1.6 vftbl4: 0.2 1.4 1.6 vftbl5: 0.4 1.0 1.2 vftbl6: 0.2 1.0 1.2 vftbl7: 0.4 1.2 1.2 vftbl8: 0.2 1.2 1.2
chapter 3 control application note u13119ej4v0an 34 3.5 registers table 3-8 lists the register banks used by the sample application, as well as those that are not used. table 3-8. register banks number use 0 main processing 1 inttm7 timing set interrupt processing 2 intp0 safety stop interrupt processing 3 not used table 3-9 lists the uses of the registers used in interrupt processing. table 3-9. registers used in interrupt processing register bank 5 bank 7 rp0 (ax) not used accumulator rp1 (bc) input wait not used rp6 (de) not used sine wave table reference argument rp7 (hl) not used sine wave reference phase (1) sine wave reference phase indicates the sine wave phase of the output waveform, with 0 to 0ffh/3ffh corresponding to 0 to 2 . at the start of interrupt processing, the previous sine wave reference phase is set. every time interrupt processing is performed, the phase is advanced (by adding sadr) to give the current sine wave reference phase. at the start of output, 0 is initially set. (2) sine wave table reference argument this value is used as the argument for sine wave table reference. the phase that is referenced is set in rp7 (hl). however, sine wave data consists of 256 bytes or 512 words, so only the higher 8 or 9 bits are valid. four bits in rp6 (de) are shifted to the right to set a doubled value.
chapter 3 control application note u13119ej4v0an 35 3.6 program description 3.6.1 initialization (symbol name: restart, ramclr, init) initialization is performed at a reset start. initialization is explained below. ? the control register and stack pointer are set (restart). (as the stack area, 32 bytes of the saddr area, starting from 0fb00h, are secured.) ? port initialization is performed (restart). ? excluding sfr and register bank 0, all of internal ram is cleared (ramclr). ? initial setting of interrupts and the 10-bit inverter control timer (tm7) is performed (init). ? dip sw is input (operating mode is set) (init). (1) tm7 timer size (8/10 bits) selection the size (8/10 bits) of tm7 is specified according to the setting of dip sw2 bit 7 (p17). a size of 10 bits is selected when _10bit is set to 1. a size of 8 bits is selected when _10bit is set to 0. (2) v/f control on/off selection whether to turn v/f control on or off is selected according to the setting of dip sw2 bit 6 (p16). v/f control is turned on when _vfon is set to 1. v/f control is turned off when _vfon is set to 0. (3) inttm7 interrupt occurrence frequency selection the frequency of inttm7 interrupt occurrences is selected according to the input of dip sw2 bits 0 to 2 (p10 to p12). tm7cnt will hold the value input from p10 to p12 plus 1. (4) tm7 count clock selection the count clock for tm7 is selected according to the input of dip sw2 bits 3 to 5 (p13 to p15). the tm7clk will hold the value input from p13 to p15. (5) v/f table selection the v/f table is selected according to the input of dip sw1 bits 0 to 2 (p20 to p22). the vftblno will hold the v/f table storage address obtained from vftbl[] using the value input from p20 to p22 as an argument.
chapter 3 control application note u13119ej4v0an 36 3.6.2 main processing in the main processing loop, the following processing is performed every 5 ms. ? led, 8-segment led output ? key input ? key setting ? setting mode transition ? main mode transition ? inverter output setting ? led, 8-segment led display setting
chapter 3 control application note u13119ej4v0an 37 (1) led, 8-segment led output led output is performed according to the led display setting (_ledout). _ledout: set ............led lit _ledout: reset ........led not lit 8-segment led digit switching and segment output change are performed. figure 3-2. digit switching 2nd digit 3rd digit 1st digit every 5 ms table 3-10. segment display pattern display abcde f gh 0 11111100 1 01100000 2 11011010 3 11110010 4 01100110 5 10110110 6 10111110 7 11100100 8 11111110 9 11110110 d 01111010 o 00111010 off 00000000 figure 3-4. 8-segment led display pattern 0123456 7 89offdo decimal point figure 3-3. segment arrangement fb c e a g d h
chapter 3 control application note u13119ej4v0an 38 (2) key input as shown in figure 3-5, key input port sampling is performed, and fixed key code kcode2 is set. also, at the beginning of input processing, to transfer kcode2 to kcode1, kcode1 is set to the key code fixed at the previous sampling. figure 3-5. key input port sampling read twice non-matching read twice matching read twice matching read twice matching read twice matching read twice matching port input sampling 10 ms 10 ms 10 ms 10 ms 10 ms fixed fixed fixed if the [on/off], [+], [ ? ], and [changeover] keys are pressed simultaneously, only the key having the highest priority is effective. table 3-11. key input priority key port code priority [on/off] p54 04h high [+] p55 03h [ ? ] p56 02h [changeover] p57 01h low (3) key setting processing for the key set by key input (kcode2) is performed. when kcode1 kcode2, new input is considered. the processing performed for each input key is listed in table 3-12. table 3-12. processing performed for input keys processing performed according to mode input key output setting mode off mode [on/off] output setting value nset fixed set _pchng output start (during stop) rfout sfout output stop (during output) rfout 0ffh [+] nset increment (+1) [ ? ] nset decrement ( ? 1) [changeover] output set value nset clear display mode dmode change
chapter 3 control application note u13119ej4v0an 39 (4) setting mode transition key input setting mode transition is performed. table 3-13 lists the setting mode state transitions for key input. during mode processing indicated by one of <1> to <3> in "mode," upon the key input indicated in "key," transition to the mode corresponding to the number shown is performed. an "*" in a column indicates that the key is valid and that state transition is not performed. a " ? " in a column indicates that the key is invalid. table 3-13. setting mode state transition mode key [on/off] [+] [ ? ] [changeover] <1> table setting <3> * * ? <2> output setting <3> * * <3> <3> off * <2> <2> * remark upon a reset start, table setting mode <1> is assumed. (5) main mode transition as indicated in table 3-1, inverter output mode mmode is changed and _minit is set. _minit is the flag used for mode initialize processing, and is set only when the state is changed (upon a reset start, depending on the initialize processing, stop mode is assumed). table 3-14 lists the values set for mmode. table 3-14. mmode set values main mode mmode (protection) stop mode 0 fixed output mode 1 output change mode 2 (6) inverter output variable setting (subroutine: invset) in output change mode (mmode = 2), every time the wait counter (decremented by 1 every 5 ms) reaches 0, output frequency nfout is incremented or decremented by 1 such that it corresponds as closely as possible to set target frequency rfout. when the output frequency is changed, and when the settings of the carrier frequency, dead time, and rate of frequency change are changed by key input (_pchng: set), the value of the transfer buffer for interrupt variable setting is calculated as indicated in table 3-15 (the method of calculation is given in table 3-3 ). to reference the interrupt variable by means of interrupt processing, a value is set in the transfer buffer during main processing, and _chngst is set. during interrupt processing _chngst is checked and, if set, the interrupt variable is set to the value in the transfer buffer and _chngst is reset (see figure 3-6 ).
chapter 3 control application note u13119ej4v0an 40 table 3-15. interrupt variables and transfer buffer transfer buffer interrupt variable bsadr boffset bvf _bsvf bcm03 bdtime sadr offset vf _svf remark the values of bcm03 and bdtime are transferred to cm3 and dtime of sfr. table 3-16. wait counter set values rate of frequency change wait counter set value remarks 0.5 hz/s 400 1.0 hz/s 200 1.5 hz/s 133 2.0 hz/s 100 wait time (counter value) 5 [ms] figure 3-6. interrupt variable setting bsadr boffset _bsvf bcm03 dtime bdtime _chngst set main processing setting sadr bsadr vf bvf, _svf _bsvf offset boffset bfcm3 bcm03 _chngst reset interrupt processing transfer while _minit is set, mode initialize processing (output start, stop setting) is performed (see table 3-17 ). table 3-17. output start, stop setting output start setting output stop setting subroutine tm7 output enabled prohibited outst interrupt processing enabled prohibited outst output frequency set to 4 hz stop setting invset wait set not set waitset interrupt variable set not set frqcng
chapter 3 control application note u13119ej4v0an 41 (7) led and 8-segment led display setting the current pwm output signal state is set as shown below. led at pwm output (mmode 0) _ledout is set. at pwm output (mmode = 0) _ledout is reset. 8-segment led depending on display mode dmode, the character code to be displayed is set in 8- segment led display buffer segbuf. table 3-18. character codes character code character code character code character code character code 0 00h 5 05h d 0ah 0. 10h 5. 15h 1 01h 6 06h o 0bh 1. 11h 6. 16h 2 02h 7 07h 2. 12h 7. 17h 3 03h 8 08h " " 0dh 3. 13h 8. 18h 4 04h 9 09h 4. 14h 9. 19h remark there are no character codes above 0eh, 0fh and 1ah. table 3-19. 8-segment led display in each mode when off mode is set when other than off mode is set led 8-segment led led 8-segment led remarks change pattern selection not lit p01 note when pattern 1 is set signal output stopped target frequency not lit 65 not lit 65 note when 65 hz is set carrier frequency not lit 10.0 not lit 10.0 note when 10,000 hz is set dead time not lit d10 not lit d10 note when 10 s is set rate of frequency change not lit o2.0 not lit o2.0 note when 2 hz/s is set output frequency change target/output frequency flashing 65 flashing 65 note when 65 hz is set carrier frequency flashing 10.0 flashing 10.0 note when 10,000 hz is set rate of frequency change flashing o2.0 flashing o2.0 note when 2 hz/s is set fixed frequency output target/output frequency lit 65 lit 65 note when 65 hz is set carrier frequency lit 10.0 lit 10.0 note when 10,000 hz is set rate of frequency change lit o2.0 lit o2.0 note when 2 hz/s is set note flashing display (50% duty, 1-s cycle). the flash cycle is reset every time key input is performed.
chapter 3 control application note u13119ej4v0an 42 3.6.3 setting pwm switching timing figure 3-7 shows the configuration of the 10-bit inverter control timer (tm7) when sawtooth wave modulation is performed with the pd780988. as shown in figure 3-7, the carrier frequency is set in compare register cm3 and the dead time is set in dead time setting register dtime. the timings at which switching is performed are set in transfer buffers bfcm0 to bfcm2. upon the occurrence of the inttm7 interrupt, the values set in bfcm0 to bfcm2 are transferred to compare registers cm0 to cm2 (see figure 3-8 ). figure 3-7. block diagram of 10-bit inverter control timer dtm0 bfcm3 tm7 cm3 rtm0 inttm7 bfcm0 bfcm1 bfcm2 cm2 dtime dtm1 dtm2 f x f x /2 f x /2 2 f x /2 3 f x /2 4 f x /2 5 f x 10 8 pulse generation circuit to70 (u phase) to71 (u phase) to72 (v phase) to73 (v phase) to74 (w phase) to75 (w phase) output off function controlled by external interrupt or intwdt cm0 cm1
chapter 3 control application note u13119ej4v0an 43 figure 3-8. tm7 operation timing inverted phase output normal phase output dtm count value cm bfcm cm3 cm3 a cm match a cm match b cm match ab c b a inttm7 inttm7 interrupt request tm7 count value
chapter 3 control application note u13119ej4v0an 44 the setting of the timing for bfcm0 to bfcm2 is explained below. figure 3-9. sine wave table 2 0 0 3ffh 1ffh figure 3-10. v/f modulation 2 0 0 m cm3 m cm3 2 figure 3-11. offset revision according to v/f modulation 2 0 m cm3 cm3 2 2 ? ? m cm3 2 (1) sine wave data reference sine wave table reference is performed according to the output phase. the range of the reference value is between 0 to 0ffh/1ffh, as shown in figure 3-9. (2) v/f modulation the sine wave data is multiplied by v/f modulation ratio vf. the higher 8 or 10 bits correspond to the carrier frequency multiplied by the modulation ratio (see figure 3-10 ). (3) offset revision according to v/f modulation within the v/f modulated sine wave data, because the cm3/2 data exists together with much other data, offset revision according to the v/f modulation is performed. when the v/f modulation ratio is greater than or equal to 1, the offset value is decremented. when the v/f modulation ratio is less than 1, the offset value is incremented. the value set for the offset determined by v/f modulation is calculated as follows: (4) timing setting the value obtained by performing steps (1) to (3), above, is set in bfcm0x. vf 2 cm3 2 ?
chapter 3 control application note u13119ej4v0an 45 3.6.4 intp0 safety stop processing processing starts at the falling edge of the external interrupt input to the intp0 input pin. to prevent the occurrence of a safety stop that is caused by noise, intp0 pin sampling is repeated during interrupt processing. stop setting processing is performed only when two consecutive reads of the active (low) level give the same value. figure 3-12. safety stop conditions input error signal 40 s min. (igbt specification) input 7 s during stop setting, output of the 10-bit inverter control timer (tm7) is prohibited and target frequency rfout is set to the stop setting (0ffh). during main processing, when the target frequency is set to the stop setting, the main mode is also set to the stop setting. also, timing set interrupt is prohibited. 3.6.5 dead time input during other than pwm output processing, to measure the dead time of the cpu, test pin (p66, p67) output is performed. test pin output consists of the processing shown below. (1) inverter output setting (subroutine: invset) p67 is set immediately before the subroutine call of the main loop. p67 is reset immediately after the subroutine call of the main loop. (2) inttm7 interrupt processing at the beginning of interrupt processing, p66 is set. after the completion of interrupt processing, p66 is restored.
application note u13119ej4v0an 46 chapter 4 notes on time required for timing set interrupt processing in the sample application, the switching timing for pwm output is calculated based on the interrupt processing for each carrier cycle. therefore, the interrupt processing time that must be secured within the carrier cycle is as follows: ? 64 s if tm7 is 8 bits long ? 256 s if tm7 is 10 bits long remark tm7: 10-bit inverter control timer figure 4-1. time required for timing set interrupt processing carrier wave inttm7 t < 64/256 s carrier cycle inttm7 interrupt processing however, if tm7 is 8 bits long, a carrier frequency of 15.6 khz or higher cannot be output. if tm7 is 10 bits long, a carrier frequency of 3.9 khz or higher cannot be output. to solve this problem, it is necessary to select the frequency of inttm7 interrupt occurrences and divide the frequency by an appropriate value. therefore, the frequency of inttm7 interrupt occurrences must be specified as listed below: ? ? ? ? if tm7 is 8 bits long carrier frequency interrupt occurrence frequency -15.6 khz once 15.6 to 20 khz twice ? ? ? ? if tm7 is 10 bits long carrier frequency interrupt occurrence frequency -3.9 khz once 3.9 to 7.8 khz twice 7.9 to 11.7 khz three times 11.8 to 15.6 khz four times 15.7 to 19.5 khz five times
application note u13119ej4v0an 47 chapter 5 flowcharts timer interrupt every 50 s to 2 ms, note, however, that the interrupt occurrence frequency must be adjusted to a time not shorter than 150 s if tm7 is 8 bits, and to 300 s if tm7 is 10 bits. see 6.2 interrupt processing . yes inttm7 reti pwm output change processing sine wave table reference address setting setting of pwm switching timing external interrupt error signal fall vectored interrupt see 6.2 interrupt processing . no yes yes intp0 reti pwm output stop processing error signal input active? no yes initialize processing dip sw input start see 6.1 (4) . main routine led, 8-segment led output processing key input processing setting for key input setting mode transition processing main mode transition processing inverter output setting led, 8-segment led display setting [ledout] [keyin] [keyset] [smchng] [pmset] [invset] [ledset] 5 ms elapsed?
chapter 5 flowcharts application note u13119ej4v0an 48 [ledout] yes nmi reti display data set segment output on ret digit output on segment output off digit output off led and 8-segment led output processing see 6.1 (19) . digit changeover flash processing? yes (not lit) no
chapter 5 flowcharts application note u13119ej4v0an 49 key code setting non-matching code setting no yes yes new input? port input (read twice) setting of previous fixed code key code clear no yes yes no input? no yes match? port input value setting ret key input processing [keyin] see 6.1 (15) .
chapter 5 flowcharts application note u13119ej4v0an 50 ret off on off on off on [changeover] key processing [+], [ ? ] key single press processing new input? new input? [changeover] key? no yes no yes [keyset] [+], [ ? ] key continuous press processing [on/off] key? [on/off] key processing new input? no yes [+], [ ? ] key? key set processing see 6.1 (10) .
chapter 5 flowcharts application note u13119ej4v0an 51 target frequency setting carrier frequency setting rate of frequency change setting yes yes rate of frequency change display? target frequency display? set value store processing [pset] no yes no yes dead time display? dead time setting no yes no yes carrier frequency display? see 6.1 (11) . ret
chapter 5 flowcharts application note u13119ej4v0an 52 ret target frequency setting clear carrier frequency setting clear dead time setting clear rate of frequency change setting clear [pclr] see 6.1 (12) . no yes no yes target frequency display? carrier frequency display? rate of frequency change display? no yes no yes dead time display? set value clear processing ret increase set value reduce set value see 6.1 (13) . no yes [+] key? no yes within range in which dead time can be set? maximum set value? increase set value no yes carrier frequency change? no yes no yes no yes no yes maximum set value? reduce set value minimum set value? no yes [+] key? no yes within range in which output frequency can be set? minimum set value? [pchng] set value change processing
chapter 5 flowcharts application note u13119ej4v0an 53 ret setting of lower limit that can be set for carrier frequency setting of lower limit that can be set for dead time setting of lower limit that can be set for rate of frequency change setting of lower limit that can be set for target frequency setting of upper limit that can be set for carrier frequency setting of upper limit that can be set for dead time setting of upper limit that can be set for rate of frequency change setting of upper limit that can be set for target frequency carrier frequency display setting dead time display setting rate of frequency change display setting target frequency display setting see 6.1 (14) . no yes target frequency display? carrier frequency display? no yes no yes dead time display? [dchng] display changeover processing is tm7 operating? yes no
chapter 5 flowcharts application note u13119ej4v0an 54 ret see 6.1 (16) . off table setting [on/off] key? yes no any new input? on off [on/off] key? off on off output setting on [changeover] key? setting mode? [smchng] setting mode transition processing setting mode change ( output setting mode) setting mode change ( off mode) setting mode change ( off mode) [+], [ ? ] key? on off setting mode change ( output setting mode)
chapter 5 flowcharts application note u13119ej4v0an 55 error signal? ret stop mode? pwm mode transition processing see 6.1 (9) . 'l' 'h' 'h' 'l' no yes target frequency? (= stop setting) ( stop setting) fixed output mode? target frequency? stop signal? no yes target frequency? (= output frequency) (= stop setting) (= output frequency) ( output frequency) ( stop setting) ( output frequency) target frequency? initialize flag set mode change ( output change mode) mode change ( stop mode) initialize flag set initialize flag reset initialize flag set initialize flag reset initialize flag set mode change ( fixed output mode) [pmset] mode change ( output change mode)
chapter 5 flowcharts application note u13119ej4v0an 56 exit output stop initialize no yes wait setting interrupt variable set processing interrupt variable set processing stopped? output change mode? no no yes [frqcng] [invset] see 6.1 (17) . [waitset] [outst] [waitset] [frqcng] yes stop mode? output start initialize output enable setting wait setting target frequency setting no yes mode initialize? inverter output setting mode initialize ret mode initialize main mode processing
chapter 5 flowcharts application note u13119ej4v0an 57 target frequency setting wait counter update yes yes any setting change? yes yes fixed output mode? output change mode? main mode processing yes no no yes yes yes no wait elapsed? no yes any setting change? interrupt variable set processing target frequency stop processing [waitset] [frqcng] interrupt variable set processing [frqcng] wait setting exit no
chapter 5 flowcharts application note u13119ej4v0an 58 [frqcng] nmi reti v/f modulation ratio setting offset revision value setting ret step address setting dead time setting frequency setting change see 6.1 (22) . carrier frequency setting carrier frequency 2 setting of currently set carrier frequency carrier frequency table reference exit carrier frequency setting count clock carrier frequency carrier frequency setting count clock f x : 8,000,000 f x /2: 4,000,000 f x /4: 2,000,000 f x /8: 1,000,000 f x /16: 500,000 f x /32: 250,000
chapter 5 flowcharts application note u13119ej4v0an 59 v/f modulation ratio table reference calculation of step address step address setting setting of currently set carrier frequency carrier frequency table reference v/f modulation ratio flag setting calculation of v/f modulation ratio v/f modulation ratio setting exit offset revision value setting calculation of offset revision value step address setting
chapter 5 flowcharts application note u13119ej4v0an 60 ret rate of output frequency change setting see 6.1 (25) . see 6.1 (18) . u-phase, v-phase, w-phase switching avoidance output setting change tm7 mode setting inttm7 interrupt enable tm7 start ret pwm output start processing in wait counter, set rate of change set by key processing [outst] [waitset]
chapter 5 flowcharts application note u13119ej4v0an 61 ret output frequency display setting carrier frequency display setting dead time display setting rate of frequency change display setting [ledset] see 6.1 (20) . no yes carrier frequency display? output frequency display? no yes no yes led and 8-segment led display set processing dead time display? [bufset] nmi reti zero suppression ret unit digit setting 100s digit setting output buffer initialization 8-segment led output buffer setting see 6.1 (21) . 10s digit setting
chapter 5 flowcharts application note u13119ej4v0an 62 [ladr] nmi reti test pin output reti setting change processing v-phase timing setting u-phase timing setting test pin output sine wave table reference address calculation every 50 s to 2 ms, note, however, that the interrupt occurrence frequency must be adjusted to a time not shorter than 150 s if tm7 is 8 bits, and to 300 s if tm7 is 10 bits. see 6.2 interrupt processing . w-phase timing setting inttm7 output enable set processing reference address calculation reti change of valid bit length exit sine wave table reference address calculation
chapter 5 flowcharts application note u13119ej4v0an 63 timing value 0000h offset value subtract offset value add no yes yes underflow? multiply by modulation ratio sine wave table reference yes no yes modulation ratio < 1? timing setting reti exit u-phase, v-phase, w-phase timing set processing
application note u13119ej3v0an 64 chapter 6 program list this chapter lists the programs of this application software.
chapter 6 program list application note u13119ej4v0an 65 6.1 main processing extrn crrytbl,vftbl ; table extrn vftbl1, vftbl2, vftbl3, vftbl4 ; table extrn vftbl5, vftbl6, vftbl7, vftbl8 ; table extrn chngtbl ; table extrn ledtbl, fmxtbl, dmxtbl, chdsptbl ; table extrn tmclktbl,cmntbl10,cmntbl08 ; table extrn ladr, intp0 ; interrupt public bvf, vf, bsadr, sadr ; saddr variable public boffset,offset, rfout ; saddr variable public bcm03 ; saddr variable public ikake1, ikake2, ikotae ; saddr variable public _chngst,_bsvf, _svf, _10bit ; flag (1) stack area allocation stack dseg at 0fb00h ;************ stack definition ds 32 stkini:
chapter 6 program list application note u13119ej4v0an 66 (2) variable definition sdat dseg saddr ;************ variable definition pmode: ds 1 ; main mode rfout: ds 1 ; target frequency nfout: ds 1 ; output frequency ncrry: ds 1 ; carrier frequency ndead: ds 1 ; dead time nchng: ds 1 ; change rate nset: ds 1 ; setting number nsetmn: ds 1 ; maximum setting number nsetmx: ds 1 ; minimum setting number sfout: ds 1 ; carrier frequency buffer kin: ds 1 ; port input pattern smode: ds 1 ; key input setting mode dmode: ds 1 ; seg led display mode dummy: ds 1 waitcnt:ds 2 ; wait counter bsadr: ds 2 ; step address buffer bvf: ds 2 ; modulation ratio buffer bcm03: ds 2 ; cm03 buffer boffset:ds 2 ; v/f offset revision value buffer sadr: ds 2 ; step address vf: ds 2 ; modulation ratio vfp: ds 2 ; v/f modulation ratio data pointer offset: ds 2 ; v/f offset revision value buffer mkake1: ds 2 ; multiplicand area (2 bytes) for main processing mkake2: ds 2 ; multiplier area (2 bytes) for main processing mkotae: ds 4 ; calculation result storage area (4 bytes) for main processing ikake1: ds 2 ; multiplicand area (2 bytes) for interrupt processing ikake2: ds 2 ; multiplier area (2 bytes) for interrupt processing ikotae: ds 4 ; calculation result storage area (4 bytes) for interrupt processing waru1: ds 4 ; dividend area (4 bytes) waru2: ds 2 ; divider area (2 bytes) amari: ds 2 ; remainder storage area (2 bytes) vftblno:ds 2 ; v/f table selection tm7clk: ds 1 ; tm7 count clock selection tm7cnt: ds 1 ; inttm7 occurrence frequency selection bdtime: ds 1 ; dead time counter segbuf: ds 3 ; seg led display buffer segcnt: ds 1 ; seg led flash counter ledcnt: ds 1 ; led flash counter ksmpcnt:ds 1 ; key input sampling counter koncnt: ds 1 ; hold-down counter kcode1: ds 1 ; key code buffer 1 kcode2: ds 1 ; key code buffer 2 psmpcnt:ds 1 ; stop signal sampling counter
chapter 6 program list application note u13119ej4v0an 67 flag bseg unit _chngst dbit ; frequency change request _ledout dbit ; led output _minit dbit ; pwm mode initialization _pchng dbit ; pwm variable change _svf dbit ; v/f modulation ratio (0: modulation ratio < 1) _bsvf dbit ; v/f modulation buffer _10bit dbit ; flag to indicate whether timer 7 is 10 or 8 bits _vfon dbit ; v/f control selection flag (3) vector table ; *********************************************** ; * vector table * ; *********************************************** vereset cseg at 0000h dw restart ; reset start dw restart ; dummy dw restart ; 0 intwdt dw intp0 ; 1 intp0 dw restart ; 2 intp1 dw restart ; 3 intp2 dw restart ; 4 intp3 dw ladr ; 5 inttm7 dw restart ; 6 intser0 dw restart ; 7 intsr0 dw restart ; 8 intst0 dw restart ; 9 intser1 dw restart ; 10 intsr1 dw restart ; 11 intst1 dw restart ; 12 inttm50 dw restart ; 13 inttm51 dw restart ; 14 inttm52 dw restart ; 15 intad0 vdibrk cseg at 003eh dw restart ; brk mainrut cseg at 80h ; main start address 80h
chapter 6 program list application note u13119ej4v0an 68 (4) initialization ; *********************************************** ; * initialization * ; *********************************************** restart: di ; ; *** stack pointer initialization *** movw sp,#stkini ; ; *** register bank setting *** sel rb0 ; register bank = 0 ; *** cpu clock setting *** mov pcc,#00000000b ; cpu clock = f x (8 mhz: 0.25 s) ; *** port initialization *** ; ///// expansion mode setting ///// mov mm,#00000000b ; mov mem,#00000000b ; ; ///// port setting ///// ; port latch setting mov p0,#00000000b ; input port mov p2,#00000000b ; input port mov p3,#00000000b ; input port mov p4,#00000000b ; p40 to p47: low output mov p5,#00000001b ; p50: high, p51 to p53: low mov p6,#00010000b ; p64: high, p65 to p67: low ; port mode setting mov pm0,#11111111b ; input mode mov pm2,#11111111b ; input mode mov pm3,#11111111b ; input mode mov pm4,#00000000b ; output mode mov pm5,#11110000b ; p50 to p53: output mode mov pm6,#00001111b ; p64 to p67: output mode ; pull-up resistor setting mov pu0,#00000000b ; not to be used mov pu2,#00000000b ; not to be used mov pu3,#00000000b ; not to be used mov pu4,#00000000b ; not to be used mov pu5,#00000000b ; not to be used mov pu6,#00000000b ; not to be used ; ///// priority specification flag clearing ///// mov pr0l,#0ffh ; mov pr0h,#0ffh ;
chapter 6 program list application note u13119ej4v0an 69 ; ///// external interrupt valid edge setting ///// mov egp,#00000000b ; mov egn,#00000001b ; intp0 low active (5) ram initialization ; *********************************************** ; * ram initialization * ; *********************************************** ; ********** ram clearing ********** ramclr: mov a,#00h movw hl,#0fef7h ramclr0: mov [hl],a dec l bnz $ramclr0
chapter 6 program list application note u13119ej4v0an 70 (6) dip sw input ; *********************************************** ; * dip sw input * ; *********************************************** init: mov a,p1 xor a,#0ffh sw_in_1: bf a.7,$sw_in_2 set1 _10bit sw_in_2: bf a.6,$sw_in_3 set1 _vfon sw_in_3: and a,#00111111b mov b,a and a,#00000111b inc a mov tm7cnt,a mov a,b ror a,1 ror a,1 ror a,1 and a,#00000111b mov tm7clk,a ; ********** vf table selection sw input ********** mov a,p2 xor a,#0ffh and a,#00000111b rol a,1 ; a = a x 2 mov c,a movw hl,#vftbl mov a,[hl+c] mov x,a inc c mov a,[hl+c] movw vftblno,ax
chapter 6 program list application note u13119ej4v0an 71 (7) ram initialization ; *********************************************** ; * ram initialization * ; *********************************************** mov pmode,#pmstop ; main mode: output stop mov dmode,#dmfout ; display mode: output frequency mov smode,#smoff ; setting mode: off mov ndead,#5 ; dead time initialization mov nchng,#0 ; frequency change rate initialization mov a,tm7clk mov c,a movw hl,#cmntbl10 bt _10bit,$ramset1 movw hl,#cmntbl08 ramset1: mov a,[hl+c] mov ncrry,a ; carrier frequency initialization mov c,a movw hl,#fmxtbl mov a,[hl+c] mov nset,a ; initialization display no. mov sfout,a ; target frequency initialization mov nsetmx,a ; target frequency upper limit setting mov nsetmn,#4 ; target frequency lower limit setting mov nfout,#frqstop ; output frequency: stop setting mov rfout,#frqstop ; target frequency: stop setting mov ksmpcnt,#3 ; key input sampling counter setting mov psmpcnt,#1 ; stop signal sampling counter setting mov segcnt,#80h+segini ; 8-segment led flash counter setting mov ledcnt,#80h+ledini ; led flash counter setting mov segbuf,#chrspc ; 8-segment led display buffer 1: " " mov segbuf+1,#chrspc ; 8-segment led display buffer 2: " " mov segbuf+2,#chrspc ; 8-segment led display buffer 3: " "
chapter 6 program list application note u13119ej4v0an 72 (8) sfr initialization ; *********************************************** ; * sfr initialization * ; *********************************************** mov a,b mov tmc7,a mov tmm7,#00000000b ; clr1 pif0 clr1 pmk0 ; intp0 (motor failure detection) interrupt enable ei mloop: ;************ main loop btclr tmif50,$mloop1 ; 5 ms elapsed (main processing execution) nop nop nop br mloop mloop1: clr1 p6.7 ; turn on led for main processing time measurement output call !ledout ; led and 8-segment led output processing call !keyin ; key input processing call !keyset ; key setting call !smchng ; setting mode transition processing call !pmset ; main mode transition processing call !invset ; inverter output setting call !ledset ; led and 8-segment led display setting set1 p6.7 ; turn off led for main processing time measurement output br mloop
chapter 6 program list application note u13119ej4v0an 73 (9) pwm mode transition processing ;sssssssssssssssssssssssssssssssssssssssss ;ss pwm mode transition processing ss ;sssssssssssssssssssssssssssssssssssssssss pmset: ;************ ; branch for output stop mode cmp pmode,#pmstop bnz $pmset2 pmset0: mov1 cy,p0.0 ; stop signal input (first time) mov1 a.0,cy mov b,#1 pmsetw1: dbnz b,$pmsetw1 xor1 cy,p0.0 ; stop signal input (second time) bc $pmset0 bf a.0,$pmset1 ; stop signal active? cmp rfout,#frqstop ; frequency stop setting? bz $pmset1 mov pmode,#pmchng set1 _minit br $pmset6 pmset1: clr1 _minit br $pmset6 pmset2: ;************ branch for output mov1 cy,p0.0 ; stop signal input (first time) mov1 a.0,cy mov b,#1 pmsetw2: dbnz b,$pmsetw2 xor1 cy,p0.0 ; stop signal input (second time) bc $pmset2 bt a.0,$pmset4 pmset3: ;************ stop directed by stop signal mov pmode,#pmstop ; stop mode setting set1 _minit br $pmset6 pmset4: cmp rfout,#frqstop ; stop setting? bz $pmset3 cmp pmode,#pmfout bnz $pmset5 mov a,rfout cmp a,nfout bz $pmset1 mov pmode,#pmchng set1 _minit br $pmset6 pmset5: mov a,rfout cmp a,nfout bnz $pmset1 movw waitcnt,#0 bnz $pmset1 mov pmode,#pmfout set1 _minit pmset6: ret
chapter 6 program list application note u13119ej4v0an 74 (10) key setting ;sssssssssssssssssssssssssssssssssssssssss ;ss key setting ss ;sssssssssssssssssssssssssssssssssssssssss keyset: ;************ [on/off] key setting cmp kcode2,#konof ; [on/off] key pressed? bnz $keyset1 mov a,kcode1 cmp a,kcode2 bz $keyset6 cmp smode,#smoff bz $keyset7 call !pset ; set value store subroutine br $keyset6 keyset7: cmp pmode,#pmstop bz $keyset10 mov rfout,#frqstop br $keyset6 keyset10: mov a,sfout mov rfout,a cmp dmode,#dmdead bnz $keyset6 mov dmode,#dmfout mov nset,a mov a,ncrry ;@mov a,fmxtbl[a] mov c,a movw hl,#fmxtbl mov a,[hl+c] mov nsetmx,a ; upper limit setting mov nsetmn,#4 ; lower limit setting br $keyset6 keyset1: ;************ [changeover] key setting cmp kcode2,#kchng ; [changeover] key pressed? bnz $keyset3 mov a,kcode1 cmp a,kcode2 bz $keyset6 cmp smode,#smoff bz $keyset2 call !pclr ; set value clear subroutine br $keyset6 keyset2: call !dchng br $keyset6 keyset3: ;************ [+], [?] key setting bf kcode2.1,$keyset6 mov a,kcode1 cmp a,kcode2 bz $keyset4 mov koncnt,#konini br $keyset5
chapter 6 program list application note u13119ej4v0an 75 keyset4: bf dmode.4,$keyset6 dbnz koncnt,$keyset6 mov koncnt,#konres keyset5: mov segcnt,#80h+segini call !pchng ; set value change subroutine keyset6: ret (11) set value store subroutine ;sssssssssssssssssssssssssssssssssssssssss ;ss set value store subroutine ss ;sssssssssssssssssssssssssssssssssssssssss pset: ;************ target frequency setting cmp dmode,#dmfout ; target frequency display? bnz $pset1 mov a,nset mov sfout,a ; target frequency setting cmp pmode,#pmstop bz $pset5 mov a,nset mov rfout,a br $pset5 pset1: ;************ carrier frequency setting cmp dmode,#dmcrry ; carrier frequency display? bnz $pset2 mov a,nset mov ncrry,a ; carrier frequency setting br $pset5 pset2: ;************ dead time setting cmp dmode,#dmdead ; dead time display? bnz $pset3 mov a,nset mov ndead,a ; dead time setting br $pset5 pset3: ;************ setting of rate of frequency change mov a,nset mov nchng,a ; setting of rate of frequency change pset5: cmp pmode,#pmstop bz $pset6 set1 _pchng pset6: ret
chapter 6 program list application note u13119ej4v0an 76 (12) set value clear subroutine ;sssssssssssssssssssssssssssssssssssssssss ;ss set value clear subroutine ss ;sssssssssssssssssssssssssssssssssssssssss pclr: ;************ target frequency setting clear processing cmp dmode,#dmfout ; target frequency display? bnz $pclr1 mov a,sfout mov nset,a ; target frequency setting clear br $pclr4 pclr1: ;************ carrier frequency setting clear processing cmp dmode,#dmcrry ; carrier frequency display? bnz $pclr2 mov a,ncrry mov nset,a ; carrier frequency setting clear br $pclr4 pclr2: ;************ dead time setting clear processing cmp dmode,#dmdead ; dead time display? bnz $pclr3 mov a,ndead mov nset,a ; dead time setting clear br $pclr4 pclr3: ;************ setting clear processing of rate of frequency change cmp dmode,#dmchng ; display of frequency change rate? bnz $pclr4 mov a,nchng mov nset,a ; clear frequency change rate setting pclr4: ret
chapter 6 program list application note u13119ej4v0an 77 (13) set value change subroutine ;sssssssssssssssssssssssssssssssssssssssss ;ss set value change subroutine ss ;sssssssssssssssssssssssssssssssssssssssss pchng: ;************ changing set values other than carrier frequency cmp dmode,#dmcrry bz $pchng2 cmp kcode2,#kplus bnz $pchng1 ;************ [+] key processing mov a,nset cmp a,nsetmx ; maximum set value? bz $pchng4 add nset,#1 ; increase set value br $pchng4 pchng1: ;************ [?] key processing mov a,nset cmp a,nsetmn ; minimum set value? bz $pchng4 sub nset,#1 ; decrease set value br $pchng4 pchng2: ;************ changing set value of carrier frequency cmp kcode2,#kplus bnz $pchng3 ;************ [+] key processing mov a,nset cmp a,nsetmx ; maximum set value? bz $pchng4 mov a,nset inc a ;@mov a,dmxtbl[a] mov c,a movw hl,#dmxtbl mov a,[hl+c] cmp a,ndead bc $pchng4 inc nset br $pchng4 pchng3: ;************ [?] key processing mov a,nset cmp a,nsetmn ; minimum set value? bz $pchng4 mov a,nset dec a ;@mov a,fmxtbl[a] mov c,a movw hl,#fmxtbl mov a,[hl+c] cmp a,sfout bc $pchng4 dec nset pchng4: ret
chapter 6 program list application note u13119ej4v0an 78 (14) display changeover processing ;sssssssssssssssssssssssssssssssssssssssss ;ss display changeover processing ss ;sssssssssssssssssssssssssssssssssssssssss dchng: ;************ target frequency to carrier frequency cmp dmode,#dmfout ; display target frequency? bnz $dchng1 mov dmode,#dmcrry ; carrier frequency display setting mov a,tm7clk mov c,a movw hl,#cmntbl10 bt _10bit,$dchng01 movw hl,#cmntbl08 dchng01: mov a,[hl+c] mov nsetmx,#100 ; upper limit setting mov nsetmn,a ; lower limit setting mov a,ncrry mov nset,a br dchng4 dchng1: ;************ carrier frequency to dead time cmp dmode,#dmcrry ; display carrier frequency? bnz $dchng2 cmp pmode,#pmstop ; pwm operating? bnz $dchng21 mov dmode,#dmdead ; dead time display setting mov a,ncrry ;@mov a,dmxtbl[a] mov c,a movw hl,#dmxtbl mov a,[hl+c] mov nsetmx,a ; upper limit setting mov nsetmn,#deadmn1 mov a,ndead mov nset,a br dchng4 dchng2: ;************ dead time to frequency change rate cmp dmode,#dmdead ; display dead time? bnz $dchng3 dchng21: mov dmode,#dmchng ; frequency change rate display setting mov nsetmx,#3 ; upper limit setting mov nsetmn,#0 ; lower limit setting mov a,nchng mov nset,a br $dchng4 dchng3: ;************ frequency change rate to target frequency mov dmode,#dmfout ; target frequency display setting mov a,ncrry ;@mov a,fmxtbl[a] mov c,a movw hl,#fmxtbl mov a,[hl+c] mov nsetmx,a ; upper limit setting
chapter 6 program list application note u13119ej4v0an 79 mov nsetmn,#4 ; lower limit setting mov a,sfout mov nset,a dchng4: ret (15) key input processing ;sssssssssssssssssssssssssssssssssssssssss ;ss key input processing ss ;sssssssssssssssssssssssssssssssssssssssss keyin: mov a,kcode2 mov kcode1,a dbnz ksmpcnt,$keyin8 mov ksmpcnt,#ksmpini mov a,p5 mov b,#2 keyin1: dbnz b,$keyin1 cmp a,p5 bnz $keyin7 xor a,#0ffh and a,#0f0h mov x,a and a,kin bz $keyin5 bf a.4,$keyin2 mov kcode2,#konof br $keyin6 keyin2: bf a.5,$keyin3 mov kcode2,#kplus br $keyin6 keyin3: bf a.6,$keyin4 mov kcode2,#kmins br $keyin6 keyin4: mov kcode2,#kchng br $keyin6 keyin5: mov a,x or a,kin bnz $keyin6 mov kcode2,#knull keyin6: mov a,x mov kin,a br $keyin8 keyin7: mov kcode2,#kerr keyin8: ret
chapter 6 program list application note u13119ej4v0an 80 (16) setting mode transition processing ;sssssssssssssssssssssssssssssssssssssssss ;ss setting mode transition processing ss ;sssssssssssssssssssssssssssssssssssssssss smchng: mov a,kcode1 cmp a,kcode2 bz $smchng4 cmp smode,#smout bnz $smchng2 cmp kcode2,#konof bz $smchng1 cmp kcode2,#kchng bz $smchng1 mov smode,#smout br $smchng4 smchng1: mov smode,#smoff br $smchng4 smchng2: bf kcode2.1,$smchng4 mov smode,#smout smchng4: ret
chapter 6 program list application note u13119ej4v0an 81 (17) inverter output setting ;sssssssssssssssssssssssssssssssssssssssss ;ss inverter output setting ss ;sssssssssssssssssssssssssssssssssssssssss invset: bf _minit,$invset5 cmp pmode,#pmstop bnz $invset1 ;************ initialization for stop mode set1 pmk0 ; prohibit intp0 set1 tmmk7 ; prohibit inttm7 clr1 ce7 ; tm7 count stop set1 p6.4 ; output enable signal setting (prohibit output) mov nfout,#frqstop ; output frequency stop setting mov rfout,#frqstop ; target frequency stop setting br !invset8 invset1: cmp pmode,#pmchng bnz $invset8 ;************ initialization for change mode cmp nfout,#frqstop bnz $invset3 ;************ output start processing mov nfout,#foutini ; output frequency setting movw vfp,#vfpini ; vf modulation ratio pointer setting call !frqcng ; variable buffer setting call !waitset call !outst ; output start processing clr1 p6.4 ; output enable signal setting br $invset8 invset3: ;************ output frequency setting change mov a,nfout cmp a,rfout bc $invset4 dec nfout ; reduce output frequency ;@subw vfp,#2 ; change vf modulation ratio pointer movw ax,vfp subw ax,#1 movw vfp,ax br $invset6 invset4: inc nfout ; increase output frequency ;@addw vfp,#2 ; increase vf modulation ratio pointer movw ax,vfp addw ax,#1 movw vfp,ax br $invset6 invset5: ;************ frequency change mode processing cmp pmode,#pmchng bnz $invset10 ;@cmpw waitcnt,#0 movw ax,waitcnt cmpw ax,#0 bz $invset3
chapter 6 program list application note u13119ej4v0an 82 decw ax movw waitcnt,ax btclr _pchng,$invset9 br $invset8 invset6: call !waitset invset9: call !frqcng ; variable buffer setting set1 _chngst ; change start flag setting invset8: ret invset10: ;************ constant-rate output mode processing cmp pmode,#pmfout bnz $invset11 btclr _pchng,$invset9 br $invset8 invset11: ;************ stop mode processing mov rfout,#frqstop br $invset8
chapter 6 program list application note u13119ej4v0an 83 (18) pwm output start processing ;sssssssssssssssssssssssssssssssssssssssss ;ss pwm output start processing ss ;sssssssssssssssssssssssssssssssssssssssss outst: bt _10bit,$outst_10 movw ax,bvf movw vf,ax ; v/f modulation ratio transfer movw ax,bsadr movw sadr,ax ; step address transfer mov a,boffset mov offset,a ; v/f offset revision value transfer movw tm0wadr,#00h ; address calculation variable setting mov1 cy,_bsvf mov1 _svf,cy ; v/f modulation ratio flag transfer mov x,#0h mov a,bcm03 xch a,x movw bfcm3,ax movw cm3,ax ; carrier frequency change xch a,x clr1 cy rorc a,1 ; cm03/2 mov bfcm0l,a ; buffer register initialization mov bfcm1l,a mov bfcm2l,a mov a,bdtime ; dead time change mov dtime,a movw ax,#0ffh movw cm0,ax ; u-phase switching avoidance movw cm1,ax ; v-phase switching avoidance movw cm2,ax ; w-phase switching avoidance clr1 pif0 ; intp0 interrupt request clear clr1 pmk0 ; intp0 interrupt enable clr1 tmif7 ; inttm7 interrupt request clear clr1 tmmk7 ; inttm7 interrupt enable set1 ce7 ; tm7 operation setting ret outst_10: movw ax,bvf movw vf,ax ; v/f modulation ratio transfer movw ax,bsadr movw sadr,ax ; step address transfer movw ax,boffset movw offset,ax ; v/f offset revision value transfer movw tm0wadr,#00h ; address calculation variable setting mov1 cy,_bsvf mov1 _svf,cy ; v/f modulation flag transfer movw ax,bcm03 movw bfcm3,ax movw cm3,ax ; carrier frequency change
chapter 6 program list application note u13119ej4v0an 84 movw cm3,ax ; carrier frequency change ;@shrw ax,1 ; cm03/2 clr1 cy rorc a,1 xch a,x rorc a,1 xch a,x movw bfcm0,ax ; buffer register initialization movw bfcm1,ax movw bfcm2,ax mov a,bdtime ; dead time change mov dtime,a movw ax,#03ffh movw cm0,ax ; u-phase switching avoidance movw cm1,ax ; v-phase switching avoidance movw cm2,ax ; w-phase switching avoidance clr1 tmif7 ; inttm7 interrupt request clear clr1 tmmk7 ; inttm7 interrupt enable set1 ce7 ; tm7 operation setting ret (19) led and 8-segment led output processing ;sssssssssssssssssssssssssssssssssssssssssssssss ;ss led and 8-segment led output processing ss ;sssssssssssssssssssssssssssssssssssssssssssssss ledout: mov a,p5 ; mov p5,#0 ; digit output stop mov p4,#0 ; pattern output stop clr1 cy rorc a,1 mov1 a.2,cy mov1 cy,_ledout and1 cy,ledcnt.7 mov1 a.3,cy ; led output setting mov p5,a ; digit output start bf segcnt.7,$ledout1 mov1 cy,a.1 rolc a,1 and a,#00000011b ;@mov a,segbuf[a] ; display buffer reference mov c,a movw hl,#segbuf mov a,[hl+c] ;@mov a,ledtbl[a] ; display pattern reference mov c,a movw hl,#ledtbl mov a,[hl+c] mov p4,a ; pattern output start ledout1: ret
chapter 6 program list application note u13119ej4v0an 85 (20) led and 8-segment led display setting ;sssssssssssssssssssssssssssssssssssssssssssss ;ss led and 8-segment led display setting ss ;sssssssssssssssssssssssssssssssssssssssssssss ledset: ;************ output frequency display setting cmp dmode,#dmfout bnz $ledset3 cmp smode,#smoff bnz $ledset1 cmp pmode,#pmchng bz $ledset30 mov a,sfout br $ledset2 ledset30: mov a,nfout br $ledset2 ledset1: mov a,nset ledset2: call !bufset ; seg led display buffer setting br $ledset13 ledset3: ;************ carrier frequency display setting cmp dmode,#dmcrry bnz $ledset6 cmp smode,#smoff bnz $ledset4 mov a,ncrry br $ledset5 ledset4: mov a,nset ledset5: rol a,1 and a,#11111110b ;@movw ax,crrytbl[a] mov c,a movw hl,#crrytbl mov a,[hl+c] mov x,a inc c mov a,[hl+c] mov c,#100 divuw c mov a,x call !bufset ; seg led display buffer setting cmp segbuf+1,#chrspc ; less than 1.0? bz $ledset50 add segbuf+1,#10h ; add decimal point br $ledset13 ledset50: mov segbuf+1,#chrz ; set "0." br $ledset13 ledset6: ;************ dead time display setting cmp dmode,#dmdead bnz $ledset9 cmp smode,#smoff ; setting mode off?
chapter 6 program list application note u13119ej4v0an 86 bnz $ledset7 mov a,ndead br $ledset8 ledset7: mov a,nset ledset8: call !bufset ; seg led display buffer setting mov segbuf,#chrd ; set "d " br $ledset13 ledset9: ;************ change rate display setting cmp smode,#smoff bnz $ledset10 mov a,nchng br $ledset11 ledset10: mov a,nset ledset11: ;@mov a,chdsptbl[a] mov c,a movw hl,#chdsptbl mov a,[hl+c] call !bufset ; seg led display buffer setting mov segbuf,#chro ; set "o " cmp segbuf+1,#chrspc bz $ledset60 add segbuf+1,#10h ; add decimal point br $ledset13 ledset60: mov segbuf+1,#chrz ledset13: ;************ led flash counter setting cmp pmode,#pmstop bnz $ledset17 clr1 _ledout br $ledset14 ledset17: cmp pmode,#pmchng bnz $ledset18 dec ledcnt cmp ledcnt,#80h-ledini bnz $ledset19 ledset18: mov ledcnt,#80h+ledini ledset19: mov1 cy,ledcnt.7 mov1 _ledout,cy ledset14: ;************ 8-segment led flash counter setting cmp smode,#smoff bz $ledset16 dec segcnt cmp segcnt,#80h-segini bnz $ledset15 mov segcnt,#80h+segini br $ledset15 ledset16: mov segcnt,#80h+segini
chapter 6 program list application note u13119ej4v0an 87 ledset15: ret (21) 8-segment led output buffer setting ;sssssssssssssssssssssssssssssssssssssssss ;ss 8-segment led output buffer setting ss ;sssssssssssssssssssssssssssssssssssssssss bufset: ;************ initialization, third digit setting mov segbuf,#0 ; set "0 " mov segbuf+1,#0 ; set "0 " bufset1: ;************ first-digit setting cmp a,#100 bc $bufset2 inc segbuf sub a,#100 br $bufset1 bufset2: ;************ second-digit setting cmp a,#10 bc $bufset3 inc segbuf+1 sub a,#10 br $bufset2 bufset3: ;************ leading zero deletion cmp segbuf,#0 bnz $bufset4 mov segbuf,#chrspc cmp segbuf+1,#0 bnz $bufset4 mov segbuf+1,#chrspc bufset4: ;************ first-digit setting mov segbuf+2,a ret
chapter 6 program list application note u13119ej4v0an 88 (22) frequency setting change processing ;sssssssssssssssssssssssssssssssssssssssss ;ss frequency setting change processing ss ;sssssssssssssssssssssssssssssssssssssssss frqcng: ;********** change pattern setting (8-bit timer in use) bf _10bit,$frqcng_ br frqcng_x frqcng_: ;************ dtime (dead time) setting mov a,ndead mov x,#8 mulu x mov a,x mov bdtime,a ;************ bcm03 (carrier frequency) setting mov a,ncrry add a,a ;@movw ax,crrytbl[a] mov c,a movw hl,#crrytbl ; frqcng1: mov a,[hl+c] ; mov x,a ; inc c ; mov a,[hl+c] ; ;@addw ax,ax clr1 cy xch a,x rolc a,1 xch a,x rolc a,1 movw waru2,ax mov a,tm7clk rol a,1 rol a,1 and a,#11111100b mov c,a movw hl,#tmclktbl mov a,[hl+c] mov x,a inc c mov a,[hl+c] movw waru1,ax inc c mov a,[hl+c] mov x,a inc c mov a,[hl+c] movw waru1+2,ax call !divux mov a,waru1 mov bcm03,a ;************ bsadr (step address) setting mov a,ncrry add a,a
chapter 6 program list application note u13119ej4v0an 89 ;@movw ax,crrytbl[a] mov c,a movw hl,#crrytbl ; frqcng10: mov a,[hl+c] ; mov x,a ; inc c ; mov a,[hl+c] ; movw waru2,ax mov a,nfout mov x,#0 xch a,x movw waru1,#00h movw waru1+2,ax call !divux mov a,waru1 mov x,a mov a,tm7cnt mulu x movw bc,ax mov a,waru1+1 mov x,a mov a,tm7cnt mulu x xch a,x add b,a movw ax,bc movw bsadr,ax ;************ bvf (modulation ratio buffer) setting movw ax,bcm03 movw mkake1,ax movw ax,vfp movw hl,ax ;@movw hl,ax ;@movw ax,vftbl1[hl] movw ax,vftblno xch a,x add l,a xch a,x ; addc h,a ; mov a,[hl] ; bt _vfon,$frqcng15 mov a,#80h frqcng15: clr1 _bsvf cmp a,#80h ; v/f modulation ratio < 0? bc $frqcng20 ; then [next] set1 _bsvf ; else [_bsvf set] frqcng20: mov x,a mov a,bcm03 mulu x xch a,x rolc a,1 xch a,x rolc a,1
chapter 6 program list application note u13119ej4v0an 90 xch a,x rolc a,1 and a,#00000001b movw bvf,ax ;************ boffset (v/f offset revision value) setting mov a,bcm03 clr1 cy rorc a,1 ; cm03/2 mov e,a movw ax,bvf ;@shrw ax,1 ; vf/2 clr1 cy rorc a,1 xch a,x rorc a,1 cmp a,e bnc $frqcng30 xch a,e frqcng30: sub a,e ; offset revision value = |vf/2 - cm03/2| mov boffset,a dec bcm03 dec bdtime ret frqcng_x: ;********** change pattern setting (10-bit timer in use) ;************ dtime (dead time) setting mov a,ndead mov x,#8 mulu x mov a,x mov bdtime,a ;************ bcm03 (carrier frequency) setting mov a,ncrry add a,a ;@movw ax,crrytbl[a] mov c,a movw hl,#crrytbl frqc1_x: mov a,[hl+c] ; mov x,a ; inc c ; mov a,[hl+c] ; ;@addw ax,ax clr1 cy xch a,x rolc a,1 xch a,x rolc a,1 movw waru2,ax mov a,tm7clk rol a,1 rol a,1 and a,#11111100b mov c,a movw hl,#tmclktbl
chapter 6 program list application note u13119ej4v0an 91 mov a,[hl+c] mov x,a inc c mov a,[hl+c] movw waru1,ax inc c mov a,[hl+c] mov x,a inc c mov a,[hl+c] movw waru1+2,ax call !divux mov a,waru1 mov bcm03,a ;************ bsadr (step address) setting mov a,ncrry add a,a ;@movw ax,crrytbl[a] mov c,a movw hl,#crrytbl ; frqcng10: mov a,[hl+c] ; mov x,a ; inc c ; mov a,[hl+c] ; movw waru2,ax mov a,nfout mov x,#0 xch a,x movw waru1,#00h movw waru1+2,ax call !divux mov a,waru1 mov x,a mov a,tm7cnt mulu x movw bc,ax mov a,waru1+1 mov x,a mov a,tm7cnt mulu x xch a,x add b,a movw ax,bc movw bsadr,ax ;************ bvf (modulation ratio buffer) setting movw ax,bcm03 movw mkake1,ax movw ax,vfp movw hl,ax ;@movw hl,ax ;@movw ax,vftbl1[hl] movw ax,vftblno xch a,x add l,a xch a,x ;
chapter 6 program list application note u13119ej4v0an 92 addc h,a ; mov a,[hl] ; bt _vfon,$frqc15_x mov a,#80h frqc15_x: clr1 _bsvf cmp a,#80h ; v/f modulation ratio < 0? bc $frqc20_x ; then [next] set1 _bsvf ; else [_bsvf set] frqc20_x: xch a,x mov a,#0 movw mkake2,ax call !muluw mov a,mkotae rolc a,1 mov a,mkotae+1 rolc a,1 xch a,x mov a,mkotae+2 rolc a,1 movw bvf,ax ;************ boffset (v/f offset revision value) setting movw ax,bcm03 ;@shrw ax,1 ; cm03/2 clr1 cy rorc a,1 xch a,x rorc a,1 xch a,x movw de,ax movw ax,bvf ;@shrw ax,1 ; vf/2 clr1 cy rorc a,1 xch a,x rorc a,1 xch a,x ;@cmpw ax,de cmp a,d bz $frqc40_x bnc $frqc30_x frqc29_x: xchw ax,de frqc30_x: ;@subw ax,de ; offset revision value = |vf/2 ? cm03/2| xch a,x sub a,e xch a,x subc a,d movw boffset,ax ;@decw bcm03 movw ax,bcm03 decw ax movw bcm03,ax dec bdtime
chapter 6 program list application note u13119ej4v0an 93 ret frqc40_x: xch a,x cmp a,e xch a,x bnc $frqc30_x br frqc29_x (23) binary division (32 16) ;sssssssssssssssssssssssssssssssssssssssss ;ss binary division (32 16) ss ;sssssssssssssssssssssssssssssssssssssssss divux: movw amari,#00h ; mov b,#32 divux1: clr1 cy mov a,waru1 ; rolc a,1 mov waru1,a mov a,waru1+1 ; rolc a,1 mov waru1+1,a mov a,waru1+2 ; rolc a,1 mov waru1+2,a mov a,waru1+3 ; rolc a,1 mov waru1+3,a mov a,amari ; rolc a,1 mov amari,a mov a,amari+1 ; rolc a,1 mov amari+1,a movw ax,amari xch a,x sub a,waru2 xch a,x subc a,waru2+1 bc $divux2 movw amari,ax set1 waru1.0 ; divux2: dbnz b,$divux1 ret
chapter 6 program list application note u13119ej4v0an 94 (24) binary multiplication (16 16) ;sssssssssssssssssssssssssssssssssssssssss ;ss binary multiplication (16 16) ss ;sssssssssssssssssssssssssssssssssssssssss muluw: mov a,mkake1 mov x,a mov a,mkake2 mulu x movw mkotae,ax mov a,mkake1+1 mov x,a mov a,mkake2+1 mulu x movw mkotae+2,ax mov a,mkake1 mov x,a mov a,mkake2+1 mulu x xch a,x add a,mkotae+1 mov mkotae+1,a xch a,x addc a,mkotae+2 mov mkotae+2,a addc mkotae+3,#0 mov a,mkake1+1 mov x,a mov a,mkake2 mulu x xch a,x add a,mkotae+1 mov mkotae+1,a xch a,x addc a,mkotae+2 mov mkotae+2,a addc mkotae+3,#0 ret
chapter 6 program list application note u13119ej4v0an 95 (25) output frequency change rate setting ;ssssssssssssssssssssssssssssssssssssssssssss ;ss output frequency change rate setting ss ;ssssssssssssssssssssssssssssssssssssssssssss waitset: mov a,nchng rol a,1 and a,#11111110b ;@movw ax,chngtbl[a] mov c,a movw hl,#chngtbl mov a,[hl+c] mov x,a inc c mov a,[hl+c] movw waitcnt,ax ; wait counter setting ret end
chapter 6 program list application note u13119ej4v0an 96 6.2 interrupt processing $ processor(f0924) $include(inc092x.inc) ; constant definition extrn sintbl, sintbl1 ; table extrn bvf, vf, bsadr, sadr ; saddr variable extrn bcm03, boffset,offset ; saddr variable extrn ikake1, ikake2, ikotae ; saddr variable extrn rfout ; saddr variable extbit _chngst,_bsvf, _svf,_10bit ; flags public ladr, intp0 ; interrupts code cseg ; iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii ; ii intp0 vectored interrupt ii ; iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii intp0: sel rb2 ; register bank setting intp0_1: mov a,p0 ; stop signal input (first time) and a,#00000001b xch a,x mov b,#1 intp0_2: dbnz b,$intp0_2 mov a,p0 ; stop signal input (second time) and a,#00000001b cmp a,x bnz $intp0_1 ; match? bt a.0,$intp0_3 ; error signal active? mov rfout,#0ffh ; clr1 ce7 ; stop setting set1 pmk0 ; intp0 di intp0_3: ret1 ;iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii ;ii inttm7 vectored interrupt ii ;iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii ladr: ;************ output enable setting sel rb1 ladr0: ;************ test pin output processing set1 p6.6 ;;bt _10bit,$ladr1_x bf _10bit,$ladr1 br ladr1_x ; *---------------------------------------------- ; * 8-bit timer in use ; *---------------------------------------------- ladr1: ;************ reference address calculation movw ax,hl xch a,x
chapter 6 program list application note u13119ej4v0an 97 add a,sadr xch a,x addc a,sadr+1 movw hl,ax luadr: ;************ u-phase timing setting movw ax,vf mov a,h movw de,#sintbl ; sine wave table reference add a,e xch a,e mov a,#00 addc a,d xch a,d mov a,[de] mov e,a mulu x ; multiplication by modulation ratio clr1 cy bf (vf+1).0,$luadr0 add a,e luadr0: xch ax rolc a,1 and a,#00000001b xch a,x bf _svf,$luadr1 ; v/f modulation ratio < 1? sub a,offset ; else [subtract offset value] xch a,x subc a,#0 bnc $luskp movw ax,#00h br $luskp luadr1: add a,offset ; then [add offset value] xch a,x addc a,#0 luskp: bf a.0,$luskp_0 mov x,#0ffh luskp_0: xch a,x mov bfcm0l,a ; timing setting lvadr: ;************ v-phase timing setting movw ax,vf mov a,h add a,#addadr1 movw de,#sintbl ; sine wave table reference add a,e xch a,e mov a,#00 addc a,d xch a,d mov a,[de] mov e,a mulu x ; multiplication by modulation ratio clr1 cy bf (vf+1).0,$lvadr0
chapter 6 program list application note u13119ej4v0an 98 add a,e luadr0: xch a,x rolc a,1 and a,#00000001b xch a,x bf _svf,$luadr1 ; v/f modulation ratio < 1? sub a,offset ; else [subtract offset value] xch a,x subc a,#0 bnc $luskp movw ax,#00h br $luskp luadr1: add a,offset ; then [add offset value] xch a,x addc a,#0 luskp: bf a.0,$luskp_0 mov x,#0ffh luskp_0: xch a,x mov bfcm0l,a ; timing setting lvadr: ;************ v-phase timing setting movw ax,vf mov a,h add a,#addadr1 movw de,#sintbl ; sine wave table reference add a,e xch a,e mov a,#00 addc a,d xch a,d mov a,[de] mov e,a mulu x ; multiplication by modulation ratio clr1 cy bf (vf+1).0,$lvadr0 add a,e lvadr0: xch a,x rolc a,1 and a,#00000001b xch a,x bf _svf,$lvadr1 ; v/f modulation ratio < 1? sub a,offset ; else [subtract offset value] xch a,x subc a,#0 bnc $lvskp movw ax,#00h br $lvskp lvadr1: add a,offset ; then [add offset value] xch a,x addc a,#0 lvskp:
chapter 6 program list application note u13119ej4v0an 99 bf a.0,$lvskp_0 mov x,#0ffh lwskp_0: xch a,x mov bfcm2l,a ; timing setting lend: bf _chngst,$ladr3 ladr2: clr1 _chngst ; change flag clear mov x,#0 mov a,bcm03 xch a,x movw bfcm3,ax ; carrier frequency transfer movw ax,bvf ; movw vf,ax ; v/f modulation ratio transfer movw ax,bsadr ; movw sadr,ax ; step address transfer mov a,boffset ; mov offset,a ; v/f offset revision value transfer mov1 cy,_bsvf ; mov1 _svf,cy ; v/f modulation ratio < 1 (flag transfer) ladr3: ;************ test pin output processing clr1 p6.6 reti ; *---------------------------------------------- ; * 10-bit timer in use ; *---------------------------------------------- ladr1_x: ;************ reference address calculation movw ax,vf movw ikake1,ax movw ax,hl ;;addw ax,sadr xch a,x add a,sadr xch a,x addc a,sadr+1 movw hl,ax xch a,x rol a,1 xch a,x rolc a,1 xch a,x mov a,#00h addc a,#00h ;;addw ax,ax clr1 cy xch a,x rolc a,1 xch a,x rolc a,1 rolc a,1 xch a,x rolc a,1 movw bc,ax
chapter 6 program list application note u13119ej4v0an 100 luadr_x: ;************ u-phase timing setting ;;@movw ax,sintbl[de] ; sine wave table reference movw de,#sintbl1 ; xch a,x add e,a xch a,x addc d,a mov a,[de] mov x,a incw de mov a,[de] ;;vfxsintbl[] ; multiplication by modulation ratio movw ikake2,ax call !smuluw mov a,ikotae+1 mov x,a mov a,ikotae+2 rorc a,1 xch a,x rorc a,1 xch a,x rorc a,1 xch a,x rorc a,1 xch a,x and a,#00000111b bf _svf,$luadr1_x ; v/f modulation ratio < 1? ;;subw ax,offset ; else [subtract offset value] xch a,x sub a,offset xch a,x subc a,offset+1 bnc $luskp_x movw ax,#0000h br $luskp_x luadr1_x: ;;addw ax,offset ; then [add offset value] xch a,x add a,offset xch a,x addc a,offset+1 luskp_x: bf a.2,$luskp_x1 movw ax,#03ffh luskp_x1: movw bfcm0,ax ; timing setting lvadr_x: ;************ v-phase timing setting ;; movw ax,vf ;; movw ikake1,ax movw ax,bc addw ax,#addadr1x and a,#00000011b ;;@movw ax,sintbl[de] ; sine wave table reference movw de,#sintbl1 xch a,x add e,a
chapter 6 program list application note u13119ej4v0an 101 xch a,x addc d,a mov a,[de] mov x,a incw de mov a,[de] ;;vfxsintbl[] ; multiplication by modulation ratio movw ikake2,ax call !smuluw mov a,ikotae+1 mov x,a mov a,ikotae+2 rorc a,1 xch a,x rorc a,1 xch a,x rorc a,1 xch a,x rorc a,1 xch a,x and a,#00000111b bf _svf,$lvadr1_x ; v/f modulation ratio < 1? ;;subw ax,offset ; else [subtract offset value] xch a,x sub a,offset xch a,x subc a,offset+1 bnc $lvskp_x movw ax,#0000h br $lvskp_x lvadr1_x: ;;addw ax,offset ; then [add offset value] xch a,x add a,offset xch a,x addc a,offset+1 lvskp_x: bf a.2,$lvskp_x1 movw ax,#03ffh lvskp_x1: movw bfcm1,ax ; timing setting lwadr_x: ;************ w-phase timing setting ;; movw ax,vf ;; movw ikake1,ax movw ax,bc addw ax,#addadr2x and a,#00000011b ;@movw ax,sintbl[de] ; sine wave table reference movw de,#sintbl1 xch a,x add e,a xch a,x addc d,a mov a,[de] mov x,a incw de
chapter 6 program list application note u13119ej4v0an 102 mov a,[de] ;;vfxsintbl[] ; multiplication by modulation ratio movw ikake2,ax call !smuluw mov a,ikotae+1 mov x,v mov a,ikotae+2 rorc a,1 xch a,x rorc a,1 xch a,x rorc a,1 xch a,x rorc a,1 xch a,x and a,#00000111b bf _svf,$lwadr1_x ; v/f modulation ratio < 1? ;;subw ax,offset ; else [subtract offset value] xch a,x sub a,offset xch a,x subc a,offset+1 bnc $lwskp_x movw ax,#0000h br $lwskp_x lwadr1_x: ;;addw ax,offset ; then [add offset value] xch a,x add a,offset xch a,x addc a,offset+1 lwskp_x: bf a.2,$lwskp_x1 movw ax,#03ffh lwskp_x1: movw bfcm2,ax ; timing setting lend_x: bf _chngst,$ladr3_x ladr2_x: clr1 _chngst ; change flag clear movw ax,bcm03 movw bfcm3,ax ; carrier frequency transfer movw ax,bvf ; movw vf,ax ; v/f modulation ratio transfer movw ax,bsadr ; movw sadr,ax ; step address transfer movw ax,boffset ; movw offset,ax ; v/f offset revision value transfer mov1 cy,_bsvf ; mov1 _svf,cy ; v/f modulation ratio < 1 (flag transfer) ladr3_x: ;************ test pin output processing clr1 p6.6 reti
chapter 6 program list application note u13119ej4v0an 103 ; *-------------------------------------------------------- ; * 16 bit x 16 bit multiplication subroutine ; *-------------------------------------------------------- smuluw: mov a,ikake1 mov x,a mov a,ikake2 mulu x movw ikotae,ax mov a,ikake1+1 mov x,a mov a,ikake2+1 mulu x movw ikotae+2,ax mov a,ikake1 mov x,a mov a,ikake2+1 mulu x xch a,x add a,ikotae+1 mov ikotae+1,a xch a,x addc a,ikotae+2 mov ikotae+2,a addc ikotae+3,#0 mov a,ikake1+1 mov x,a mov a,ikake2 mulu x xch a,x add a,ikotae+1 mov ikotae+1,a xch a,x addc a,ikotae+2 mov ikotae+2,a addc ikotae+3,#0 ret end
chapter 6 program list application note u13119ej4v0an 104 6.3 table data public sintbl, sintbl1,vftbl ; table public vftbl1, vftbl2, vftbl3, vftbl4 ; table public vftbl5, vftbl6, vftbl7, vftbl8 ; table public crrytbl,fmxtbl, dmxtbl ; table public chngtbl,ledtbl, chdsptbl ; table public tmclktbl,cmntbl10,cmntbl08 ; table (1) sine wave table (256*1 bytes)/007fh table cseg ;ttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt ;tt sine wave table (256*1 bytes) / 007fh tt ;ttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt ; table data = sin(x)*007fh + 007fh ; sintbl: db 07fh, 082h, 085h, 088h, 08bh, 08fh, 092h, 095h ; db 098h, 09bh, 09eh, 0a1h, 0a4h, 0a7h, 0aah, 0adh ; db 0b0h, 0b2h, 0b5h, 0b8h, 0bbh, 0beh, 0c0h, 0c3h ; db 0c6h, 0c8h, 0cbh, 0cdh, 0d0h, 0d2h, 0d4h, 0d7h ; db 0d9h, 0dbh, 0ddh, 0dfh, 0e1h, 0e3h, 0e5h, 0e7h ; db 0e9h, 0eah, 0ech, 0edh, 0efh, 0f0h, 0f2h, 0f3h ; db 0f4h, 0f5h, 0f7h, 0f8h, 0f9h, 0f9h, 0fah, 0fbh ; db 0fch, 0fch, 0fdh, 0fdh, 0fdh, 0feh, 0feh, 0feh ; db 0feh, 0feh, 0feh, 0feh, 0fdh, 0fdh, 0fdh, 0fch ; db 0fch, 0fbh, 0fah, 0f9h, 0f9h, 0f8h, 0f7h, 0f6h ; db 0f4h, 0f3h, 0f2h, 0f0h, 0efh, 0eeh, 0ech, 0eah ; db 0e9h, 0e7h, 0e5h, 0e3h, 0e1h, 0dfh, 0ddh, 0dbh ; db 0d9h, 0d7h, 0d4h, 0d2h, 0d0h, 0cdh, 0cbh, 0c8h ; db 0c6h, 0c3h, 0c0h, 0beh, 0bbh, 0b8h, 0b5h, 0b3h ; db 0b0h, 0adh, 0aah, 0a7h, 0a4h, 0a1h, 09eh, 09bh ; db 098h, 095h, 092h, 08fh, 08ch, 088h, 085h, 082h ; db 07fh, 07ch, 079h, 076h, 073h, 070h, 06ch, 069h ; db 066h, 063h, 060h, 05dh, 05ah, 057h, 054h, 051h ; db 04eh, 04ch, 049h, 046h, 043h, 040h, 03eh, 03bh ; db 039h, 036h, 033h, 031h, 02eh, 02ch, 02ah, 027h ; db 025h, 023h, 021h, 01fh, 01dh, 01bh, 019h, 017h ; db 015h, 014h, 012h, 011h, 00fh, 00eh, 00ch, 00bh ; db 00ah, 009h, 007h, 006h, 005h, 005h, 004h, 003h ; db 002h, 002h, 001h, 001h, 001h, 000h, 000h, 000h ; db 000h, 000h, 000h, 000h, 001h, 001h, 001h, 002h ; db 002h, 003h, 004h, 005h, 005h, 006h, 007h, 008h ; db 00ah, 00bh, 00ch, 00eh, 00fh, 010h, 012h, 014h ; db 015h, 017h, 019h, 01bh, 01dh, 01fh, 021h, 023h ; db 025h, 027h, 02ah, 02ch, 02eh, 031h, 033h, 036h ; db 038h, 03bh, 03eh, 040h, 043h, 046h, 049h, 04bh ; db 04eh, 051h, 054h, 057h, 05ah, 05dh, 060h, 063h ; db 066h, 069h, 06ch, 06fh, 072h, 076h, 079h, 07ch ;
chapter 6 program list application note u13119ej4v0an 105 (2) sine wave table (512*2 bytes)/01ffh ;ttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt ;tt sine wave table (512*2 bytes) / 01ffh tt ;ttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt ; table data = sin(x)*01ffh + 01ffh ; sintbl1: dw 01ffh, 0205h, 020ch, 0212h, 0218h, 021eh, 0225h, 022bh ; dw 0231h, 0237h, 023eh, 0244h, 024ah, 0250h, 0256h, 025dh ; dw 0263h, 0269h, 026fh, 0275h, 027bh, 0281h, 0287h, 028dh ; dw 0293h, 0299h, 029fh, 02a5h, 02abh, 02b1h, 02b7h, 02bdh ; dw 02c3h, 02c8h, 02ceh, 02d4h, 02d9h, 02dfh, 02e5h, 02eah ; dw 02f0h, 02f5h, 02fbh, 0300h, 0306h, 030bh, 0310h, 0316h ; dw 031bh, 0320h, 0325h, 032ah, 032fh, 0334h, 0339h, 033eh ; dw 0343h, 0348h, 034dh, 0351h, 0356h, 035bh, 035fh, 0364h ; dw 0368h, 036dh, 0371h, 0375h, 037ah, 037eh, 0382h, 0386h ; dw 038ah, 038eh, 0392h, 0396h, 0399h, 039dh, 03a1h, 03a4h ; dw 03a8h, 03abh, 03afh, 03b2h, 03b5h, 03b8h, 03bch, 03bfh ; dw 03c2h, 03c5h, 03c7h, 03cah, 03cdh, 03d0h, 03d2h, 03d5h ; dw 03d7h, 03d9h, 03dch, 03deh, 03e0h, 03e2h, 03e4h, 03e6h ; dw 03e8h, 03eah, 03ebh, 03edh, 03efh, 03f0h, 03f2h, 03f3h ; dw 03f4h, 03f5h, 03f6h, 03f7h, 03f8h, 03f9h, 03fah, 03fbh ; dw 03fch, 03fch, 03fdh, 03fdh, 03fdh, 03feh, 03feh, 03feh ; dw 03feh, 03feh, 03feh, 03feh, 03fdh, 03fdh, 03fdh, 03fch ; dw 03fch, 03fbh, 03fah, 03f9h, 03f8h, 03f8h, 03f7h, 03f5h ; dw 03f4h, 03f3h, 03f2h, 03f0h, 03efh, 03edh, 03ech, 03eah ; dw 03e8h, 03e6h, 03e4h, 03e2h, 03e0h, 03deh, 03dch, 03dah ; dw 03d7h, 03d5h, 03d2h, 03d0h, 03cdh, 03cah, 03c8h, 03c5h ; dw 03c2h, 03bfh, 03bch, 03b9h, 03b5h, 03b2h, 03afh, 03abh ; dw 03a8h, 03a4h, 03a1h, 039dh, 039ah, 0396h, 0392h, 038eh ; dw 038ah, 0386h, 0382h, 037eh, 037ah, 0376h, 0371h, 036dh ; dw 0368h, 0364h, 0360h, 035bh, 0356h, 0352h, 034dh, 0348h ; dw 0343h, 033eh, 033ah, 0335h, 0330h, 032bh, 0325h, 0320h ; dw 031bh, 0316h, 0311h, 030bh, 0306h, 0301h, 02fbh, 02f6h ; dw 02f0h, 02ebh, 02e5h, 02dfh, 02dah, 02d4h, 02ceh, 02c9h ; dw 02c3h, 02bdh, 02b7h, 02b1h, 02abh, 02a5h, 02a0h, 029ah ; dw 0294h, 028eh, 0288h, 0281h, 027bh, 0275h, 026fh, 0269h ; dw 0263h, 025dh, 0257h, 0250h, 024ah, 0244h, 023eh, 0238h ; dw 0231h, 022bh, 0225h, 021fh, 0218h, 0212h, 020ch, 0206h ; dw 01ffh, 01f9h, 01f3h, 01ech, 01e6h, 01e0h, 01dah, 01d3h ; dw 01cdh, 01c7h, 01c1h, 01bbh, 01b4h, 01aeh, 01a8h, 01a2h ; dw 019ch, 0195h, 018fh, 0189h, 0183h, 017dh, 0177h, 0171h ; dw 016bh, 0165h, 015fh, 0159h, 0153h, 014dh, 0147h, 0142h ; dw 013ch, 0136h, 0130h, 012ah, 0125h, 011fh, 011ah, 0114h ; dw 010eh, 0109h, 0103h, 00feh, 00f9h, 00f3h, 00eeh, 00e9h ; dw 00e3h, 00deh, 00d9h, 00d4h, 00cfh, 00cah, 00c5h, 00c0h ; dw 00bbh, 00b6h, 00b1h, 00adh, 00a8h, 00a3h, 009fh, 009ah ; dw 0096h, 0092h, 008dh, 0089h, 0085h, 0080h, 007ch, 0078h ; dw 0074h, 0070h, 006ch, 0069h, 0065h, 0061h, 005dh, 005ah ; dw 0056h, 0053h, 004fh, 004ch, 0049h, 0046h, 0043h, 0040h ; dw 003dh, 003ah, 0037h, 0034h, 0031h, 002fh, 002ch, 0029h ; dw 0027h, 0025h, 0022h, 0020h, 001eh, 001ch, 001ah, 0018h ; dw 0016h, 0014h, 0013h, 0011h, 000fh, 000eh, 000dh, 000bh ; dw 000ah, 0009h, 0008h, 0007h, 0006h, 0005h, 0004h, 0003h ; dw 0003h, 0002h, 0001h, 0001h, 0001h, 0000h, 0000h, 0000h ; dw 0000h, 0000h, 0000h, 0000h, 0001h, 0001h, 0001h, 0002h ;
chapter 6 program list application note u13119ej4v0an 106 dw 0002h, 0003h, 0004h, 0005h, 0005h, 0006h, 0007h, 0009h ; dw 000ah, 000bh, 000ch, 000eh, 000fh, 0011h, 0012h, 0014h ; dw 0016h, 0018h, 001ah, 001ch, 001eh, 0020h, 0022h, 0024h ; dw 0027h, 0029h, 002ch, 002eh, 0031h, 0034h, 0036h, 0039h ; dw 003ch, 003fh, 0042h, 0045h, 0048h, 004ch, 004fh, 0052h ; dw 0056h, 0059h, 005dh, 0061h, 0064h, 0068h, 006ch, 0070h ; dw 0074h, 0078h, 007ch, 0080h, 0084h, 0088h, 008dh, 0091h ; dw 0095h, 009ah, 009eh, 00a3h, 00a7h, 00ach, 00b1h, 00b6h ; dw 00bah, 00bfh, 00c4h, 00c9h, 00ceh, 00d3h, 00d8h, 00ddh ; dw 00e3h, 00e8h, 00edh, 00f2h, 00f8h, 00fdh, 0103h, 0108h ; dw 010eh, 0113h, 0119h, 011eh, 0124h, 012ah, 012fh, 0135h ; dw 013bh, 0141h, 0147h, 014ch, 0152h, 0158h, 015eh, 0164h ; dw 016ah, 0170h, 0176h, 017ch, 0182h, 0188h, 018fh, 0195h ; dw 019bh, 01a1h, 01a7h, 01adh, 01b3h, 01bah, 01c0h, 01c6h ; dw 01cch, 01d3h, 01d9h, 01dfh, 01e5h, 01ech, 01f2h, 01f8h ; (3) vf modulation ratio table no. 1 ;ttttttttttttttttttttttttttttttttttttttttt ;tt vf modulation ratio table no. 1 tt ;ttttttttttttttttttttttttttttttttttttttttt ; 10 hz: 0.4 60 hz: 1.0 110 hz: 1.6 ; table data = (modulation ratio)*100h vftbl1: ;+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 [hz] db 02ah,02ch,02dh,02fh,030h,032h ; 0 hz db 033h,035h,036h,038h,039h,03bh,03ch,03eh,03fh,041h ; 10 hz db 043h,044h,046h,047h,049h,04ah,04ch,04dh,04fh,050h ; 20 hz db 052h,053h,055h,057h,058h,05ah,05bh,05dh,05eh,060h ; 30 hz db 061h,063h,064h,066h,067h,069h,06ah,06ch,06eh,06fh ; 40 hz db 071h,072h,074h,075h,077h,078h,07ah,07bh,07dh,07eh ; 50 hz db 080h,082h,083h,085h,086h,088h,089h,08bh,08ch,08eh ; 60 hz db 08fh,091h,092h,094h,096h,097h,099h,09ah,09ch,09dh ; 70 hz db 09fh,0a1h,0a2h,0a3h,0a5h,0a6h,0a8h,0a9h,0abh,0adh ; 80 hz db 0aeh,0b0h,0b1h,0b3h,0b4h,0b6h,0b7h,0b9h,0bah,0bch ; 90 hz db 0bdh,0bfh,0c1h,0c2h,0c4h,0c5h,0c7h,0c8h,0cah,0cbh ; 100 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 110 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 120 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 130 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 140 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 150 hz db 0cdh ; 160 hz (4) vf modulation ratio table no. 2 ;ttttttttttttttttttttttttttttttttttttttttt ;tt vf modulation ratio table no. 2 tt ;ttttttttttttttttttttttttttttttttttttttttt ; 10 hz: 0.2 60 hz: 1.0 110 hz: 1.6 ; table data = (modulation ratio)*100h vftbl2: ;+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 [hz] db 00dh,00fh,011h,013h,016h,018h ; 0 hz db 01ah,01ch,01eh,020h,022h,024h,026h,028h,02ah,02ch ; 10 hz db 02eh,030h,032h,034h,036h,038h,03ah,03ch,03eh,041h ; 20 hz db 043h,045h,047h,049h,04bh,04dh,04fh,051h,053h,055h ; 30 hz db 057h,059h,05bh,05dh,05fh,061h,063h,065h,067h,069h ; 40 hz db 06ch,06eh,070h,072h,074h,076h,078h,07ah,07ch,07eh ; 50 hz
chapter 6 program list application note u13119ej4v0an 107 db 080h,082h,083h,085h,086h,088h,089h,08bh,08ch,08eh ; 60 hz db 0b8h,0b9h,0b9h,0bah,0bah,0bbh,0bbh,0bch,0bch,0bdh ; 70 hz db 0bdh,0beh,0beh,0bfh,0bfh,0c0h,0c1h,0c1h,0c2h,0c2h ; 80 hz db 0c3h,0c3h,0c4h,0c4h,0c5h,0c5h,0c6h,0c6h,0c7h,0c7h ; 90 hz db 0c8h,0c8h,0c9h,0c9h,0cah,0cah,0cbh,0cbh,0cch,0cch ; 100 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 110 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 120 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 130 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 140 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 150 hz db 0cdh ; 160 hz (5) vf modulation ratio table no. 3 ;ttttttttttttttttttttttttttttttttttttttttt ;tt vf modulation ratio table no. 3 tt ;ttttttttttttttttttttttttttttttttttttttttt ; 10 hz: 0.4 60 hz: 1.4 110 hz: 1.6 ; table data = (modulation ratio)*100h vftbl3: ;+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 [hz] db 024h,026h,029h,02ch,02eh,031h ; 0 hz db 033h,036h,038h,03bh,03dh,040h,043h,045h,048h,04ah ; 10 hz db 04dh,04fh,052h,054h,057h,05ah,05ch,05fh,061h,064h ; 20 hz db 066h,069h,06ch,06eh,071h,073h,076h,078h,07bh,07dh ; 30 hz db 080h,083h,085h,088h,08ah,08dh,08fh,092h,094h,097h ; 40 hz db 09ah,09ch,09fh,0a1h,0a4h,0a6h,0a9h,0ach,0aeh,0b1h ; 50 hz db 0b3h,0b4h,0b4h,0b5h,0b5h,0b6h,0b6h,0b7h,0b7h,0b8h ; 60 hz db 0b8h,0b9h,0b9h,0bah,0bah,0bbh,0bbh,0bch,0bch,0bdh ; 70 hz db 0bdh,0beh,0beh,0bfh,0bfh,0c0h,0c1h,0c1h,0c2h,0c2h ; 80 hz db 0c3h,0c3h,0c4h,0c4h,0c5h,0c5h,0c6h,0c6h,0c7h,0c7h ; 90 hz db 0c8h,0c8h,0c9h,0c9h,0cah,0cah,0cbh,0cbh,0cch,0cch ; 100 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 110 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 120 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 130 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 140 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 150 hz db 0cdh ; 160 hz (6) vf modulation ratio table no. 4 ;ttttttttttttttttttttttttttttttttttttttttt ;tt vf modulation ratio table no. 4 tt ;ttttttttttttttttttttttttttttttttttttttttt ; 10 hz: 0.2 60 hz: 1.4 110 hz: 1.6 ; table data = (modulation ratio)*100h vftbl4: ;+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 [hz] db 007h,00ah,00dh,010h,013h,017h ; 0 hz db 01ah,01dh,020h,023h,026h,029h,02ch,02fh,032h,035h ; 10 hz db 038h,03bh,03eh,042h,045h,048h,04bh,04eh,051h,054h ; 20 hz db 057h,05ah,05dh,060h,063h,066h,069h,06dh,070h,073h ; 30 hz db 076h,079h,07ch,07fh,082h,085h,088h,08bh,08eh,091h ; 40 hz db 094h,098h,09bh,09eh,0a1h,0a4h,0a7h,0aah,0adh,0b0h ; 50 hz db 0b3h,0b4h,0b4h,0b5h,0b5h,0b6h,0b6h,0b7h,0b7h,0b8h ; 60 hz db 0b8h,0b9h,0b9h,0bah,0bah,0bbh,0bbh,0bch,0bch,0bdh ; 70 hz db 0bdh,0beh,0beh,0bfh,0bfh,0c0h,0c1h,0c1h,0c2h,0c2h ; 80 hz db 0c3h,0c3h,0c4h,0c4h,0c5h,0c5h,0c6h,0c6h,0c7h,0c7h ; 90 hz
chapter 6 program list application note u13119ej4v0an 108 db 0c8h,0c8h,0c9h,0c9h,0cah,0cah,0cbh,0cbh,0cch,0cch ; 100 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 110 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 120 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 130 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 140 hz db 0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh,0cdh ; 150 hz db 0cdh ; 160 hz (7) vf modulation ratio table no. 5 ;ttttttttttttttttttttttttttttttttttttttttt ;tt vf modulation ratio table no. 5 tt ;ttttttttttttttttttttttttttttttttttttttttt ; 10 hz: 0.4 60 hz: 1.0 80 hz: 1.2 ; table data = (modulation ratio)*100h vftbl5: ;+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 [hz] db 02ah,02ch,02dh,02fh,030h,032h ; 0 hz db 033h,035h,036h,038h,039h,03bh,03ch,03eh,03fh,041h ; 10 hz db 043h,044h,046h,047h,049h,04ah,04ch,04dh,04fh,050h ; 20 hz db 052h,053h,055h,057h,058h,05ah,05bh,05dh,05eh,060h ; 30 hz db 061h,063h,064h,066h,067h,069h,06ah,06ch,06eh,06fh ; 40 hz db 071h,072h,074h,075h,077h,078h,07ah,07bh,07dh,07eh ; 50 hz db 080h,081h,083h,084h,085h,086h,088h,089h,08ah,08ch ; 60 hz db 08dh,08eh,08fh,091h,092h,093h,094h,096h,097h,098h ; 70 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 80 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 90 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 100 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 110 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 120 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 130 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 140 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 150 hz db 09ah ; 160 hz (8) vf modulation ratio table no. 6 ;ttttttttttttttttttttttttttttttttttttttttt ;tt vf modulation ratio table no. 6 tt ;ttttttttttttttttttttttttttttttttttttttttt ; 10 hz: 0.2 60 hz: 1.0 80 hz :1.2 ; table data = (modulation ratio)*100h vftbl6: ;+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 [hz] db 00dh,00fh,011h,013h,016h,018h ; 0 hz db 01ah,01ch,01eh,020h,022h,024h,026h,028h,02ah,02ch ; 10 hz db 02eh,030h,032h,034h,036h,038h,03ah,03ch,03eh,041h ; 20 hz db 043h,045h,047h,049h,04bh,04dh,04fh,051h,053h,055h ; 30 hz db 057h,059h,05bh,05dh,05fh,061h,063h,065h,067h,069h ; 40 hz db 06ch,06eh,070h,072h,074h,076h,078h,07ah,07ch,07eh ; 50 hz db 080h,081h,083h,084h,085h,086h,088h,089h,08ah,08ch ; 60 hz db 08dh,08eh,08fh,091h,092h,093h,094h,096h,097h,098h ; 70 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 80 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 90 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 100 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 110 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 120 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 130 hz
chapter 6 program list application note u13119ej4v0an 109 db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 140 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 150 hz db 09ah ; 160 hz (9) vf modulation ratio table no. 7 ;ttttttttttttttttttttttttttttttttttttttttt ;tt vf modulation ratio table no. 7 tt ;ttttttttttttttttttttttttttttttttttttttttt ; 10 hz: 0.2 60 hz: 1.2 80 hz: 1.2 ; table data = (modulation ratio)*100h vftbl7: ;+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 [hz] db 027h,029h,02bh,02dh,02fh,031h ; 0 hz db 033h,035h,037h,039h,03bh,03dh,03fh,042h,044h,046h ; 10 hz db 048h,04ah,04ch,04eh,050h,052h,054h,056h,058h,05ah ; 20 hz db 05ch,05eh,060h,062h,064h,066h,068h,06ah,06dh,06fh ; 30 hz db 071h,073h,075h,077h,079h,07bh,07dh,07fh,081h,083h ; 40 hz db 085h,087h,089h,08bh,08dh,08fh,091h,093h,096h,098h ; 50 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 60 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 70 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 80 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 90 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 100 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 110 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 120 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 130 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 140 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 150 hz db 09ah ; 160 hz (10) vf modulation ratio table no. 8 ;ttttttttttttttttttttttttttttttttttttttttt ;tt vf modulation ratio table no. 8 tt ;ttttttttttttttttttttttttttttttttttttttttt ; 10 hz: 0.2 60 hz: 1.2 80 hz: 1.2 ; table data = (modulation ratio)*100h vftbl8: ;+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 [hz] db 00ah,00dh,00fh,012h,014h,017h ; 0 hz db 01ah,01ch,01fh,021h,024h,026h,029h,02ch,02eh,031h ; 10 hz db 033h,036h,038h,03bh,03dh,040h,043h,045h,048h,04ah ; 20 hz db 04dh,04fh,052h,054h,057h,05ah,05ch,05fh,061h,064h ; 30 hz db 066h,069h,06ch,06eh,071h,073h,076h,078h,07bh,07dh ; 40 hz db 080h,083h,085h,088h,08ah,08dh,08fh,092h,094h,097h ; 50 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 60 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 70 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 80 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 90 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 100 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 110 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 120 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 130 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 140 hz db 09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah,09ah ; 150 hz db 09ah ; 160 hz
chapter 6 program list application note u13119ej4v0an 110 (11) vf table storage address table ;tttttttttttttttttttttttttttttttttttttttt ;tt vf table storage address table tt ;tttttttttttttttttttttttttttttttttttttttt vftbl: dw vftbl1, vftbl2, vftbl3, vftbl4 dw vftbl5, vftbl6, vftbl7, vftbl8 (12) carrier frequency table (10*2 bytes) ;tttttttttttttttttttttttttttttttttttttttttttt ;tt carrier frequency table (10*2 bytes) tt ;tttttttttttttttttttttttttttttttttttttttttttt ; table data = (carrier frequency [hz]) crrytbl: dw 0, 200, 400, 600, 800, 1000, 1200, 1400, 1600, 1800 dw 2000, 2200, 2400, 2600, 2800, 3000, 3200, 3400, 3600, 3800 dw 4000, 4200, 4400, 4600, 4800, 5000, 5200, 5400, 5600, 5800 dw 6000, 6200, 6400, 6600, 6800, 7000, 7200, 7400, 7600, 7800 dw 8000, 8200, 8400, 8600, 8800, 9000, 9200, 9400, 9600, 9800 dw 10000,10200,10400,10600,10800,11000,11200,11400,11600,11800 dw 12000,12200,12400,12600,12800,13000,13200,13400,13600,13800 dw 14000,14200,14400,14600,14800,15000,15200,15400,15600,15800 dw 16000,16200,16400,16600,16800,17000,17200,17400,17600,17800 dw 18000,18200,18400,18600,18800,19000,19200,19400,19600,19800 dw 20000 (13) maximum frequency limit table ;ttttttttttttttttttttttttttttttttttttttttt ;tt maximum frequency limit table tt ;ttttttttttttttttttttttttttttttttttttttttt ; table data = (output frequency number) fmxtbl: ; +0.2 +0.4 +0.6 +0.8 +1.0 +1.2 +1.4 +1.6 +1.8 +2.0 db 0, 25, 50, 75, 100, 120, 140, 160, 160, 160, 160 ; 0[khz] db 160, 160, 160, 160, 160, 160, 160, 160, 160, 160 ; 2 db 160, 160, 160, 160, 160, 160, 160, 160, 160, 160 ; 4 db 160, 160, 160, 160, 160, 160, 160, 160, 160, 160 ; 6 db 160, 160, 160, 160, 160, 160, 160, 160, 160, 160 ; 8 db 160, 160, 160, 160, 160, 160, 160, 160, 160, 160 ; 10 db 160, 160, 160, 160, 160, 160, 160, 160, 160, 160 ; 12 db 160, 160, 160, 160, 160, 160, 160, 160, 160, 160 ; 14 db 160, 160, 160, 160, 160, 160, 160, 160, 160, 160 ; 16 db 160, 160, 160, 160, 160, 160, 160, 160, 160, 160 ; 18 db 160, 160, 160, 160, 160, 160, 160, 160, 160, 160 ; 20
chapter 6 program list application note u13119ej4v0an 111 (14) maximum dead time limit table ;ttttttttttttttttttttttttttttttttttttttttt ;tt maximum dead time limit table tt ;ttttttttttttttttttttttttttttttttttttttttt ; table data = (dead time number) dmxtbl: ; +0.2 +0.4 +0.6 +0.8 +1.0 +1.2 +1.4 +1.6 +1.8 +2.0 db 0, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32 ; 0[khz] db 32, 32, 32, 32, 32, 32, 32, 32, 32, 31 ; 2 db 29, 28, 27, 26, 25, 24, 23, 22, 21, 20 ; 4 db 20, 19, 18, 18, 17, 17, 16, 16, 16, 15 ; 6 db 15, 14, 14, 14, 13, 13, 13, 13, 12, 12 ; 8 db 12, 12, 11, 11, 11, 11, 10, 10, 10, 10 ; 10 db 10, 10, 9, 9, 9, 9, 9, 9, 9, 8 ; 12 db 8, 8, 8, 8, 8, 8, 8, 9, 7, 7 ; 14 db 7, 7, 7, 7, 7, 7, 7, 7, 7, 6 ; 16 db 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 ; 18 (15) tm7 operating clock table ;ttttttttttttttttttttttttttttttttttttttttt ;tt tm7 operating clock table tt ;ttttttttttttttttttttttttttttttttttttttttt tmclktbl: dw 1200h, 007ah ; fclk dw 0900h, 003dh ; fclk/2 dw 8480h, 001eh ; fclk/4 dw 4240h, 000fh ; fclk/8 dw 0a120h, 0007h ; fclk/16 dw 0d090h, 0003h ; fclk/32 dw 0d090h, 0003h ; fclk/32 dw 0d090h, 0003h ; fclk/32 (16) minimum carrier frequency limit table ;ttttttttttttttttttttttttttttttttttttttttttttt ;tt minimum carrier frequency limit table tt ;ttttttttttttttttttttttttttttttttttttttttttttt cmntbl10: ; 4 khz 2 khz 1 khz 600 hz 400 hz 200 hz 200 hz 200 hz db 20, 10, 5, 3, 2, 1, 1, 1 cmntbl08: ; 16 khz 8 khz 4 khz 2 khz 1 khz 600 hz 600 hz 600 hz db 80, 40, 20, 10, 5, 3, 3, 3
chapter 6 program list application note u13119ej4v0an 112 (17) change rate table ;ttttttttttttttttttttttttttttttttttttttttt ;tt change rate table tt ;ttttttttttttttttttttttttttttttttttttttttt chdsptbl: ;************ display table db 5, 10, 15, 20 chngtbl: ;************ counter table dw 400, 200, 133, 100 (18) display pattern table ;ttttttttttttttttttttttttttttttttttttttttt ;tt display pattern table tt ;ttttttttttttttttttttttttttttttttttttttttt ledtbl: ; 0 1 2 3 4 5 6 7 8 9 db 03fh,006h,05bh,04fh,066h,06dh,07dh,027h,07fh,06fh ; d o p _ db 05eh,05ch,073h,000h,000h,000h ; 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. db 0bfh,086h,0dbh,0cfh,0e6h,0edh,0fdh,0a7h,0ffh,0efh end
chapter 6 program list application note u13119ej4v0an 113 6.4 constant definitions ; *********************************************** ; constant definitions ; *********************************************** frqstop equ 0ffh ; output stop setting foutini equ 004h ; initial value of output frequency deadmn1 equ 1 ; initial value of dead time vfpini equ 0 ; initial value of vf modulation ratio pointer addadr1 equ 85 ; inter-phase step address 120 (256/3) addadr2 equ 170 ; inter-phase step address 240 ((256/3) x 2) addadr1x equ 170*2 ; inter-phase step address 120 (512/3) addadr2x equ 340*2 ; inter-phase step address 240 ((512/3) x 2) konini equ 100 ; initial value of hold-down counter konres equ 19 ; re-set value of hold-down counter ksmpini equ 2 ; key input sampling interval psmpini equ 2 ; stop signal sampling interval segini equ 100 ; 8-segment led flash cycle ledini equ 100 ; led flash cycle pmstop equ 0 ; main mode: signal output stop pmfout equ 1 ; main mode: constant-frequency output pmchng equ 2 ; main mode: output frequency change smout equ 0 ; key setting mode: pwm output setting smoff equ 1 ; key setting mode: off knull equ 0 ; key code: null kchng equ 1 ; key code: [changeover] kmins equ 2 ; key code: [-] kplus equ 3 ; key code: [+] konof equ 4 ; key code: [on/off] kerr equ 10h ; key code: inconsistency dmfout equ 10h ; 8-segment led display mode: output frequency dmcrry equ 11h ; 8-segment led display mode: carrier frequency dmdead equ 12h ; 8-segment led display mode: dead time dmchng equ 03h ; 8-segment led display mode: frequency change rate chrd equ 0ah ; "d " pattern code chro equ 0bh ; "o " pattern code chrp equ 0ch ; "p " pattern code chrspc equ 0dh ; " " pattern code chrz equ 10h ; "0." pattern code tm0wadr equ 0fef6h ; intp0 table reference address work register
application note u13119ej4v0an 114 appendix revision history the revision history of this manual is listed below. the applicable chapter column indicates the chapters in the corresponding edition. edition revisions from previous edition revised section the following products have been deleted: pd780924, pd780964 subseries the following products have been deleted: pd780921, pd780922, pd780923, pd780924, pd78f0924, pd780961, pd780962, pd780963, pd780964, pd78f0964 the following products has been added: pd780983 the representative product has been changed from the pd780924 to the pd780988. throughout 2nd edition the memory map in figure 2-2 is changed to that of the pd780988. the circuit diagram in 2.3 is changed to that of the pd780988. chapter 2 hardware configuration 3rd edition the following product has been added: pd780982 the status of the following products has been changed from ?under development? to ?development completed?: pd780983, pd780984 throughout the following product name has been modified: pd78f0988 pd78f0988a throughout figure 3-8 tm7 operation timing has been modified. chapter 3 control 4th edition the interrupt processing time has been modified accordingly under the following conditions: ? tm7 is used as an 8-bit timer. ? tm7 is used as a 10-bit timer. chapter 4 notes on time required for timing set interrupt processing
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