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tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 1 post office box 655303 ? dallas, texas 75265 fully integrated v cc and v pp switching for dual-slot pc card ? interface compatible with controllers from cirrus, intel, and texas instruments meets pcmcia standards internal charge pump (no external capacitors required) 12-v supply can be disabled except for programming short-circuit and thermal protection space saving ssop (db) package for 3.3-v, 5-v and 12-v pc cards power saving i dd = 83 m a typ, i q = 1 m a low r ds(on) (160-m w v cc switch) break-before-make switching description the tps2201 pc card (pcmcia) power interface switch provides an integrated power-management solution for two pc cards. all of the discrete power mosfets, a logic section, current limiting, thermal protection, and power-good reporting for pc card control are combined on a single integrated circuit (ic), using texas instruments linbicmos ? process. the circuit allows the distribution of 3-v, 5-v and/or 12-v card power and is compatible with most pcmcia controllers. the current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability; current-limit reporting can help the user isolate a system fault to a bad card. the tps2201 maximizes battery life by generating its own switch-drive voltage using an internal charge pump. therefore, the 12-v supply can be powered down and only brought out of standby when flash memory needs to be written to or erased. end equipment for the tps2201 includes notebook computers, desktop computers, personal digital assistants (pdas), digital cameras, handiterminals, and bar-code scanners. typical pc card power distribution application cpu pcmcia controller 12 v power supply v pp1 v pp2 v cc v cc pc card a v dd tps2201 5 v 3 v shdn bpwr_good oc control lines 8 v pp1 v pp2 v cc v cc pc card b 12v 5v 3v avpp avcc avcc bvpp bvcc bvcc apwr_good bvcc avcc copyright ? 2001, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. pc card is a trademark of pcmcia (personal computer memory card international association). linbicmos is a trademark of texas instruments. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5v 5v a_vpp_pgm a_vpp_vcc a_vcc5 a_vcc3 12v avpp avcc avcc avcc gnd apwr_good shdn 3v 5v b_vpp_pgm b_vpp_vcc b_vcc5 b_vcc3 v dd 12v bvpp bvcc bvcc bvcc bpwr_good oc 3v 3v db or df package (top view)
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 2 post office box 655303 ? dallas, texas 75265 available options packaged devices chip form t j shrink small-outline (db) 2 small-outline (df) 2 chip form (y) 40 c to 150 c tps2201idbr TPS2201IDFR tps2201y 2 the db and df packages are only available taped and reeled, indicated by the r suffix on the device type. terminal functions terminal i/o description name no. i/o description a_vcc3 6 i logic input that controls voltage on avcc (see control-logic table) a_vcc5 5 i logic input that controls voltage on avcc (see control-logic table) a_vpp_pgm 3 i logic input that controls voltage on avpp (see control-logic table) a_vpp_vcc 4 i logic input that controls voltage on avpp (see control-logic table) apwr_good 13 o logic-level power-ready output that stays low as long as avpp is within limits avcc 9, 10, 11 o switched output that delivers 0 v, 3.3 v, 5 v, or high impedance avpp 8 o switched output that delivers 0 v, 3.3 v, 5 v, 12 v, or high impedance b_vcc3 26 i logic input that controls voltage on bvcc (see control-logic table) b_vcc5 27 i logic input that controls voltage on bvcc (see control-logic table) b_vpp_pgm 29 i logic input that controls voltage on bvpp (see control-logic table) b_vpp_vcc 28 i logic input that controls voltage on bvpp (see control-logic table) bpwr_good 19 o logic-level power-ready output that stays low as long as bvpp is within limits bvcc 20, 21, 22 o switched output that delivers 0 v, 3.3 v, 5 v, or high impedance bvpp 23 o switched output that delivers 0 v, 3.3 v, 5 v, 12 v, or high impedance shdn 14 i logic input that shuts down the tps2201 and set all power outputs to high-impedance state oc 18 o logic-level overcurrent reporting output that goes low when an overcurrent condition exists v dd 25 5-v power to chip gnd 12 ground 3v 15, 16, 17 i 3-v v cc input for card power 5v 1, 2, 30 i 5-v v cc input for card power 12v 7, 24 i 12-v vpp input for card power
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 3 post office box 655303 ? dallas, texas 75265 tps2201y chip information this chip, when properly assembled, displays characteristics similar to the tps2201. thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. the chip may be mounted with conductive epoxy or a gold-silicon preform. bonding pad assignments chip thickness: 15 mils typical bonding pads: 4 4 mils minimum t j max = 150 c tolerances are 10% all dimensions are in mils 204 142 tps2201y (2) (28) (1) (3) (29) (30) (27) (4) 5v 5v 5v a_vpp_pgm a_vpp_vcc b_vpp_pgm b_vpp_vcc b_vcc5 (6) (5) (7) (8) a_vcc5 a_vcc3 12v avpp (10) (9) (11) (12) avcc avcc avcc gnd (14) (13) (15) apwr_good shdn 3v (24) (25) (26) (23) b_vcc3 v dd 12v bvpp (20) (21) (22) (19) bvcc bvcc bvcc bpwr_good (16) (17) (18) oc 3v 3v (2) (1) (3) (4) (6) (5) (7) (8) (10) (9) (11) (12) (14) (13) (15) (20) (21) (22) (19) (16) (17) (18) (28) (29) (30) (27) (24) (25) (26) (23)
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 4 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted) 2 supply voltage range, v dd 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range for card power: v i(5v) 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v i(3v) 0.3 v to v i(5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v i(12v) 0.3 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . logic input voltage 0.3 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current (each card): i o(xvcc) internally limited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i o(xvpp) internally limited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating virtual junction temperature range, t j 40 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. dissipation rating table package t a 25 c power rating derating factor 3 above t a = 25 c t a = 70 c power rating t a = 85 c power rating db 1024 mw 8.2 mw/ c 655 mw 532 mw df 1158 mw 9.26 mw/ c 741 mw 602 mw 3 maximum values are calculated using a derating factor based on r q ja = 108 c/ w for the package. these devices are mounted on an fr4 board with no special thermal considerations. recommended operating conditions min max unit supply voltage, v dd 4.75 5.25 v v i(5v) 0 5.25 v input voltage range, v i v i(3v) 0 v i(5v) v v i(12v) 0 13.5 v out p ut current i o i o(xvcc) at 25 c 1 a o u tp u t c u rrent , i o i o(xvpp) at 25 c 150 ma operating virtual junction temperature, t j 40 125 c v i(3v) should not be taken above v i(5v) .
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 5 post office box 655303 ? dallas, texas 75265 electrical characteristics, t a = 25 c, v dd = 5 v (unless otherwise noted) dc characteristics parameter test conditions tps2201 unit parameter test conditions min typ max unit 5 v to xvcc 160 m w 3 v to xvcc 225 m w switch resistances 5 v to xvpp 6 3 v to xvpp 6 w 12 v to xvpp 1 clamp low voltage i pp at 10 ma 0.8 v clamp low voltage i cc at 10 ma 0.8 v i high im p edance state t a = 25 c 1 10 leakage current i pp high - impedance state t a = 85 c 50 m a leakage c u rrent i cc high im p edance state t a = 25 c 1 10 m a i cc high - impedance state t a = 85 c 50 in p ut current i dd v o(avcc) = v o(bvcc) = 5 v, v o(avpp) = v o(bvpp) = 12 v 83 150 m a inp u t c u rrent i dd in shutdown v o(bvcc) = v o(avcc) = v o(avpp) = v o(bvpp) = high z 1 m a power-ready threshold, pwr_good 10.72 11.05 11.4 v power-ready hysteresis, pwr_good ( 12-v mode) 50 mv short-circuit output- i o(xvcc) t j =85 c out p ut shorted to gnd 0.75 1.3 1.9 a current limit i o(xvpp) t j = 85 c , o u tp u t shorted to gnd 120 200 400 ma logic section parameter test conditions tps2201 unit parameter test conditions min max unit input current 1 m a high-level input voltage 2.7 v low-level input voltage 0.8 v high-level output voltage i o =1ma v dd 0.4 v low-level output voltage i o = 1 ma 0.4 v switching characteristics 2 parameter test conditions tps2201 unit parameter test conditions min typ max unit t out p ut rise time v o(xvcc) 1.2 ms t r o u tp u t rise time v o(xvpp) 5 ms t f out p ut fall time v o(xvcc) 10 ms t f o u tp u t fall time v o(xvpp) 14 ms 3 v i( vpp pgm) to v o( vpp) t on 5.8 ms 3 v i(x_vpp_pgm) to v o(xvpp) t off 18 ms t d pro p agation delay (see figure 1 3 ) v i( vcc3 ) to xvcc (3 v) t on 5.8 ms t pd propagation dela y (see fig u re 1 3 ) v i(x_vcc3) to xvcc (3 v) t off 28 ms v i( vcc5 ) to xvcc (5 v) t on 4 ms v i(x_vcc5) to xvcc (5 v) t off 30 ms 2 refer to parameter measurement information 3 rise and fall times are with c l = 100 m f.
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 6 post office box 655303 ? dallas, texas 75265 electrical characteristics, t a = 25 c, v dd = 5 v (unless otherwise noted) (continued) dc characteristics parameter test conditions tps2201y unit parameter test conditions min typ max unit leakage current i pp high-impedance state 1 m a leakage c u rrent i cc high-impedance state 1 m a input current i dd v o(avcc) = v o(bvcc) = 5 v, v o(avpp) = v o(bvpp) = 12 v 83 m a power-ready threshold, pwr_good 11.05 v power-ready hysteresis, pwr_good ( 12-v mode) 50 mv switching characteristics 2 parameter test conditions tps2201y unit parameter test conditions min typ max unit t out p ut rise time v o(xvcc) 1.2 ms t r o u tp u t rise time v o(xvpp) 5 ms t f out p ut fall time v o(xvcc) 10 ms t f o u tp u t fall time v o(xvpp) 14 ms 3 v i( vpp pgm) to v o( vpp) t on 5.8 ms 3 v i(x_vpp_pgm) to v o(xvpp) t off 18 ms t d pro p agation delay (see figure 1 3 ) v (cc ) to xvcc t on 5.8 ms t pd propagation dela y (see fig u re 1 3 ) v i(x_vcc3) t o x vcc t off 28 ms v i( vcc5 ) to xvcc t on 4 ms v i(x_vcc5) to xvcc t off 30 ms 2 refer to parameter measurement information 3 rise and fall times are with c l = 100 m f.
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 7 post office box 655303 ? dallas, texas 75265 parameter measurement information load circuit c l t on voltage waveforms v i(12v) gnd 50% 50% 90% v dd gnd v x_vpp_pgm v o(xvpp) v pp load circuit c l v cc t on t off voltage waveforms v i(5v) gnd 50% 50% 90% 10% v dd gnd v x_vccx v o(xvcc) 10% t off figure 1. test circuits and voltage waveforms table of timing diagrams figure xvcc propagation delay and rise times with 1- m f load, 3-v switch 2 xvcc propagation delay and fall times with 1- m f load, 3-v switch 3 xvcc propagation delay and rise times with 100- m f load, 3-v switch 4 xvcc propagation delay and fall times with 100- m f load, 3-v switch 5 xvcc propagation delay and rise times with 1- m f load, 5-v switch 6 xvcc propagation delay and fall times with 1- m f load, 5-v switch 7 xvcc propagation delay and rise times with 100- m f load, 5-v switch 8 xvcc propagation delay and fall times with 100- m f load, 5-v switch 9 xvpp propagation delay and rise times with 1- m f load, 12-v switch 10 xvpp propagation delay and fall times with 1- m f load, 12-v switch 11 xvpp propagation delay and rise times with 100- m f load, 12-v switch 12 xvpp propagation delay and fall times with 100- m f load, 12-v switch 13
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 8 post office box 655303 ? dallas, texas 75265 parameter measurement information 0123456789 xvcc (1 v/div) x_vcc3 (2 v/div) t time ms 0 5 10 15 20 25 30 35 40 45 xvcc (1 v/div) x_vcc3 (2 v/div) t time ms figure 2. xvcc propagation delay and rise times with 1- m f load, 3-v switch figure 3. xvcc propagation delay and fall times with 1- m f load, 3-v switch 0123456789 xvcc (1 v/div) x_vcc_3 (2 v/div) t time ms 0 5 10 15 20 25 30 35 40 45 xvcc (1 v/div) x_vcc_3 (2 v/ div) t time ms figure 4. xvcc propagation delay and rise times with 100- m f load, 3-v switch figure 5. xvcc propagation delay and fall times with 100- m f load, 3-v switch
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 9 post office box 655303 ? dallas, texas 75265 parameter measurement information 01234 xvcc (1 v/div) x_vcc_5 (2 v/div) t time ms 0 5 10 15 20 25 30 35 40 45 xvcc (1 v/div) x_vcc_5 (2 v/div) t time ms figure 6. xvcc propagation delay and rise times with 1- m f load, 5-v switch figure 7. xvcc propagation delay and fall times with 1- m f load, 5-v switch figure 8. xvcc propagation delay and rise times with 100- m f load, 5-v switch figure 9. xvcc propagation delay and fall times with 100- m f load, 5-v switch 0123456789 xvcc (1 v/div) x_vcc_5 (2 v/div) t time ms 0 5 10 15 20 25 30 35 40 45 xvcc (1 v/div) x_vcc_5 (2 v/div) t time ms
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 10 post office box 655303 ? dallas, texas 75265 parameter measurement information figure 10. xvpp propagation delay and rise times with 1- m f load, 12-v switch figure 11. xvpp propagation delay and fall times with 1- m f load, 12-v switch 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 xvpp (5 v/div) x_vpp_pgm (2 v/div) 0123456789 xvpp (5 v/div) x_vpp_pgm (2 v/div) t time ms t time ms 0123456789 xvpp (5 v/div) x_vpp_pgm (2 v/div) 0 5 10 15 20 25 30 35 40 45 xvpp (5 v/div) x_vpp_pgm (2 v/div) t time ms t time ms figure 12. xvpp propagation delay and rise times with 100- m f load, 12-v switch figure 13. xvpp propagation delay and fall times with 100- m f load, 12-v switch
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 11 post office box 655303 ? dallas, texas 75265 typical characteristics 2 table of graphs figure i dd supply current vs junction temperature 14 r ds(on) static drain-source on-state resistance, 3-v switch vs junction temperature 15 r ds(on) static drain-source on-state resistance, 5-v switch vs junction temperature 16 r ds(on) static drain-source on-state resistance, 12-v switch vs junction temperature 17 v o(xvcc) output voltage, 5-v switch vs output current 18 v o(xvcc) output voltage, 3-v switch vs output current 19 xvpp output voltage, v pp switch vs output current 20 i sc(xvcc) short-circuit current, 5-v switch vs junction temperature 21 i sc(xvpp) short-circuit current, 12-v switch vs junction temperature 22 supply current supply current vs junction temperature t j junction temperature c i dd a m 90 85 80 75 100 0 150 95 v o(avcc) = v o(bvcc) = 5 v v o(avpp) = v o(bvpp) = 12 v no load 50 100 50 figure 14 2 t = pulse tested
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 12 post office box 655303 ? dallas, texas 75265 typical characteristics 2 200 100 0 400 300 static drain-source on-state resistance m 3-v switch static drain-source on-state resistance vs junction temperature 50 0 125 r ds(on) w t j junction temperature c 120 100 80 160 140 5-v switch static drain-source on-state resistance vs junction temperature t j junction temperature c v dd = 5 v v cc = 3.3 v 25 25 50 75 100 50 0 125 25 25 50 75 100 240 220 250 150 50 350 v dd = 5 v v cc = 5 v static drain-source on-state resistance m r ds(on) w 200 180 figure 15 figure 16 1100 900 700 500 1300 1500 1700 50 50 125 12-v switch static drain-source on-state resistance vs junction temperature t j junction temperature c 5 4.99 4.85 4.8 4.75 4.9 0 0.1 0.2 0.3 0.4 0.5 output voltage v 5.05 5-v switch output voltage vs output current 0.6 0.7 v o(xvcc) i o(xvcc) output current a 40 c 25 0 25 75 100 v dd = 5 v v pp = 12 v 25 c 85 c 125 c v dd = 5 v v cc = 5 v static drain-source on-state resistance m r ds(on) w figure 17 figure 18 2 t = pulse tested
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 13 post office box 655303 ? dallas, texas 75265 typical characteristics 2 3.2 3.15 3.1 3.05 0 0.1 0.2 3.25 3.3 3.35 0.3 0.4 0.6 0.7 0.5 i o(xvcc) output current a 3-v switch output voltage vs output current 11.80 0 0.02 0.04 0.06 11.95 12 v pp switch output voltage vs output current 12.05 0.08 0.12 11.90 11.85 0.1 i o(xvpp) output current a output voltage v xv pp 40 c 85 c 125 c v dd = 5 v v cc = 3.3 v output voltage v v o(xvcc) 25 c v dd = 5 v v pp = 12 v 125 c 40 c 25 c 85 c figure 19 figure 20 5-v switch short-circuit current vs junction temperature t j junction temperature ct j junction temperature c 12-v switch short-circuit current vs junction temperature short-circuit current a i sc(xvcc) short-circuit current ma i sc(xvpp) 1 0.5 050 1.5 2 100 150 50 v dd = 5 v v cc = 5 v 200 150 100 300 250 v dd = 5 v v pp = 12 v 400 350 0 50 50 150 100 figure 21 figure 22 2 t = pulse tested
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 14 post office box 655303 ? dallas, texas 75265 application information overview pc cards were initially introduced as a means to add eeprom (flash memory) to portable computers with limited on-board memory. the idea of add-in cards quickly took hold: modems, wireless lans, gps systems, multimedia, and hard-disk versions were soon available. as the number of pc card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. to this end, the pcmcia (personal computer memory card international association) was established and was comprised of members from leading computer, software, pc card, and semiconductor manufacturers. one key goal was to realize the concept of plug-and-play, cards and hosts from different vendors should be compatible and able to communicate with one another transparently. pc card power specification system compatibility also means power compatibility. the most current set of specifications (pc card standard) set forth by the pcmcia committee states that power is to be transferred between the host and the card through eight of the pc card connector's 68 pins. this power interface consists of two v cc , two v pp , and four ground pins. multiple v cc and ground pins are used to minimize connector-pin and line resistance. the two v pp pins were originally specified as separate signals but are commonly tied together in the host to form a single node to minimize voltage losses. card primary power is supplied through the v cc pins; flash-memory programming and erase voltage is supplied through the v pp pins. as each pin is rated to 0.5 a, v cc and v pp can theoretically supply up to 1 a, assuming equal pin resistance and no pin failure. a conservative design would limit current to 500 ma. some applications, however, require higher v cc currents; disk drives, for example, may need as much as 750-ma peak current to create the initial torque necessary to spin up the platter. v pp currents, on the other hand, are defined by flash-memory programming requirements, typically under 120 ma. future power trends the 1-a physical-pin current alluded to in the pc card specification has caused some host-system engineers to believe they are required to deliver 1 a within the voltage tolerance of the card. future applications, such as rf cards, could use the extra power for their radio transmitters. the 5 w required for these cards will require very robust power supplies and special cooling considerations. the limited number of host sockets that will be able to support them makes the market for these high-powered pc cards uncertain. the vast majority of the cards require less than 600 ma continuous current and the trend is towards even lower-powered pc cards that will assure compatibility with a greater number of host systems. recognizing the need for power derating, an adhoc committee of the pcmcia is currently working to limit the amount of steady-state dc current to the pc card to something less than the currently implied 1 a. if a system is designed to support 1 a, then the switch r ds(on) , power supply requirements, and pc card cooling need to be carefully considered. designing around 1-a delivery delivering 1 a means minimizing voltage (and power) losses across the pc card power interface, which requires that designers trade off switch resistance and the cost associated with large-die (low r ds(on) ) mosfet transistors. the pc card standard requires that 5 v 5%, or 3.3 v 0.3 v be supplied to the card. the approximate 10% tolerance for the 3.3-v supply makes the 3.3-v r ds(on) less critical than the 5-v switch. a conservative approach is to allow 2% for voltage-regulator tolerance and 1% for etch- and terminal-resistance drops, which leaves 2% (100 mv) voltage drop for the 5-v switch, and at least 6% (198 mv) for the 3.3-v switch.
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 15 post office box 655303 ? dallas, texas 75265 application information designing around 1-a delivery (continued) calculating the r ds(on) necessary to support a 100 mv or 198 mv switch loss, using r = e/i and setting i = 1 a, the 5-v and 3.3-v switches would need to be 100 m w and 198 m w respectively. one solution would be to pay for a more expensive switch with lower r ds(on) . a second, less expensive approach is to increase the headroom of the power supplyefor example, to increase the 5-v supply 1.5% or to 5.075 2%. working through the numbers once more, the 2% for the regulator plus 1% for etch and terminal losses leaves 97% or 4.923 v. the allowable voltage loss across the power distribution switch is now 4.923 v minus 4.750 v or 173 mv. therefore, a switch with 173 m w or less could deliver 1 a or greater. setting the power supply high is a common practice for delivering voltages to allow for system switch, connector, and etch losses and has a minimal effect on overall battery life. in the example above, setting the power supply 1.5% high would only decrease a 3-hour battery life by approximately 2.7 minutes, trivial when compared with the decrease in battery life when running a 5-w pc card. heat dissipation a greater concern in delivering 1 a or 5 w is the ability of the host to dissipate the heat generated by the pc card. for desktop computers the solution is simpler: locate the pc card cage such that it receives convection cooling from the forced air of the fan. notebooks and other handheld equipment will not be able to rely on convection, but must rely on conduction of heat away from the pc card through the rails into the card cage. this is difficult because pc card/card cage heat transfer is very poor. a typical design scenario would require the pc card to be held at 60 c maximum with the host platform operating as high as 50 c. preliminary testing reveals that a pc card can have a 20 c rise, exceeding the 10 c differential in the example, when dissipating less than 2 w of continuous power. the 60 c temperature was chosen because it is the maximum operating temperature allowable by pc card specification. power handling requirements and temperature rises are topics of concern and are currently being addressed by the pcmcia committee. overcurrent and overtemperature protection pc cards are inherently subject to damage that can result from mishandling. host systems require protection against short-circuited cards that could lead to power supply or pcb-trace damage. even systems sufficiently robust to withstand a short circuit would still undergo rapid battery discharge into the damaged pc card, resulting in the rather sudden and unacceptable loss of system power. this can be particularly frustrating to the consumer who has already experienced problems with shortened battery life due to improper nicad conditioning or memory effect. most hosts include fuses for protection. the reliability of fused systems is poor, though, as blown fuses require troubleshooting and repair, usually by the manufacturer. the tps2201 takes a two-pronged approach to overcurrent protection. first, instead of fuses, sense fets monitor each of the power outputs. excessive current generates an error signal that linearly limits the output current, preventing host damage or failure. sense fets, unlike sense resistors or polyfuses, have the added advantage that they do not add to the series resistance of the switch and thus produce no additional voltage losses. second, when an overcurrent condition is detected, the tps2201 asserts a signal at oc that can be monitored by the microprocessor to initiate diagnostics and/or send the user a warning message. in the event that an overcurrent condition persists, causing the ic to exceed its maximum junction temperature, thermal-protection circuitry engages, shutting down all power outputs until the device cools to within a safe operating region. 12-v supply not required most pc card switches use the externally supplied 12-v v pp power for switch-gate drive and other chip functions, requiring that it be present at all times. the tps2201 offers considerable power savings by using an internal charge pump to generate the required higher voltages from the 5-v v dd supply; therefore, the external 12-v supply can be disabled except when needed for flash-memory functions, thereby extending battery lifetime. additional power savings are realized by the tps2201 during a software shutdown, in which quiescent current drops to a maximum of 1 m a.
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 16 post office box 655303 ? dallas, texas 75265 application information voltage transitioning requirement pc cards, like portables, are migrating from 5 v to 3.3 v to minimize power consumption, optimize board space, and increase logic speeds. the tps2201 is designed to meet all combinations of power delivery as currently defined in the pcmcia standard. the latest protocol accommodates mixed 3.3-v/5-v systems by first powering the card with 5 v, then polling it to determine its 3.3-v compatibility. the pcmcia specification requires that the capacitors on 3.3-v compatible cards be discharged to below 0.8 v before applying 3.3-v power. this ensures that sensitive 3.3-v circuitry is not subjected to any residual 5-v charge and functions as a power reset. the tps2201 offers a selectable v cc and v pp ground state, per pcmcia 3.3-v/5-v switching specifications, to fully discharge the card capacitors while switching between v cc voltages. output ground switches several pcmcia power-distribution switches on the market do not have an active-grounding fet switch. these devices do not meet the pc card specification requiring a discharge of v cc within 100 ms. pc card resistance can not be relied on to provide a discharge path for voltages stored on pc card capacitance because of possible high-impedance isolation by power-management schemes. a method commonly shown to alleviate this problem is to add to the switch output an external 100-k w resistor in parallel with the pc card. considering that this is the only discharge path to ground, a timing analysis will reveal that the rc time constant delays the required discharge time to over 2 seconds. the only way to ensure timing compatibility with pc card standards is to use a power-distribution switch that has an internal ground switch, like that of the tps22xx family, or add an external ground fet to each of the output lines with the control logic necessary to select it. in summary, the tps2201 is a complete single-chip dual-slot pc card power interface. it meets all currently defined pcmcia specifications for power delivery in 5-v, 3.3-v, and mixed systems, and offers a serial controller interface. the tps2201 offers functionality, power savings, overcurrent and thermal protection, and fault reporting in one 30-pin ssop surface-mount package for maximum value added to new portable designs. power-supply considerations the tps2201 has multiple terminals for each of its 3.3 v, 5 v, and 12 v power inputs and for the switched v cc outputs. any individual terminal can conduct the rated input or output current. unless all terminals are connected in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops and lost power. both 12-v inputs must be connected for proper v pp switching; it is recommended that all input and output power terminals be paralleled for optimum operation. the v dd input lead must be connected to the 5-v input leads. although the tps2201 is fairly immune to power input fluctuations and noise, it is generally considered good design practice to bypass power supplies typically with a 1- m f electrolytic or tantalum capacitor paralleled by a 0.047- m f to 0.1- m f ceramic capacitor. it is strongly recommended that the switched v cc and v pp outputs be bypassed with a 0.1- m f or larger capacitor; doing so improves the immunity of the tps2201 to electrostatic discharge (esd). care should be taken to minimize the inductance of pcb traces between the tps2201 and the load. high switching currents can produce large negative-voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. the tps2201, unlike other pc card power-interface switches, does not use the 12-v power supply for switching or other chip functions. instead, an internal charge pump generates the necessary voltage from v dd , allowing the 12-v input supply to be shut down except when the v pp programming or erase voltage is needed. careful system design, making use of this feature, reduces power consumption and extends battery lifetime. the 3.3-v power input should not be taken higher than the 5-v input. doing so, though nondestructive, results in high current flow into the device, and could result in abnormal operation. in any case, this occurrence indicates a malfunction of one input voltage or both, which should be investigated. similarly, no terminal should be taken below 0.3 v; forward biasing the parasitic-substrate diode results in substrate currents and unpredictable performance.
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 17 post office box 655303 ? dallas, texas 75265 application information overcurrent and thermal protection the tps2201 uses sense fets to check for overcurrent conditions in each of the v cc and v pp outputs. unlike sense resistors or polyfuses, these fets do not add to the series resistance of the switch; therefore, voltage and power losses are reduced. overcurrent sensing is applied to each output separately. when an overcurrent condition is detected, only the power output affected is limited; all other power outputs continue to function normally. the oc indicator, normally a logic high, is a logic low when any overcurrent condition is detected, providing for initiation of system diagnostics and/or sending a warning message to the user. during power up, the tps2201 controls the rise time of the v cc and v pp outputs and limits the current into a faulty card or connector. if a short circuit is applied after power is established (e.g., hot insertion of a bad card), current is initially limited only by the impedance between the short and the power supply. in extreme cases, as much as 10 a to 15 a may flow into the short before the current limiting of the tps2201 engages. if the v cc or v pp outputs are driven below ground, the tps2201 may latch nondestructively in an off state. cycling power will reestablish normal operation. overcurrent limiting for the v cc outputs is designed to engage if powered up into a short in the range of 0.75 a to 1.9 a, typically at about 1.3 a; the v pp outputs limit from 120 ma to 400 ma, typically around 200 ma. the protection circuitry acts by linearly limiting the current passing through the switch, rather than initiating a full shutdown of the supply. shutdown occurs only during thermal limiting. thermal limiting prevents destruction of the ic from overheating when the package power-dissipation ratings are exceeded. thermal limiting disables all power outputs (both a and b slots) until the device has cooled. calculating junction temperature the switch resistance, r ds(on) , is dependent on the junction temperature, t j , of the die. the junction temperature is dependent on both r ds(on) and the current through the switch. to calculate t j , first find r ds(on) from figures 16, 17, and 18 using an initial temperature estimate about 50 c above ambient. then calculate the power dissipation for each switch, using the formula: p d r ds(on) i 2 next, sum the power dissipation and calculate the junction temperature: t j p d r ja t a ,r ja 108 c w compare the calculated junction temperature with the initial temperature estimate. if they are not within a few degrees of each other, reiterate using the calculated temperature as the initial estimate. logic input and outputs the tps2201 was designed to be compatible with most popular pcmcia controllers and current pcmcia and jeida standards. however, some controllers require slightly counterintuitive connections to achieve desired output states. the tps2201 control logic inputs a_vcc3 , a_vcc5 , b_vcc3 and b_vcc5 are defined active low (see figure 23 and control-logic table). as such, they are directly compatible with the logic outputs of the cirrus logic cl-pd6720 controller (see figure 24). the separate v pp power-good indicators of the tps2201 can be ored together to provide a single input to the cirrus controller.
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 18 post office box 655303 ? dallas, texas 75265 application information a_vpp_pgm a_vpp_vcc a_vcc5 a_vcc3 b_vpp_pgm b_vpp_vcc b_vcc5 b_vcc3 d0 d7 shdn apwr_good oc internal current monitor cpu controller thermal vpp1 vpp2 vcc vcc vcc vcc vpp1 22 23 21 20 11 10 8 12v 5v 12v 5v 5v 3v 3v 3v 24 30 7 2 1 17 16 15 18 13 14 logic s6 s5 s4 s3 s2 s1 s12 s11 s10 s9 s8 s7 tps2201 card a card b v dd 25 vpp2 9 gnd 12 3 4 5 6 29 28 27 26 bpwr_good 19 51 17 52 18 51 17 52 18 cs cs cs cs figure 23. internal switching matrix
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 19 post office box 655303 ? dallas, texas 75265 application information tps2201 control logic avpp control signals internal switch settings output shdn a_vpp_pgm a_vpp_vcc s7 s8 s9 vavpp 1 0 0 closed open open 0 v 1 0 1 open closed open vcc 2 1 1 0 open open closed vpp(12 v) 1 1 1 open open open hi-z 0 x x open open open hi-z bvpp control signals internal switch settings output shdn b_vpp_pgm b_vpp_vcc s10 s11 s12 vbvpp 1 0 0 closed open open 0 v 1 0 1 open closed open vcc 3 1 1 0 open open closed vpp(12 v) 1 1 1 open open open hi-z 0 x x open open open hi-z avcc control signals internal switch settings output shdn a_vcc3 a_vcc5 s1 s2 s3 vavcc 1 0 0 closed open open 0 v 1 0 1 open closed open 3 v 1 1 0 open open closed 5 v 1 1 1 closed open open 0 v 0 x x open open open hi-z bvcc control signals internal switch settings output shdn b_vcc3 b_vcc5 s4 s5 s6 vbvcc 1 0 0 closed open open 0 v 1 0 1 open closed open 3 v 1 1 0 open open closed 5 v 1 1 1 closed open open 0 v 0 x x open open open hi-z 2 output depends on avcc 3 output depends on bvcc
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 20 post office box 655303 ? dallas, texas 75265 application information logic input and outputs (continued) a_v pp _pgm a_v pp_vcc a_v cc_3 a_v cc_5 b_v pp _pgm b_v pp _vcc b_v cc_3 b_v cc_5 cirrus logic cl-pd6720 to cpu gnd a_vpp_pgm a_vpp_vcc a_vcc3 a_vcc5 b_vpp_pgm b_vpp_vcc b_vcc3 b_vcc5 apwr_good tps2201 v pp _valid oc bpwr_good figure 24. logic connections to cl-pd6720 intel's 82365sldf controller uses active-high control logic for v cc selection, which requires connecting the 3-v control outputs (a_vcc_en0, b_vccen0) of the 82365sldf to the 5-v control inputs (a_vcc5 , b_vcc5 ) of the tps2201 and the 5-v control outputs (avcc_en1, b_vcc_en1) to the 3-v control inputs (a_vcc3 , b_vcc3 ), as illustrated in figure 25. examination of the control logic tables on page 16 will confirm that these connections will in fact select the correct output voltage. an alternative approach would be to invert the intel v cc control logic signals before routing them to the tps2201. the separate v pp power-good indicators of the tps2201 can be connected directly to the intel controller as shown in figure 25. cirrus logic defines a (1, 1) on the v cc select lines to be the pc card no connect state; intel chose (0, 0) to select this state. as the tables show, either combination switches the v cc outputs to 0 v. the decision to provide 0 v versus a high impedance for the no connect state eliminates potential charging at the switch-to-card interface. feedback from the pc card design community favors this approach. v pp logic allows for 0-v or high-impedance output for no connect (0, 0) or reserved (1, 1) logic inputs, respectively (refer to avpp and bvpp control-logic tables on page 16). both the cirrus logic and intel controllers interface directly with the v pp control inputs of the tps2201. the shutdown input of the tps2201, shdn , when held at a logic low places all v cc and v pp outputs in a high-impedance state and reduces chip quiescent current to 1 m a to conserve battery power. an overcurrent output (oc ) is provided to indicate an overcurrent condition in any of the v cc or v pp supplies (see discussion above). esd protection all tps2201 inputs and outputs incorporate esd-protection circuitry designed to withstand a 2-kv human-body-model discharge as defined in mil-std-883c. the v cc and v pp outputs can be exposed to potentially higher discharges from the external environment through the pc card connector. bypassing the outputs with 0.1- m f capacitors protects the devices from discharges up to 10 kv.
tps2201 dual-slot pc card power-interface switches for parallel pcmcia controllers slvs094c august 1994 revised january 2001 21 post office box 655303 ? dallas, texas 75265 application information a_vcc5 a_vcc3 a_vpp_vcc a_vpp_pgm b_vcc5 b_vcc3 b_vpp_vcc b_vpp_pgm apwr_good a_v cc _en0 a_v cc _en1 a_v pp _en0 a_v pp _en1 b_v cc _en0 b_v cc _en1 b_v pp _en0 b_v pp _en1 a:gpi b:gpi v pp1 v pp2 v cc v pp1 v pp2 v cc cs shdn pc card connector b pc card connector a intel 82365sl df avcc avcc avcc bvcc bvcc bvcc avpp avpp bvpp bvpp 3v 3 v 0.1 m f 5 v 12 v v dd shutdown signal from cpu to cpu oc bpwr_good v cc v cc 5v 5 v gnd 3v 5v 3v 5v 12v 12v tps2201 0.1 m f 0.1 m f 0.1 m f figure 25. detailed operating circuits using intel 82365sldf controller
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