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document number: sc900844 rev. 2.0, 5/2011 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, inc., 2010-2011. all rights reserved. integrated power management ic for ultra-mobile and embedded applications the 900844 is a high efficiency po wer management integrated circuit (pmic) capable of providing ope rating voltages for ultra-mobile platforms for netbook, tablets, and embedded devices through its 20 voltage rails. it has 5 switching power supplies running at frequencies from 1.0 to 4.0 mhz,14 highly efficient ldos, and one 3.3 v power switch. it incorporates a 10-bit a dc, real time clock, 8 gpios and 8 gpos. the 900844 is fully configurable a nd controllable through its spi interface. it provides an optimized power managem ent solution for ultra- mobile platforms used on netbooks, tablets, and slates. optimum partitioning, hi gh feature integration, and state-of-the-art technology, allow freescale to effectively serve this growing market segment. features ? main system power management integrated in a single chip ? fully programmable dc/dc switching, low drop-out regulators, and load switches ? spi interface (up to 25 mhz operation) ? 10-bit adc for internal and ex ternal sensing with touch screen interface ? real time clock (rtc) ? 8 interrupt capable gpios and 8 gpos ? i/o interrupt and reset controller figure 1. 900844 simplified application diagram 900844 ordering information device temperature range (t a ) package SC900844JVK -40 c to 85 c 338-mapbga power management applications ? netbooks ? tablet pc ?slates ? embedded devices 11 mm x 11 mm 98asa10841d 338-mapbga freescale pmic ultra-mobile 900844 core pmic core i/o gpio / gpo spi control cpu (central platform 3.3 v smps smps 5.0 v 19 v adp charger 3-4 cell battery pack pwr sw display ec cam backlight sata usb processing unit) controller hub adc inputs adc / touch screen inputs platform smps 1.8 v memory rails rail rails memory system control interface vr vr vpwr input power path 5 x dc/dc converters 14 x ldos 1 x 3.3 v power switch 5va 3va
analog integrated circuit device data 2 freescale semiconductor 900844 internal block diagram internal block diagram figure 2. 900844 internal block diagram gndadc 10 bit adc thermal protection power path manager sc900844 tsref touch screen interface spi control voutpnl33 pvin3p3 fbsdio sdiogt vpwr li-cell switch switchers rtc calibration pll spi registers system & peripheral interface spivcc spiclk gndspi miso mosi shift register control adin21 mux gpo control gpio control .... adin20 adin19 adin18 adin17 adin16 adin15 adin14 adin13 adin12 adin11 adin10 voltage / current sensing /& translation spicsb spi interface spi registers shift register shift register a / d control trigger handling gndaud1 gndaud2 gndaud3 gndaud4 32.768khz internal osc 32.768khz crystal osc gndrtc xtal1 xtal2 clk32k gndctrl ictest viden0 viden1 vid0 vid1 vid2 vid3 vid4 vid5 vid6 pwrgd resetb vrcomp pmicint exitstby thermtripb pwrbtn enables & control timers li-cell charger power fail detect gpiovcc gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 gpovcc gpo0 gpo1 gpo2 gpo3 gpo4 gpo5 gpo6 gpo7 voutimg25 voutimg28 pvinimg gndimg voutccpaoac voutccpddr voutaon pvin1p5 voutmm voutccp fbccp fbccpddr gnd1p5 pvinymxyfi18 voutymxyfi18 gnd2p1 voutbg voutcca pvin1p8 gnd1p8 fbcca gndcoms1 gndcoms2 pvinddq pgndddq fbddq swddq pvincc voutfbcc hsccgt lsccgt swfbcc cspcc pgndcc vid[6:0] viden[1:0] gndsub1 gndsub2 gndsub3 gndsub31 gndsub32 refgndsw gndrefvcc gndcore ldorefp9 ldorefp8 vcoreref vcoredig vcore gndled gndbklt pgndbklt refgndchg pgndchg vpwr isnsbatp isnsbatn vbat vntc ntc gndbat startup sequencer trim reference generation vcc 3600ma buck vid controller output driver vnn 1600ma buck output driver pvinnn voutfbnn hsnngt lsnngt swfbnn cspnn pgndnn vddq 1500ma buck output driver v21 1000ma buck pvin21 pgnd21 fb21 sw21 output driver v15 1500ma buck output driver pvin15 pgnd15 fb15 sw15 vbg ldo vcca ldo vcc180 ldo vpnl18 ldo vpmic ldo pvin2p1 voutcc180 voutpnl18 voutpmic vymxyfi18 ldo vccpaoac ldo vccpddr ldo vaon ldo vmm ldo vccp ldo vimg25 ldo vimg28 ldo vsdio ldo / switch vpnl33 switch pvinvib coincell 900844 output pin input pin bi-directional pin package pin legend sc900844
analog integrated circuit device data freescale semiconductor 3 900844 internal block diagram pin out description and ball map refer to pin description for a detailed list of pins and ball assignments. the ball map of the package is given in figure 3 as a top view. the bga footprint on the application pcb will have the same mapping as given in figure 3 . figure 3. 900844 package ball map 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829 a nc1 nc1 pvin1p5 fbccp nc pvin2p1 voutpnl 18 spiclk nc gndlsp r gndlspl nc nc nc2 nc2 b nc1 voutcc paoac ldorefp 8 cs voutpmi c voutcc 180 vcore pmicint vinlspr nc nc nc nc nc2 c nc1 voutcc a pvin1p5 voutao n voutcc p pvin2p1 vcorer ef resetb nc vymxpa en vinlspl nc nc2 d voutbg viden0 pvin1p8 spicsb nc nc nc e vid2 vid0 viden1 fbcca nc gndcp nc f vid6 vid4 nc g cspcc swfbcc fbccpd dr voutcc pddr pwrbtn ldorefp 9 mosi thermt ripb nc gndaud 4 gndaud 1 nc gndaud xtal h lsccgt lsccgt vid1 gnd1p5 sck gndcor e vrcomp gndsub nc gndsub nc rx2 j pgndcc pgndcc vid5 vid3 voutmm vcoredi g miso exitstb y gndsub gndsub gndsub fs2 bcl2 k hsccgt hsccgt voutfb cc nc nc bcl1 l hsnngt pvinnn pvincc pvincc pgndnn gndref vcc gndspi spivcc gndsub gndsub gndaud 2 rx1 i2svcc fs1 nc m lsnngt voutfb nn pgnddd q pgnddd q gnd2p1 gndsub pwrgd gndsub nc gndsp n swddq swddq pgnddd q pgnddd q swfbnn cspnn gnd1p8 gndsub gndsub gndsub nc nc nc nc p swddq swddq pvinddq pvinddq gndsub g ndsub gndsub gndsub nc nc nc r pgndym x3g pgndym x3g pvinddq pvinddq fbddq gndsub gndsub gndsub gndsub gndaud 3 nc ictest nc gndled t nc nc nc nc gndsub gndsub gndsub gndsub gndsub nc nc u pgnd21 pgnd21 pgnd21 refgnd sw nc gndsub gndsub gndsub gndsub gndsub nc nc nc nc nc v sw21 sw21 sw21 fb21 gndsub gndimg gndadc gndsub nc nc pgndot g pgndot g w pvin21 pvin21 pvin21 fb15 gndcom s2 ncadin20tsrefncncncncncnc y pgnd15 pgnd15 pgnd15 gpo4 nc pgndbk lt pgndbk lt aa sw15 sw15 sw15 gndcom s1 nc gpio3 nc nc adin13 nc gndbat nc nc nc nc ab pvin15 pvin15 pvin15 gpo7 gpio1 sdiogt gndctr l adin11 gpio6 nc nc vpwr gndbklt ac nc nc gpo1 nc gpiovcc fbsdio adin21 adin15 gpio4 refgnd chg ntc chgbyp gt vbat coincel l ad pvinymx yfi18 gpo2 pgndym xpa nc isnsbat p nc ae voutym xyfi18 nc gpovcc nc adin14 nc nc nc chggt vntc af nc gpo0 nc pgndym xpa xtal2 gpio5 nc nc pgndch g isnsbat n ag nc3 gpo3 gpo6 gpio0 voutpnl 33 nc pvinvib voutimg 28 adin16 xtal1 gpio7 rawchg nc nc nc4 ah nc3 gpo5 nc nc nc pgndym xpa voutimg 25 adin19 adin17 adin10 clk32k nc pgndch g nc4 aj nc3 nc3 nc gpio2 pvin3p3 nc nc pvinimg adin18 adin12 gndrtc nc nc nc4 nc4
analog integrated circuit device data 4 freescale semiconductor 900844 internal block diagram pin description the type column indicates the maximum average current through each ball assigned to the different nodes, 500 ma maximum for hipwr, 300 ma maximum for mdpwr, and 100 ma maximum for lopwr table 1. 900844 pin description node name type i/o rating # of balls bga location pin description vcc - (0.65 v-1.2 v) / 3.5 a vid cpu buck with external fets pvincc hipwr - 4.8 v 2 l5, l7 gate drivers power supply input hsccgt hipwr - 4.8 v 2 k2, k4 high side fet gate drive lsccgt hipwr - 4.8 v 2 h2, h4 low side fet gate drive pgndcc hipwrgnd - - 2 j1, j3 local ground for internal circuitry voutfbcc sgnl i 4.8 v 1 k8 output voltage sensing input and negative current sense terminal swfbcc sgnl i 3.6 v 1 g3 switch node feedback cspcc sgnl i 3.6 v 1 g1 positive current sense terminal vnn - (0.65 v-1.2 v) / 1.6 a vid cpu buck with external fets pvinnn hipwr - 4.8 v 1 l3 gate drivers power supply input hsnngt hipwr - 4.8 v 1 l1 high side fet gate drive lsnngt hipwr - 4.8 v 1 m2 low side fet gate drive pgndnn hipwrgnd - - 1 l9 local ground for internal circuitry voutfbnn sgnl i 4.8 v 1 m4 output voltage sensing input and negative current sense terminal swfbnn sgnl i 3.6 v 1 n9 switch node feedback cspnn sgnl i 3.6 v 1 n11 positive current sense terminal vddq - 1.8 v / 1.3 a buck pvinddq hipwr - 4.8 v 4 p6, p8, r5, r7 power supply input swddq hipwr - 4.8 v 4 n1, n3, p2, p4 switch node pgndddq hipwrgnd - - 4 m6, m8, n5, n7 power ground fbddq sgnl i 3.6 v 1 r9 output voltage feedback input v21 - 2.1 v / 1.0 a buck pvin21 hipwr - 4.8 v 3 w1, w3, w5 power supply input sw21 hipwr - 4.8 v 3 v2, v4, v6 switch node pgnd21 hipwrgnd - - 3 u1, u3, u5 power ground fb21 sgnl i 3.6 v 1 v8 output voltage feedback input v15 - 1.5 v (or 1.6 v) / 1.5 a buck pvin15 hipwr - 4.8 v 3 ab2, ab4, ab6 power supply input sw15 hipwr - 4.8 v 3 aa1, aa3, aa5 switch node pgnd15 hipwrgnd - - 3 y2, y4, y6 power ground fb15 sgnl i 3.6 v 1 w7 output voltage feedback input
analog integrated circuit device data freescale semiconductor 5 900844 internal block diagram vbg - 1.25 v/2 ma ldo vcca - 1.5 v/150 ma ldo pvin1p8 lopwr - 3.6 v 1 d6 power supply input, shared by vbg and vcca gnd1p8 gnd - - 1 n13 ground reference voutbg lopwr - 2.5 v 1 d2 vbg output voltage node voutcca lopwr - 2.5 v 1 c3 vcca output voltage node fbcca sgnl i 2.5 v 1 e7 vcca output voltage feedback input vcc180- 1.8 v/390 ma ldo vpnl18- 1.8 v/225 ma ldo vpmic - 1.8 v/50 ma ldo pvin2p1 hipwr - 3.6 v 2 a11, c11 power supply input, shared by vcc180, vpnl18, and vpmic gnd2p1 gnd - - 1 m12 ground reference voutcc180 hipwr - 2.5 v 1 b12 vcc180 output voltage node voutpnl18 mdpwr - 2.5 v 1 a13 vpnl18 output voltage node voutpmic lopwr - 2.5 v 1 b10 vpmic output voltage node vymxyfi18 - (ymx:1.8 v/200 ma - yfi:1.8 v/200 ma) ldo pvinymxyfi18 mdpwr - 4.8 v 1 ad2 power supply input for vymxyfi18 voutymxyfi18 mdpwr - 3.6 v 1 ae1 vymxyfi18 output voltage node gndcoms1 gnd - - 1 aa7 ground reference gndcoms2 gnd - - 1 w11 ground reference vccpaoac- 1.05 v/155 ma ldo vccpddr - 1.05 v/60 ma ldo vaon - 1.2 v/250 ma ldo vmm- 1.2 v/5 ma ldo vccp - 1.05 v/445 ma ldo pvin1p5 hipwr - 3.6 v 2 a5, c5 power supply input, shared by vccpaoac, vccpddr, vaon, vmm, and vccp gnd1p5 gnd - - 1 h10 ground reference voutccpaoac lopwr - 2.5 v 1 b4 vccpaoac output voltage node voutccpddr lopwr - 2.5 v 1 g9 vccpddr output voltage node fbccpddr sgnl i 2.5 v 1 g7 vccpddr output voltage feedback input voutaon mdpwr - 2.5 v 1 c7 vaon output voltage node voutmm lopwr - 2.5 v 1 j11 vmm output voltage node voutccp hipwr - 2.5 v 1 c9 vccp output voltage node fbccp sgnl i 2.5 v 1 a7 vccp output voltage feedback input vimg25- 2.5 v/80 ma ldo vimg28- 2.8 v/225 ma ldo pvinimg mdpwr - 4.8 v 1 aj15 power supply input, shared by vimg25 and vimg28 gndimg gnd - - 1 v14 ground reference voutimg25 lopwr - 3.6 v 1 ah14 vimg25 output voltage node table 1. 900844 pin description node name type i/o rating # of balls bga location pin description
analog integrated circuit device data 6 freescale semiconductor 900844 internal block diagram voutimg28 mdpwr - 3.6 v 1 ag15 vimg28 output voltage node vpnl33 - 3.3 v/100 ma switch pvin3p3 mdpwr - 3.6 v 1 aj9 power supply input, shared by vpnl33 and vsdio voutpnl33 lopwr - 3.6 v 1 ag9 vpnl33 output voltage node vsdio - 3.3 v/215 ma switch or 1.8 v/215 ma ldo sdiogt lopwr - 3.6 v 1 ab12 gate driver output for vsdio pass fet fbsdio sgnl - 3.6 v 1 ac13 feedback node when vsdio is in switch mode; output voltage node when vsdio is in ldo mode. internal supplies vcore lopwr - 3.6 v 1 b14 internal supply output voltage node vcoredig lopwr - 1.5 v 1 j13 internal supply output voltage node vcoreref lopwr - 3.6 v 1 c13 internal band gap supply output voltage node ldorefp8 lopwr - 3.6 v 1 b6 internal divided down band gap supply output voltage node dedicated for ldos ldorefp9 lopwr - 3.6 v 1 g13 internal divided down band gap supply output voltage node dedicated for ldos gndcore lopwrgnd - - 1 h14 ground for internal supplies input power path vpwr mdpwr - 4.8 v 1 ab26 input power node for pmic vbat lopwr - 4.8 v 1 ac27 battery voltage sensing input gndbat lopwrgnd - - 1 aa21 input supply ground vntc lopwr - 3.6 v 1 ae29 bias voltage for ntc resistor stack ntc sgnl i 3.6 v 1 ac23 ntc connection node isnsbatp sgnl i 4.8 v 1 ad26 connect to vbat isnsbatn sgnl i 4.8 v 1 af28 connect to vbat pvinvib mdpwr - 4.8 v 1 ag13 always connect to vpwr coin cell charger coincell lopwr - 3.6 v 1 ac29 coin cell supply input, coin cell charger output adc + ts i/f adin10 sgnl i 4.8 v 1 ah20 adc generic input 1, used as touchscreen input x1, tsx1 adin11 sgnl i 4.8 v 1 ab16 adc generic input 2, used as touchscreen input x2, tsx2 adin12 sgnl i 4.8 v 1 aj19 adc generic input 3, used as touchscreen input y1, tsy1 adin13 sgnl i 4.8 v 1 aa17 adc generic input 4, used as touchscreen input y2, tsy2 adin14 sgnl i 4.8 v 1 ae17 adc generic input 5 adin15 sgnl i 4.8 v 1 ac17 adc generic input 6 adin16 sgnl i 4.8 v 1 ag17 adc generic input 7 adin17 sgnl i 4.8 v 1 ah18 adc generic input 8 table 1. 900844 pin description node name type i/o rating # of balls bga location pin description
analog integrated circuit device data freescale semiconductor 7 900844 internal block diagram adin18 sgnl i 4.8 v 1 aj17 adc generic input 9 adin19 sgnl i 4.8 v 1 ah16 adc generic input 10 adin20 sgnl i 4.8 v 1 w15 adc generic input 11 adin21 sgnl i 4.8 v 1 ac15 adc generic input 12 tsref lopwr - 3.6 v 1 w17 reference for touchscreen interface gndadc lopwrgnd - - 1 v16 ground reference for adc oscillator and real time clock - rtc xtal1 sgnl i 2.5 v 1 ag19 32.768 khz oscillator crystal connection 1 xtal2 sgnl o 2.5 v 1 af18 32.768 khz oscillator crystal connection 2 clk32k sgnl o 3.6 v 1 ah22 32 khz clock output gndrtc gnd - - 1 aj21 ground for the rtc block platform architecture sideband signals pmicint sgnl o 2.5 v 1 b16 pmic interrupt. asserted by pmic to wake platform controller hub and begin communications. level-sensitive, read to clear. vrcomp sgnl o 2.5 v 1 h16 voltage regulator complete. asserted high by the pmic when a spi voltage regulation request has been decoded. the signal is de-asserted on completion of the request (i.e. the rail is in regulation). resetb sgnl o 2.5 v 1 c15 active low hard reset for platform controller hub. when asserted, the platform controller hub should return to its initial default state. pwrgd sgnl o 2.5 v 1 m16 power good: the 900844 asserts this signal to indicate that all power rails to the platform controller hub are good. assertion of pwrgd also means that vcca_osc has been valid for at least 30 microseconds. the platform controller hub will remain ?off? until this signal is asserted. exitstby sgnl i 2.5 v 1 j17 exit standby. when asserted, the 900844 exits the aoac standby settings for regulating the platform supplies. when asserted, the 900844 switches vrs on which are defined in registers 0x09 through 0x0d. this is a low latency vr context switch. thermtripb sgnl i 1.5 v 1 g17 thermal trip. asserted by the cpu to indicate a catastrophic thermal event. viden0 sgnl i 1.5 v 1 d4 driven by the cpu to indicate which vr the vid bus is addressed to (vcc or vnn). debounced inside the 900844 for 150 ns. the cpu will hold the value for at least 300 ns. viden1 sgnl i 1.5 v 1 e5 vid0 sgnl i 1.5 v 1 e3 driven by the cpu to indicate the output voltage setting for the vcc and vnn rails. debounced inside the 900844 for 150 ns. the cpu will hold t he value for at least 300 ns. vid1 sgnl i 1.5 v 1 h8 vid2 sgnl i 1.5 v 1 e1 vid3 sgnl i 1.5 v 1 j9 vid4 sgnl i 1.5 v 1 f4 vid5 sgnl i 1.5 v 1 j7 vid6 sgnl i 1.5 v 1 f2 gndctrl gnd - - 1 ab14 logic control ground table 1. 900844 pin description node name type i/o rating # of balls bga location pin description
analog integrated circuit device data 8 freescale semiconductor 900844 internal block diagram spi interface spivcc lopwr - 3.6 v 1 l15 supply for spi bus spiclk sgnl i 3.6 v 1 a15 spi clock input mosi sgnl i 3.6 v 1 g15 spi write input miso sgnl o 3.6 v 1 j15 spi read output spicsb sgnl i 3.6 v 1 d14 spi chip select input gndspi gnd - - 1 l13 ground for spi interface gpios & gpos & power button gpiovcc lopwr - 3.6 v 1 ac11 gpio power gpio0 sgnl i/o 3.6 v 1 ag7 fully configurable gpio inputs/outputs for general purpose sensing and platform control gpio1 sgnl i/o 3.6 v 1 ab10 gpio2 sgnl i/o 3.6 v 1 aj7 gpio3 sgnl i/o 3.6 v 1 aa11 gpio4 sgnl i/o 3.6 v 1 ac19 gpio5 sgnl i/o 3.6 v 1 af20 gpio6 sgnl i/o 3.6 v 1 ab18 gpio7 sgnl i/o 3.6 v 1 ag21 gpovcc lopwr - 3.6 v 1 ae5 gpo power gpo0 sgnl o 3.6 v 1 af4 general purpose outputs gpo1 sgnl o 3.6 v 1 ac7 gpo2 sgnl o 3.6 v 1 ad4 gpo3 sgnl o 3.6 v 1 ag3 gpo4 sgnl o 3.6 v 1 y8 gpo5 sgnl o 3.6 v 1 ah4 gpo6 sgnl o 3.6 v 1 ag5 gpo7 sgnl o 3.6 v 1 ab8 pwrbtn sgnl i 1.5 v 1 g11 pmic hardware on/off button test pins ictest sgnl i 7.5 v 1 r23 always connect to gnd reference supplies vinlspr mdpwr - 5.5v 1 b18 always connect to vpwr vinlspl mdpwr - 5.5v 1 c21 always connect to vpwr i2svcc lopwr - 3.6 v 1 l25 always connect to vpmic table 1. 900844 pin description node name type i/o rating # of balls bga location pin description
analog integrated circuit device data freescale semiconductor 9 900844 internal block diagram ground references pgndchg hipwrgnd - - 2 af26, ah26 power gnd bcl1 sgnl i/o 3.6 v 1 k28 always connect to gnd fs1 sgnl i/o 3.6 v 1 l27 always connect to gnd rx1 sgnl i 3.6 v 1 l23 always connect to gnd bcl2 sgnl i/o 3.6 v 1 j29 always connect to gnd fs2 sgnl i/o 3.6 v 1 j27 always connect to gnd rx2 sgnl i 3.6 v 1 h28 always connect to gnd sck sgnl i 3.6 v 1 h12 always connect to gnd gndsp lopwrgnd - - 1 m28 analog gnd gndlspr mdpwrgnd - - 1 a19 analog gnd gndlspl mdpwrgnd - - 1 a21 analog gnd gndcp lopwrgnd - - 1 e27 analog gnd pgndymxpa hipwrgnd - - 3 ad12, af12, ah12 power gnd pgndymx3g hipwrgnd - - 2 r1, r3 power gnd pgndotg hipwrgnd - - 2 v26, v28 power gnd pgndbklt hipwrgnd - - 2 y26, y28 power gnd gndaudxtal gnd - - 1 g29 analog gnd gndaud1 gnd - - 1 g23 analog gnd gndaud2 gnd - - 1 l21 analog gnd gndaud3 gnd - - 1 r19 analog gnd gndaud4 gnd - - 1 g21 analog gnd gndbklt gnd - - 1 ab28 analog gnd gndled gnd - - 1 r29 analog gnd refgndchg gnd - - 1 ac21 dedicated reference ground for the input power path refgndsw gnd - - 1 u7 dedicated reference ground for the switching regulators gndrefvcc gnd - - 1 l11 dedicated reference ground for vcc regulator gndsub gnd - - 32 h18, h22, j19, j21, j23, l17, l19, m14, m18, n15, n17, n19, p12, p14, p16, p18, r11, r13, r15, r17, t12, t14, t16, t18, t22, u11, u13, u15, u17, u19, v12, v18 substrate gnd table 1. 900844 pin description node name type i/o rating # of balls bga location pin description
analog integrated circuit device data 10 freescale semiconductor 900844 internal block diagram reserved rawchg mdpwr - 20 v 1 ag23 reserved - do not connect chgbypgt mdpwr - 4.8 v 1 ac25 reserved - do not connect chggt mdpwr - 4.8 v 1 ae27 reserved - do not connect vymxpaen sgnl i 2.5 v 1 c19 reserved - do not connect cs sgnl i 3.6 v 1 b8 reserved - do not connect notes 1. the type column indicates the maximum average current through each ball assigned to the different nodes. 500 ma maximum for hipwr, 300 ma maximum for mdpwr, and 100 ma maximum for lopwr table 1. 900844 pin description node name type i/o rating # of balls bga location pin description
analog integrated circuit device data freescale semiconductor 11 900844 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground, unle ss otherwise noted. exceeding these rati ngs may cause malfunction or permanent damage to the device. the detailed maximum voltage rating per pin can be found in the pin list section. ratings symbol value unit electrical ratings input voltage - -0.3 to +4.4 v coin cell voltage - -0.3 to +3.6 v esd rating, all pins, human body model (hbm) (4) v esdhbm 2000 v esd rating, all pins, charge device model (cdm) (4) , (5) v esdcdm 450 v thermal ratings ambient operating temperature range t a -40 to +85 c operating junction temperature range t j -30 to +125 c storage temperature range t st -65 to +150 c peak package reflow temperature (2) , (3) t pprt 260 c power ratings hard mechanical off there is no valid vbat voltage connected to the 900844, batdet = 0 0 mw soft mechanical off the 900844 has input power from 3.3 v supply into vbat. all vrs are programmed ?off?, batdet = 1 5.0 mw power on the 900844 has input power from 3.3 v supply into vbat. the cold-boot rails are ?on?. v21 = 2.1 v, v15 = 1.5 v, vaon = 1.2 v, vccpaoac = 1.05 v, vpmic = 1.8 v, all vr outputs are set in pfm or aps mode driving purely capacitive loads. batdet = 1 100 mw notes 2. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion soldering. exceeding these lim its may cause a malfunction or permanent damage to the device. 3. freescale's package reflow capability m eets the pb-free requirements for jedec standard j-std-020c, for peak package reflow temperature and moisture sensitivity levels (msl) 4. esd testing is performed in accordance with the human body model (hbm) (czap = 100 pf, rzap = 1500 ), and the charge device model (cdm), robotic (czap = 4.0 pf). 5. all pins meet 500 v cdm except vcoreref.
analog integrated circuit device data 12 freescale semiconductor 900844 electrical characteristics maximum ratings power dissipation during operation, the te mperature of the die must not exceed the maximum junction tem perature. depending on the operating ambient temperature and the total internal dissipation this limit can be exceeded. to optimize the thermal management scheme and avoid over heating, the 900844 provides a thermal management system that protects against overheating. this protection should be considered as a fail-safe mechani sm, and the application design should initiate thermal shutdown under normal conditions. reference thermal management for more details. power consumption table 2 defines the maximum power consumption specifications in the various system and device states. for each entry in the table, the component is assumed to be configured for drivin g purely capacitive loads, and the voltages listed in each entry are nominal output voltages. note that the ?soft mechanical off? state is a tr ansitional state. the device will spend less than 150 s in this state before v15 starts to turn on, upon detection of a valid input voltage.
analog integrated circuit device data freescale semiconductor 13 900844 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit system control interface input low voltage exitstby, vid[6:0] thrmtripb, viden[1:0] v il 0 0 - - 0.3*v ccp 0.3*v ccpa oac v input high voltage exitstby, vid[6:0] thrmtripb, viden[1:0] v ih 0.7*v ccp 0.7*v ccpa oac - - v ccp v ccpaoac v output low voltage pmicint, vrcomp, resetb, pwrgd. v ol 0 - 0.1 v output high voltage pmicint, vrcomp, resetb, pwrgd. v oh v pmic - 0.1 - v pmic v spi interface logic io operating voltage range (spivcc pin) v spivcc 1.74 1.8 3.1 v input high spicsb, mosi, spiclk - 0.7* v spivcc - v spivcc +0.3 v input low spicsb, mosi, spiclk - 0 - 0.3* v spivcc v output low miso (output sink 100 a) - 0 - 0.1 v output high miso (output source 100 a) - v spivcc -0.1 - v spivcc v oscillator and clock outputs main characteristics operating voltage - 1.2 - 1.5 v rtc osc consumption current rtc mode: all blocks disabled, no main battery attached, coin cell is attached to coincell) - - 1.0 2.0 a output low clk32k (output sink 100 a) - 0 - 0.1 v output high clk32k (output source 100 a) - v spivcc - 0.1 - v spivcc v clk32k output duty cycle - 40 50 60 % rtc input voltage range - 1.2 - 1.5 v consumption current - - 15 25 a crystal osc frequency tolerance - -30 - +30 ppm crystal osc peak temperature frequency (turn over temperature) - 20 25 30 c crystal osc maximum series resistance - - 80 - k crystal osc maximum drive level - - 0.5 - w
analog integrated circuit device data 14 freescale semiconductor 900844 electrical characteristics static electrical characteristics crystal osc operating drive level - 0.25 - 0.5 w crystal osc nominal lead capacitance - - 9.0 - pf crystal osc aging - - - 3.0 ppm/year coin cell charger coin cell charge voltage (selectable through vcoin[2:0] bits) v coincell 2.5 - 3.3 v coin cell charge voltage accuracy - -100 - 100 mv coin cell charge current i coin - 60 - a coin cell charge current accuracy - -15 - 15 % power states detection thresholds battery cutoff threshold (depending on battery model) v batoff 2.2 - 2.4 v coin cell disconnect threshold v coinoff 1.8 - 2.0 v low battery threshold v lowbat 3.2 - - v valid battery threshold v trkl - 3.0 - v vpwr rising under-voltage threshold v pwruvr - 3.1 - v vpwr falling under-voltage threshold v pwruvf - 2.55 - v vcc electrical characteristics input voltage range v pwr 3.0 3.6 4.4 v extended input voltage range v pwr 2.8 3.6 4.7 v output voltage programmability range low power mode active mode v cc 0.3 0.65 - - 0.7 1.2 v output voltage programmability step size - - 12.5 - mv output voltage accuracy 0.6 v < v cc < 12 v, 1.5 a < i cc < 3.5 a 0.6 v < v cc < 12 v, i cc < 1.5 a 0.3 v < v cc < 0.6 v - -5.0 -4.0 -7.0 - - - 5.0 4.0 7.0 % output voltage overshoot maximum overshoot voltage above vid setting voltage. maximum overshoot time is 10-30 s, output voltage = 0.9 v at 50 ma v os - - 50 mv continuous output load current low power mode active mode i cc - 0.2 - - 0.2 3.5 a peak current limit i limcc - 5.0 - a output current limit accuracy - 15 - % transient load change low power mode active mode i cc - - - - 0.2 1.2 a table 3. static electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 900844 electrical characteristics static electrical characteristics vnn electrical characteristics input voltage range v pwr 3.0 3.6 4.4 v extended input voltage range v pwr 2.8 3.6 4.7 v output voltage programmability range (set by vid control signals) v nn 0.65 - 1.2 v output voltage programmability step size - - 12.5 - mv output voltage accuracy - -5.0 - 5.0 % output voltage overshoot maximum overshoot voltage above vid setting voltage. maximum overshoot time is 10 s, output voltage = 0.9 v at 50 ma v os - - 50 mv continuous output load current low power mode active mode i nn - 0.2 - - 0.2 1.6 a peak current limit i limnn - 2.5 - a output current limit accuracy - - 20 - % transient load change i nn - - 0.5 a vddq electrical characteristics input voltage range v pwr 3.0 3.6 4.4 v extended input voltage range v pwr 2.8 3.6 4.7 v output voltage setting v ddq - 1.8 - v output voltage accuracy - -5.0 - 5.0 % continuous output load current i ddq - - 1.3 a peak current limit i limddq - 1.78 - a output current limit accuracy 0.5 a < i ddq < 1.3 a i ddq < 0.5 a - -15 -20 - - +15 +20 % transient load change i ddq - - 0.5 a effective quiescent current consumption (pwm, no load) i qddq - 30 - a v21 electrical characteristics input voltage range v pwr 3.0 3.6 4.4 v extended input voltage range v pwr 2.8 3.6 4.7 v output voltage setting v 21 - 2.1 - v output voltage accuracy - -5.0 - 5.0 % continuous output load current i 21 - - 1.0 a peak current limit i lim21 - 1.42 - a output current limit accuracy - -20 - +20 % transient load change i 21 - - 0.5 a effective quiescent current consumption (pwm, no load) i q21 - 30 - a table 3. static electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 900844 electrical characteristics static electrical characteristics v15 electrical characteristics input voltage range v pwr 3.0 3.6 4.4 v extended input voltage range v pwr 2.8 3.6 4.7 v output voltage setting (also programmable to 1.6 v, typical) v 15 - 1.5 - v output voltage accuracy - -5.0 - 5.0 % continuous output load current i 15 0 0.75 1.5 a peak current limit i lim15 - 1.6 - a output current limit accuracy - -20 - +20 % transient load change i 15 - - 0.5 a effective quiescent current consumption (pwm, no load) i q15 - 30 - a vbg electrical characteristics input voltage range v ddq v 21 1.71 1.995 1.80 2.100 1.89 2.205 v output voltage setting v bg - 1.25 - v output voltage accuracy - -2.0 - 2.0 % under-voltage detection threshold (with respect to the output voltage) v bguv - -12 - % under-voltage detection threshold hysteresis v bguvh - 1.0 - % continuous output load current active mode low power mode i bg - - - - 2.0 40 ma a current limit i limbg - 94 - ma transient load change i bg - - 1.0 ma power supply rejection ratio (psrr) (20 to 100 khz, i bg = 1.5 ma, v ddq = 1.8 v) psrr bg 50 60 - db effective quiescent current consumption active mode low power mode i qbg - - - - 18 10 a vcca electrical characteristics input voltage range v ddq v 21 1.71 1.995 1.80 2.100 1.89 2.205 v output voltage setting v cca - 1.5 - v output voltage accuracy - -2.0 - 2.0 % under-voltage detection threshold (with respect to the output voltage) v ccauv - -12 - % under-voltage detection threshold hysteresis v ccauvh - 1.0 - % continuous output load current active mode low power mode i cca - - - - 150 3.0 ma ma table 3. static electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 17 900844 electrical characteristics static electrical characteristics current limit i limcca - 225 - ma transient load change i cca - - 50 ma power supply rejection ratio (psrr) (20 to 100 khz, i cca = 112.5 ma, v ddq = 1.8 v) psrr cca 50 60 - db effective quiescent current consumption active mode low power mode i qcca - - - - 18 10 a vcc180 electrical characteristics input voltage range v 21 1.995 2.1 2.205 v output voltage setting v cc180 - 1.8 - v output voltage accuracy - -5.0 - 5.0 % under-voltage detection threshold (with respect to the output voltage) v cc180uv - -12 - % under-voltage detection threshold hysteresis v cc180uvh - 1.0 - % continuous output load current active mode low power mode i cc180 - - - - 390 7.8 ma ma current limit i limcc180 - 585 - ma transient load change i cc180 - - 350 ma power supply rejection ratio (psrr) (20 to 100 khz, i cc180 = 292.5 ma, v 21 = 2.1 v) psrr cc180 50 60 - db effective quiescent current consumption active mode low power mode i qcc180 - - - - 18 10 a vpnl18 electrical characteristics specification input voltage range v 21 1.995 2.1 2.205 v output voltage setting v pnl18 - 1.8 - v output voltage accuracy - -5.0 - 5.0 % under-voltage detection threshold (with respect to the output voltage) v pnl18uv - -12 - % under-voltage detection threshold hysteresis v pnl18uvh - 1.0 - % continuous output load current active mode low power mode i pnl18 - - - - 210 4.2 ma current limit i limpnl18 - 315 - ma transient load change i pnl18 - - 100 ma power supply rejection ratio (psrr) (20 to 100 khz, i pnl18 = 157.5 ma, v 21 = 2.1 v) psrr pnl18 50 60 - db effective quiescent current consumption active mode low power mode i qpnl18 - - - - 18 10 a table 3. static electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data 18 freescale semiconductor 900844 electrical characteristics static electrical characteristics vpmic electrical characteristics input voltage range v 21 1.995 2.1 2.205 v output voltage setting v pmic - 1.8 - v output voltage accuracy - -5.0 - 5.0 % under-voltage detection threshold (with respect to the output voltage) v pmicuv - -12 - % under-voltage detection threshold hysteresis v pmicuvh - 1.0 - % continuous output load current active mode low power mode i pmic - - - - 100 2.0 ma current limit i limpmic - 150 - ma transient load change i pmic - - 20 ma power supply rejection ratio (psrr) (20 to 100 khz, i pmic = 75 ma, v 21 = 2.1 v) psrr pmic 50 60 - db effective quiescent current consumption active mode low power mode i qpmic - - - - 18 10 a vymxyfi18 electrical characteristics input voltage range v 21 1.995 2.1 2.205 v output voltage setting v ymxyfi18 - 1.8 - v output voltage accuracy - -5.0 - 5.0 % under-voltage detection threshold (with respect to the output voltage) v ymxyfi18uv - -12 - % under-voltage detection threshold hysteresis v ymxyfi18uvh - 1.0 - % continuous output load current active mode low power mode i ymxyfi18 - - - - 200 4.0 ma current limit i limymxyfi18 - 300 - ma transient load change i ymxyfi18 - - 100 ma power supply rejection ratio (psrr) (20 to 100 khz, i ymxyfi18 = 150 ma), (v 21 = 2.1 v or v pwr = 3.6 v) psrr ymxyfi18 40 - - db output noise (10 hz to 100 khz, i ymxyfi18 = 200 ma), (v 21 = 2.1 v or v pwr = 3.6 v) v noiseymxyfi18 - - 40 v rms effective quiescent current consumption active mode low power mode i qymxyfi18 - - - - 18 10 a table 3. static electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 19 900844 electrical characteristics static electrical characteristics vccpaoac electrical characteristics input voltage range v 15 1.425 1.5 1.680 v output voltage setting v ccpaoac - 1.05 - v output voltage accuracy - -5.0 - 5.0 % under-voltage detection threshold (with respect to the output voltage) v ccpaoacuv - -12 - % under-voltage detection threshold hysteresis v ccpaoacuvh - 1.0 - % continuous output load current active mode low power mode i ccpaoac - - - - 155 3.1 ma current limit i limccpaoac - 232.5 - ma transient load change i ccpaoac - - 50 ma power supply rejection ratio (psrr) (20 to 100 khz, i ccpaoac = 116 ma, v 15 = 1.5 v) psrr ccpaoac 50 60 - db effective quiescent current consumption active mode low power mode i qccpaoac - - - - 18 10 a vccpddr electrical characteristics input voltage range v 15 1.425 1.5 1.680 v output voltage setting v ccpddr - 1.05 - v output voltage accuracy - -2.0 - 2.0 % under-voltage detection threshold (with respect to the output voltage) v ccpddruv - -12 - % under-voltage detection threshold hysteresis v ccpddruvh - 1.0 - % continuous output load current active mode low power mode i ccpddr - - - - 60 1.2 ma current limit i limccpddr - 90 - ma transient load change i ccpddr - - 10 ma power supply rejection ratio (psrr) (20 to 100 khz, i ccpddr = 45 ma, v 15 = 1.5 v) psrr ccpddr 50 60 - db effective quiescent current consumption active mode low power mode i qccpddr - - - - 18 10 a vaon electrical characteristics input voltage range v 15 1.425 1.5 1.680 v output voltage setting v aon - 1.2 - v output voltage accuracy - -5.0 - 5.0 % under-voltage detection threshold (with respect to the output voltage) v aonuv - -12 - % under-voltage detection threshold hysteresis v aonuvh - 1.0 - % table 3. static electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data 20 freescale semiconductor 900844 electrical characteristics static electrical characteristics continuous output load current active mode low power mode i aon - - - - 250 5.0 ma current limit i limaon - 375 - ma transient load change i aon - - 100 ma power supply rejection ratio (psrr) (20 to 100 khz, i aon = 187.5 ma, v 15 = 1.5 v) psrr aon 50 60 - db effective quiescent current consumption active mode low power mode i qaon - - - - 18 10 a vmm electrical characteristics input voltage range v 15 1.425 1.5 1.680 v output voltage setting v mm - 1.2 - v output voltage accuracy - -5.0 - 5.0 % under-voltage detection threshold (with respect to the output voltage) v mmuv - -12 - % under-voltage detection threshold hysteresis v mmuvh - 1.0 - % continuous output load current active mode low power mode i mm - - - - 5.0 0.1 ma current limit i limmm - 25 - ma transient load change i mm - - 3.0 ma power supply rejection ratio (psrr) (20 to 100 khz, i mm = 4.0 ma, v 15 = 1.5 v) psrr mm 50 60 - db effective quiescent current consumption active mode low power mode i qmm - - - - 18 10 a vccp electrical characteristics input voltage range v 15 1.425 1.5 1.680 v output voltage setting v ccp - 1.05 - v output voltage accuracy - -5 - 5.0 % under-voltage detection threshold (with respect to the output voltage) v ccpuv - -12 - % under-voltage detection threshold hysteresis v ccpuvh - 1.0 - % continuous output load current active mode low power mode i ccp - - - - 445 8.9 ma current limit i limccp - 667.5 - ma transient load change i ccp - - 100 ma table 3. static electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 21 900844 electrical characteristics static electrical characteristics power supply rejection ratio (psrr) (20 to 100 khz, i ccp = 334 ma, v 15 = 1.5 v) psrr ccp 50 60 - db effective quiescent current consumption active mode low power mode i qccp - - - - 18 10 a vimg25 electrical characteristics input voltage range v pwr 3.0 3.6 4.4 v output voltage setting v img25 - 2.5 - v output voltage accuracy - -5.0 - 5.0 % under-voltage detection threshold (with respect to the output voltage) v img25uv - -12 - % under-voltage detection threshold hysteresis v img25uvh - 1.0 - % continuous output load current active mode low power mode i img25 - - - - 80 1.6 ma current limit i limimg25 - 120 - ma transient load change i img25 - - 10 ma power supply rejection ratio (psrr) (20 to 100 khz, i img25 = 60 ma, v pwr = 3.3 v) psrr img25 50 60 - db effective quiescent current consumption active mode low power mode i qimg25 - - - - 18 10 a vimg28 electrical characteristics input voltage range v pwr 3.0 3.6 4.4 v output voltage setting v img28 (selectable, see table 43 ) v output voltage accuracy - -5.0 - 5.0 % under-voltage detection threshold (with respect to the output voltage) v img28uv - -12 - % under-voltage detection threshold hysteresis v img28uvh - 1.0 - % continuous output load current active mode low power mode i img28 - - - - 225 4.5 ma current limit i limimg28 - 337.5 - ma transient load change i img28 - - 100 ma power supply rejection ratio (psrr) (20 to 100 khz, i img28 = 169 ma, v pwr = 3.3 v) psrr img28 50 60 - db effective quiescent current consumption active mode low power mode i qimg28 - - - - 18 10 a table 3. static electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data 22 freescale semiconductor 900844 electrical characteristics static electrical characteristics vsdio electrical characteristics input voltage range v pwr 3.135 3.3 3.465 v output voltage setting v sdio (selectable, see table 44 ) v output voltage accuracy - -5.0 - 5.0 % under-voltage detection threshold (with respect to the output voltage) v sdiouv - -12 - % under-voltage detection threshold hysteresis v sdiouvh - 1.0 - % continuous output load current active mode low power mode i sdio - - - - 215 4.3 ma current limit i limsdio - 322.5 - ma transient load change i sdio - - 100 ma power supply rejection ratio (psrr) (20 to 100 khz, i sdio = 161 ma, v pwr = 3.3 v) psrr sdio 50 60 - db effective quiescent current consumption active mode low power mode i qsdio - - - - 18 10 a vpnl33 power switch electrical characteristics input voltage range v pwr 3.135 3.3 3.465 v drop across switch with reference to v pwr - - - 3.0 % continuous output load current i pnl33 - - 100 ma adc electrical characteristics conversion current - - - 1.2 ma off supply current - - - 1.0 a converter reference voltage - - 2.4 - v integral nonlinearity (rs = 5.0 k maximum) (6) - - - 3.0 lsb differential nonlinearity (rs = 5.0 k maximum) (6) - - - 1.0 lsb zero scale error (offset) (rs = 5.0 k maximum) (6) - - - 10 lsb full scale error (gain) (rs = 5.0 k maximum) (6) , (7) - - - 11 lsb drift over temperature 2.0 lsb source impedance no bypass capacitor at input bypass capacitor at input of (10 nf) - - - - - - 5.0 30 k k input buffer input range (8) - 0.02 - 2.4 v notes 6. rs represents a possible external series resi stor between the voltage source and the adin input. 7. at room temperature. 8. refer to table 57 for analog valid input range and input buffer range characteristics for each adc channel table 3. static electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 23 900844 electrical characteristics static electrical characteristics gpios electrical characteristics gpio voltage level (this is wire d externally though gpiovcc pin) v gpiovcc - 1.8 v, 2.5 v, 3.3 v - v gpo voltage level (this is wir ed externally though gpovcc pin) v gpovcc - 1.8 v, 2.5 v, 3.3 v - v accuracy for gpiovcc, gpovcc - -5.0 - 5.0 % gpio output drive capability - - 20 - input low voltage v il 0 - 0.3*v cc v input high voltage v ih 0.7*v cc - v cc v output low voltage (v cc = v cc_min , i ol = 4.0 ma) v ol - - 0.1 v output high voltage (v cc = v cc_min , i oh = -4.0 ma) v ol v cc -0.1 - - v table 3. static electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data 24 freescale semiconductor 900844 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering these parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit spi interface timing and logic io time spicsb has to be low before the first rising edge of spiclk t selsu 20 - - ns time spicsb has to remain low after the last falling edge of spiclk t selhld 20 - - ns time spicsb has to remain high between two transfers t selhigh 20 - - ns clock period of spiclk (equivalent to a maximum clock frequency of 25 mhz) t clkper 40 - - ns part of the clock period where spiclk has to remain high t clkhigh 18 - - ns part of the clock period where spiclk has to remain low t clklow 18 - - ns time mosi has to be stable before the next falling edge of spiclk t wrtsu 5.0 - - ns time mosi has to remain stable after the falling edge of spiclk t wrthld 5.0 - - ns time miso will be stable before the next falling edge of spiclk t rdsu 5.0 - - ns time miso will remain stable after the falling edge of spiclk t rdhld 5.0 - - ns time miso needs to become active after the falling edge of spicsb t rden refer to figure 6 for more details time miso needs to become inactive after the rising edge of spicsb t rddis 5.0 - - ns viden/vid timing specification viden/vid debounce time t db 100 - 400 ns viden invalid state hold time t hold 1.0 - - s oscillator and clock outputs main characteristics rtc osc startup time (upon application of power) - - - 500 ms rtc rtc clock frequency, crystal osc nominal frequency - - 32.768 - khz vcc electrical characteristics transient load speed of change i cc /t - - 1.0 a/ns soft start time (enable to output voltage ramp up from 0 to 1.0 v (25 mv/s)) t sscc - - 0.06 ms turn off time (off to output voltage ramp down to 0 v) t ccoff - - 1.0 ms dac slew rate - - 25 - mv/s switching frequency f sw - 1.0 - mhz vnn electrical characteristics transient load speed of change i nn /t - - 1.0 a/ns soft start time (enable to output voltage ramp up from 0 v to 1.0 v (25 mv/s)) t ssnn - - 0.06 ms turn off time (off to output voltage ramp down to 0 v) t nnoff - - 1.0 ms dac slew rate - - 25 - mv/s switching frequency f sw - 1.0 - mhz
analog integrated circuit device data freescale semiconductor 25 900844 electrical characteristics dynamic electrical characteristics vddq electrical characteristics transient load speed of change i ddq /t - - 1.0 a/s soft start time (enable to output voltage ramp up from 0 to 1.8 v) t ssddq - - 200 s turn off time (off to output voltage ramp down to 0 v) t ddqoff - - 1.0 ms switching frequency f sw - 4.0 - mhz v21 electrical characteristics transient load speed of change i 21 /t - - 0.1 a/s soft start time (enable to output voltage ramp up from 0 v to 2.1 v) t ss21 - - 84 s turn off time (off to output voltage ramp down to 0 v) t 21off - - 1.0 ms switching frequency f sw - 4.0 - mhz v15 electrical characteristics transient load speed of change i 15 /t - - 0.1 a/s soft start time (enable to output voltage ramp up from 0 to 2.1 v) t ss15 - - 100 s turn off time (off to output voltage ramp down to 0 v) t 15off - - 1.0 ms switching frequency f sw - 4.0 - mhz vbg electrical characteristics transient load speed of change i bg /t - - 0.001 a/s soft start time (enable to output voltage ramp up from 0 to 1.0 v) t ssbg - - 20 s turn off time (off to output voltage ramp down to 0 v) t bgoff - - 5.0 ms vcca electrical characteristics transient load speed of change i cca /t - - 0.01 a/s soft start time (enable to output voltage ramp up from 0 to 1.5 v) t sscca - - 30 s turn off time (off to output voltage ramp down to 0 v) t ccaoff - - 5.0 ms vcc180 electrical characteristics transient load speed of change i cc180 /t - - 1.0 a/s soft start time (enable to output voltage ramp up from 0 to 1.8 v) t sscc180 - - 30 s turn off time (off to output voltage ramp down to 0 v) t cc180off - - 5.0 ms vpnl18 electrical characteristics transient load speed of change i pnl18 /t - - 0.1 a/s soft start time (enable to output voltage ramp up from 0 to 1.8 v) t sspnl18 - - 140 s turn off time (off to output voltage ramp down to 0 v) t pnl18off - - 5.0 ms vpmic electrical characteristics transient load speed of change i pmic /t - - 0.01 a/s soft start time (enable to output voltage ramp up from 0 to 1.8 v) t sspmic - - 700 s turn off time (off to output voltage ramp down to 0 v) t pmicoff - - 5.0 ms table 4. dynamic electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering th ese parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data 26 freescale semiconductor 900844 electrical characteristics dynamic electrical characteristics vymxyfi18 electrical characteristics transient load speed of change i ymxyfi18 /t - - 0.1 a/s soft start time (enable to output voltage ramp up from 0 to 1.8 v ) t ssymxyfi18 - - 200 s turn off time (off to output voltage ramp down to 0 v ) t ymxyfi18off - - 5.0 ms vccpaoac electrical characteristics transient load speed of change i ccpaoac /t - - 0.1 a/s soft start time (enable to output voltage ramp up from 0 to 1.0 v) t ssccpaoac - - 30 s turn off time (off to output voltage ramp down to 0 v) t ccpaoacoff - - 5.0 ms vccpddr electrical characteristics transient load speed of change i ccpddr /t - - 0.1 a/s soft start time (enable to output voltage ramp up from 0 to 1.0 v) t ssccpddr - - 35 s turn off time (off to output voltage ramp down to 0 v) t ccpddroff - - 5.0 ms vaon electrical characteristics transient load speed of change i aon /t - - 0.1 a/s soft start time (enable to output voltage ramp up from 0 to 1.0 v) t ssaon - - 25 s turn off time (off to output voltage ramp down to 0 v) t aonoff - - 5.0 ms vmm electrical characteristics transient load speed of change i mm /t - - 0.01 a/s soft start time (enable to output voltage ramp up from 0 to 1.2 v) t ssmm - - 125 s turn off time (off to output voltage ramp down to 0 v) t mmoff - - 5.0 ms vccp electrical characteristics transient load speed of change i ccp /t - - 0.1 a/s soft start time (enable to output voltage ramp up from 0 to 1.0 v ) t ssccp - - 26 s turn off time (off to output voltage ramp down to 0 v ) t ccpoff - - 5.0 ms vimg25 electrical characteristics transient load speed of change i img25 /t - - 0.01 a/s soft start time (enable to output voltage ramp up from 0 to 2.5 v) t ssimg25 - - 200 s turn off time (off to output voltage ramp down to 0 v) t img25off - - 5.0 ms vimg28 electrical characteristics transient load speed of change i img28 /t - - 0.1 a/s soft start time (enable to output voltage ramp up from 0 to 2.9 v) t ssimg28 - - 200 s turn off time (off to output voltage ramp down to 0 v) t img28off - - 5.0 ms table 4. dynamic electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering th ese parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 27 900844 electrical characteristics dynamic electrical characteristics vsdio electrical characteristics transient load speed of change i sdio /t - - 0.01 a/s soft start time (enable to output voltage ramp up from 0 to 1.8 v) t sssdio - - 100 s turn off time (off to output voltage ramp down to 0 v) t sdiooff - - 5.0 ms power switches electrical characteristics ramp up time - - 50 s adc electrical characteristics conversion time per channel - - 10 s turn on/off time - - 31 s table 4. dynamic electrical characteristics t a = -40 to 85 c, v pwr = 3.0 to 4.4 v, in gathering th ese parametrics, freescale used the external components described in the hardware design considerations section of this document, over the full load current range, unless otherwise noted. typical values are characterized at v pwr = 3.6 v and 25 c. characteristic symbol min typ max unit
analog integrated circuit device data 28 freescale semiconductor 900844 functional description general description functional description general description the 900844 is a high efficiency power management integrated circu it (pmic). it is optimized for ultra-mobile platforms for netbook, tablets, slates, embedded devices, and other applications requiring ?multi-cell? battery voltage. the 900844 pmic, is designed to provide cpu power requireme nts and control as an integral part of freescale's power management solution to meet the needs of ultra-mobile platforms. optimum partitioning, high feat ure integration, and state of the art technology, enable freescale to support ultra-mobile platforms that are cost effective, by reducing component coun t and board area. the freescale solution also allows ease of system design, resulting in a faster time to market development cycle. it accepts input from a supply in the range of 3.0 to 4.4 v (for example, from a multi- cell battery scaled down to 3.3 v) to deliver regulated power to various components (cpu, chip sets, wirele ss, memory, storage, display, sensors, and others) on ultra- mobile platforms. figure 4. power management solution - high level block diagram feature list ? netbook, tablets, and embedded devices, ul tra-mobile platform architecture support ? fully programmable dc/dc switching, low drop-out regulators, and load switches ? delivers regulated reliable power to various system components ? high efficiency multi mode power conversion ensuring extended battery life ? fully programmable with ex tensive protection features and co mplete fault reporting for best in class overall system reliabilit y ? internal compensation ? 5 buck dc/dc regulators - 2x vid controlled with 1.0 mhz switching and external switches for cpu and graphics core support - 3x with 4.0 mhz switching and integrated mosfet for platform support and ldo supply for optimized thermal performance and power efficiency. ? 14 low dropout (ldo) regulators. ? one configurable ldo/switch regulator for sdio card support ?a 3.3 v load switch for platform support ? coin cell backup battery charger ? spi communication interface (up to 25 mhz operation) ? 22 channel (32 capable) 10-bit adc for internal and external sensing with touch screen interface ? low power 32.786 khz xtal oscillator. ? real time clock (rtc) to provide time reference and alarm functions with wake up control. ? eight interrupt capable gpios and 8 gpos ? various control and status reporting i/os ? interrupt and reset controller. all interrupt signals can be masked. ? overall solution size target of < 400 mm 2 (including clearance and routing) ? operating temperature of -40 to +85 c 5 x dc/dc multi-mode switchers 2 x vid 4.0 mhz switching core, i/o, mem 14 x ldo regulators +1 x power switch low noise high performance 22 channel 10 bit adc pmic temp monitoring 4-wire resistive touch screen select rails current monitoring general purpose inputs freescale?s pmic platform solution power control logic state machine control interface 8 interrupt capable gpios spi interface + status and control inputs / outputs rtc 32.768 khz xtal oscillator
analog integrated circuit device data freescale semiconductor 29 900844 functional description general description functional block diagram figure 5. 900844 functional block diagram the component list for those items listed in this schematic can be found in the external components bom (23) . general purpose adc inputs touch screen interface gndadc 10 bit adc thermal protection power path manager sc900844 tsref touch screen interface spi control voutpnl33 pvin3p3 fbsdio sdiogt msdio vpwr li-cell switch from button switchers rtc calibration pll spi registers system & peripheral interface spivcc spiclk gndspi miso mosi shift register control adin21 mux gpo control gpio control ?? adin20 adin19 adin18 adin17 adin16 adin15 adin14 adin13 adin12 adin11 adin10 voltage / current sensing /& translation spicsb spi interface spi registers shift register shift register a / d control trigger handling cadref rxinr gndaud1 gndaud2 gndaud3 gndaud4 32.768khz internal osc 32.768khz crystal osc gndrtc cxtalrtc2 cxtalrtc1 xtalrtc xtal1 xtal2 clk32k gndctrl ictest viden0 viden1 vid0 vid1 vid2 vid3 vid4 vid5 vid6 pwrgd resetb vrcomp pmicint exitstby thermtripb pwrbtn from cpu to / from i/o chip enables & control timers li-cell charger power fail detect coincell gpiovcc gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 gpovcc gpo0 gpo1 gpo2 gpo3 gpo4 gpo5 gpo6 gpo7 copnl33 cosdio cinsdio rsdio voutimg25 voutimg28 pvinimg coimg25 vpwr gndimg coimg28 cinimg voutccpaoac voutccpddr voutaon coaon pvin1p5 coccpddr coccpaoac voutmm voutccp coccp comm v15 cin1p5 fbccp fbccpddr gnd1p5 pvinymxyfi18 voutymxyfi18 coymxyfi18 cinymxyfi18 copmic copnl18 cocc180 cin2p1 gnd2p1 voutbg voutcca pvin1p8 cobg v21 gnd1p8 cocca cin1p8 fbcca gndcoms1 gndcoms2 co15 l15 cin15 pvinddq pgndddq fbddq swddq coddq lddq cinddq mnn v15 pvincc voutfbcc hsccgt lsccgt swfbcc vpwr cincc cocc lcc mlscc mhscc vcc cspcc pgndcc vid[6:0] viden[1:0] gndsub1 gndsub2 gndsub3 gndsub31 gndsub32 refgndsw gndrefvcc gndcore ldorefp9 ldorefp8 cldorefp8 cldorefp9 optional components vcoreref vcoredig vcore ccore ccoreref ccoredig gndled gndbklt pgndbklt refgndchg pgndchg vpwr isnsbatp isnsbatn vbat vntc ntc rntc gndbat ccoin startup sequencer trim v3a reference generation vcc 3600ma buck vid controller output driver vnn 1600ma buck output driver pvinnn voutfbnn hsnngt lsnngt swfbnn vpwr cinnn conn lnn vnn cspnn pgndnn vddq 1500ma buck output driver vpwr vddq v21 1000ma buck pvin21 pgnd21 fb21 sw21 co21 l21 cin21 output driver vpwr v21 v15 1500ma buck output driver pvin15 pgnd15 fb15 sw15 vpwr vbg ldo vcca ldo vcc180 ldo vpnl18 ldo vpmic ldo pvin2p1 v21 voutcc180 voutpnl18 voutpmic vymxyfi18 ldo v21 vccpaoac ldo vccpddr ldo vaon ldo vmm ldo vccp ldo vimg25 ldo vimg28 ldo vpwr vsdio ldo / switch vsdio vpnl33 switch vpwr pvinvib rntcev 900844 v pwr v3a output pin input pin bi-directional pin package pin legend sc900844
analog integrated circuit device data 30 freescale semiconductor 900844 functional device operation system control interface functional device operation system control interface overview this section addresses the various interfaces and i/os be tween the pmic solution and the rest of the system. the system control interf ace includes the following: ? spi interface. ? interrupt controller ? platform sideband signals ? special registers spi interface the 900844 contains a spi interface port which allows a host co ntroller to access the register set. using these registers, 900844 resources can be controlled. the registers also provide info rmation on the pmic status, as well as information on extern al signals. the addressable register map spans 1024 registers of 8 data bi ts each. the map is not fully populated. a detailed structure of the register set along with bit names, posi tions, and basic descriptions, are given in table 74 . expanded bit descriptions are included in the individual functional sections for application guidance. note that not all bits are truly writable. refer to the individual sub-circuit descriptions and table 74 to determine the read/write capability of each bit. the system controller unit (s cu) within the platform controller hub (pch) is the master, while the pmic is the slave. the spi interface operates at a typical frequency of 12.5 mhz, and at a maximum frequency of 25 mhz, with lower speeds supported. the spi interface is configured in mode 1: clock polarity is active high (cpol = 0), and data is latched on the falling edge of the clock (cpha = 1). the chip select si gnal, spicsb, is active low. the spicsb lin e must remain active during the entire spi transfer. the miso line will be tri-stated while spicsb is high. the spi frame consists of 24 bits: a read/write bit, a 10-bit add ress code (msb first), 5 "dead" bits and 8 data bits (also msb first). the read/write bit selects whether th e spi transaction is a read or a write: for a write operation, the r/w bit must be a one; for a read operation, it must be a zero. for a read transaction, any data on the mo si pin after the address bits is ignored . the miso pin will output the data field pointed to by the 10-bit address loaded at the beginning of the spi sequence. spi re ad backs of the address field and unused bits are returned as zero. for read operatio ns, the pmic supports address auto-increment. for a write operation, once all the data bi ts are written, the data is transferred into the registers on the falling edge of th e 24th clock cycle. all unused spi bits in each register must be written to a zero. to start a new spi transfer, the spicsb li ne must go inactive and then active. after the lsb of data is sent, if the spicsb lin e is held low, up to seven additional address/data packe ts may be sent as writes to the pmic. refer to the vrcomp pin section. the following diagrams illustrate the spi writ e protocol, spi read protocol, and spi timing. table 5. spi interface pin functionality pin name spi functionality spiclk spi clock input (up to 25 mhz) mosi master out / slave in (serial data in) miso master in / slave out (serial data out) spicsb chip select (active low) spivcc spi bus supply - 1.8 v typical
analog integrated circuit device data freescale semiconductor 31 900844 functional device operation system control interface figure 6. spi read from pmic diagram (one address/data packet shown) figure 7. spi write to pmic di agram (one address/data packet shown) figure 8. spi interface timing diagram (processor input capacitance is 3.0 pf) interrupt controller control the pmic informs the system of important events using interrupts. unmasked inte rrupt events are signaled to the host by driving the pmicint pin high. each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. i f a new interrupt occurs while the controller clears an existi ng interrupt bit, the interrupt line will remain high. each interrupt can be masked by setting the corresponding mask bi t to a ?1?. as a result, when a masked interrupt bit goes high, the interrupt line will not go high. a masked interrupt can still be read from the register. if a masked interrupt bit wa s already high, the interrupt line will go high after unmasking. the following is the interrupt handling mechanism whic h has inherent latency that the clients must expect: 1. pmic interrupts scu, if both the 1st and 2nd level bits are not masked. 2. scu reads pmic master, 1st level, interrupt event register. 3. scu then traverses all the branches of the interrupt tree where events are indicated. 4. scu will service events in leaf node registers.
analog integrated circuit device data 32 freescale semiconductor 900844 functional device operation system control interface when an unmasked interrupt event happens: ? the 2nd level bit is set. ? the 1st level bit is set by a rising edge sent from the 2nd level register, and the pmicint signal goes from low to high ? when the system controller, the scu, reads the 1st level register the 2nd level registers that we re set, remain set. any unset registers are free to accept an interrupt event. ? when the 1st level register is read, any 1st level register bits that were set at the point the spi read strobe shifts the reg ister value into the spi transmit shift register, that bit will be clea red by the spi self clear signal immediately following the rea d strobe. this allows new interrupts to be recorded without being lo st. if all unmasked 1st level bi ts get cleared by the read, t he pimcint pin will de-assert. if a new unmasked 1st level interrupt event happens, just after the r ead of the 1st level register, the pimcint pin interrupt pin will remain asserted. the scu reads each 2nd level register and these are cleared on read. ? when the 2nd level register is read, any 2nd level register bits that were set at the point the spi read strobe sweeps, the register value into the spi transmit shif t register, that bit will be cleared by t he spi self clear signal immediately followin g the read strobe. this allows new interrupts to be recorded without being lost. if a new unmasked 2nd level interrupt event happens just after the read of the 2nd level register, the pmic int pin will assert if the 1st level bit is not masked. interrupt bit summary table 7 summarizes all 1st and 2nd level interrupt bits associated with the interrupt controller. for more detailed behavioral descriptions, refer to the related sections. table 6. interrupt registers summary block addr register name rw d7 d6 d5 d4 d3 d2 d1 d0 initial irq 0x04 interrupt r ext aux vrfault gpio rtc chr adc pwrbtn 0x00 irq 0x05 intmask r/w mext maux mvrfaul t mgpio mrtc mchr madc mpwrbtn 0xfa rtc 0x1c rtcc r irqf pf (=0) af uf rsvd rsvd rsvd rsvd 0x00 power 0x30 vrfaultin t r rsvd rsvd rsvd rsvd rsvd vrfail batocp thrm 0x00 power 0x31 mvrfaulti nt r/w rsvd rsvd rsvd rsvd rsvd mvrfail mbatocp mthrm 0x03 adc 0x5f adcint r rsvd rsvd rsvd rsvd rsvd overflow pendet rnd 0x00 adc 0x60 madcint r/w rsvd rsvd rsvd rsvd rsvd moverflo w mpendet mrnd 0x00 gpio 0xe8 gpioint r gpiint7 gpiint6 gpiint5 gpiint4 gpiint3 gpiint2 gpiint1 gpiint0 0x00 notes 9. because of the design of the clear on read logic, any interrupt event is allowed to happen at any time. if the interrupt even t happens close to when a read of the interrupt register happens, if the spi read captures that interrupt bit as being set, then that bit will get cleared. if the read does not capture the bit as being set, it will not be cleared. in this way no interrupt events are lost. 10. the 2nd level interrupts that get "ored" together to set the 1st level interrupt bits can block other 2nd level interrupts f rom setting the 1st level interrupt register. this is because if any of the 2nd le vel interrupts is high, the output of the or will remain high, bl ocking the other 2nd level interrupt?s rising edge. this shoul d not be a problem. because when the 2nd level register is read, the scu will see all the bits that are active when it is read. the so ftware will decide which one to se rvice first, just as it needs to do when more than one 1st level interrupt bits are set when that register is read. 11. masking has no affect on interrupt bits being set or cleared. masking just prevents the interrupt event from asserting the i nterrupt pin. if an interrupt bit is set, but is masked, the interrupt pin does not assert. if the mask bit is cl eared while the bit is still se t, the interrupt pin will assert. most interrupt registers have 1st and 2nd level mask bits. both mask bits must be in the unmasked state to generat e an interrupt to the scu. 12. some 2nd level interrupt registers are level sensitive. if the level that sets these interrupts registers is active when the register is read, it will clear during the active time of th e clear on read signal and then reassert. this will reassert the 1st level interrupt bit. 13. the gpio interrupts do not have interrupt masking bits, they ha ve interrupt prevention bits. this is controlled by bits 5:4 of the gpio control register. see gpios for more details on using the gpio as interrupt inputs. 14. interrupts generated by external events are de-bounced. theref ore, the event needs to be stable throughout the de-bounce per iod before an interrupt is generated. nominal de-bounc e periods for each event are documented in table 7 . due to the asynchronous nature of the de-bounce timer, the effectiv e de-bounce time can vary slightly.
analog integrated circuit device data freescale semiconductor 33 900844 functional device operation system control interface table 7. interrupt bit summary 1st level 2nd level interrupt event condition detect debounce time name bit name bit pwrbtn d0 - - pwrbtn falling edge detection falling 10 ms adc d1 rnd d0 adc round robin cycle complete hi level - pendet d1 touch screen wake-up rising - rsvd d7:d2 - - - chr d2 rsvd d0 - - - batovp d1 battery over-voltage rising/falling (16) temp d2 battery temperature outside valid window hi level 1.0 ms rsvd d3 - - - rsvd d4 - - - batdet d5 battery connect/disconnect hi level 0.5 sec rsvd d6 - - - usbovp d7 input over-voltage reached hi level 10 ms rtc d3 rsvd d3:d0 - - - uf d4 update cycle hi level - af d5 current time = alarm time hi level - rsvd d6 - - - irqf d7 irqf=uie*uf + aie*af hi level - gpio d4 gpint0 d0 edge detect rising/falling/both gpidbnc0 gpint1 d1 edge detect rising/falling/both gpidbnc1 gpint2 d2 edge detect rising/falling/both gpidbnc2 gpint3 d3 edge detect rising/falling/both gpidbnc3 gpint4 d4 edge detect rising/falling/both gpidbnc4 gpint5 d5 edge detect rising/falling/both gpidbnc5 gpint6 d6 edge detect rising/falling/both gpidbnc6 gpint7 d7 edge detect rising/falling/both gpidbnc7 vrfault d5 thrm d0 junction temperature > thermal warning threshold hi level 10 ms rsvd d1 - - - vrfail d2 regulator fault present hi level (15) rsvd d7:d3 - - - aux d6 rsvd d0 - - - rsvd d1 - - - rsvd d0 - - - rsvd d1 - - - rsvd d7:d4 - - - ext d7 not supported notes 15. varies by regulator. normally it is 1.5 times the regulator turn on time. 16. 32 ms rising and 120 s falling
analog integrated circuit device data 34 freescale semiconductor 900844 functional device operation system control interface sideband signals the following pins are included as part of the sideband signals: pmcint pin the pmicint pin interrupts the platform controller hub by risi ng from low to high when an unmasked interrupt event occurs. it is a level sensitive pin and it is cleared when the plat form controller hub reads the in terrupt registers. reference interrupt controller for a more detailed explanation of the interrupt mechanism. the pmicint pin follows the dc signaling specifications in table 3 with a reference of 1.8 v (vpmic). vrcomp pin this is an active high voltage regulator complete signal. it is asserted low by the pmic when a spi voltage regulation request, or other write request has been dec oded. the signal is de-asserted on completion of the request (i.e. the rail is in regulation ). this signal is relevant to the spi in itiated writes and exitstby assertion. the vrcomp pin follows the dc signaling specifications in table 3 with a reference of 1.8 v (vpmic). figure 9 illustrates the voltage regulators register write cycles and vrcomp functionality. t he rising edge on the spicsb pin indicates the end of the block of voltage regulators configur ations, at which point the vrco mp pin is driven low. as an address/data block is written, the pmic can start to ramp those rails (dc-dc, ldo, or switch). once all of the rails are in regulation, the pmic drives the vrcomp pin high, indicating to the platform controller hub that the voltage regulator configura tion request is completed, and the pmic is ready for subsequent transactions. the maximum number of voltage regulator change packets (address/data combinations) is 8. the voltage regulators should ramp at the rate defined in the regulators tables. due to the relatively long turn-off time of the voltage regu lators, the vrcomp signal is to be gated-off after a 500 ns minimum (30 ms max.) low time. figure 9. vrcomp functionality in a spi voltage regulators configuration table 8. sidebands pin functionality pin name i/o pin functionality pmicint o active high pmic interrupt output pin vrcomp o active high voltage regulator complete signal resetb o active low hard reset for platform controller hub pwrgd o active high power good output signal exitstby i active high exit standby signal thrmtripb i active low thermal trip assertion input signal viden[1:0] i active high input signals driven by the cpu, to indicate if the vid bus is addressing vcc or vnn. vid[6:0] i active high input signals driven by the cpu, to indicate the output voltage setting for the vcc and vnn rails. idle spi packet spi packet spi packet spi packet idle idle vr reconfigure existing mode 4 - t vr_comp spi_cs# spi bus vr status vr_comp
analog integrated circuit device data freescale semiconductor 35 900844 functional device operation system control interface reset pin this is an active low, hard reset for the platform controller hub. when this pin is asserted, the platform controller hub retur ns to its initial default state. this signal can be asserted when a co ld or warm reset is initiated, depending on the settings in the chipcntl register. the reset pin follows the dc signaling specifications in table 3 with a vcc of 1.8 v (vpmic) pwrgd pin this is a power good output signal from the 900844 to the platform controller hub. assert ion of pwrgd means that the vccpaoac, vaon, and vpmic rails have been valid for at least 100 microseconds. the platform controller hub will remain off until this signal is asserted. this signal is only de-assert ed if vccpaoac, vaon, or vpmic is out of regulation, or a cold reset is initiated by the firmware. the pwrgd pin follows the dc si gnaling specifications in table 3 with a reference of 1.8 v (vpmic) warm and cold reset the reset and pwrgd signals have two function s which are initiated through the regist er file. together they define a warm reset or cold reset to the platform controller hub. the sequencing shown in figure 10 and is controlled from the register chipcntrl through bits warmrst and col drst. the pulse will be held low for 5.0 s < t < 31 s. figure 10. warm/cold reset functionality exitstby pin when the exitstby pin is asserted high, the 900844 exits the aoac standby settings for r egulating the platform supplies. when asserted, the pmic switches the voltage regulators, as defin ed in the voltage regulator registers from the ctl bits to the aoactl bits. this is a low latency voltage regulators context switch. exitstby pin follows the dc signaling specifications in table 3 with a reference of 1.05 v (v ccp ) aoac exit standby when the exitstby signal is asserted high from the platform controller hub, the vrcomp si gnal will be driven low. the aoactl bits will be copied to the ctl bits in the different voltage regulator control regist ers on the rising edge of the exits tby signal, unless bit 5 is '0'. if bit 5 is '0', then the ctl bits are not modified. the vrcomp signal is de-asserted at this poin t. the rails defined in the new ctl registers will be ramped up together or remain in the same state, as if the aoactl settings were the same as the previous ctl setting. once all of the rails are in regulation, the vrcomp signal will be driven high. figure 11 shows the timing diagram of the exitstby signal. there is a special case (optimized case) when the exitstby signal is asserted with the vccp, vccpddr, vcca, and vcc180 rails. if some combinatio n of these four rails turn on with the assertion of the exitstby signal, the entire time fo r the re-configuration should take no longer than 30 ms. see figure 12 . table 9. chipcntl register structure and bit description name bits description chipcntl (addr 0x 06 - r/w - default value: 0x00) coldrst 0 cold reset function enable x0 = no change x1 = pulse reset and pwrgd low warmrst 1 warm reset function enable x0 = no change x1 = pulse reset low reserved 7:2 reserved
analog integrated circuit device data 36 freescale semiconductor 900844 functional device operation system control interface figure 11. general exit standby diagram figure 12. optimized exit standby diagram the power-on default aoacctlvxx register setting for the vc cp, vccpddr, vcca, and vcc180 rails, are to be turned on by the assertion of the exitstby signal. however, every regulator has an aoacctlvxx register setting, and can be configured to turn on, turn off, or have no change. the power-on default aoacctlvxx register setting for all other regulators is set to no change. note that the v ddq regulator has to be enabled in order for the v cca regulator to turn on. thermtripb pin thermtripb is an active low thermal trip in put signal. it is asserted by the cpu to indicate a catastrophic thermal event. on the falling edge of thermtripb, the pmic has 500 ms to sequence off all rails from the highest to lowest. the pmic will turn on automatically upon detecting a turn on event, at which point the cold boot flow should be followed as shown in turn on events . the pmic provides a weak (50 -100 k ) pull-up to vccpaoac. the pmic only responds to a thermtripb signal if the v ccp regulator is on. the platform controller hub output driver is a nominal 55 . the thermtripb pin follows the dc signaling specifications in table 3 with a reference of 1.05 v (vccpaoac). viden[1:0] & vid[6:0] pins both vcc and vnn regulators are variable in the cpu and supp ly two different sub-systems. the cpu implements a vid mechanism that minimizes the number of r equired pins. the vid for vnn and vcc are mu ltiplexed on to the same set of pins, and a separate 2-bit enable/id is defined to specify to which sub-system the driven vid corresp onds. one of th e combinations notifies that the vid is invali d. this is used when the cpu is in c6/standby , to tri-state the vid pins to save power. exit_stby spi bus vr stats vr_comp# idle existing mode vr reconfigure new mode t vr_comp aoacctlvxx copied to tvxx status exit_stby spi bus vr status vr_comp# idle existing mode vr reconfigure new mode t vr_comp aoacctlvxx copied to ctlvxx 30 sec
analog integrated circuit device data freescale semiconductor 37 900844 functional device operation system control interface both vcc and vnn have initial boot voltage (vcc v boot = 1.1 v; vnn v boot = 0.9 v) settings that the platform controller hub sets to the vnn and vcc regulators by a spi write to t he vnnlatch and vcclatch registers. once all of the platform voltage rails are up, the cpu will drive t he vid and viden signals to set the vnn and vcc output voltage to the appropriate level. the vid and viden signals will go through the sequence invalid >> vnn >> invalid >> vcc. vid[6:0] and viden[1:0] will tr ansition together and the pmic must de-bounce the vid[6:0] and viden[1:0] for 100 to 400 ns. the cpu will hold these signals valid for at least 500 ns. vid signals are disabled from controlling vcc/vnn unless the v ccp regulator is enabled both regulators support dynamic vid transitioning during norma l runtime operation. dynamic vi ds require the cpu to change the viden signals for the vnn regulator to invalid each time, to change the vnn output voltage. the vcc regulator is different in that it does not require the viden signals to change to chan ge the vcc output voltage. if th e viden signals are set for vcc (01), the vid signals can change and the vcc regulator will respond by changing the output voltage accordingly. figure 13 shows how the vcc output voltage can change during no rmal runtime operation when the viden signals are set to vcc (01). if the viden signals are set to vcc (01), the vcc regulator must monitor the vid signals, latch any changes, and change the output voltage setting accordin gly. when the cpu is dynamically changing the vid setting for the vcc regulator during normal operation, it will only change the vid combinati on by 1 step, which corresponds to a voltage step of 12.5 mv. during these changes, the vcc regulator must follow the 25 mv/ms slew rate specification. the vnn regulator differs from the vcc r egulator, in that dynamic changes to the vnn regulator output voltage require the viden signals to change to invalid each time. figure 14 shows how the vnn output voltage can change during normal runtime operation. the viden[1:0] pins are active high signa ls driven by the cpu to indicate if th e vid bus is addressing vcc or vnn. they follow the dc signaling specifications in table 3 with a reference of 1.05 v (v ccpaoac ) the vid[6:0] pins are active high signals driven by the cpu to indicate the output voltage setting for the vcc and vnn rails. they follow the dc signaling specifications in table 3 with a reference of 1.05 v (v ccp ) the vid output buffer driver is of the cmos type. the platform controller hub output driver impedance is a pull-up (55 +20%/ -55%) and pull-down (55 +20%/-55%). motherboard impedance is 55 15%. under extreme conditions, there could be ringing that cross the 70/30% threshold, hence the de-bounce requirements. maximu m leakage current on the vid pins is 100 ma. vid[6:0] for each of the vcc and vnn rails will be latched in an internal register that will be updated with every vid[6:0] pin signaling. note that the term reserved or rsvd is used throughout this docu ment. this nomenclature refers to reserved registers that are not for designed customer use. for question regarding these registers, contact freescale semiconductor technical support. table 10. viden selections viden[1:0] bits selection 0 0 invalid 0 1 vcc 1 0 vnn 1 1 unused table 11. vcc and vnn latch register structure and bit description name bits description fslvcclatch (addr 0x1c9 - r - default value: 0x7f) vccvid 6:0 this register latches an image of the last vid[6:0] signals for vcc reserved 7 reserved fslvnnlatch (addr 0x1ca - r - default value: 0x7f) vnnvid 6:0 this register latches an image of the last vid[6:0] signals for vnn reserved 7 reserved
analog integrated circuit device data 38 freescale semiconductor 900844 functional device operation system control interface figure 13. dynamic vcc timing diagram figure 14. dynamic vnn timing diagram figure 15 shows the 7-bit vid codes vs. the output voltage of vcc and vnn.
analog integrated circuit device data freescale semiconductor 39 900844 functional device operation system control interface figure 15. 7-bit vid code vs. vcc/vnn output voltage as explained previously, the output voltage setting for the vcc and vnn regulators can be set via the vid/viden pins from the cpu, or by programming the vnnlatch and vcclatch register s through the spi interface via the platform controller hub. figure 16 shows the relationship between the vid/viden signals, the dvpxvrd bit in the latch registers, and the vrcomp output signal. the figure shows v cc as an example, but is also applicable to v nn the dvpxvrd bit in the vnnlatch and vcclatch registers contro ls the select input to the multiplexer. if the dvpxvrd bit is set to a '0', the regulator uses t he vid/viden pins from the cpu, and if the dvpxvrd bit is set to a '1', the regulator uses the vnnlatch and vcclatch register s to set the output voltage. when the dvpxvrd bit is set to a '0', any changes to t he vnnlatch and vcclatch registers should be ignored. when the dvpxvrd bit is set to a '1', any changes on t he vid/viden pins from the cpu should be ignored. as soon as the dvpxvrd bit is set to a '1', the regulator switches from using the vid/viden pins to using the vcclatch register, and the output voltage of the regulator changes to what the vcclatch register is set. figure 16 shows how the pmic controls the v rcomp signal. the pmic toggles the vrcomp signal any time the dvpxvrd bit is set to a '1' and t he output voltage of the v nn or the v cc regulator changes. if t he output voltage of the v cc /v nn regulator changes and the dvpxvrd bit is set to a '0', the vrcomp sig nal should not toggle. vrcomp only toggles for changes to v cc and v nn through the spi registers. 6543210 6543210 6543210 6543210 0000000 1.2000 0100000 1.1000 1000000 0.7000 1100000 0.3000 0000001 1.2000 0100001 1.0875 1000001 0.6875 1100001 off 0000010 1.2000 0100010 1.0750 1000010 0.6750 1100010 off 0000011 1.2000 0100011 1.0625 1000011 0.6625 1100011 off 0000100 1.2000 0100100 1.0500 1000100 0.6500 1100100 off 0000101 1.2000 0100101 1.0375 1000101 0.6375 1100101 off 0000110 1.2000 0100110 1.0250 1000110 0.6250 1100110 off 0000111 1.2000 0100111 1.0125 1000111 0.6125 1100111 off 0001000 1.2000 0101000 1.0000 1001000 0.6000 1101000 off 0001001 1.2000 0101001 0.9875 1001001 0.5875 1101001 off 0001010 1.2000 0101010 0.9750 1001010 0.5750 1101010 off 0001011 1.2000 0101011 0.9625 1001011 0.5625 1101011 off 0001100 1.2000 0101100 0.9500 1001100 0.5500 1101100 off 0001101 1.2000 0101101 0.9375 1001101 0.5375 1101101 off 0001110 1.2000 0101110 0.9250 1001110 0.5250 1101110 off 0001111 1.2000 0101111 0.9125 1001111 0.5125 1101111 off 0010000 1.2000 0110000 0.9000 1010000 0.5000 1110000 off 0010001 1.2000 0110001 0.8875 1010001 0.4875 1110001 off 0010010 1.2000 0110010 0.8750 1010010 0.4750 1110010 off 0010011 1.2000 0110011 0.8625 1010011 0.4625 1110011 off 0010100 1.2000 0110100 0.8500 1010100 0.4500 1110100 off 0010101 1.2000 0110101 0.8375 1010101 0.4375 1110101 off 0010110 1.2000 0110110 0.8250 1010110 0.4250 1110110 off 0010111 1.2000 0110111 0.8125 1010111 0.4125 1110111 off 0011000 1.2000 0111000 0.8000 1011000 0.4000 1111000 off 0011001 1.1875 0111001 0.7875 1011001 0.3875 1111001 off 0011010 1.1750 0111010 0.7750 1011010 0.3750 1111010 off 0011011 1.1625 0111011 0.7625 1011011 0.3625 1111011 off 0011100 1.1500 0111100 0.7500 1011100 0.3500 1111100 off 0011101 1.1375 0111101 0.7375 1011101 0.3375 1111101 off 0011110 1.1250 0111110 0.7250 1011110 0.3250 1111110 off 0011111 1.1125 0111111 0.7125 1011111 0.3125 1111111 off v id vid (v) v id vid (v) v id vid (v) v id vid (v)
analog integrated circuit device data 40 freescale semiconductor 900844 functional device operation system control interface figure 16. relationship between the vid/vi den pins, the dpv1vrd bit, and vrcomp signal special registers vendor id and version id the vendor id and other version details can be read via t he identification bits. these are hard-wired on the chip. embedded memory there are 24 memory registers of general purpose embedded memo ry, which are accessible by the processor to store critical data during power down. these registers cons ist of 8 in the general purpose registers area, and 16 more in the freescale dedicated register area. general memory registers are called memx [mem1, mem2? mem8]. th e freescale dedicated registers are called fslmemx [fslmem1, fslmem2? fslm em16]. the data written to these registers is maintained by the coin cell, when the main battery is deeply discharged or removed, and is part of the rtc blo ck. the content of the embedded memory is reset by rtcporb. the banks can be used for any system need, for bit retent ion with coin cell backup. table 12. vendor id registers structure and bits description name bits description id1 (addr 0x00 - r - default value: 0x28) vendid1 2:0 chip1 vendor id rev1 5:3 chip1 revision id reserved 7:6 reserved id2 (addr 0x01 - r - default value: 0x00) vendid2 2:0 chip2 vendor id rev2 5:3 chip2 revision id reserved 7:6 reserved id3 (addr 0x02 - r - default value: 0x00) reserved 7:0 reserved id4 (addr 0x03 - r - default value: 0x00) reserved 7:0 reserved scu scu scu scu scu
analog integrated circuit device data freescale semiconductor 41 900844 functional device operation system control interface x is from 1 to 8 in table 13 . the rest of the 24 registers reside in the freescale dedicated register space. x is from 1 to 16 in table 14 . output driver control select output pins output drive capability ca n be programmed for 4 different settings as shows in the following tables. all of the following outputs follow the settings as shown. pll control the following register controls t he pll and the different divider valu es for different output frequencies. table 13. general purpose memory memx re gister structure and bits description register name bits description memx - 7:0 general purpose memory register x table 14. general purpose memory fslmemx register structure and bits description register name bits description fslmemx - 7:0 general purpose memory register x table 15. output driver control selection slope select rise time (ns) fall time (ns) 0 0 8.4 7.0 0 1 6.2 6.2 1 0 hi-z hi-z 1 1 22.3 21.3 table 16. output driver register structure and bit description name bits description fsloutdrvcntl1 (addr 0x1bf - r/w - default value: 0x00) pwrgddrv 1:0 pwrgd output pin driver capability vrcompbdrv 3:2 vrcomp output pin driver capability pmicintdrv 5:4 pmicint output pin driver capability resetbdrv 7:6 resetb output pin driver capability fsloutdrvcntl3 (addr 0x1c1 - r/w - default value: 0x01) spisdodrv 1:0 miso output pin driver capability rsvd 7:2 reserved
analog integrated circuit device data 42 freescale semiconductor 900844 functional device operation system control interface test modes test mode configuration during evaluation and testing, the ic can be configured for normal operation or test mo de via the ictest pin and other register configurations. details of test mode prog rammability are not documented herein, but should be referenced from other design for test documentation. test modes are for freescale use only, and must not be accessed in applications. in test modes, signals are multiplexed on existing functional pins. the ictest pin mu st therefore be tied to ground (for normal operation) at the board level, in product applications test mode also disables the thermal protection for high temperatur e op life testing. a proprietary protocol is included for sca n chain test configurations, which reuses the spi pins. in-package trimming during ic final test, several parameters are trimmed in the package, such as the main bandga p, and other precision analog functions. trim registers are for freescale use only and must not be accessed in product applications. fuse programming circuitry will be blocked during normal and test mode operation. table 17. pll control register structure and bit description name bits description fslpllcntl (addr 0x1e4 - r/w - default value: 0x1b) plldivide 2:0 pll divide ratio and effective vco frequency settings x0 = 112, 3.670 mhz x1 = 116, 3.801 mhz x2 = 120, 3.932 mhz x3 = 124, 4.063 mhz x4 = 128, 4.194 mhz x5 = 132, 4.325 mhz x6 = 136, 4.456 mhz x7 = 140, 4.588 mhz pll16men 3 16 mhz frequency enable x0 = 16 mhz clock disabled x1 = 16 mhz clock enabled and pll enabled pllen 4 pll enable, even if there is no block requesting a clock x0 = pll enabled based on device enables only x1 = pll enabled reserved 7:5 reserved
analog integrated circuit device data freescale semiconductor 43 900844 functional device operation clock generation and real time clock (rtc) clock generation and real time clock (rtc) clock generation a system clock is generated for internal di gital circuitry, as well as for external applications uti lizing the clock output pin s. a crystal oscillator is used for the 32.768 khz time base and generation of related derivativ e clocks. if the crystal oscillator is not running (for example, if the cryst al is not present), an internal 32 khz oscillator will be used instead. clocking scheme the internal 32 khz oscillator is an integrated backup for t he crystal oscillator and provides a 32.768 khz nominal frequency at 50% accuracy, if running. the internal oscillator only runs if a valid supply is available at the battery or coin cell, and would not be used as long as the crystal oscillator is active. the crystal oscillator continues running, supplied from one of the sources as described previously, until all power is d epleted or removed. all cont rol functions will run off the crystal derived frequency, occasionally referred to as the "32 khz". at system startup, the 32 khz clock is driven to the clk32k output pin, wh ich is spivcc referenced. clk32k is provided as a peripheral clock reference. the driver is enabled by the startup sequencer. additi onally, a spi bit m32kclk bit is provided f or direct spi control. the m32kclk bit defaults to 0 to enable t he driver and resets on the rtcporb to ensure the buffer is activated at the first power up and configur ed as desired, for subsequent power ups. the drive strength of the output drivers is programmable with clk32kdrv[1:0] (master control bits that affect the drive strength of clk32k), see fs loutdrvcntl2 register in table 16 . if a switch over occurs between the two cl ock sources (such as when the crystal oscilla tor is starting up), it will occur durin g the active low phase of both clocks, to av oid clocking glitches. a status bit, oscstp , is available to indicate to the processo r which clock is currently selected: oscstp=1 when the intern al rc is used, and oscstp=0 if the xtal source is used. oscillator specifications the 32 khz crystal oscillator has been optimized for use in conjunction with the abracon? abs07-32.768khz-t, or equivalent. the electrical characteristics of the 32 khz crystal oscillators are given in the oscillator section on table 3 and table 4 , taking into account the crystal characteristics noted previously . the oscillator accuracy depends largely on the temperature characteristics of the used cr ystal. application circuits can be optimized for required accuracy by adapting the external cryst al oscillator network (via component accuracy and/or tuning). additionally, a clock calibra tion system is provid ed to adjust the 32.768 cycle counter th at generates the 1.0 hz timer and rtc registers; see real time clock (rtc) for more detail. real time clock (rtc) the rtc block provides a real-time clock with time-of-day, year, month, and date, as well as daily alarm capabilities. the real - time clock will use the 32.768 khz oscillator as its input clock. the real-time clock will be powe red by the coin cell backup battery as a last resort, if no other power source is available (battery or usb/wall plug). the register set is compatible with the mot orola? mc146818 rtc device. overview the rtc module uses a 15-bit counter to generate a 1.0 hz clock for timekeeping. the seven time and calendar registers keep track of seconds, minutes, hours, day-of-week, day-of-mont h, month, and year. the three seconds, minutes, and hours alarm registers can be used to generate time-of-day alarm interrupts. the rtc time, alarm, and calendar values can be represente d in 8-bit binary or bcd format. the hours and hours alarm values can be represented in 24 hour or 12 hour format, with am/pm in the 12 hour mode. rtc control register b allows for software configurable clock formatting and interrupt masking. cont rol registers a, c, and d, repo rt software testable rtc statu s, including interrupt flags, update- in-progress, and valid-ram-time. the rtc resets when the rtcporb signal is driven low. the clock and calendar registers will be initia lized to 00:00:00, sunday, january 1, 2000.
analog integrated circuit device data 44 freescale semiconductor 900844 functional device operation clock generation and real time clock (rtc) features the rtc module includes the following features: ? counts seconds, minutes, and hours of the day ? counts days of the week, date, month, and year ? binary or bcd representation of time, calendar, and alarm ? 12 or 24 hour clock with am and pm in 12 hour mode ? automatic leap year compensation ? automatic end of month recognition ? 15 bytes of clock, calendar, rtc control, and coin cell registers ? two interrupts are separately software maskable and testable ? time-of-day alarm ? end-of-clock update cycle interrupt ? 15-bit counter to generate 1.0 hz rtc clock ? software testable valid-ram-and-time status bit indicates data integrity modes of operation normal mode in normal mode, the rtc module updates time and calendar registers using the internal 1.0 hz rtc clock. once per second, the alarm registers are compared to the current time, and if e nabled, an alarm interrupt will occur when the alarm time matches the current time. during normal operation, all 14 bytes of rtc and coin cell battery registers can be read through the spi interface. control register b may be update d to enable end-of-clock update interrupts, alarm interrupts, or to put the rtc in s et mode. the coin cell charger register is available for r/w in normal mode. coin cell mode when the application is powered down, the rtc will continue to keep track of time using power provided by the coin cell battery. since the system spi will be powered down during this time, there is no re ad or write access to the rtc registers in c oin cell mode. set mode in set mode, the clock and calendar updates are suspended, and the software may update the time, calendar, and alarm registers. the time and calendar formats must match the formats specified by the dm and 12/24 format bits in rtc register b. when the format bits are modified, all 14 time, calendar, and alarm registers must be updated in the specified format. scan/test mode internal test mode not available for the end application. setting the time, calendar, and alarm before initializing the internal registers, the set bit in regi ster b should be set to a "1" to prevent time/calendar updates f rom occurring. select the rtc data format by writing the appropriate va lues to the dm and 24/12 bits in register b. this can all be done simultaneously with one spi write to register b. next, the program should initialize all 10 time, calendar, and al arm locations, in the format specified by register b (binary o r bcd, 12 or 24 hour). all 10 time, calendar, and alarm bytes must use the same data mode , either binary or bcd. both the alarm hours, and the hours bytes must use the same hours format, either 12 or 24. the set bit may now be cleared to allow updates. once initializ ed, the real-time clock makes all updates in the selected data mode. the data mode (dm) cannot be changed wit hout re-initializing the 10 data bytes. the 24/12 bit in register b establishes whet her the hour locations represent 1-to-12 or 0-to-23. when the 12 hour format is selected the high order bit of the hour by tes represents pm when it is a "1". th e 24/12 bit cannot be changed without re-initia lizing the hour and alarm-hour locations. table 18 shows the binary and bcd formats of the 10 time, calendar, and alarm locations.
analog integrated circuit device data freescale semiconductor 45 900844 functional device operation clock generation and real time clock (rtc) reading the time, calendar, and alarm under normal operation, the current time and date may be read by accessing the rtc registers through the system spi. since the alarm is only updated by a spi write in struction, the three alarm registers may be read at any time and will always be defi ned. the 900844 spi will run at a minimum of 12.5 mhz. each individual spi read transac tion requires 25 cycles (less for burst- read). the rtc contains seve n timekeeping registers to keep track of second s, minutes, hours, day- of-week, day-of-month, month, and year. if the spi is clocked at the slowest frequency, and the rtc is read using individual (not burst) spi read commands, the following equation gives the maximum amount of time it takes the processor to read a complete date and time (assuming the reads are done sequentially, and uninterrupted): (25 * 7) / (12.5 mhz) = 14 s. this equation shows that a program which randomly accesses the time and date information will find the data in transition statistically 14 times per million attempts. if a clock update o ccurs during the time it takes to read all seven timekeeping re gisters, the values read may be inconsistent. in other words, if the program starts to read the seven date/time registers and an rtc update occurs, the data collected may be in tr ansition. in this event, it is possible to read transition data in one of the reg isters, resulting in undefined output. it is more likely that the registers read after the u pdate would be incremented (by one second), and the registers read before the update would not. the time, calendar, and alarm bytes are always accessible by t he processor program. once per second, the seven bytes are advanced by one second and checked for an alarm condition. if any of the seven bytes are read at this time, the data outputs should be considered undefined. similarly, all seven bytes should be read between updates to get a consistent time and date. reading some of the bytes before an update and some after, may result in an erroneous output. the update cycle section explains how to accommodate the update cycle in the processor program. update cycle the rtc module executes an update cycle once per second, assu ming one of the proper time bases is in place, and the set bit in register b is clear. the set bit in the ?1? state permits the program to initialize the time and calendar bytes, by stopping an existing update and preventing a new one from occurring. the primary function of the up date cycle is to increment the seconds byte, ch eck for overflow, increment the minutes byte when appropriate, and so forth, up through the m onth and year bytes. the update cycle al so compares each alarm byte with the corresponding time byte, and issues an alarm if a match is present in all three positions. table 18. time, calendar, and alarm data modes address location function decimal range range example (17) binary data mode bcd data mode binary data mode bcd data mode 0x10 seconds 0-59 $00-$3b $00-$59 15 21 0x11 seconds alarm 0-59 $00-$3b $00-$59 15 21 0x12 minutes 0-59 $00-$3b $00-$59 3a 58 0x13 minutes alarm 0-59 $00-$3b $00-$59 3a 58 0x14 hours (12 hour mode) (24 hour mode) 1-12 0-23 $01-$0c(am) / $81-$92(pm) $00-$17 $01-$12(am) / $81-$92(pm) $00-$23 0b 11 0x15 hours alarm (12 hour mode) (24 hour mode) 1-12 0-23 $01-$0c(am) / $81-$92(pm) $00-$17 $01-$12(am) / $81-$92(pm) $00-$23 0b 11 0x16 day of the week sunday=1 1-7 $01-$07 $01-$07 05 05 0x17 date of the month 1-31 $01-$1f $01-$31 0f 15 0x18 month 1-12 $01-$0c $01-$12 02 02 0x19 year 0-99 $00-$63 $00-$99 08 08 notes 17. example: 11:58:21 thursday 15 february 2008 (time is am)
analog integrated circuit device data 46 freescale semiconductor 900844 functional device operation clock generation and real time clock (rtc) two methods of avoiding undefined output during updates are us able by the program. in discussing the two methods, it is assumed that at random points, user programs are able to call a subr outine to obtain the time of day. the first method uses the update-ended interrupt. if enabled, an in terrupt occurs after every update cycle, which indicates tha t over 999 ms are available to read valid time and date information. be fore leaving the interrupt serv ice routine, the irqf bit in register c should be cleared. the second method uses the update-in-progress bit (uip) in regi ster a, to determine if the update cycle is in progress. the uip bit will pulse once per second. statistica lly, the uip bit will indicate that time and date information is unavailable once every 3,640 attempts. after the uip bit go es high, the update cycle begins 244.1 s later. therefore, if a low is read on the uip bit, the user has at least 244.1 s before the time/calendar data will be changed. if a ?1 ? is read in the uip bit, the time/calendar data may not be valid. the user should avoid in terrupt service routines which would cause the time needed to read valid time/calenda r data to exceed 244.1 s. the rtc uses seven synchronous counters to increment the ti me and calendar values. all seven timekeeping registers are clocked by the sa me internal 1.0 hz clock, so updates occur simultaneously, even during rollover. after the counters are incremented, the current time is compar ed to the time-of-day alarm registers 30.5 s later, and if they match, the af bit in register c will be set. the update-cycle begins when the clock and calendar registers are incremented, and ends when the alarm comparison is complete. during this 30.5 s update cycle, the time, calendar, and alarm bytes are fully accessible by the processor program. if the processor reads these locations du ring an update, the transitional output may be undefined. the update in progress (uip) status bit is set 244.1 s before this interval, and is cleared when the update cycle completes. interrupts the rtc includes two separate, fully automatic sources of interrupts to the processor. the alarm interrupt may be programmed to occur at a rate of once per day. the update-ended in terrupt may be used to indicate to the program that an update cycle is completed. the processor program selects which interrupt s, if any, it wishes to receive. two bi ts in register b enable the two interrupts. writing a ?1? to an interrupt-enable bit pe rmits that interrupt to be initiated when the event occurs. a ?0? in the interrupt-e nable bit, prohibits the irqf bit from being asserted due to the interrupt cause. if an interrupt flag is already set when the interrupt becomes enabled, the irqf bit is immediately activated, though the interrupt initiating the event may have occurred much earlier. thus, there are cases where the program should clear such earlie r initiated interrupts before enabling new interrupts. when an interrupt event occurs, a flag bit is set to a ?1? in register c. each of the two interrupt sources have separate flag bits in register c, which are set indepen dent of the state of the corre sponding enable bits in register b. the flag bit may be used with or without enabling the corresponding enable bits. in the software scanned case, the program does not enable the inte rrupt. the interrupt flag bit becomes a status bit, which the software interrogates when it wishes. when the software detects the flag is set, it is an indication to th e software an interru pt event occurred since the bit was last read. however, there is one precaution. the flag bits in register c are cleared (record of the interrupt event is erased) when regist er c is read. double latching is included with register c, so the bits which are set ar e stable throughout the read cycle. all bit s which are high when read by the program are clea red, and new interrup ts (on any bits) are held until after the read cycle. one or two flag bits may be found to be set when register c is used. the program should inspect all utilized flag bits every time register c is read to insure that no interrupts are lost. the second flag bit usage method is with fully enabled interrupt s. when an interrupt flag bit is set and the corresponding interrupt enable bit is also set, the irqf bit is asserted high. irqf is asserted as long as at least one of the two interrupt sources has its flag and enable bits both set. the processor program can determine that the rtc initiated the interrupt by reading register c. a ?1? in bit 7 (irqf bit) indicates that one or more interrupts have been initiated by th e part. the act of reading register c clears all the then active flag bits, plus the irqf bit. when the program finds irqf set, it shou ld look at each of the individual flag bits in the same byte, which have the corresponding interrupt mask bits set and service each interrupt which is set. ag ain, more than one interrupt flag bit may be set. alarm interrupt the three alarm bytes may be used to generate a daily alarm interrupt. when the program inserts an alarm time in the appropriate hours, minutes, and seconds alarm locations, the ala rm interrupt is initiated at the specified time each day, if th e alarm enable bit is high.
analog integrated circuit device data freescale semiconductor 47 900844 functional device operation clock generation and real time clock (rtc) update-ended interrupt if enabled, an in terrupt occurs after every update cycle which indicates that there is over 999 ms available to read valid time and date information. rtc timer calibration by default, the calibration circuit is off and clock accuracy is limited to the performance of the 32.768 khz crystal input. for clock accuracy beyond the limits of the crystal oscillator, a calib ration circuit is included. the processor can use a high-fre quency clock to sample the 32.768 khz output to determine if it is fast or slow, and calculate an adjustment value. the adjustment algorithm has a resolution of 477 nanoseconds-per-second average adjustment, which equates to a time accuracy of approximately 1.2 seconds per month. calibration can be turned on by setting the rtc adj bit of the adj register. a "0" in the adj bit turns calibration off. the si gn bit in the trim register determines if periodic adjust ments are made to speed up or slow down the clock. when calibration is enabled, the trim register is used to grow or shrink the average 1.0 hz clock period. by default, one second is defined as 32,768 periods of the clk32k input pin. each period of the input clock is approximately 30.5 s. by occasionally adding (or subtracting) one extra cycle per second, the average second can be adjusted. if s ign is high (subtract one), occasional seconds will be trimmed to 32,767 cycles. if sign is low (add one), occasional seconds will be trimmed to 32,769 cycles. the 6-bit trimval in the trim register represents the number of seconds to adjus t out of every 64 seconds, and can range from 0-63. for example, trimval = 0x08 then 8 seconds out of every 64 will be adjus ted up or down, according to the sign bit. clock generation and real time cloc k (rtc) registers a nd bits description table 19. rtc date/time configuration register structure and bits description name bits description rtcs (addr 0x10 - r/w - default value: 0x00) sec 6:0 seconds counter register reserved 7 reserved rtcsa (addr 0x11 - r/w - default value: 0x00) secalarm 6:0 seconds alarm setting register reserved 7 reserved rtcm1 (addr 0x12 -r/w - default value: 0x00) min 6:0 minutes counter register reserved 7 reserved rtcma (addr 0x13 - r/w - default value: 0x00) minalarm 6:0 minutes alarm setting register reserved 7 reserved rtch (addr 0x14 - r/w - default value: 0x00) hrs 5:0 hours counter register reserved 6 fixed to 0 pa-h 7 am/pm indication, only active during 12 hr. mode x0 = am x1 = pm
analog integrated circuit device data 48 freescale semiconductor 900844 functional device operation clock generation and real time clock (rtc) rtcha (addr 0x15 - r/w - default value: 0x00) hrsalarm 5:0 hours alarm setting register reserved 6 reserved (fixed to 0) pa-ha 7 am/pm alarm setting, only active during 12 hr. mode x0 = am x1 = pm rtcdw (addr 0x16 - r/w - default value: 0x01) dow 2:0 day of week counter regist er: 1= sunday... 7= saturday reserved 7:3 reserved rtcdm (addr 0x17 - r/w - default value: 0x01) dom 5:0 day of month counter register reserved 7:6 reserved rtcm2 (addr 0x18 - r/w - default value: 0x01) month 4:0 months counter register reserved 6:5 reserved 19/20 7 this bit is not supported always reads 0 (treated as a reserved bit) rtcy (addr 0x19 - r/w - default value: 0x00) year 7:0 year counter register. note: values range from 0 to 99 table 20. rtc control registers structure and bit description name bits description rtca (addr 0x1a - r - default value: 0x20) reserved 6:0 fixed to 010000 uip 7 this is the update in progress (uip) bit used as a status flag x0 = update cycle not in progress x1 = update cycle is in progress or will begin soon rtcb (addr 0x1b - r/w - default value: 0x02) reserved 0 fixed to 0 hrmode 1 hour format control x0 = 12 hour mode x1 = 24 hour mode dm 2 data mode for time and calendar updates x0 = binary-coded-decimal (bcd) x1 = binary reserved 3 fixed to 0 uie 4 update-ended interrupt enable x0 = update-end (uf) bit in register c is not permitted to assert the interrupt request flag (irqf) in register c x1 = update-end (uf) bit in register c is permitted to assert the interrupt request flag (irqf) in register c table 19. rtc date/time configuration register structure and bits description name bits description
analog integrated circuit device data freescale semiconductor 49 900844 functional device operation clock generation and real time clock (rtc) aie 5 alarm interrupt enable x0 = alarm flag (af) bit in register c is not permitted to assert the interrupt request flag (irqf) in register c x1 = alarm flag (af) bit in register c is permitted to assert the interrupt request flag (irqf) in register c reserved 6 fixed to 0 set 7 set mode enable bit for the program to initialize the time and calendar bytes x0 = the update cycle functions normally by advancing the counts once-per-second. x1 = any update cycle in progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the midst of initializing. rtcc (addr 0x1c - r - default value: 0x00) reserved 3:0 reserved uf 4 update-ended interrupt flag. set after each update cycle. x0 = uie bit will not effect irqf state x1 = when uie bit goes high, the irqf bit goes high af 5 alarm interrupt flag. indicates that the current time has matched the alarm time. x0 = aie bit will not effect irqf state x1 = when aie bit goes high, the irqf bit goes high reserved 6 fixed to 0 irqf 7 interrupt request flag. irqf = (af&aie) + (uf&uie) the interrupt request flag (irqf) is set to a ?1? when one or more of the following are true: af = aie = ?1? uf = uie = ?1? x0 = above equation is not true x1 = above equation is true rtcd (addr 0x1d - r - default value: 0x00) reserved 6:0 fixed to 000000 vrt 7 the valid ram and time (vrt) bit indicates the condition of the contents of the rtc time and calendar registers. a "0" appears in the vrt bit when the rtc registers have been reset. the processor program should set the vrt bit after the time and calendar are initialized to indicate t hat the time and calendar are valid. the vrt bit can only be set by reading register d. rtce (addr 0x1e - r/w - default value: 0x05) oscstp 0 oscillator (32 khz) clock stop flag x0 = xtal oscillator x1 = internal rc oscillator bkdet 1 coin cell backup voltage status x0 = no change x1 = coin cell below "low-voltage" threshold when this bit is set to 1, the sw takes corresponding action for a coin cell well below the operating voltage, and clears the bkdet to get ready for the next event. por 2 rtc reset flag x0 = no reset was detected x1 = por occurred scratch 7:3 these bits shall not exert any contro l over the operation of the rtc, and are intended to be used as scratch pad registers by the system controller . their contents are erased on rtcporb. table 20. rtc control registers structure and bit description name bits description
analog integrated circuit device data 50 freescale semiconductor 900844 functional device operation power states and control power states and control overview there are three different power states in the operation of the 900844 pmic: 1. no power state: no input voltage is available at the main supply or the coin cell battery input. 2. active state: the pmic has enough power to supply the system. 3. rtc state: the pmic has enough power to support the rtc operation and the ke ep alive registers, but not enough to pow er the rest of the system. the power state of the pmic at any given time is determined by the conditions of the following inputs: 1. vpwr: this is the main s upply to the system. it must be externally connected to vbat. 2. vbat: this is the main supply voltage sensing input. 3. vcoincell: this is the backup input voltage, typically from a rechargeable coin cell battery. internal supplies power tree figure 17 shows the 900844 internal power tree. adj (addr 0x1f - r/w - default value: 0x00) adj 0 rtc trim enable signal x0 = do not trim x1 = trim reserved 7:1 fixed to 0000000 trim (addr 0x20 - r/w - default value: 0x00) trimval 5:0 6-bit trim control this is a number from 0 to 63 that represents the number of seconds to adjust out of every 64 seconds sign 6 rtc calibration sign bit x0 = add x1 = subtract reserved 7 fixed to 0 clkout (addr 0x21 - r/w - default value: 0x00) m32kclk 0 32 khz clock output mask x0 = 32 khz clock output enabled x1 = 32 khz clock output masked (disabled) reserved 7:1 fixed to 0000000 table 20. rtc control registers structure and bit description name bits description
analog integrated circuit device data freescale semiconductor 51 900844 functional device operation power states and control figure 17. 900844 internal power tree block diagram as part of the turn on sequence, the 900844 enables a set of inte rnal supplies that provide power to the rest of the circuitry: 1. v coreref : this is the main bandgap and reference voltage for all internal circuitries. 2. v core : this is the supply for the internal analog circuitry. 3. v coredig : this is the supply for th e internal digital circuitry. table 21 summarizes the voltage references on the 900844. there is an internal node called the best of supply node (vbo s), which supplies the real time clock and the keep alive registers. this ensures that power to these critical circuits is maintained for maximum life. vbos represents the highest of th e vbat and vcoincell in put voltages. when vcoredig is > 1.2 v, an internal switch is clos ed, and the circuitry that was powered from vbos is now powered from vcoredig. table 21. 900844 internal power supply summary reference parameter target vcoreref (bandgap & regulators reference) output voltage 1.2 v bypass capacitor 100 nf typ. vcoredig (digital core supply) output voltage 1.5 v bypass capacitor 2.2 f typ. vcore (analog core supply) output voltage 2.775 v bypass capacitor 2.2 f typ. v bat v coincell v bos vcorertc keep alive bandgap 1.2v clock rc/xtal keep alive registers 1.2v 0.9v v pwr vcoreref vcoredig vcore uvdet en en en en closed when vcoredig > 1.2v 1.5v digital supply 1.2v reference supply 2.775v analog supply active state rtc state
analog integrated circuit device data 52 freescale semiconductor 900844 functional device operation power states and control power states figure 18 shows the flow of power, the different power states, and the conditions necessa ry to transition between the different states. this diagram serves as the basis for t he description in the remainder of this section. figure 18. 900844 power states no pwr v bat < v batoff v coin < v coinoff rtc state * rtc is powered * time of day is kept * keep alive registers are powered * all other circuits off v bat > v batoff ramp up bat operation * v pwr = v bat * v pwr > v pwruvr batdet int= 1 * internal supplies/references on * logic is reset * initial power sequence performed * spi ready * scu interrupted v bat > v lowbat active state scu control (bat operation) * v pwr = v bat rdstate = 0x00 * scu takes control * scu sets the system v bat < v lowbat & v coin > v coinoff v bat < v batoff & v coin < v coinoff v bat < v batoff & v coin < v coinoff v bat < v trkl & v coin > v coinoff v pwr < v pwruvf & v coin > v coinoff v bat > v lowbat
analog integrated circuit device data freescale semiconductor 53 900844 functional device operation power states and control no power state in this state, every source of power has been removed or is fully depleted: ?v bat < v batoff : the input voltage is under the cutoff threshold, indi cating that the main supply has been removed, or has been isolated by its own protection circuitry, and ?v coin < v coinoff : the coin cell backup battery has been removed or has been isolated by the 900844 coin cell discharge prevention circuitry (see coin cell battery backup/charger ) the 900844 has lost any source of power to maintain the rtc and its keep alive registers, and all the internal circuits power down and time of day cannot be kept. rtc state in this state, the 900844 has limited power. the vbos is available and powers the rtc and the keep alive registers. however, the system does not have enough power to enter the active state: ?v coin > coinoff: the backup battery is above the coin cell disconnect threshold. ?v pwr < v pwruvf : the system voltage is less than the under-voltage falling threshold. during this mode, all voltage regulators are off and cannot be powered. the rtc is operating ( real time clock (rtc) ), and the time of day and all keep alive registers are maintained. active state in this state, the 900844 inter nal circuits are fully powered: ?v pwr > v pwruvr : the system voltage, v pwr , is available and valid, and ?v bat > v lowbat : the main input voltage is above a low battery condition. all features of the 900844 are either operating or can be enabled, which is under the control of the system control unit (sc u) within the platform controller hub (pch). power state transitions when power is applied to the 900844 for the first time, it goes from the no power state into th e active state, with a brief transition through the rtc state. the rtc a nd the keep alive registers are powered, and the time of day is initialized to a fac tory set value (see real time clock (rtc) ). when v pwr crosses the under-voltage rising detection threshold (v pwruvr ), the internal supplies power on, the logic is reset, the initial power sequence is performed, spi communicat ion is enabled, and an interrupt to the platform controller hub i s generated. the pmic enters the active state and the system is under control of the scu. if v pwr crosses the under-voltage falling detection threshold (v pwruvf ), and at least one of the vbos supplies (v coin or v bat ) is still valid, the 900844 enters the rtc state. only the rtc is operating and the rtc and keep al ive registers are maintained. if the 900844 is in the rtc state, full operation is obtained when the voltage at vpwr crosses again the under-voltage risin g detection threshold (vpwruvr). turn on events a turn on event occurs when a valid input voltage is present at vbat (v bat > v lowbat ), and the system voltage goes above the under-voltage rising threshold (v pwr > v pwruvr ). otherwise, the 900844 is in the rtc or no power state. when a turn on event occurs, the batdet interrupt bit is set. reference interrupt controller for more information on the different system interrupts.
analog integrated circuit device data 54 freescale semiconductor 900844 functional device operation power states and control figure 19. 900844 initial power up sequence initial power up sequence figure 19 shows the 900844 initial power up sequence: 1. a valid system voltage is applied 2. v pwr ramps up 3. the 900844 internal circuits are powered 4. the 900844 turns on a minimal set of voltage rails as outlined in figure 19 5. spi communication is ready 6. pmicint pin is asserted 7. the system controller un it (scu) reads the 900844 interrupt flag register (over spi) to see why the 900844 interrupted the platform controller hub. 8. the scu decides wh ether to boot the rest of the system, or just run scu code to manage various functions. 9. if the scu decides to power up system, then cpu (central processing unit) drives vnn vid, viden[1:0] = 10 to the 900844 and bsel to the platform controller hub. 10. the 900844 drives cpu selected voltage for vnn 11. there will be no explicit signaling from the 900844 that indicates that the vnn ramp has been complete. 12. viden[1:0] is driven to 00 to avoid it switching from 10 to 01 directly. 13. the cpu drives the vcc boot vid on the vid pins. the viden[1:0] = 1 enables, only after hpll has locked. 14. x86 instruction executions starts. vpwr vccpaoac battery or brick inserted table 22. 900844 initial power up timing parameter description min typ max t 1 pmic internal regulator ramp-up - - 100 s t 2 v15 turn on delay 18 ms - 550 ms t 3 v15 ramp-up - - 10 s t 4 vaon/vccpaoac turn on delay 0 s - 31 s t 5 vaon/vccpaoac ramp-up - - 700 s
analog integrated circuit device data freescale semiconductor 55 900844 functional device operation power states and control turn off events the following conditions cause the 900844 to power off the syst em, including the scu, but the 900844 internal circuitry and logic are still active: ? pwrbtn pressed for more than 5 seconds. see power button functionality (pwrbtn) . ? the 900844 junction temperature is above the thermal shutdown threshold. see thermal management for more details. ? a thermtripb assertion. see thermtripb pin for more details. power button functionality (pwrbtn) the power button is pulled up internally through a 132 k resistor to the v coredig output voltage node. see figure 20 for more details. figure 20. pwrbtn circuit diagram figure 21 describes the functionality of the pwrbtn . figure 21. pwrbtn function flow diagram t 6 v21 turn on delay 0 s - 31 s t 7 v21 ramp-up - - 100 s t 8 vpmic turn on delay 0 s - 31 s t 9 vpmic ramp-up - - 700 s t 10 pwrgd delay 70 ms - 90 ms t 11 reset delay 1.0 s - 31 s t 12 pmicint delay 31 s - 124 s table 22. 900844 initial power up timing parameter description min typ max v coredig pwrbtn 132k
analog integrated circuit device data 56 freescale semiconductor 900844 functional device operation power supplies detection thresholds table 23 summarizes the various detection thre sholds between the different states: power supplies power map figure 22 is a power map of freescale?s power management solution for ultra-mobile platforms for netbooks/ and tablet pc: figure 22. 900844 power map table 23. power states detection thresholds characteristic symbol min typ max unit input voltage cutoff threshold v batoff 2.2 - 2.4 v coin cell disconnect threshold v coinoff 1.8 - 2.0 v low input voltage threshold v lowbat 3.2 - - v valid input voltage threshold v trkl - 3.0 - v vpwr rising under-voltage threshold v pwruvr - 3.1 - v vpwr falling under-voltage threshold v pwruvf - 2.55 - v vcc (0.65v-1.2v) max current 3500ma vnn (0.65v-1.2v) max current 1600ma vddq (1.5v) max current 1000ma vbg (1.25v) max current 2ma vcca (1.5v) max current 75ma v21 (2.1v) max current 1035ma vcc180 (1.8v) max current 390ma vpnl18 (1.8v) max current 225ma vccpddr (1.05v) max current 60ma vmm (1.2v) max current 3ma vccpaoac (1.05v) max current 40ma vccp (1.05v) max current 418ma vaon (1.2v) max current 250ma v15 (1.5v) max current 1185.8ma vimg25 (2.5v) max current 80ma vpmic (1.8v) max current 50ma vimg28 (2.8v) max current 225ma vpnl33 (3.3v) max current 100ma vsdio 1.8v - ldo 207.5ma vymxyfi18 yfi - 1.8v 200ma dc/dc ldo ldo ldo dc/dc dc/dc dc/dc 3.3v - switch 207.5ma ymx - 1.8v 200ma ldo ldo ldo ldo ldo ldo ldo ldo/switch ldo ldo switch ldo dc/dc input power power path manager 3.3 v pvin vpwr adapter always on or battery
analog integrated circuit device data freescale semiconductor 57 900844 functional device operation power supplies dc/dc power supplies freescale?s power management solution for the ultra-mobile platform for netbook/tablets and slates, includes 5 dc/dc switching regulators integrated on the 900844 pmic. the five dc-dc regulators are bu ck converters, and these can be set to work in the following operation modes: buck converters operation modes selections (vcc, vnn, vddq, v21, v15) ? off - the regulator is switched o ff and the output voltage is discharged. ? pfm - the regulator is switched on and set to pfm mode opera tion. in this mode, the regulator is always running in pfm mode. useful at light loads for optimized efficiency. ? automatic pulse skip - the regulator is switched on and set to automatic pulse skipping. in this mode, the regulator moves automatically between pulse skipping and full pwm mode depending on load conditions. ? pwm - the regulator is switched on and set to pwm mode. in this mode, the regulator is always in full pwm mode operation regardless of load conditions. ? test/trim - this is not a functional mode, thus requiring certain steps to prevent un intentional activation of this mode. duri ng this mode, the device performs measurements and trimming. dc-dc power supply summary table table 24 provides a summary of all dc/dc regulators on the 900844. note that all of the dc/dc regulators specify an ex tended input voltage range beyond the 3.0 to 4.4 v applications range. below this, extended range functionality is maintain ed, but parametric performance could be compromised. vcc this is a vid controlled single-phase 1.0 mhz 2-switch synchronous buck pwm voltage mode control dc/dc regulator, designed to power high performance cpus. vcc uses ex ternal mosfets, p-ch high side and n-ch low side. vcc includes support for vid active voltage positioning requir ements. a 7-bit dac reads the vi d input signals and sets the output voltage level. the output voltage has a range of 0.3 to 1.2 v. the programming step size is 12.5 mv. values will be read in real time and will be stored in internal re gisters not accessible to the system host . reference viden[1:0] & vid[6:0] pins for more details. the same vid input signals are shared between vcc and vnn, where a latch signal for each regulator decides which regulator takes control of the vid input signals. the dac value represents the output volta ge value. the output voltage node is connect ed directly to the inverting input of the error amplifier that uses the dac output as its reference, unity gain configuration. using this configuration with internal compensation eliminates the need for the feedback and compen sation network, which saves board space and cost. the dac/ output voltage slew rate is internally set 25 mv/s to minimize transient currents and audible noise. table 24. 900844 dc-dc power supplies. regulator typ. voltage max continuous current description vcc 0.3 - 1.2 v 3.5 a 1.0 mhz synchronous buck converter with external switching mosfets. internally compensated. vid is controlled using a shared 7-bit bus for voltage coding and 2 vid enable signals for vcc or vnn selection. vnn 0.3 - 1.2 v 1.6 a 1.0 mhz synchronous buck converter with external switching mosfets. internally compensated. vid is controlled using a shared 7-bit bus for voltage coding and 2 vid enable signals for vcc or vnn selection. vddq 1.8 v/1.5 v 1.3 a 4.0 mhz fully integrated 2-switch synchronous buck pwm voltage mode control dc/dc regulator. v21 2.1 v 1.0 a 4.0 mhz fully integrated 2-switch synchronous buck pwm voltage mode control dc/dc regulator. v15 1.5 v 1.5 a 4.0 mhz fully integrated 2-switch synchronous buck pwm voltage mode control dc/dc regulator.
analog integrated circuit device data 58 freescale semiconductor 900844 functional device operation power supplies the switcher can operate in di fferent modes depending on the load conditions . these modes can be set through the spi and include a pfm mode, an automatic pulse skipping mode, and a pwm mode. the above selection is optimized to maximum battery life based on load conditions. vcc will be discharged every time the regulator is shutting down. the output current will be sensed using an intelligent impl ementation of the dcr sensing me thod using internal sensing circuitry, which eliminates the need for an external rc filter network in parallel with the output inductor and its winding res istance. dcr sensing theory is that if the impedance of t he two filters are matching by insuring that r*c = l/r w , then the voltage across the capacitor is equal to the value of the voltage across the winding resistance r w , v cap = i load *r w . based on this, the voltage across the capacitor is measured, and with a known r w value, the load current can be extracted. the measured current value will be digitized by the adc and stored in a register for the processor to access. the method used on the 900844 measures the voltage across r w in a similar fashion, while using internal sensing circuitry. the sensed output current value will also be used for over-curr ent protection. if an over-curre nt condition is detected, the regulator will limit the current through cyc le by cycle operation, and alert the system through the vccfault signal, which will in turn assert the vrfault interrupt signal. figure 23. vcc detailed internal block diagram main features ? uses the v pwr rail as its power supply ? it is used to provide power to the cpu core. ? single-phase solution with integrated drivers and external mosfets ? vid controlled for dynamic voltage scaling requirements of high performance processors ?1.0 mhz switching frequency ? high efficiency operating modes depending on load conditions ? output can be discharged through the low side switch. ? loss-less output current sensin g with over-current protection ? uses internal compensation ? gate drive circuits are supplied directly from vpwr efficiency curves the efficiency curves in figure 24 are calculated under pwm mode, based on the recommended external component values and typical output voltage of 1.2 v. 3.0 v vpwr 4.4 v. gndrefvcc driver controller ea z1 z2 internal compensation voutfbcc v pwr c occ c incc l cc v cc hsccgt lsccgt pgndcc current sense amp cspcc i cc pvincc swfbcc spi interface ctlvcc aoacctlvcc vccfault v ref dac vid6 vid5 vid4 vid3 vid2 vid1 vid0 m hscc m lscc viden0 viden1
analog integrated circuit device data freescale semiconductor 59 900844 functional device operation power supplies figure 24. vcc efficiency curve vcc status/control registers and bits description reference the register ma p for read/write conditions and defaul t state for each of these registers. vnn this is a vid controlled single-phase 1.0 mhz 2-switch synchronous buck pwm voltage mode control dc/dc regulator, designed to power high performance cpus. vnn uses ex ternal mosfets, p-ch high side and n-ch low side. vnn includes support for vid active voltage positioning requir ements. a 7-bit dac reads the vi d input signals and sets the output voltage level. the output voltage has a range of 0.3 to 1.2 v. the programming step size is 12.5 mv. values will be read in real time and will be stored in internal re gisters not accessible to the system host . reference viden[1:0] & vid[6:0] pins . table 25. vcc status registers structure and bits description name bits description vcccnt (addr 0x35 - r/w - default value: 0x24) ctlvcc 2:0 vcc state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = pfm x6 = automatic pulse skipping x7 = pwm aoacctlvcc 5:3 vcc state control during aoac exit (when exit pin is exitst by pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = pfm x6 = automatic pulse skipping x7 = pwm reserved 7:6 reserved vcclatch (addr 0x32 - r/w - default value: 0x7f) vidvcc 6:0 vid vcc control through spi. signal codes are identical to the vid signal codes. reference figures 15 for more details dvp1vrd 7 vcc register override enable bit. x0 = vcc vid control follows the external pins x1 = vcc vid control follows the vidvcc control register bits 4
analog integrated circuit device data 60 freescale semiconductor 900844 functional device operation power supplies the same vid input signals are shared between vnn and vnn, where a latch signal for each regulator decides which regulator takes control of the vid input signals. the dac value represents the output volta ge value. the output voltage node is connect ed directly to the inverting input of the error amplifier that uses the dac output as its reference, unity gain configuration. using this configuration with internal compensation eliminates the need for the feedback and compen sation network, which saves board space and cost. the dac/ output voltage slew rate is internally set 25 mv/s to minimize transient currents and audible noise. the switcher can operate in di fferent modes depending on the load conditions . these modes can be set through the spi and include a pfm mode, an automatic pulse skipping mode, and a pw m mode. the previous selection is optimized to maximum battery life based on load conditions. vnn will be discharged every time the regulator is shutting down. the output current is sense in the same way as it is done on vcc regulator. (see vcc ) the sensed output current value will also be used for over-curr ent protection. if an over-curre nt condition is detected, the regulator will limit the current through cy cle by cycle operation and alert the system through the vnnfault signal, which will in turn assert the vrfault interrupt signal. figure 25. vnn detailed internal block diagram main features ? uses the v pwr rail as its power supply ? it is used to provide po wer to the graphics core. ? single-phase solution with integrated drivers and external mosfets ? vid controlled for dynamic voltage scaling requirements of high performance processors ?1.0 mhz switching frequency ? high efficiency operating modes depending on load conditions ? output can be discharged through the low side switch. ? loss-less output current sensin g with over-current protection ? uses internal compensation ? gate drive circuits are supplied directly from vpwr efficiency curves figure 26 efficiency curves are calculated under pwm mode based on the recommended external component values and typical output voltage of 1.2 v. 3.0 v vpwr 4.4 v. driver controller ea z1 z2 internal compensation voutfbnn v pwr c onn c incc l nn v nn hsnngt lsnngt pgndnn cspnn pvinnn swfbnn spi interface ctlvnn aoacctlvnn vnnfault v ref dac vid6 vid5 vid4 vid3 vid2 vid1 vid0 m hsnn m lsnn current sense amp i nn viden0 viden1
analog integrated circuit device data freescale semiconductor 61 900844 functional device operation power supplies figure 26. vnn efficiency curve vnn status/control registers and bits description reference the register ma p for read/write conditions and defaul t state for each of these registers vddq this is a 4.0 mhz fully integrated 2-switch synchronous buck pwm voltage mode control dc/dc regulator. the switcher can operate in di fferent modes depending on the load conditions . these modes can be set through the spi and include a pfm mode, an automatic pulse skipping mode, and a pwm mode. vddq will be discharged every time the regulator is shutting down. table 26. vnn status and control regist ers structure and bits description name bits description vnncnt (addr 0x36 - r/w - default value: 0x04) ctlvnn 2:0 vnn state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = pfm x6 = automatic pulse skipping x7 = pwm aoacctlvnn 5:3 vnn state control during aoac exit (when the exit pin is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = pfm x6 = automatic pulse skipping x7 = pwm reserved 7:6 reserved vnnlatch (addr 0x33 - r/w - default value: 0x7f) vidvnn 6:0 vid vnn control through spi. signal codes are id entical to the vid signal codes. reference figure 15 for more details dvp1vrd 7 vnn register override enable bit. x0 = vnn vid control follows the external pins x1 = vnn vid control follows the vidvnn control register bits 4
analog integrated circuit device data 62 freescale semiconductor 900844 functional device operation power supplies the output current is measured internally, di gitized by the adc, and stored in a regi ster for the processor to access. the peak current is sensed internally for over-curr ent protection purposes. if an over-current condition is detected, the regulator will limit the current through a cycle by cycl e operation and alert the system through the vddqfault signal, wh ich will in turn assert the vrfault interrupt signal. vddq is originally prepared to provide 1.8 v by connecting vddq output voltage directly to fbddq node, refer to figure 27 . to provide flexibility, vddq can also be set to 1.5 v by adding a resistor divider from vddq output to the fbddq using vcore as voltage reference, refer to figure 28 . the following are the recommended resistor values for the feedback divider: ? rfbddq15_1 = 680 ? rfbddq15_2 = 2.21 k figure 27. vddq detailed inte rnal block diagram (vddq at 1.8 v) figure 28. vddq detailed inte rnal block diagram (vddq at 1.5 v) main features ? uses the v pwr rail as its power supply ? it is used as a pre-regulator to many ldo rails, for enhanced ef ficiency and reduced thermal dissipation. it also supplies pow er to rails in the cpu (central processing un it), platform controller hub, and the platform ? uses integrated mosfets ?4.0 mhz switching frequency ? high efficiency operating modes depending on load conditions ? output can be discharged through the low side switch. ? peak current sensing with over-current protection driver controller ea v ref z1 z2 internal com pensation pvinddq swddq fbddq i sen se 5 v pwr c oddq c inddq l ddq spi interface pgndddq v ddq ctlvddq aoacctlvddq vddqfault driver controller ea v ref z1 z2 internal compensation pvinddq swddq fbddq i sense5 v pwr c oddq c inddq l ddq spi interface pgndddq v ddq ctlvddq aoacctlvddq vddqfault vcore rfbddq15_2 rfbddq15_1
analog integrated circuit device data freescale semiconductor 63 900844 functional device operation power supplies ? uses internal compensation ? gate drive circuits are supplied directly from vpwr efficiency curves figure 29 efficiency curves are calculated under pwm mode, bas ed on the recommended external component values and typical output voltage of 1.8 v. 3.0 v vpwr 4.4 v. figure 29. vddq efficiency curves vddq status/control regist ers and bits description reference the register ma p for read/write conditions and defaul t state for each of these registers. v21 this is a 4.0 mhz fully integrated 2-switch synchronous bu ck pwm voltage-mode control dc/dc regulator. the switcher can operate in di fferent modes depending on the load conditions . these modes can be set through the spi and include a pfm mode, an automatic pulse skipping mode, and a pw m mode. the previous selection is optimized to maximum battery life based on load conditions. v21 will be discharged every time the regulator is shutting down. table 27. vddq status and control regi ster structure an d bits description name bits description vddqcnt (addr 0x37 - r/w - default value: 0x04) ctlvddq 2:0 vddq state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = pfm x6 = automatic pulse skipping x7 = pwm aoacctlvddq 5:3 vddq state control during aoac exit (when exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = pfm x6 = automatic pulse skipping x7 = pwm reserved 7:6 reserved 4
analog integrated circuit device data 64 freescale semiconductor 900844 functional device operation power supplies the output current is measured internally, digitized by the a dc, and stored in a register for the processor to access. the peak current is sensed internally for over-current protection purposes. if an over-current conditi on is detected, the regulator will limit the current through cycle by cycle oper ation and alert the syst em through the v21fau lt signal, which will in turn assert the vrfault interrupt signal. figure 30. v21 detailed internal block diagram main features ? uses the v pwr rail as its power supply ? it is used as a pre-regulator to many ldo rails, for enhanced efficiency and reduced thermal dissipation. ? uses integrated mosfets ?4.0 mhz switching frequency ? high efficiency operating modes depending on load conditions ? output can be discharged through the low side switch. ? peak current sensing with over-current protection ? uses internal compensation ? gate drive circuits are supplied directly from vpwr efficiency curves figure 31 efficiency curves are calculated under pwm mode, bas ed on the recommended external component values and typical output voltage of 2.1 v. 3.0 v v pw 4.4 v. driver contr oller ea v ref z1 z2 internal com pensation pvin 21 sw 21 fb21 i sen se 5 v pw r c o21 c in 2 1 l 21 spi interface pgnd21 v 21 ctlv21 aoacctlv 21 v21 fault
analog integrated circuit device data freescale semiconductor 65 900844 functional device operation power supplies figure 31. v21 efficiency waveforms 4
analog integrated circuit device data 66 freescale semiconductor 900844 functional device operation power supplies v21 status/control regist ers and bits description reference the register ma p for read/write conditions and defaul t state for each of these registers. v15 this is a 4.0 mhz fully integrated 2-switch synchronous bu ck pwm voltage-mode control dc/dc regulator. the switcher can operate in di fferent modes depending on the load conditions . these modes can be set through the spi and include a pfm mode, an automatic pulse skipping mode, and a pwm mode. the above selection is optimized to maximum battery life based on load conditions. v15 will be discharged every time the regulator is shutting down. the output current is measured internally, digitized by the a dc, and stored in a register for the processor to access. the peak current is sensed internally for over-current protection purposes. if an over-current conditi on is detected, the regulator will limit the current through cycle by cycle oper ation and alert the syst em through the v15fau lt signal, which will in turn assert the vrfault interrupt signal. figure 32. v15 detailed internal block diagram main features ? uses the v pwr rail as its power supply ? it is used as a pre-regulator to many ldo rails, for enhanced ef ficiency and reduced thermal dissipation. it also supplies pow er to rails in the platform controller hub ? uses integrated mosfets table 28. v21 status/control registers structure and bits description name bits description v21cnt (addr 0x38 - r/w - default value: 0x07) ctlv21 2:0 v21 state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = pfm x6 = automatic pulse skipping x7 = pwm aoacctlv21 5:3 v21 state control during aoac exit (when exitstby pin is as serted). these bits will be initialized by the system spi controller after power up x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = pfm x6 = automatic pulse skipping x7 = pwm reserved 7:6 reserved driver controller ea v ref z1 z2 inter nal compensation pvin 15 sw 15 fb15 i sen se 5 v pw r c o15 c in 1 5 l 15 spi interface pgnd15 v 15 ctlv15 aoacctlv 15 v15 fault selv 15
analog integrated circuit device data freescale semiconductor 67 900844 functional device operation power supplies ?4.0 mhz switching frequency ? high efficiency operating modes depending on load conditions ? output can be discharged through the low side switch. ? peak current sensing with over-current protection ? uses internal compensation ? gate drive circuits are supplied directly from vpwr efficiency curves figure 33 efficiency curves are calculated under pwm mode, bas ed on the recommended external component values and typical output voltage of 1.5 v. 3.0 v v pwr 4.4 v. figure 33. v15 efficiency curves v15 status/control regist ers and bits description reference the register ma p for read/write conditions and defaul t state for each of these registers. table 29. v15cnt register structure and bits description name bits description v15cnt (addr 0x39 - r/w - default value: 0x07) ctlv15 2:0 v15 state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = pfm x6 = automatic pulse skipping x7 = pwm aoacctlv15 5:3 v15 state control during aoac exit (when exitstby pin is asse rted). these bits will be initialized by the system spi controller after power up x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = pfm x6 = automatic pulse skipping x7 = pwm selv15 7:6 v15 output voltage selection (fsl usage only) x0 = 1.5 v x1 = 1.6 v x2, x3 = reserved 4
analog integrated circuit device data 68 freescale semiconductor 900844 functional device operation power supplies ldo power supplies freescale?s power management solution for the ultra-mobile platform for netbooks, tablets, and slates includes 14 ldo regulators, all of which are housed in the 900844 pmic. ldo operation modes selections ? off - the regulator is switched off ? active - the regulator is switched on and the output is at the programmed level. the maximum load current is allowed. ? low power - the regulator is switched on and the outputs is at the programmed level. the load current is limited. ? test/trim - this is not a functional mode, thus requiring certain steps to prevent un intentional activation of this mode. duri ng this mode, the device performs measurements and trimming. all ldos are able to work in a low power mode, in which th e bias current is reduced. th e output drive capability and performance are limited in this mode. this mode occurs automa tically when the load current decreases below the low power mode limit, except on vbg and vmm, in which this mode can on ly be set through spi programming. all other ldos can set the low power mode through spi programming. note: if low power mode is set through the spi at a load curr ent higher than the maximum al lowed, the performance of the ldo is not guaranteed. table 30 is a summary of ldo characteristics table 30. 900844 ldo power supplies summary regulator typ. voltage max continuous current description vbg 1.25 v 2.0 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vcca 1.5 v 150 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vcc180 1.8 v 390 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vpnl18 1.8 v 225 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vpmic 1.8 v 50 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vymxyfi18 1.8 v 200 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vccpaoac 1.05 v 155 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vccpddr 1.05 v 60 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vaon 1.2 v 250 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vmm 1.2 v 5.0 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vccp 1.05 v 445 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vimg25 2.5 v 80 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vimg28 1.5 - 2.9 v 225 ma low dropout (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr with a low quiesc ent current and fast transient response. vsdio 1.8 or 3.3 v 215 ma vsdio is a combo low dropout (ldo) and power switch. it uses an external p-ch pass fet, applicable only in power switch mode. vsdio serves as an ldo when its output voltage is set to 1.8 v, and as a switch when its output voltage is set to 3.3 v.
analog integrated circuit device data freescale semiconductor 69 900844 functional device operation power supplies vbg vbg is a low drop-out (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient re sponse. vbg is actively discharged during shutdown. vbg shares an input voltage pin (pvin1 p8) and a reference ground pin (gnd1p8) wi th the vcca regulator, yet each has independent control. pvin1p8 is supplied from th e vddq voltage if vddq output is set to 1.8 v, otherwise connect to v21 when vddq is set to 1.5 v. figure 34. vbg detailed internal block diagram main features ? uses vddq or v21 as the main power supply ?2.0 ma maximum continuous output current ? optimized for a 1.0 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vbg status/control regist ers and bits description reference the register ma p for read/write conditions and defaul t state for each of these registers. vcca vcca is a low drop-out (ldo) fully integr ated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient response. vcca is actively discharged during shutdown. table 31. vbg control register st ructure and bits description name bits description vlbgcnt (addr 0x3f - r/w - default value: 0 x24) ctlvbg 2:0 vbg state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvbg 5:3 vbg state control during aoac exit (when the exit pin is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ controller v obg v ddq pvin 1p 8 voutbg output monitor i obg spi interface c in 1 p8 c obg v obg ctlvbg aoacctlvbg vbgfault v ref gnd1 p8 discharge
analog integrated circuit device data 70 freescale semiconductor 900844 functional device operation power supplies vcca shares an input voltage pin (pvin1p8) and a refere nce ground pin (gnd1p8) with vbg regulator, yet each has independent control. pvin1p8 is supplied from th e vddq voltage if vddq output is set to 1.8 v, otherwise connect to v21 when vddq is set to 1.5 v. figure 35. vcca detailed internal block diagram main features ? uses vddq or v21 as the main power supply ? 150 ma maximum continuous output current ? optimized for a 2.2 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vcc180 vcc180 is a low drop-out (ldo) fully integrated regulator with a p-ch pass fet. it is high perfo rmance, low noise, and high psrr, with a low quiescent current and fast transient response. vcc180 is actively discharged during shutdown. vcc180 shares an input voltage pin (pvin2p1) and a refe rence ground pin (gnd2p1) with vpnl18 and vpmic regulators, yet each has independent control. pvin2p1 is supplied from the v21 voltage. the output current for vcc180 is measured and reported through the adc. reference adc subsystem for more information. table 32. vcca control register structure and bits description name bits description vccacnt (addr 0x40 - r/w - default value: 0x3c) ctlvcca 2:0 vcca state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvcca 5:3 vcca state control during aoac exit (w hen the exit pin is exitstby pin is asse rted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ controller v occa pvin 1p 8 (shared with vbg) voutcca output m onitor i occa spi interface c occa v occa ctlvcca aoacctlvcca vccafault v ref discharge fbcca gnd1p8 (shared with vbg)
analog integrated circuit device data freescale semiconductor 71 900844 functional device operation power supplies figure 36. vcc180 detailed internal block diagram main features ? uses v21 as the main power supply ? 390 ma maximum continuous output current ? optimized for a 2.2 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vpnl18 vpnl18 is a low drop-out (ldo) fully integrated regulator wit h a p-ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient response. vpnl18 is actively discharged during shutdown. vpnl18 shares an input voltage pin (pvin2p1) and a refere nce ground pin (gnd2p1) with vcc180 and vpmic regulators, yet each has independent control. pvin2 p1 is supplied from the v21 voltage. table 33. vcc180cnt register st ructure and bits description name bits description vcc180cnt (addr 0x43 - r/w - 0x3c) ctlvcc180 2:0 vcc180 state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvcc180 5:3 vcc180 state control during aoac exit (when the exit pi n is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ controller v occ180 v 21 pvin 2p1 voutcc180 output monitor i occ180 spi interface c in 2 p1 c occ180 v occ180 ctlvcc180 aoacctlvcc 180 vcc180 fault v ref gnd2p1 dischar ge
analog integrated circuit device data 72 freescale semiconductor 900844 functional device operation power supplies figure 37. vpnl18 detailed internal block diagram main features ? uses v21 as the main power supply ? 225 ma maximum continuous output current ? optimized for a 2.2 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vpmic vpmic is a low drop-out (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient re sponse. vpmic is actively discharged during shutdown. vpmic shares an input voltage pin (pvin2p1) and a refer ence ground pin (gnd2p1) with vcc180 and vpnl18 regulators, yet each has independent control. pvin2 p1 is supplied from the v21 voltage. table 34. vpnl18 control register structure and bits description name bits description vpanel18cnt (addr 0x46 - r/w - default value: 0x24) ctlvpanel18 2:0 vpnl18 state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvpanel18 5:3 vpnl18 state control during aoac exit (when the exit pi n is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ controller v opnl18 voutpnl 18 output monitor i opnl18 spi interface c opnl18 v opnl18 ctlvpnl18 aoacctlvpnl 18 vpnl 18 fault v ref discharge pvin 2p 1 (shared with vcc180 and vpmic) gnd2p 1 (shared with vcc180 and vpmic)
analog integrated circuit device data freescale semiconductor 73 900844 functional device operation power supplies figure 38. vpmic detailed internal block diagram main features ? uses v21 as the main power supply ? 100 ma maximum continuous output current ? optimized for a 2.2 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vymxyfi18 vymxyfi18 is a low drop-out (ldo) fully in tegrated regulator with a p- ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient response. vymxyfi18 is actively discharged during shutdown. vymxyfi18 can be supplied by either the v 21 output voltage (v21) or directly from the vpwr node. using v21 as the input voltage supply offers enhanced thermal performance and hi gher efficiency. using the vpwr node can offer enhanced performance against noise coupling from an output of a dc/dc r egulator. users are encouraged to take the resulting thermal dissipation in account when supplying vymxyfi18 directly from vpwr. for more information about package thermal capabilities, reference thermal management . table 35. vpmic register structure and bits description name bits description vpmiccnt (addr 0x41 - r/w - default value: 0x07) ctlvpmic 2:0 vpmic state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvpmic 5:3 vpmic state control during aoac exit (when the exit pin is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ controller v opmic voutpmic output monitor i opmic spi interface c opmic v opmic ctlvpmic aoacctlvpmic vpmicfault v ref discharge pvin 2p 1 (shared with vcc180 and vpnl18) gnd2p 1 (shared with vcc180 and vpnl18)
analog integrated circuit device data 74 freescale semiconductor 900844 functional device operation power supplies figure 39. vymxyfi18 detailed internal block diagram main features ? uses v21 or vpwr as the main power supply ? 200 ma maximum continuous output current ? optimized for a 2.2 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vccpaoac vccpaoac is a low drop-out (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient re sponse. vccpaoac is actively discharged during shutdown. vccpaoac shares an input voltage pin (pvin1p5) and a reference ground pin (gnd1p5) with vccpddr, vaon, vmm, and the vccp regulator. each has independent cont rol. pvin1p5 is supplied from the v15 voltage. table 36. vymxyfi18 register structure and bits description name bits description vwymxarfcnt (addr 0x4c - r/w - default value: 0x24) ctlvwymxarf 2:0 vymxyfi18 state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvwymxarf 5:3 vymxyfi18 state control during aoac exit (when the exit pin is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ contr oller v oymxyfi 18 v 21 or v pw r pvinymxyfi 18 voutymxyfi 18 output monitor i oymxyfi 1 8 spi interface c in ymxyfi 1 8 c o ymxyfi 1 8 v oymxyfi 1 8 ctlvymxyfi 18 aoacctlvymxyfi 18 vymxyfi 18 fault v ref gndcomms1 discharge gndcomms2 two gnd pins shared between vymxyfi18, vymxyfi , and vymxgps
analog integrated circuit device data freescale semiconductor 75 900844 functional device operation power supplies figure 40. vccpaoac detailed internal block diagram main features ? uses v15 as the main power supply. ? 155 ma maximum continuous output current ? optimized for a 2.2 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vccpddr vccpddr is a low drop-out (ldo) fully inte grated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient re sponse. vccpddr is actively discharged during shutdown. vccpddr shares an input voltage pin (pvin1p5) and a refer ence ground pin (gnd1p5) with the vccpaoac, vaon, vmm, and vccp regulators, yet each has independent cont rol. pvin1p5 is supplied from the v15 voltage. table 37. vccpaoaccnt register structure and bits description name bits description vccpaoaccnt (addr 0x3d - r/w - default value: 0x07) ctlvccpaoac 2:0 vccpaoac state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvccpaoac 5:3 vccpaoac state control during aoac exit (when the ex it pin is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ controller v oc c paoac v 15 pvin1 p5 voutccpaoac output monitor i oc c paoac spi interface c in 1 p 5 c oc c paoac v oc c paoac ctlvccpaoac aoacctlvccpaoac vccpaoacfault v ref gnd1p5 discharge
analog integrated circuit device data 76 freescale semiconductor 900844 functional device operation power supplies figure 41. vccpddr detailed internal block diagram main features ? uses v15 as the main power supply ?60 ma maximum continuous output current ? optimized for a 1.0 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vaon vaon is a low drop-out (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient response. vaon is actively discharged during shutdown. vaon shares an input voltage pin (pvin1p5) and a refere nce ground pin (gnd1p5) with the vccpaoac, vccpddr, vmm, and vccp regulators, yet each has independent cont rol. pvin1p5 is supplied from the v15 voltage. table 38. vccpddr control register structure and bits description name bits description vccpddrcnt (addr 0x3e - r/w - default value: 0x3c) ctlvccpddr 2:0 vccpddr state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvccpddr 5:3 vccpddr state control during aoac exit (when the exit pi n is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ controller v occpddr pvin 1p5 (sh a re d wit h vccpaoac, vaon , vmm, and vccp) voutccpddr output monitor i occpddr spi interface c occpddr v occpddr ctlvccpddr aoacctlvccpddr vccpddrfault v ref dischar ge fbccpddr gnd1 p5 (sh a re d wit h vccpaoac, vaon , vmm, and vccp)
analog integrated circuit device data freescale semiconductor 77 900844 functional device operation power supplies figure 42. vaon detailed internal block diagram main features ? uses v15 as the main power supply ? 250 ma maximum continuous output current ? optimized for a 2.2 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vmm vmm is a low drop-out (ldo) fully integrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient re sponse. vmm will be actively discharged during shutdown. vmm shares an input voltage pin (pvin1p5) and a referenc e ground pin (gnd1p5) with t he vccpaoac, vccpddr, vaon, and vccp regulators, yet each has independent co ntrol. pvin1p5 is supp lied from v15 voltage. table 39. vaon control register structure and bits description name bits description vaoncnt (addr 0x45 - r/w - default value: 0x07) ctlvaon 2:0 vaon state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvaon 5:3 vaon state control during aoac exit (when the exit pin is exi tstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ controller v oaon voutaon output monitor i oaon spi interface c oaon v oaon ctlvaon aoacctlvaon vaoncfault v ref discharge pvin 1p5 (shared with vccpaoac, vccpddr, vmm, and vccp) gnd1p5 (shared with vccpaoac , vccpddr, vmm, and vccp)
analog integrated circuit device data 78 freescale semiconductor 900844 functional device operation power supplies figure 43. vmm detailed internal block diagram main features ? uses v15 as the main power supply ?5.0 ma maximum continuous output current ? optimized for a 1.0 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vccp vccp is a low drop-out (ldo) fully integr ated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient response. vccp is actively discharged during shutdown. vccp shares an input voltage pin (pvin1p5) and a re ference ground pin (gnd1p5) with the vccpaoac, vccpddr, vaon, and vmm regulators, yet each has independent control. pvin1p5 is s upplied from v15 voltage. table 40. vmm control register structure and bits description name bits description vmmcnt (addr 0x47 - r/w - default value: 0x24) ctlvmm 2:0 vmm state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvmm 5:3 vmm state control during aoac exit (when the exit pin is exi tstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ contr oller v omm voutmm output monitor i omm spi interface c omm v omm ctlvmm aoacctlvmm vmmcfault v ref discharge pvin 1p5 (sh a re d wit h vccpaoac, vccpddr, vaon, and vccp) gnd1p5 (sh a re d wit h vccpaoac , vccpddr, vaon , and vccp)
analog integrated circuit device data freescale semiconductor 79 900844 functional device operation power supplies figure 44. vccp detailed internal block diagram main features ? uses v15 as the main power supply ? 445 ma maximum continuous output current ? optimized for a 2.2 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vimg25 vimg25 is a low drop-out (ldo) fully int egrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient res ponse. vimg25 is actively discharged during shutdown. vimg25 shares an input voltage pin (pvi nimg) and a reference ground pin (gndimg ) with the vimg28 regulator, yet each has independent control. both can be supplied by the vpwr (3.3 v) node. table 41. vccp control register structure and bits description name bits description vccpcnt (addr 0x44 - r/w - default value: 0x3c) ctlvccp 2:0 vccp state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvccp 5:3 vccp state control during aoac exit (when the exit pi n is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ controller v occp pvin1 p5 (shared with vccpaoac, vccpddr, vaon , and vmm ) voutccp output monitor i occp spi interface c occp v occp ctlvccp aoacctlvccp vccpfault v ref discharge fbccp gnd1p5 (shared with vccpaoac , vccpddr, vaon , and vmm )
analog integrated circuit device data 80 freescale semiconductor 900844 functional device operation power supplies figure 45. vimg25 detailed internal block diagram main features ? uses vpwr (3.3v) as the main power supply ?80 ma maximum continuous output current ? optimized for a 2.2 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vimg28 vimg28 is a low drop-out (ldo) fully int egrated regulator with a p-ch pass fet. it is high performance, low noise, and high psrr, with a low quiescent current and fast transient res ponse. vimg28 is actively discharged during shutdown. vimg28 shares an input voltage pin (pvi nimg) and a reference ground pin (gndimg ) with the vimg25 regulator, yet each has independent control. both can be supplied by the vpwr (3.3 v) node. this ldo is optimized to work with 300 mv headroom, which leaves enough margin between the input and the highest outp ut of this ldo. for more information about package thermal capabilities, reference thermal management . ? note: at high vimg28 output voltage selections, th e output will start tracking the battery voltage when v bat decreases below v oimg28 + 300 mv. table 42. vimg25 register stru cture and bits description name bits description vimg25cnt (addr 0x42 - r/w - default value: 0x04) ctlvimg25 2:0 vimg25 state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvimg25 5:3 vimg25 state control during aoac exit (when the exit pin is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved z + _ controller v oimg 25 v 33 or v pw r pvinimg voutimg 25 output monitor i oimg25 spi interface c in img c oimg 25 v oimg25 ctlvimg25 aoacctlvimg 25 vimg 25 fault v ref gndimg discharge
analog integrated circuit device data freescale semiconductor 81 900844 functional device operation power supplies figure 46. vimg28 detailed internal block diagram main features ? uses 3.3 v or v pwr as the main power supply ? 225 ma maximum continuous output current ? optimized for a 2.2 f external filter capacitor with a maximum of 10 m esr ? uses internal pass fet ? the output for each ldo is monitored for ov er-current conditions and under-voltage events vsdio vsdio is a combo low drop-out (ldo) and power switch. it us es an external p-ch pass fet in switch mode, and internal pass fet on ldo mode. vsdio serves as an ldo when its output voltage is set to 1.8 v, and as a switch when its output voltage is set to 3.3 v. it takes its input voltage directly from the 3.3 v output voltage node. vsdio supplies the sdio card module. the card is initially powered up to 3.3 v. if the card is detected to be a low voltage card, then the rail will be shutdown, configured as 1.8 v, and then turned on. vsdio will be actively discharged during shutdown. table 43. vimg28 control register structure and bits description name bits description vimgacnt (addr 0x0x48 - r/w - default value: 0x24) ctlvimga 2:0 vimg28 state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvimga 5:3 vimg28 state control during aoac exit (when the exit pin is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active selvimga 7:6 vimg28 output voltage selections: x0 = 1.5 v x1 = 2.7 v x2 = 2.8 v x3 = 2.9 v z + _ controller v oimg 28 voutimg 28 output monitor i oimg28 spi interface c oimg 28 v oimg28 ctlvimg28 aoacctlvimg 28 vimg28 cfault v ref discharge pvinimg (shared with vimg25) gndimg (shared with vimg25) selvimg 28
analog integrated circuit device data 82 freescale semiconductor 900844 functional device operation power supplies figure 47. vsdio detailed internal block diagram main features ? uses 3.3 v as the main power supply ? 215 ma maximum continuous output current ? optimized for a 2.2 f external filter capacitor with a maximum of 10 m esr ? uses an internal pass fet on ldo mode, and external pass fet on switch mode. ? the output is monitored for under-voltage an d over-current conditions in ldo mode. power switches freescale?s power management solution for the ultra-mobile platform for netbooks, tablets and sl ates, includes 1 dedicated power switch, housed in the 900844 pmic. table 45 shows its power characteristics. vpnl33 uses an internal switch and are supplied from the 3.3 v output voltage. vpnl33 uses an internal switch and are supplied from the 3.3 v output voltage. table 44. vsdio control register structure and bits description name bits description vsdiocnt (addr 0x4d - r/w - default value: 0x64) ctlvsdio 2:0 vsdio state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvsdio 5:3 vsdio state control during aoac exit (when exit pin is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active selvsdio 7:6 vsdio output voltage selections: x0 = 1.8 v x1 = 3.3 v x2 = reserved x3 = reserved table 45. 900844 power sw itch voltage rail switch typ. voltage max current description vpnl33 3.3 v 100 ma power switch with integrated mosfet and less than 1% voltage drop. z + _ ldo/switch contr oller v osdio output m onitor spi interface c osdio v occp ctlvsdio aoacctlvsdio vsdiofault v ref discharge fbsdio v 33 m sd io sdiogt selvsdio c in sd io
analog integrated circuit device data freescale semiconductor 83 900844 functional device operation power supplies power supply register mask mask writes to the power supply registers, in order to avoid the need for the system controller to do read-modify-write cycles. the mask register is shown in table 47 . figure 48 shows an example of the operation of the pwrmask register. figure 48. pwrmask register implementation example power supply programmable ramp rate turn on time of all buck regulators can be programmed through the spi, reference table 48 table 46. power switches control regist ers structure and bits description name bits description vpanel33cnt (addr 0x4f - r/w - default value: 0x24) ctlvpanel33 2:0 vpnl33 state control x0 = reserved x1 = reserved x2 = reserved x3 = reserved x4 = off x5 = low power x6 = active x7 = active aoacctlvpanel33 5:3 vpnl33 state control during aoac exit (when the exit pin is exitstby pin is asserted). these bits will be initialized by the system spi controller after power up. x0 = do not copy x1 = do not copy x2 = do not copy x3 = do not copy x4 = off x5 = low power x6 = active x7 = active reserved 7:6 reserved table 47. mask register register name addr r/w d7 d6 d5 d4 d3 d2 d1 d0 initial pwrmask 0x34 r/w m7 m6 m5 m4 m3 m2 m1 m0 0x00 table 48. ramp rate control registers (freescale defined) name bits description fsltontcntl1 (addr 0x1c8 - r/w - default value: 0xaa) vcctont 1:0 turn on time settings for vcc regulator x0 = 180 s x1 = 90 s x2 = 45 s x3 = 22 s vnntont 3:2 turn on time settings for vnn regulator x0 = 180 s x1 = 90 s x2 = 45 s x3 = 22 s d7 d6 d5 d4 d3 d2 d1 d0 power supply register before write10101010 pwrmask register settings 11110000 example spi write to power supply 1 1 1 1 1 1 1 1 power supply register after write10101111
analog integrated circuit device data 84 freescale semiconductor 900844 functional device operation power supplies power supplies fault management this section discusses faults related to, or caused by power supplies (directly or indirectly ) operating outside their specifie d boundaries. reference interrupt controller for more information on the various interrupt signals, and the interrupt mechanism used to communicate to the system controller. thermal management the thermal protection is based on a circuit with a voltage output that is proportional to the abs olute temperature. this volta ge can be read out via the adc for precise temperature readouts. see adc subsystem . this voltage is monitored by an integrat ed comparator. interrupt thrm will be genera ted, if not masked, when crossing the thermal warning threshold twarn, and sets the vrfault 1st leve l interrupt that causes the pmicint pin to assert, notifying the system controlle r of a system event. in addition to the previous, the 900844 includes integrated th ermal protection that shuts down and powers off the system, in cases of over dissipation, if the junction temperature exceeds the tshutdo wn threshold. this therma l protection will act above the maximum junction temperature, to avoid any unwanted power downs. the protection is de -bounced by one period of the 32 khz clock in order to suppress any (thermal) noise. this protecti on should be considered as a fa il-safe mechanis m. therefore, the application design should execute a thermal shutdown under normal conditions. once the thermal event is cleared and the temperature is back to its normal range, the 900844 restarts automatically, by following the steps outlined in initial power up sequence vddqtont 5:4 turn on time settings for vddq regulator x0 = 240 s x1 = 120 s x2 = 60 s x3 = 30 s rsvd 7:6 rsvd fsltontcntl2 (addr 0x1cb - r/w - default value: 0xaa) v21tont 1:0 turn on time settings for v21 regulator x0 = 320 s x1 = 160 s x2 = 80 s x3 = 40 s v15tont 3:2 turn on time settings for v15 regulator x0 = 200 s x1 = 100 s x2 = 50 s x3 = 25 s reserved 7:4 reserved table 49. thermal warning/ shutdown thresholds parameter min typ max unit thermal warning threshold 115 120 125 c thermal warning hysteresis 2 - 4 c thermal shutdown threshold 130 140 150 c table 48. ramp rate control registers (freescale defined) name bits description
analog integrated circuit device data freescale semiconductor 85 900844 functional device operation power supplies vrfault every supply is equipped with a fault repo rting signal called xxxfault , where xxx is the name of the power supply. this fault signal is an or function of all of the following possible f aults, or just a subset of them depending on the power supply: ? output under-voltage ? output over-voltage ? over-current ? short-circuit reference each power supply?s section for more information on w hat faults are included, and how the supply protects itself and the load in resp onse to the fault. all of the xxxfault signals from all power supplies are ored together into the batocp interrupt signal, which if unmasked, sets the vrfault 1st level inte rrupt that causes the pmicint pin to assert, notifying the sc of a syst em event. the sc can service the vrfault register and access the faultx registers for more information on which supply caused the fault. the sc can then take different measures, depending on the supply in question. the xxxfault signals are stored in the freescale defined regist ers section (addr 0x180 - 0x1ff), which is meant for extended functionality. table 50. fslfault1 fault status register structure and bit description name bits description fslfault1 (addr 0x1cc - r/w - default value: 0x00) vccfault 0 vcc regulator fault signal x0 = no fault exists x1 = fault exists vnnfault 1 vnn regulator fault signal x0 = no fault exists x1 = fault exists vddqfault 2 vddq regulator fault signal x0 = no fault exists x1 = fault exists v21fault 3 v21 regulator fault signal x0 = no fault exists x1 = fault exists v15fault 4 v15 regulator fault signal x0 = no fault exists x1 = fault exists rsvd 7:5 reserved table 51. fslfault2 fault status regist er structure and bit description name bits description fslfault2 (addr 0x1cd - r/w - default value: 0x00) rsvd 2:0 reserved vbgfault 3 vbg regulator fault signal x0 = no fault exists x1 = fault exists vccafault 4 vcca regulator fault signal x0 = no fault exists x1 = fault exists vcc180fault 5 vcc180 regulator fault signal x0 = no fault exists x1 = fault exists vpnl18fault 6 vpnl18 regulator fault signal x0 = no fault exists x1 = fault exists vpmicfault 7 vpmic regulator fault signal x0 = no fault exists x1 = fault exists
analog integrated circuit device data 86 freescale semiconductor 900844 functional device operation power supplies power supplies fault management interrupt/mask registers. table 52. fslfault3 fault status regist er structure and bit description name bits description fslfault3 (addr 0x1ce - r/w - default value: 0x00) vymxyfi18fa ult 0 vymxyfi18 regulator fault signal x0 = no fault exists x1 = fault exists rsvd 2:1 reserved vccpaoacfa ult 3 vccpaoac regulator fault signal x0 = no fault exists x1 = fault exists vccpddrfau lt 4 vccpddr regulator fault signal x0 = no fault exists x1 = fault exists vaonfault 5 vaon regulator fault signal x0 = no fault exists x1 = fault exists vmmfault 6 vmm regulator fault signal x0 = no fault exists x1 = fault exists vccpfault 7 vccp regulator fault signal x0 = no fault exists x1 = fault exists table 53. fslfault4 fault status regist er structure and bit description name bits description fslfault4 (addr 0x1cf - r/w - default value: 0x00) vimg25fault 0 vimg25 regulator fault signal x0 = no fault exists x1 = fault exists vimg28fault 1 vimg28 regulator fault signal x0 = no fault exists x1 = fault exists rsvd 2 reserved vsdiofault 3 vsdio regulator fault signal x0 = no fault exists x1 = fault exists reserved 7:4 reserved table 54. fault management stat us and control register structure and bits description name bits description vrfaultint (addr 0x30 - r - default value: 0x00) thrm 0 pmic thermal warning flag x0 = pmic temperature below warning threshold x1 = pmic temperature above warning threshold rsvd 1 reserved vrfail 2 regulator fault present flag x0 = no fault x1 = fault exists reserved 7:3 reserved mvrfaultint (addr 0x31 - r/w - default value: 0x03) mthrm 0 pmic thermal warning flag mask x0 = flag unmasked x1 = flag masked rsvd 1 reserved vrfail 2 regulator fault present flag mask x0 = flag unmasked x1 = flag masked reserved 7:3 reserved
analog integrated circuit device data freescale semiconductor 87 900844 functional device operation coin cell battery charger interface coin cell battery charger interface coin cell battery backup/charger the coin cell pin provides a connection for a coin cell backup battery or supercap. if the main battery is deeply discharged or removed, and in the absence of a usb/wa ll input source, the rtc system and coin ce ll maintained logic, will switch over to the coin cell for backup power. a small capacitor should be placed from the coin cell pin to ground under all circumstances. the coin cell charger circuit will function as a current limited voltage source, resulting in the cc/cv taper characteristic, typically used for rechargeable lithium-ion batteries. the coin cell charger is enabled via the coinchgen bit. which is enabled by default. the output voltage (v coin ) is programmable through the vcoin[2:0] bits. the coin cell charger voltage is programmable in the active state, where the charge current is fixed at i coinhi . the coin cell charging will be stopped when v pwr goes below v pwruvf . reference power path manager spi registers for a more detailed description of the coin cell related bits. a large capacitor, electrolytic or super cap, can also be used instead of a lithium based coin cell. to avoid discharge by leak age currents from external components or by the 9 00844, the coinchgen bit should always remain set. coin cell charge is equipped with a disconnect circuitry that isolates the coin cell from any loads, if v coin goes below 2.0 v, to prevent the coin cell from being deeply discharged and damaged. this will also cause the adc reading of the coin cell voltag e to yield zero. power path manager spi registers table 55. input power interrupt /mask registers structur e and bits description name bits description chrgint (addr 0xd0 - r - default value: 0x00) reserved 0 reserved batovp 1 input voltage over-voltage interrupt signal (v bat > v chgcv + v ovrvolt ) x0 = no over-voltage condition x1 = over-voltage condition temp 2 battery over/under-temperature interrupt signal (battery temperature is out of valid window) x0 = no over/under-temperature condition x1 = over/under-temperature condition rsvd 3 reserved rsvd 4 reserved batdet 5 input voltage detection interrupt signal this is a dual edge interrupt signal that is set any time a valid input voltage (vbat > vtrkl) is connected or disconnected x0 = no interrupts pending x1 = 3.3 v supply is connected/disconnected (refer to the schrgint register) rsvd 7:6 reserved mchrgint (addr 0xd1 - r/w - default value: 0x00) reserved 0 reserved mbatovp 1 input voltage over-voltage interrupt signal mask x0 = unmask x1 = mask mtemp 2 input voltage over/under-temperature interrupt signal mask x0 = unmask x1 = mask rsvd 3 reserved rsvd 4 reserved
analog integrated circuit device data 88 freescale semiconductor 900844 functional device operation adc subsystem input power path registers and bits description adc subsystem converter core the adc core is a 10 bit converter. the adc core and logi c run at an internally genera ted frequency of approximately 1.33 mhz. if an adc conversion is requested while the pll was not active, it will automatically be enabled by the adc. a 32.768 khz equivalent time base is derived from the 2.0 mhz clock to time adc events. the adc is supplied from vcore. the adc core has an integrated auto calibration circui t which reduces the offset and gain errors. mbatdet 5 battery detection interrupt signal mask x0 = unmask x1 = mask rsvd 7:6 reserved schrgint (addr 0xd2 - r - default value: 0x00) reserved 0 reserved sbatovp 1 input voltage over-voltage status x0 = input voltage is lower than the limit (< v chgcv + v ovrvolt ) x1 = input voltage is higher than the limit (> v chgcv + v ovrvolt ) stemp 2 battery temperature status x0 = battery temperature is within valid window x1 = battery temperature is out of valid window rsvd 3 reserved rsvd 4 reserved sbatdet 5 battery present status signal x0 = battery not present (vbat < vtrkl) x1 = battery present (vbat > vtrkl) rsvd 7:6 reserved table 56. fsl charger control register structure and bits description name bits description fslchrgcntl (addr 0x1d1 - r/w - default value: 0x13) rsvd 0 reserved coinchen 1 coin cell charger enable/disable x0 = disable x1 = enable (default) vcoin 4:2 coin cell charger output voltage setting x0 = 2.5 v x1 = 2.7 v x2 = 2.8 v x3 = 2.9 v x4 = 3.0 v (default) x5 = 3.1 v x6 = 3.2 v x7 = 3.3 v reserved 7:5 reserved table 55. input power inte rrupt/mask registers struct ure and bits description name bits description
analog integrated circuit device data freescale semiconductor 89 900844 functional device operation adc subsystem the adc will be used for sensing the current through select vo ltage regulators, touch screen s upport, pmic thermal sensor, battery voltage, current, and temperature. figure 49 is a representation of the adc block. figure 49. adc block representation input selector the adc has 22 input channels selected through t he adsel[4:0] bits in the adcaddrx register. table 57 gives an overview of the characteristics of each of these channels. table 57. adc inputs channel select[4:0] adc input signal input level scaling scaled version 0 00000 pmic die temperature 1.2 ? 2.4 v x1 1.2 ? 2.4 v 1 00001 vcc current sense 0 ? 2.4 v x1 0 ? 2.4 v 2 00010 vnn current sense 0 ? 2.4 v x1 0 ? 2.4 v 3 00011 vcc180 current sense 0 ? 2.4 v x1 0 ? 2.4 v 4 00100 reserved reserved reserved reserved 5 00101 reserved reserved reserved reserved 6 00110 input voltage (v bat ) 0 ? 4.8 v /2 0 ? 2.4 v 7 00111 reserved reserved reserved reserved
analog integrated circuit device data 90 freescale semiconductor 900844 functional device operation adc subsystem some of the internal signals are first scaled to adapt the range to the input range of the adc. note that the 10 bit adc core will convert over the entire scaled version of the input channel, so always from a 2.40 v, full scale. for some applications, an external resistor divider network may be used to scale down the voltage to be measured to the adc input range. the source resistance presented by this may be greater than the maximum spec ified rs, see adc section on table 3 . in that case, the readout value will be lower than expected due to the dynamic input impe dance of the adc converter. this readout error presents itself as a gain error which can be co mpensated for by factory phasing. an alternative is to place a 100 nf bypass capacitor at the adin input concerned. reserved channels possible usage only 22 of the possible 32 adc channels are currently asso ciated with an specific function. the remaining channels are currently designated as reserved channels for future needs. table 58 is a proposed usage for some of these channels for additional flexibility. 8 01000 reserved reserved reserved reserved 9 01001 battery pack thermistor 0 ? 2.4 v x1 0? 2.4 v 10 01010 general purpose adin10 touch screen x+ 0-200 mv / 0-2.0 v 0 ? 1.2 10x / 1x x2 0 ? 2.4 v 0 ? 2.4 v 11 01011 general purpose adin11 touch screen x- 0-200 mv / 0-2.0 v 0 ? 1.2 10x / 1x x2 0 ? 2.4 v 0 ? 2.4 v 12 01100 general purpose adin12 touch screen y+ 0-200 mv / 0-2.0 v 0 ? 1.2 10x / 1x x2 0 ? 2.4 v 0 ? 2.4 v 13 01101 general purpose adin13 touch screen y- 0-200 mv / 0-2.0 v 0 ? 1.2 10x / 1x x2 0 ? 2.4 v 0 ? 2.4 v 14 01110 general purpose adin14 0-200 mv / 0-2.0 v 10x / 1x 0 ? 2.4 v 15 01111 general purpose adin15 0-200 mv / 0-2.0 v 10x / 1x 0 ? 2.4 v 16 10000 general purpose adin16 0-200 mv / 0-2.0 v 10x / 1x 0 ? 2.4 v 17 10001 general purpose adin17 0-200 mv / 0-2.0 v 10x / 1x 0 ? 2.4 v 18 10010 general purpose adin18 0-200 mv / 0-2.0 v 10x / 1x 0 ? 2.4 v 19 10011 general purpose adin19 0-200 mv / 0-2.0 v 10x / 1x 0 ? 2.4 v 20 10100 general purpose adin20 0-200 mv / 0-2.0 v 10x / 1x 0 ? 2.4 v 21 10101 general purpose adin21 0-200 mv / 0-2.0 v 10x / 1x 0 ? 2.4 v 22 10110 reserved reserved reserved reserved 23 10111 reserved reserved reserved reserved 24 11000 reserved reserved reserved reserved 25 11001 reserved reserved reserved reserved 26 11010 reserved reserved reserved reserved 27 11011 reserved reserved reserved reserved 28 11100 reserved reserved reserved reserved 29 11101 reserved reserved reserved reserved 30 11110 reserved reserved reserved reserved 31 11111 reserved reserved reserved reserved notes 18. equivalent to -3.0 to +3.0 a of current with a 20 mohm sense resistor table 57. adc inputs channel select[4:0] adc input signal input level scaling scaled version
analog integrated circuit device data freescale semiconductor 91 900844 functional device operation adc subsystem activating the prior channels to provide t he signal specified occurs by asserting t he following bits to 1. if the following bit s are 0, then these channels are reserved: ? vpwrcon for channel 22 ? licon for channel 25 control the adc block consists of a 5-bit wide, 32-entry register file , which stores the address of the analog input for sampling. the 10-bit result is then stored in a separate register file 10+1 bits wide and 32 entries deep. in order to operate the adc, it has to be enabled first by setting the aden bit high in the adccntl1 register. when the register adccntl1 adstrt bit is enabled, th e pmic will cycle through the 3 + 5 bit selector addresses in registers adcaddrx. the high 3-bits control the touch screen bias fets, as described in touch screen interface . the lower 5-bits address the adc selector to connect one of 32 channels to the adc. the result of the adc conversion is stored into the result registers (adcsnsx), along with the input gain setting (1 msb). an address in the selector table of 0x1f designates the stop location of the selection loop. at which point the interrupt flag bit 0 (rnd), which can be masked through the mrnd bit in the madcint register, is set in register adcint, bit 1 of the interrupt register (adc) is set, a nd the external pmicint signal is asserted, if bit 1 of the intmask register is clear. the adc sleeps for 0 to 27 ms as set by adc register adccntl1 through the adslp[2:0] bits and then r epeats the selector cycle. the new dat a overwrites the old in the result registers. at most, all 32 r esult registers will be filled within 15.625 ms (2048/32 = 1/64 hz). the result registers will no t be read until the rnd flag is set. dedicated channels reading two different lsb value settings are possible by us ing the lsbsel bit in the fsladccntl register. lsbsel = 0 is the default setting. see table 59 for more information table 58. possible reserved channels usage channel adc input signal input level scaling scaled version 22 application supply (v pwr ) 0 ? 4.8 v /2 0 ? 2.4 v 23 reserved reserved reserved reserved 24 reserved reserved reserved reserved 25 backup voltage (v coincell ) 0 ? 3.6 v x2/3 0 ? 2.4 v 26 reserved reserved reserved reserved 27 reserved reserved reserved reserved 28 reserved reserved reserved reserved 29 reserved reserved reserved reserved 30 reserved reserved reserved reserved 31 reserved reserved reserved reserved table 59. adc lsb settings # select[4:0] adc input signal signal range lsb value (lsbsel = 0) lsb value (lsbsel = 1) 0 00000 pmic die temperature 1.2 ? 2.4 v 0.4244 k 1c 1 00001 vcc current sense 4.2 a 4.1015 ma 10 ma 2 00010 vnn current sense 1.9 a 1.8554 ma 10 ma 3 00011 vcc180 current sense 0.5 a 0.4883 ma 10 ma 4 00100 reserved reserved reserved reserved 5 00101 reserved reserved reserved reserved 6 00110 battery voltage (v bat ) 4.8 v 4.6875 mv 10 mv
analog integrated circuit device data 92 freescale semiconductor 900844 functional device operation adc subsystem pmic die temperature the die temperature can be read out on ch annel 0 of the adc. the relation betwe en the read out code and temperature is given in table 60 . 7 00111 reserved reserved reserved reserved 8 01000 reserved reserved reserved reserved 9 01001 battery pack thermistor 2.4 v 2.3438 mv 10mv 10 01010 general purpose adin10 touch screen x+ 0-200 mv / 0-2.0 v 0 ? 1.2 195.3 v - 1.953 mv 1.17 mv 195.3 v - 1.953 mv 1.17 mv 11 01011 general purpose adin11 touch screen x- 0-200 mv / 0-2.0 v 0 ? 1.2 195.3 v - 1.953 mv 1.17 mv 195.3 v - 1.953 mv 1.17 mv 12 01100 general purpose adin12 touch screen y+ 0-200 mv / 0-2.0 v 0 ? 1.2 195.3 v - 1.953 mv 1.17 mv 195.3 v - 1.953 mv 1.17 mv 13 01101 general purpose adin13 touch screen y- 0-200 mv / 0-2.0 v 0 ? 1.2 195.3 v - 1.953 mv 1.17 mv 195.3 v - 1.953 mv 1.17 mv 14 01110 general purpose adin14 0-200 mv / 0-2.0 v 195.3 v - 1.953 mv 195.3 v - 1.953 mv 15 01111 general purpose adin15 0-200 mv / 0-2.0 v 195.3 v - 1.953 mv 195.3 v - 1.953 mv 16 10000 general purpose adin16 0-200 mv / 0-2.0 v 195.3 v - 1.953 mv 195.3 v - 1.953 mv 17 10001 general purpose adin17 0-200 mv / 0-2.0 v 195.3 v - 1.953 mv 195.3 v - 1.953 mv 18 10010 general purpose adin18 0-200 mv / 0-2.0 v 195.3 v - 1.953 mv 195.3 v - 1.953 mv 19 10011 general purpose adin19 0-200 mv / 0-2.0 v 195.3 v - 1.953 mv 195.3 v - 1.953 mv 20 10100 general purpose adin20 0-200 mv / 0-2.0 v 195.3 v - 1.953 mv 195.3 v - 1.953 mv 21 10101 general purpose adin21 0-200 mv / 0-2.0 v 195.3 v - 1.953 mv 195.3 v - 1.953 mv 22 10110 application supply (v pwr ) 0 ? 4.8 v 4.6875 mv 4.6875 mv 23 10111 reserved reserved reserved reserved 24 11000 reserved reserved reserved reserved 25 11001 backup voltage (v coincell ) 0 ? 3.6 v 3.5156 mv 3.5156 mv 26 11010 reserved reserved reserved reserved 27 11011 reserved reserved reserved reserved 28 11100 reserved reserved reserved reserved 29 11101 reserved reserved reserved reserved 30 11110 reserved reserved reserved reserved 31 11111 reserved reserved reserved reserved table 59. adc lsb settings # select[4:0] adc input signal signal range lsb value (lsbsel = 0) lsb value (lsbsel = 1)
analog integrated circuit device data freescale semiconductor 93 900844 functional device operation adc subsystem current sensing the load current sourced by a select set of regulators can be measured and recorded by t he adc on channels 1 through 5. table 61 shows a summary of these regulators, type, and their current ranges. input voltage the input voltage is read at the vbat pin at channel 6. the input voltage is first scaled by subtracting 2.40 v in order to fit the input range of the adc. general purpose analog inputs there are twelve general purpose analog input channels that can be measured through the adin10-adin21 pins. two voltage scaling (gain) settings can be selected to accommodate a wid er range of inputs through the adccntl3 and adccntl4 registers. a gain of 0 sets a corresponding sca ling factor of 1 (for an input range of 2.0 v) and a gain of 1 sets a corresponding scaling factor of 10 (for an input range of 200 mv). table 60. pmic die temperature voltage reading parameter typical die temperature read out code at 25 c 1011000001 temperature change per lsb +0.4244 c customer defined lsb value 1.0000 c multiplier value for output register x2.36 table 61. regulators current sensing regulator type current range vcc buck 0 ? 3.5 a vnn buck 0 ? 1.6 a vcc180 ldo 0 ? 0.39 a table 62. battery voltage reading coding conversion code voltage at adc input voltage at vbat 1 111 111 111 2.400 v 4.800 v 1 000 010 100 1.250 v 2.500 v 0 000 000 000 0.000 v 0.000 v table 63. general purpose anal og inputs reading coding conversion code voltage at adc input voltage at adinx input gain 1 111 111 111 2.400 0.200 1 1 011 111 111 1.800 0.150 0 011 111 111 0.600 0.050 0 000 000 000 0.000 0.000 1 111 111 111 2.400 2.000 0 1 011 111 111 1.800 1.500 0 011 111 111 0.600 0.500 0 000 000 000 0.000 0.000
analog integrated circuit device data 94 freescale semiconductor 900844 functional device operation adc subsystem application supply (if used) channel 22 can be used to read the application supply volt age at the vpwr pin. this can be enabled by setting the vpwrcon bit in the fsladccntl register high. the battery voltage is first scaled as vpwr/2 in order to fit the input range of the adc. backup voltage (if used) channel 25 can be used to read the voltage of the coin cell co nnected to the coincell. this is enabled by setting the licon bit in the fsladccntl register to 1. sinc e the voltage range of the coin cell exceeds the input voltage range of the adc, the coincell voltage is first scaled as v coin *2/3. touch screen interface the pmic touch screen support consists of four analog input channels with built in bi as control. the bias fet control bits are part of the adc round robin address register adcaddrx. the t ouch screen x plate is connected to adin10 (x+) and adin11 (x-), while the y plate is connected to adin12(y+) and adin13(y-). a local supply, tsref, of 1.2 v will serve as a reference. the system processor will handle the touch screen sequencing and any necessary conversion delays. the system processor will direct the desired bias control for every reading though the adcaddrx registers. if fet bi asing is enabled though the adcaddrx registers, then touch screen r eadings will start according based on the channels chosen, and also by the adcaddrx registers. if the touch screen is not used, then the above inputs can be used as general purpose inputs. in this case, the bias control will always be programmed to no bias. figure 50 is a touch screen representation. figure 50. touch screen configuration example table 64. application supply voltage reading coding conversion code voltage at adc input voltage at vpwr 1 111 111 111 2.400 v 4.800 v 1 000 010 100 1.250 v 2.500 v 0 000 000 000 0.000 v 0.000 v table 65. backup (coin cell) voltage reading coding conversion code voltage at adc input voltage at coincell 1 111 111 111 2.400 v 3.600 v 1 000 000 000 1.200 v 1.800 v 0 000 000 000 0.000 v 0.000 v
analog integrated circuit device data freescale semiconductor 95 900844 functional device operation adc subsystem touch screen pen detection bias can be enabled via the pendet en bit in the adccntl1 register . when this bit is enabled and a pen touch is detected, the pendet bit in register adcint is set and the pmicint pin is asserted. this is to interrupt the system, because a touch screen pen touch has been detected at the next adc cycle, unless the interrupt is masked. the prior reference for the touch screen (touch bias) is ts ref and is powered from vcore. in touch screen operation, tsref is a dedicated regulator. no loads other than the touch screen should be connected here. when the adc performs non touch screen conversions, the adc does not rely on tsref and the reference can be disabled. the readouts are designed such that the on chip switch resist ances are of no influence to the overall read out. the readout scheme does not account for contact resistances, as present in the touch screen connectors. therefore, the touch screen readings have to be calibrated by the user or in the factory, where one has to point wit h a stylus to the opposite corners of t he screen. when reading out the x-coordinate , the 10-bit adc reading represents a 10-bit coordinate with '0' for a coordinate equa l to x- and full scale '1023' when equal to x+. when reading out the y-coordinate, the 10-bit a dc reading represents a 10-bit coordinate with '0' for a coordinate equal to y- and full scale '1023' when equal to y+. when reading the contact resistance th e 10-bit adc reading represents the voltage drop over the contact resistance created by the known current source multiplied by 2. adc status/control registers and bit description reference the table 67 for read/write conditions and default state for each of these registers table 66. touch screen system requirements description symbol min typ max unit plate resistance x, y - 100 - 1000 resistance between plates, contact - 180 - 1200 capacitance between plates - 0.5 2.0 - nf contact resistance current source - - 100 - a interrupt current source - - 20 - a interrupt threshold - 40 - 60 k current source inaccuracy - - - 20 % quiescent current (active mode) - 20 - a max load current (active mode) - - 20 ma settling time (position measurement) - 3.0 - 5.5 s table 67. adc interrupt/mask register s structure and bits description name bits description adcint (addr 0x5f - r - default value: 0x00) rnd 0 adc round robin cycle completion interrupt x0 = not completed x1 = completed pendet 1 touch screen pen detection interrupt x0 = pen not detected x1 = pen detected reserved 7:2 reserved madcint (addr 0x60 - r/w -default value: 0x00) mrnd 0 adc round robin cycle completion interrupt mask x0 = unmask x1 = mask mpendet 1 touch screen pen detection interrupt mask x0 = unmask x1 = mask reserved 7:2 reserved
analog integrated circuit device data 96 freescale semiconductor 900844 functional device operation adc subsystem table 68. adc control registers structure and bits description name bits description adccntl2 (addr 0x61 - r/w -default value: 0x00) adslp 2:0 adc sleep time before starting another cycle x0 = continuous loop x1 = 4.5 ms x2 = 9.0 ms x3 = 13.5 ms x4 = 18 ms x5 = 22.5 ms x6 = 27 ms x7 = no loop rsvd 4:3 reserved pendeten 5 enable touch screen pen detect bias x0 = disabled x1 = enabled adstrt 6 adc round robin start signal x0 = stop round robin after the current cycle x1 = start round robin aden 7 bring the adc out of low power state, this overrides wake from sleep x0 = disable in low power x1 = enable at full power adccntl3 (addr 0x62 - r/w -default value: 0x00) adexgain10 0 gain bit for adc channel 10, ignore when touch screen is biased x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) adexgain11 1 gain bit for adc channel 11, ignore when touch screen is biased x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) adexgain12 2 gain bit for adc channel 12, ignore when touch screen is biased x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) adexgain13 3 gain bit for adc channel 13, ignore when touch screen is biased x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) adexgain14 4 gain bit for adc channel 14 x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) adexgain15 5 gain bit for adc channel 15 x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) adexgain16 6 gain bit for adc channel 16 x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) adexgain17 7 gain bit for adc channel 17 x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) adccntl4 (addr 0x63 - r/w -default value: 0x00) adexgain18 0 gain bit for adc channel 18 x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) adexgain19 1 gain bit for adc channel 19 x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range)
analog integrated circuit device data freescale semiconductor 97 900844 functional device operation adc subsystem adexgain20 2 gain bit for adc channel 20 x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) adexgain21 3 gain bit for adc channel 21 x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) reserved 7:4 reserved table 69. adc channel selector/configu ration structure and bit description name bits description adcsnsxh (x = 0 to 31) adchxh 6:0 7 msbs of adc result for channel x gainx 7 gain bit for adc channel x, x = 0 to 31 x0 = x1 (0-2.0 v input range) x1 = x10 (0-200 mv input range) adcsnsxl (x = 0 to 31) adchxl 2:0 3 lsbs of adc result for channel x reserved 7:3 reserved adcaddrx (x = 0 to 31) adselx 4:0 adc channel to be read selection bits x00 = channel 0 x01 = channel 1 ... x1f = channel 31 xpxmx 5 turns on x+ and x- bias fets, refer to figure 50 x0 = fets off x1 = fets on ypymx 6 turns on y+ and y- bias fets, refer to figure 50 x0 = fets off x1 = fets on xmypx 7 turns on x- and y+ bias fets, refer to figure 50 x0 = fets off x1 = fets on table 68. adc control registers structure and bits description name bits description
analog integrated circuit device data 98 freescale semiconductor 900844 functional device operation gpios adc status/control registers and bit description gpios description the 900844 has eight gpios, and ei ght gpos for platform control. as outputs, the gpios support cmos/od signaling levels, based on the voltage level on the gpiovcc. the gpos support cmos signaling levels, based on the voltage level on the gpovcc pin. as inputs, they are 3.6 v tolerant and are de-bounced for a period of no more than 10 ms minimum. the 900844 provides one bank of eight conf igurable gpio inputs/outputs, gpio[7:0] for general purpose sensing and platform control. only gpios support an input function. gpios switch between a high-impedance (>1.0 m ) state and a low-impedance (20 nominal) state when operating in open drain mode. when operating in cmos mo de, the outputs drive from the voltage supplied on the gpiovcc pin with a 20 output drive capability (for gpios). the electrical characteristics of the out put buffer will therefore be specified as re lative percentages of the driving supply. any unused gpio pin should be tied to ground on the board. when any gpio is configured as an open drain, the pull-up voltage cannot exceed that of the gpiovcc voltage level. table 71 shows the default state of the di fferent gpios and their capabilities. table 70. extended adc control register structure and bits description name bits description fsladccntl (addr 0x1de - r/w - default value: 0x00) vpwrcon 0 enable channel 22 to read the v pwr voltage x0 = disable (default) x1 = enable chrgicon 1 enable channel 24 to read the battery charging current x0 = disable (default) x1 = enable licon 2 enable channel 25 to read the backup battery voltage x0 = disable (default) x1 = enable rsvd 3 reserved lsbsel 4 adc lsb selection bit x0 = refer to table 59 x1 = refer to table 59 rsvd 7:4 reserved table 71. gpios capabilities and default states gpio input output cmos od slew cntl default mode default level gpio0 yes yes yes yes no input hi-z gpio1 yes yes yes yes no input hi-z gpio2 yes yes yes yes no input hi-z gpio3 yes yes yes yes no input hi-z gpio4 yes yes yes yes no input hi-z gpio5 yes yes yes yes no input hi-z gpio6 yes yes yes yes no input hi-z gpio7 yes yes yes yes no input hi-z gpo0 no yes yes no no cmos low gpo1 no yes yes no no cmos low
analog integrated circuit device data freescale semiconductor 99 900844 functional device operation gpios gpio module structure figure 51 illustrates the logical stru cture of the gpiox modules. figure 51. gpio module structure gpo2 no yes yes no no cmos low gpo3 no yes yes no no cmos low gpo4 no yes yes no no cmos low gpo5 no yes yes no no cmos low gpo6 no yes yes no no cmos low gpo7 no yes yes no no cmos low table 71. gpios capabilities and default states gpio input output cmos od slew cntl default mode default level
analog integrated circuit device data 100 freescale semiconductor 900844 functional device operation gpios gpio status/control registers and bit description gpio module has a single 8-bit status and control register assigned to it. see table 72 for details. the ?x? in the bit names in the tabl es is from 0 to 7 for the gpios. table 72. gpio register stru cture and bits description name bits description gpiocntlx (x = 0 to 7) drvx 0 gpiox output driver type x0 = open drain x1 = cmos dirx 1 gpiox direction configuration x0 = output (type selected by bit 0) x1 = input (bit 0 is ignored) datainx 2 the value in the data_in bit reflects the electrical state of the gpiox pin at the time the register read was initiated. when bit 1, direction, is 0 (output mode), the contents of this register are not required to be updated on reads and is assumed to be invalid by the system controller. t he pmic should de-bounce the inputs over 1-10 ms to insure a clean transition. x0 = electrical low (19) x1 = electrical high (19) dataoutx 3 the value in the data_out bit reflects t he desired electrical output state of the gp iox pin. when bit 1, direction, is 1 (input mode), the contents of this register may still be read or written, but will not be reflected until the gpiox is reverted to an output (bit 1, direction, is 0) x0 = electrical low (19) x1 = electrical high (cmos) or high-impedance output (open-drain) (19) intctlx 5:4 these bits set the interrupt de finition. the mask (00) determines if the corr esponding interrupt flag bit is set or not on an interrupt. the other logic levels will set the corresponding in terrupt flag bit in the register upon the specific edge detectio n defined by the level. they will also set bit 4 of the 1st level interrupt register, see section interrupt controller for more details. (20) x0 = mask. x1 = negative edge x2 = positive edge x3 = both edges gpidbncx 7:6 these bits set the debounce time on the gpiox when configured as inputs x0 = no debounce x1 = 10 ms x2 = 20 ms x3 = 30 ms gpioint (addr 0xe8 - r - default value: 0x00) gpiint0 0 gpio0 interrupt flag x0 = no interrupt occurred or masked interrupt x1 = interrupt occurred gpiint1 1 gpio1 interrupt flag x0 = no interrupt occurred or masked interrupt x1 = interrupt occurred gpiint2 2 gpio2 interrupt flag x0 = no interrupt occurred or masked interrupt x1 = interrupt occurred gpiint3 3 gpio3 interrupt flag x0 = no interrupt occurred or masked interrupt x1 = interrupt occurred notes 19. see gpios electrical characteristics on table 3 20. an unintended interrupt is caused if interrupt settings are re configured in the middle of an application, e.g. re-setting in terrupt detection from detecting an interrupt on both edges to an interrupt on the rising edge. in this case, to mask any unwanted interrupt, cha nge the gpio interrupt detection to the new configuration, then clear lev el 1 and level 2 interrupts, finally unmask the gpio interrupt .
analog integrated circuit device data freescale semiconductor 101 900844 functional device operation spi register map spi register map overview the spi frame is organized as 24 bits. the first 16 bits is the write enable bit, 10-bit addre ss and 5 "dead" bits between the data and address fields. the next 8 bits are the data bits. the o ne write enable bit selects whether the spi transaction is a r ead or a write. the addressable register map spans 1024 registers of 8 dat a bits each. the map is not fully populated. a summarized structure of the register set is given in the following tables. expanded bit descriptions are included in the individual functi onal sections for application guidance. gpiint4 4 gpio4 interrupt flag x0 = no interrupt occurred or masked interrupt x1 = interrupt occurred gpiint5 5 gpio5 interrupt flag x0 = no interrupt occurred or masked interrupt x1 = interrupt occurred gpiint6 6 gpio6 interrupt flag x0 = no interrupt occurred or masked interrupt x1 = interrupt occurred gpiint7 7 gpio7 interrupt flag x0 = no interrupt occurred or masked interrupt x1 = interrupt occurred table 73. gpo register structure and bits description name bits description gpo (addr 0xf4 - r/w - default value: 0x00) gpo0 0 gpo0 output level x0 = low0 x1 = high (to voltage supplied on gpovcc pin) gpo1 1 gpo1 output level x0 = low x1 = high (to voltage supplied on gpovcc pin) gpo2 2 gpo2 output level x0 = low x1 = high (to voltage supplied on gpovcc pin) gpo3 3 gpo3 output level x0 = low x1 = high (to voltage supplied on gpovcc pin) gpo4 4 gpo4 output level x0 = low x1 = high (to voltage supplied on gpovcc pin) gpo5 5 gpo5 output level x0 = low x1 = high (to voltage supplied on gpovcc pin) gpo6 6 gpo6 output level x0 = low x1 = high (to voltage supplied on gpovcc pin) gpo7 7 gpo7 output level x0 = low x1 = high (to voltage supplied on gpovcc pin) table 72. gpio register st ructure and bits description name bits description
analog integrated circuit device data 102 freescale semiconductor 900844 functional device operation spi register map spi bit map the tables include the following fields: ? block: this corresponds directly to the chapter, section or topic in which the det ailed register description is included. ? address: the register memory map address allocation in hex format ? register name ? r/w: defines if the register is a read /write register or only a read register ? d7-d0: the 8-bit data included in the register with each bit's name and location within the field included ? initial: the register's default value after power up ? function: a short description of the register's function some important notes about data in the table: ? reserved registers/bits are not implemented in the design and they will always read as a 0 ? registers under the "fsl" block are freescale dedicated register s and are not defined in the customer specifications. these registers represent additional functiona lity that freescale is offering to enhanc e the performance of the overall system ? registers under the "vd2" and "vd3" blocks are blocked from being used by freescale ? the table only displays up to address 0x2f f. address space between 0x300 and 0x3ff is reserved for future application use. freescale is currently using the 0x300 to 0x3ff space for test and debug register implementatio n. this will not effect the application or any future use plans for this address space. the det ails of this space implementation are not discussed in this document. table 74. spi register map block address register name r/w d7 d6 d5 d4 d3 d2 d1 d0 initial function chip1 0x00 id1 r rsvd rsvd rev1[2:0] vendid1[2:0] 0x38 chip1 id chip2 0x01 id2 r rsvd rsvd rev2[2:0] vendid2[2:0] 0x00 chip2 id chip3 0x02 id3 r rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 chip3 id chip4 0x03 id4 r rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 chip4 id irq 0x04 interrupt r ext aux vrfault gpio rtc chr adc pwrbtn 0x00 pmic_int sources, read clears irq 0x05 intmask r/w mext maux mvrfault mgpio mrtc mchr madc mpwrbtn 0xfa irq mask cntrl 0x06 chipcntrl r/w rsvd rsvd rsvd rsvd rsvd rsvd warmrst coldrst 0x00 pwrgd/reset# control rsvd 0x07 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0x08 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0x09 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0x0a - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0x0b - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0x0c - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0x0d - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0x0e - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0x0f - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rtc 0x10 rtcs r/w rsvd sec[6:0] 0x00 rtc second rtc 0x11 rtcsa r/w rsvd secalarm[6:0] 0x00 rtc second alarm rtc 0x12 rtcm1 r/w rsvd min[6:0] 0x00 rtc minutes rtc 0x13 rtcma r/w rsvd minialarm[6:0] 0x00 rtc minutes alarm rtc 0x14 rtch r/w pa-h rsvd hrs[5:0] 0x00 rtc hours rtc 0x15 rtcha r/w pa-ha rsvd hrsalarm[5:0] 0x00 rtc hours alarm rtc 0x16 rtcdw r/w rsvd rsvd rsvd rsvd rsvd dow[2:0] 0x01 rtc day of week rtc 0x17 rtcdm r/w rsvd rsvd dom[5:0] 0x01 rtc day of month rtc 0x18 rtcm2 r/w 19/20 rsvd rsvd month[4:0] 0x01 rtc month
analog integrated circuit device data freescale semiconductor 103 900844 functional device operation spi register map rtc 0x19 rtcy r/w year[7:0] 0x00 rtc rtc 0x1a rtca r uip dv[2:0] (=010b fixed) rs[3:0] (=000b fixed) 0x20 rtc control a rtc 0x1b rtcb r/w set pie (=0) fix aie uie sqwe (=0) fix dm hrmode dse (=0) fix 0x02 rtc control b rtc 0x1c rtcc r irqf pf (=0) fix af uf rsvd rsvd rsvd rsvd 0x00 rtc control c rtc 0x1d rtcd r vrt rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 rtc control d rtc 0x1e rtce r/w scratch[4:0] por bkdet oscst 0x05 rtc optional detection rtc 0x1f adj r/w rsvd rsvd rsvd rsvd rsvd rsvd rsvd adj 0x00 rtc adjustment rtc 0x20 trim r/w rsvd sign trimval[5:0] 0x00 rtc trimming rtc 0x21 clkout r/w rsvd rsvd rsvd rsvd rsvd rsvd rsvd m32kclk 0x00 32khz clock output enable rsvd 0x22- 0x2f - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved power 0x30 vrfaultint r rsvd rsvd rsvd rsvd rsvd vrfail batocp thrm 0x00 voltage regulators fault interrupt power 0x31 mvrfaultint r/w rsvd rsvd rsvd rsvd rsvd mvrfail mbatocp mthrm 0x03 voltage regulators fault interrupt mask power 0x32 vcclatch r/w dvp1vrd vidvcc[6:0] 0x7f vcc vid control power 0x33 vnnlatch r/w dvp2vrd vidvnn[6:0] 0x7f vnn vid control power 0x34 pwrmask r/w m7 m6 m5 m4 m3 m2 m1 m0 0x00 power register write mask power 0x35 vcccnt r/w rsvd rsvd aoactlvcc[2:0] ctlvcc[2:0] 0x24 vcc power 0x36 vnncnt r/w rsvd rsvd aoactlvnn[2:0] ctlvnn[2:0] 0x04 vnn power 0x37 vddqcnt r/w rsvd rsvd aoactlvddq[2:0] ctlvddq[2:0] 0x04 vddq power 0x38 v21cnt r/w rsvd rsvd aoactlv21[2:0] ctlv21[2:0] 0x07 v21 power 0x39 v15cnt r/w selv15[1:0] aoactlv15[2:0] ctlv15[2:0] 0x07 v15 rsvd 0x3a rsvd r/w rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 rsvd rsvd 0x3b rsvd r/w rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 rsvd rsvd 0x3c rsvd r/w rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 rsvd power 0x3d vccpaoaccnt r/w rsvd rsvd aoactlvccpaoac[2:0] ctlvccpaoac[2:0] 0x07 vccpaoac power 0x3e vccpddrcnt r/w rsvd rsvd aoactlvccpddr[2:0] ctlvccpddr[2:0] 0x3c vccpddr power 0x3f vlbgcnt r/w rsvd rsvd aoactlvlbg[2:0] ctlvlbg[2:0] 0x24 vlbg power 0x40 vccacnt r/w rsvd rsvd aoactlvcca[2:0] ctlvcca[2:0] 0x3c vcca power 0x41 vpmiccnt r/w rsvd rsvd aoactlvpmic[2:0] ctlvpmic[2:0] 0x07 vpmic power 0x42 vimg25cnt r/w rsvd rsvd aoactlvimg25[2:0] ctlvimg25[2:0] 0x04 vimg25 power 0x43 vcc180cnt r/w rsvd rsvd aoactlvcc180[2:0] ctlvcc180[2:0] 0x3c vcc180 power 0x44 vccpcnt r/w rsvd rsvd aoactlvccp[2:0] ctlvccp[2:0] 0x3c vccp power 0x45 vaoncnt r/w rsvd rsvd aoactlvaon[2:0] ctlvaon[2:0] 0x07 vaon power 0x46 vpanel18cnt r/w rsvd rsvd aoactlvpanel18[2:0] ctlvpanel18[2:0] 0x24 vpanel18 power 0x47 vmmcnt r/w rsvd rsvd aoactlvmm[2:0] ctlvmm[2:0] 0x24 vmm power 0x48 vimgacnt r/w selimga[1:0] aoactlvimga[2:0] ctlvimga[2:0] 0x24 vimga rsvd 0x49 rsvd r/w rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 rsvd rsvd 0x4a rsvd r/w rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 rsvd rsvd 0x4b rsvd r/w rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 rsvd power 0x4c vwymxarfcnt r/w rsvd rsvd aoactlvwymxarf[2:0] ctlvwymxarf[2:0] 0x24 wifibt_ymx_ana logrf table 74. spi register map block address register name r/w d7 d6 d5 d4 d3 d2 d1 d0 initial function
analog integrated circuit device data 104 freescale semiconductor 900844 functional device operation spi register map power 0x4d vsdiocnt r/w selvsdio[1:0] aoactlvsdio[2:0] ctlvsdio[2:0] 0x64 vsdio rsvd 0x4e rsvd r/w rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 rsvd power 0x4f vpanel33cnt r/w rsvd rsvd aoactlvpanel33[2:0] ctlvpanel33[2:0] 0x24 vcc_panel_3.3 rsvd 0x50 rsvd r/w rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 rsvd rsvd 0x51 rsvd r/w rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 rsvd rsvd 0x52 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0x53 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0x54 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved memory 0x55 mem1 r/w scratch[7:0] 0x00 backup memory memory 0x56 mem2 r/w scratch[7:0] 0x00 backup memory memory 0x57 mem3 r/w scratch[7:0] 0x00 backup memory memory 0x58 mem4 r/w scratch[7:0] 0x00 backup memory memory 0x59 mem5 r/w scratch[7:0] 0x00 backup memory memory 0x5a mem6 r/w scratch[7:0] 0x00 backup memory memory 0x5b mem7 r/w scratch[7:0] 0x00 backup memory memory 0x5c mem8 r/w scratch[7:0] 0x00 backup memory rsvd 0x5d - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0x5e - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved adc 0x5f adcint r rsvd rsvd rsvd rsvd rsvd overflo w pendet rnd 0x00 adc interrupt adc 0x60 madcint r/w rsvd rsvd rsvd rsvd rsvd moverfl ow mpendet mrnd 0x00 adc interrupt mask adc 0x61 adccntl2 r/w aden adstrt pendeten ccclear ccen adslp[2:0] 0x00 adc control adc 0x62 adccntl3 r/w adexgain1 7 adexgain 16 adexgain 15 adexgai n14 adexgain 13 adexgai n12 adexgain 11 adexgain 10 0x00 gain for an10- an17 adc 0x63 adccntl4 r/w rsvd rsvd rsvd rsvd adexgain 21 adexgai n20 adexgain 19 adexgain 18 0x00 gain for an18- an21 adc 0x64 adcsns0h r gain0 adch0h[9:3] 0x00 adc result adc 0x65 adcsns0l r rsvd rsvd rsvd rsvd rsvd adch0l[2:0] 0x00 adc result adc 0x66 adcsns1h r gain1 adch1h[9:3] 0x00 adc result adc 0x67 adcsns1l r rsvd rsvd rsvd rsvd rsvd adch1l[2:0] 0x00 adc result adc 0x68 adcsns2h r gain2 adch2h[9:3] 0x00 adc result adc 0x69 adcsns2l r rsvd rsvd rsvd rsvd rsvd adch2l[2:0] 0x00 adc result adc 0x6a adcsns3h r gain3 adch3h[9:3] 0x00 adc result adc 0x6b adcsns3l r rsvd rsvd rsvd rsvd rsvd adch3l[2:0] 0x00 adc result adc 0x6c adcsns4h r gain4 adch4h[9:3] 0x00 adc result adc 0x6d adcsns4l r rsvd rsvd rsvd rsvd rsvd adch4l[2:0] 0x00 adc result adc 0x6e adcsns5h r gain5 adch5h[9:3] 0x00 adc result adc 0x6f adcsns5l r rsvd rsvd rsvd rsvd rsvd adch5l[2:0] 0x00 adc result adc 0x70 adcsns6h r gain6 adch6h[9:3] 0x00 adc result adc 0x71 adcsns6l r rsvd rsvd rsvd rsvd rsvd adch6l[2:0] 0x00 adc result adc 0x72 adcsns7h r gain7 adch7h[9:3] 0x00 adc result adc 0x73 adcsns7l r rsvd rsvd rsvd rsvd rsvd adch7l[2:0] 0x00 adc result adc 0x74 adcsns8h r gain8 adch8h[9:3] 0x00 adc result adc 0x75 adcsns8l r rsvd rsvd rsvd rsvd rsvd adch8l[2:0] 0x00 adc result adc 0x76 adcsns9h r gain9 adch9h[9:3] 0x00 adc result table 74. spi register map block address register name r/w d7 d6 d5 d4 d3 d2 d1 d0 initial function
analog integrated circuit device data freescale semiconductor 105 900844 functional device operation spi register map adc 0x77 adcsns9l r rsvd rsvd rsvd rsvd rsvd adch9l[2:0] 0x00 adc result adc 0x78 adcsns10h r gain10 adch10h[9:3] 0x00 adc result adc 0x79 adcsns10l r rsvd rsvd rsvd rsvd rsvd adch10l[2:0] 0x00 adc result adc 0x7a adcsns11h r gain11 adch11h[9:3] 0x00 adc result adc 0x7b adcsns11l r rsvd rsvd rsvd rsvd rsvd adch11l[2:0] 0x00 adc result adc 0x7c adcsns12h r gain12 adch12h[9:3] 0x00 adc result adc 0x7d adcsns12l r rsvd rsvd rsvd rsvd rsvd adch12l[2:0] 0x00 adc result adc 0x7e adcsns13h r gain13 adch13h[9:3] 0x00 adc result adc 0x7f adcsns13l r rsvd rsvd rsvd rsvd rsvd adch13l[2:0] 0x00 adc result adc 0x80 adcsns14h r gain14 adch14h[9:3] 0x00 adc result adc 0x81 adcsns14l r rsvd rsvd rsvd rsvd rsvd adch14l[2:0] 0x00 adc result adc 0x82 adcsns15h r gain15 adch15h[9:3] 0x00 adc result adc 0x83 adcsns15l r rsvd rsvd rsvd rsvd rsvd adch15l[2:0] 0x00 adc result adc 0x84 adcsns16h r gain16 adch16h[9:3] 0x00 adc result adc 0x85 adcsns16l r rsvd rsvd rsvd rsvd rsvd adch16l[2:0] 0x00 adc result adc 0x86 adcsns17h r gain17 adch17h[9:3] 0x00 adc result adc 0x87 adcsns17l r rsvd rsvd rsvd rsvd rsvd adch17l[2:0] 0x00 adc result adc 0x88 adcsns18h r gain18 adch18h[9:3] 0x00 adc result adc 0x89 adcsns18l r rsvd rsvd rsvd rsvd rsvd adch18l[2:0] 0x00 adc result adc 0x8a adcsns19h r gain19 adch19h[9:3] 0x00 adc result adc 0x8b adcsns19l r rsvd rsvd rsvd rsvd rsvd adch19l[2:0] 0x00 adc result adc 0x8c adcsns20h r gain20 adch20h[9:3] 0x00 adc result adc 0x8d adcsns20l r rsvd rsvd rsvd rsvd rsvd adch20l[2:0] 0x00 adc result adc 0x8e adcsns21h r gain21 adch21h[9:3] 0x00 adc result adc 0x8f adcsns21l r rsvd rsvd rsvd rsvd rsvd adch21l[2:0] 0x00 adc result adc 0x90 adcsns22h r gain22 adch22h[9:3] 0x00 adc result adc 0x91 adcsns22l r rsvd rsvd rsvd rsvd rsvd adch22l[2:0] 0x00 adc result adc 0x92 adcsns23h r gain23 adch23h[9:3] 0x00 adc result adc 0x93 adcsns23l r rsvd rsvd rsvd rsvd rsvd adch23l[2:0] 0x00 adc result adc 0x94 adcsns24h r gain24 adch24h[9:3] 0x00 adc result adc 0x95 adcsns24l r rsvd rsvd rsvd rsvd rsvd adch24l[2:0] 0x00 adc result adc 0x96 adcsns25h r gain25 adch25h[9:3] 0x00 adc result adc 0x97 adcsns25l r rsvd rsvd rsvd rsvd rsvd adch25l[2:0] 0x00 adc result adc 0x98 adcsns26h r gain26 adch26h[9:3] 0x00 adc result adc 0x99 adcsns26l r rsvd rsvd rsvd rsvd rsvd adch26l[2:0] 0x00 adc result adc 0x9a adcsns27h r gain27 adch27h[9:3] 0x00 adc result adc 0x9b adcsns27l r rsvd rsvd rsvd rsvd rsvd adch27l[2:0] 0x00 adc result adc 0x9c adcsns28h r gain28 adch28h[9:3] 0x00 adc result adc 0x9d adcsns28l r rsvd rsvd rsvd rsvd rsvd adch28l[2:0] 0x00 adc result adc 0x9e adcsns29h r gain29 adch29h[9:3] 0x00 adc result adc 0x9f adcsns29l r rsvd rsvd rsvd rsvd rsvd adch29l[2:0] 0x00 adc result adc 0xa0 adcsns30h r gain30 adch30h[9:3] 0x00 adc result adc 0xa1 adcsns30l r rsvd rsvd rsvd rsvd rsvd adch30l[2:0] 0x00 adc result adc 0xa2 adcsns31h r gain31 adch31h[9:3] 0x00 adc result adc 0xa3 adcsns31l r rsvd rsvd rsvd rsvd rsvd adch31l[2:0] 0x00 adc result table 74. spi register map block address register name r/w d7 d6 d5 d4 d3 d2 d1 d0 initial function
analog integrated circuit device data 106 freescale semiconductor 900844 functional device operation spi register map adc 0xa4 adcaddr0 r/w xmyp0 ypym0 xpxm0 adsel0[4:0] 0x00 adc selector address adc 0xa5 adcaddr1 r/w xmyp1 ypym1 xpxm1 adsel1[4:0] 0x00 adc selector address adc 0xa6 adcaddr2 r/w xmyp2 ypym2 xpxm2 adsel2[4:0] 0x00 adc selector address adc 0xa7 adcaddr3 r/w xmyp3 ypym3 xpxm3 adsel3[4:0] 0x00 adc selector address adc 0xa8 adcaddr4 r/w xmyp4 ypym4 xpxm4 adsel4[4:0] 0x00 adc selector address adc 0xa9 adcaddr5 r/w xmyp5 ypym5 xpxm5 adsel5[4:0] 0x00 adc selector address adc 0xaa adcaddr6 r/w xmyp6 ypym6 xpxm6 adsel6[4:0] 0x00 adc selector address adc 0xab adcaddr7 r/w xmyp7 ypym7 xpxm7 adsel7[4:0] 0x00 adc selector address adc 0xac adcaddr8 r/w xmyp8 ypym8 xpxm8 adsel8[4:0] 0x00 adc selector address adc 0xad adcaddr9 r/w xmyp9 ypym9 xpxm9 adsel9[4:0] 0x00 adc selector address adc 0xae adcaddr10 r/w xmyp10 ypym10 xpxm10 adsel10[4:0] 0x00 adc selector address adc 0xaf adcaddr11 r/w xmyp11 ypym11 xpxm11 adsel11[4:0] 0x00 adc selector address adc 0xb0 adcaddr12 r/w xmyp12 ypym12 xpxm12 adsel12[4:0] 0x00 adc selector address adc 0xb1 adcaddr13 r/w xmyp13 ypym13 xpxm13 adsel13[4:0] 0x00 adc selector address adc 0xb2 adcaddr14 r/w xmyp14 ypym14 xpxm14 adsel14[4:0] 0x00 adc selector address adc 0xb3 adcaddr15 r/w xmyp15 ypym15 xpxm15 adsel15[4:0] 0x00 adc selector address adc 0xb4 adcaddr16 r/w xmyp16 ypym16 xpxm16 adsel16[4:0] 0x00 adc selector address adc 0xb5 adcaddr17 r/w xmyp17 ypym17 xpxm17 adsel17[4:0] 0x00 adc selector address adc 0xb6 adcaddr18 r/w xmyp18 ypym18 xpxm18 adsel18[4:0] 0x00 adc selector address adc 0xb7 adcaddr19 r/w xmyp19 ypym19 xpxm19 adsel19[4:0] 0x00 adc selector address adc 0xb8 adcaddr20 r/w xmyp20 ypym20 xpxm20 adsel20[4:0] 0x00 adc selector address adc 0xb9 adcaddr21 r/w xmyp21 ypym21 xpxm21 adsel21[4:0] 0x00 adc selector address adc 0xba adcaddr22 r/w xmyp22 ypym22 xpxm22 adsel22[4:0] 0x00 adc selector address adc 0xbb adcaddr23 r/w xmyp23 ypym23 xpxm23 adsel23[4:0] 0x00 adc selector address adc 0xbc adcaddr24 r/w xmyp24 ypym24 xpxm24 adsel24[4:0] 0x00 adc selector address adc 0xbd adcaddr25 r/w xmyp25 ypym25 xpxm25 adsel25[4:0] 0x00 adc selector address adc 0xbe adcaddr26 r/w xmyp26 ypym26 xpxm26 adsel26[4:0] 0x00 adc selector address adc 0xbf adcaddr27 r/w xmyp27 ypym27 xpxm27 adsel27[4:0] 0x00 adc selector address adc 0xc0 adcaddr28 r/w xmyp28 ypym28 xpxm28 adsel28[4:0] 0x00 adc selector address adc 0xc1 adcaddr29 r/w xmyp29 ypym29 xpxm29 adsel29[4:0] 0x00 adc selector address table 74. spi register map block address register name r/w d7 d6 d5 d4 d3 d2 d1 d0 initial function
analog integrated circuit device data freescale semiconductor 107 900844 functional device operation spi register map adc 0xc2 adcaddr30 r/w xmyp30 ypym30 xpxm30 adsel30[4:0] 0x00 adc selector address adc 0xc3 adcaddr31 r/w xmyp31 ypym31 xpxm31 adsel31[4:0] 0x00 adc selector address rsvd 0xc4 rsvd - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xc5 rsvd - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xc6 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xc7 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xc8 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xc9 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xca - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xcb - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xcc - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xcd - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xce - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xcf - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved charger 0xd0 chrgint r rsvd rsvd batdet rsvd rsvd temp batovp rsvd 0x00 charger interrupt charger 0xd1 mchrgint r/w rsvd rsvd mbatdet rsvd rsvd mtemp mbatovp rsvd 0x00 charger interrupt mask charger 0xd2 schrgint r rsvd rsvd sbatdet rsvd rsvd stemp sbatovp rsvd 0x00 charger state charger 0xd3 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xd4 rsvd - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xd5 rsvd - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xd6 rsvd - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xd7 rsvd - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xd8 rsvd - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xd9 rsvd - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xda rsvd - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xdb rsvd - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xdc rsvd - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xdd - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xde - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xdf - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved gpio 0xe0 gpiocntl0 r/w gpidbnc0[1:0] intctl0[1:0] dataout0 datain0 dir0 drv0 0x03 gpio control gpio 0xe1 gpiocntl1 r/w gpidbnc0[1:0] intctl0[1:0] dataout0 datain0 dir0 drv0 0x03 gpio control gpio 0xe2 gpiocntl2 r/w gpidbnc0[1:0] intctl0[1:0] dataout0 datain0 dir0 drv0 0x03 gpio control gpio 0xe3 gpiocntl3 r/w gpidbnc0[1:0] intctl0[1:0] dataout0 datain0 dir0 drv0 0x03 gpio control gpio 0xe4 gpiocntl4 r/w gpidbnc0[1:0] intctl0[1:0] dataout0 datain0 dir0 drv0 0x03 gpio control gpio 0xe5 gpiocntl5 r/w gpidbnc0[1:0] intctl0[1:0] dataout0 datain0 dir0 drv0 0x03 gpio control gpio 0xe6 gpiocntl6 r/w gpidbnc0[1:0] intctl0[1:0] dataout0 datain0 dir0 drv0 0x03 gpio control gpio 0xe7 gpiocntl7 r/w gpidbnc0[1:0] intctl0[1:0] dataout0 datain0 dir0 drv0 0x03 gpio control gpio 0xe8 gpioint r gpiint7 gpiint6 gpiint5 gpiint4 gpiint3 gpiint2 gpiint1 gpiint0 0x00 gpio interrupt rsvd 0xe9 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xea - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xeb - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved table 74. spi register map block address register name r/w d7 d6 d5 d4 d3 d2 d1 d0 initial function
analog integrated circuit device data 108 freescale semiconductor 900844 functional device operation spi register map rsvd 0xec - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xed - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xee - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xef - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xf0 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xf1 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xf2 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xf3 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved gpio 0xf4 gpo r/w gpo7 gpo6 gpo5 gpo4 gpo3 gpo2 gpo1 gpo0 0x00 gpo control rsvd 0xf5 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xf6 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xf7 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved rsvd 0xf8 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved vd2 0xf9 - 0xff - - vd2 - reserved vd3 0x100 - 0x132 - - vd3 - reserved rsvd 0x133 - 0x199 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x19a - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x19b - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x19c - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x19d - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x19e - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x19f - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1a0 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1a1 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1a2 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1a3 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1a4 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1a5 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1a6 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1a7 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1a8 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1a9 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1aa - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1ab - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1ac - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1ad - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1ae fslmem1 r/w scratch[7:0] 0x00 backup memory fsl 0x1af fslmem2 r/w scratch[7:0] 0x00 backup memory fsl 0x1b0 fslmem3 r/w scratch[7:0] 0x00 backup memory fsl 0x1b1 fslmem4 r/w scratch[7:0] 0x00 backup memory fsl 0x1b2 fslmem5 r/w scratch[7:0] 0x00 backup memory table 74. spi register map block address register name r/w d7 d6 d5 d4 d3 d2 d1 d0 initial function
analog integrated circuit device data freescale semiconductor 109 900844 functional device operation spi register map fsl 0x1b3 fslmem6 r/w scratch[7:0] 0x00 backup memory fsl 0x1b4 fslmem7 r/w scratch[7:0] 0x00 backup memory fsl 0x1b5 fslmem8 r/w scratch[7:0] 0x00 backup memory fsl 0x1b6 fslmem9 r/w scratch[7:0] 0x00 backup memory fsl 0x1b7 fslmem10 r/w scratch[7:0] 0x00 backup memory fsl 0x1b8 fslmem11 r/w scratch[7:0] 0x00 backup memory fsl 0x1b9 fslmem12 r/w scratch[7:0] 0x00 backup memory fsl 0x1ba fslmem13 r/w scratch[7:0] 0x00 backup memory fsl 0x1bb fslmem14 r/w scratch[7:0] 0x00 backup memory fsl 0x1bc fslmem15 r/w scratch[7:0] 0x00 backup memory fsl 0x1bd fslmem16 r/w scratch[7:0] 0x00 backup memory fsl 0x1be - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1bf fsloutdrvcn tl1 r/w resetbdrv[1:0] pmicintdrv[1:0] vrcompbdrv[1:0] pwrgddrv[1:0] 0x00 digital outputs drive strength fsl 0x1c0 fsloutdrvcn tl2 r/w rsvd rsvd rsvd rsvd rsvd rsvd clk32kdrv[1:0] 0x04 digital outputs drive strength fsl 0x1c1 fsloutdrvcn tl3 r/w rsvd rsvd rsvd rsvd rsvd rsvd spisdodrv 0x01 digital outputs drive strength fsl 0x1c2 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1c3 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1c4 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1c5 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1c6 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1c7 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1c8 fsltontcntl1 r/w rsvd rsvd vddqtont vnntont vcctont 0xaa buck turn on time control (dvs clk) fsl 0x1c9 fslvcclatch r rsvd vidvcc[6:0] 0x7f vcc vid control fsl 0x1ca fslvnnlatch r rsvd vidvnn[6:0] 0x7f vnn vid control fsl 0x1cb fsltontcntl2 r/w rsvd rsvd rsvd rsvd v15tont rsvd v21tont rsvd 0xaa buck turn on time control (dvs clk) fsl 0x1cc fslfault1 r rsvd rsvd rsvd v15fault v21fault vddqfau lt vnnfaul t vccfault 0x00 regulator fault flag fsl 0x1cd fslfault2 r vpmicfaul t vpnl18fa ult vcc180fa ult vccafau lt vbgfault rsvd rsvd rsvd 0x00 regulator fault flag fsl 0x1ce fslfault3 r vccpfault vmmfaul t vaonfaul t vccpddr fault vccpaoa cfault rsvd rsvd vymxyfi18 fault 0x00 regulator fault flag fsl 0x1cf fslfault4 r rsvd rsvd rsvd rsvd vsdiofau lt rsvd vimg28fa ult vimg25fa ult 0x00 regulator fault flag fsl 0x1d0 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1d1 fslchrgcntl r/w rsvd rsvd rsvd vcoin[4:2] coinche n chgbyp 0x13 charger control fsl 0x1d2 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1d3 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1d4 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1d5 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1d6 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1d7 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1d8 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved table 74. spi register map block address register name r/w d7 d6 d5 d4 d3 d2 d1 d0 initial function
analog integrated circuit device data 110 freescale semiconductor 900844 functional device operation spi register map fsl 0x1d9 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1da - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1db - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1dc - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1dd - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1de fsladccntl r/w rsvd tspas adccal lsbsel batdetvc on licon chrgico n vpwrcon 0x00 adc spare channel control fsl 0x1df - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1e0 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1e1 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1e2 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1e3 - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1e4 fslpllcntl r/w rsvd rsvd rsvd pllen pll16men plldivide[2:0] 0x1b reserved rsvd 0x1e5 - 0x1fa - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1fb buck_top_lvs h_5 r/w buck_v15_ en buck_v15_pwrstg_en<6:0> 0x7f switching regulator debug fsl 0x1fc buck_top_lvs h_4 r/w buck_v21_ en buck_v21_pwrstg_en<6:0> 0x7f switching regulator debug fsl 0x1fd - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved fsl 0x1fe buck_top_lvs h_2 r/w buck_vdd q_en buck_vddq_pwrstg_en[6:0] 0x7f switching regulator debug rsvd 0x1ff - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved vd2 0x200 - 0x227 - - vd2 - reserved rsvd 0x228 - 0x2ff - - rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0x00 reserved notes 21. rsvd: reserved registers, not for customer use. 22. fsl: freescale dedicated registers for special pmic control table 74. spi register map block address register name r/w d7 d6 d5 d4 d3 d2 d1 d0 initial function
analog integrated circuit device data freescale semiconductor 111 900844 functional device operation hardware design considerations hardware design considerations external component requirement table 75. external components bom (23) component value package description qty part # manufacturer freescale package 900844 - mapbga integrated power management ic for ultra-mobile platforms for netbook computers 1 SC900844JVK freescale vcc - (0.65 - 1.2 v) / 3.5 a vid cpu buck with external fets cincc 10 f 0603 ceramic capacitor, 6.3 v, x5r 1 grm188r60j106me47d murata cocc 22 f 0603 ceramic capacitor, 4.0 v, x5r 4 amk107bj226ma-t taiyo yuden lcc 0.68 h 4x4x2 saturation current = 4.8 a for 10% drop, dcr_max = 25.3 mohm 1 xpl4020-681mlb coilcraft mhscc 46 mohm bga high side p-fet 1 fdz293p, fdc638apz or fdma291p fairchild mlscc 23 mohm bga low side n-fet 1 fdz294n, fdc637bnz or fdma430nz fairchild vnn - (0.65 - 1.2 v) / 1.6 a vid cpu buck with external fets cinnn 10 f 0603 ceramic capacitor, 6.3 v, x5r 1 grm188r60j106me47d murata conn 22 f 0603 ceramic capacitor, 4.0 v, x5r 2 amk107bj226ma-t taiyo yuden lnn 1.0 h 3.3x3.3x1.4 saturation current = 2.3 a for 10% drop, dcr_max = 55 mohm 1 lps3314-102ml coilcraft mnn 95 mohm 68 mohm microfet high side p-fet and low side n-fet housed in one package 1 fdma1032cz fairchild vddq - 1.8/1.5 v / 1.3 a buck cinddq 10 f 0603 ceramic capacitor, 6.3 v, x5r 1 grm188r60j106me47d murata coddq 22 f 0603 ceramic capacitor, 4.0 v, x5r 2 amk107bj226ma-t taiyo yuden lddq 0.50 h 2.0x2.0x1.0 saturation current = 1.8 a for 10% drop, dcr_max = 45 mohm 1 xpl2010-501ml coilcraft rfbddq15_1 (24) 681 ohm 0402 chip resistor 1% 1/10w 1 crcw0402681rfked vishay/dale rfbddq15_2 (24) 2.21 kohm 0402 chip resistor 1% 1/10w 1 crcw04022k21fked vishay/dale v21 - 2.1 v / 1.0 a buck cin21 10 f 0603 ceramic capacitor, 6.3 v, x5r 1 grm188r60j106me47d murata co21 22 f 0603 ceramic capacitor, 4.0 v, x5r 1 amk107bj226ma-t taiyo yuden l21 0.50 h 2.0x2.0x1.0 saturation current = 1.8 a for 10% drop, dcr_max = 45 mohm 1 xpl2010-501ml coilcraft v15 - 1.5 v(or 1.6 v) / 1.5 a buck cin15 10 f 0603 ceramic capacitor, 6.3 v, x5r 1 grm188r60j106me47d murata co15 22 f 0603 ceramic capacitor, 4.0 v, x5r 2 amk107bj226ma-t taiyo yuden l15 0.50 h 2.0x2.0x1.0 saturation current = 1.8 a for 10% drop, dcr_max = 45 mohm 1 xpl2010-501ml coilcraft notes 23. throughout this document, there are references to non-freescal e components. freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. while freescale offers component recommendations in this configuration, it is the cu stomer?s responsibility to validate their application. 24. to operate the vddq as a 1.5 v buck regulator, the recommended resistors, rfbddq15_1 and rfbddq15_2 are needed in the feedback path, as shown in figure 28 .
analog integrated circuit device data 112 freescale semiconductor 900844 functional device operation hardware design considerations vbg - 1.25 v/2.0 ma ldo & vcca - 1.5 v/150 ma ldo cin1p8 100 nf 0201 ceramic capacitor, 6.3 v, x5r 1 grm033r60j104ke19d murata cobg 1.0 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j105me19d murata cocca 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata vcc180- 1.8 v/390 ma ldo & vpnl18- 1.8 v/225 ma ldo & - 1.8 v/50 ma ldo cin2p1 0.47 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j474ke19d murata cocc180 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata copnl18 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata copmic 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata vymxyfi18 - (ymx:1.8 v/200 ma - yfi:1.8 v/200 ma) ldo cinymxyfi18 100 nf 0201 ceramic capacitor, 6.3 v, x5r 1 grm033r60j104ke19d murata coymxyfi18 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata vccpaoac- 1.05 v/155 ma ldo & vccpddr - 1.05 v/60 ma ldo & vaon - 1.2 v/250 ma ldo &vmm- 1.2 v/5.0 ma ldo & vccp - 1.05 v/445 ma ldo cin1p5 0.47 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j474ke19d murata coccpaoac 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata coccpddr 1.0 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j105me19d murata coaon 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata comm 1.0 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j105me19d murata coccp 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata vimg25- 2.5 v/80 ma ldo & vimg28- 2.8 v/225 ma ldo cinimg 100 nf 0201 ceramic capacitor, 6.3 v, x5r 1 grm033r60j104ke19d murata coimg25 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata coimg28 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata vpnl33 - 3.3 v/100 ma switch copnl33 100 nf 0201 ceramic capacitor, 6.3 v, x5r 1 grm033r60j104ke19d murata vsdio - 3.3 v/215 ma switch or 1.8 v/215 ma ldo cinsdio 100 nf 0201 ceramic capacitor, 6.3 v, x5r 1 grm033r60j104ke19d murata cosdio 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata rsdio 0 ohm 0402 chip resistor, 1% 1 erj-2ge0r00x panasonic msdio 95 mohm sc70 pfet, switch 1 fdg332pz fairchild internal supplies ccore 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata ccoredig 2.2 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j225me15d murata ccoreref 100 nf 0201 ceramic capacitor, 6.3 v, x5r 1 grm033r60j104ke19d murata input power path rntcev 10 kohm 0201 chip resistor, 1% 1 erj-1gef1002c panasonic rntc 10 kohm 0201 chip resistor, 1% 1 erj-1gef1002c panasonic cbat 22 f 0805 ceramic capacitor, 10 v, x5r 2 lmk212bj226mg-t taiyo yuden coin cell ccoin 100 nf 0201 ceramic capacitor, 6.3 v, x5r 1 grm033r60j104ke19d murata table 75. external components bom (23) component value package descript ion qty part # manufacturer
analog integrated circuit device data freescale semiconductor 113 900844 functional device operation hardware design considerations adc cadref 1.0 f 0402 ceramic capacitor, 6.3 v, x5r 1 grm155r60j105me19d murata oscillator and real time clock - rtc xtalrtc 32.768 khz 3.2x1.5x0.9 crystal 32.768 khz 12.5 pf smd 1 abs07-32.768khz-t abracon cxtalrtc1 22 pf 0201 ceramic capacitor, 25 v, c0g 1 grm0335c1e220jd01d murata cxtalrtc2 22 pf 0201 ceramic capacitor, 25 v, c0g 1 grm0335c1e220jd01d murata gpios & gpos & power button rpullupx (25) 100 kohm 0201 chip resistor, 1% - pull-up resistors for od configured gpios 0 erj-1gef1003c panasonic total component count 62 notes 25. this is a recommended resistor when required by a specific gpio. table 75. external components bom (23) component value package descript ion qty part # manufacturer
analog integrated circuit device data 114 freescale semiconductor 900844 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. jvk suffix 338-pin 98asa10841d revision 0
analog integrated circuit device data freescale semiconductor 115 900844 packaging package dimensions jvk suffix 338-pin 98asa10841d revision 0
analog integrated circuit device data 116 freescale semiconductor 900844 packaging package dimensions package mechanical outline drawing the package style is an 11x11 fine interstitial pitch, thin prof ile pbga. the package has a semi populated matrix that includes 338 balls. the ball count includes 322 assigned signal pins and four sets of 4 corner balls. package assembly recommendations for improved protection against mechanical shock, freescale recommends applying corner glue to the mounted 900844 mapbga package. this corner glue applic ation is described in the an3954 - "pcb layout guidelines for sc900841 and sccsp900842" application note. freescale?s preferred material for the corner glue application is the loctite 3128 board level adhesive, applied at a 0 or 45 dispense angle in a continuous motion, and with the fillet l ength extended to a minimum of 3 ball rows and columns, at each corner.
analog integrated circuit device data freescale semiconductor 117 900844 revision history revision history revision date description of changes 1.0 8/2010 ? initial release ? ball map updates ? fix default values for various vr control registers. ? fix package suffix to ?jvk? ? freescale format, form and style corrections. 2.0 5/2011 ? no parametrics were altered. only various adjus tments, corrections, and clarifications were made to text, tables, and images, for improved accuracy.
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2010-2011. all rights reserved. sc900844 rev. 2.0 5/2011 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part.

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