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rev 3.0 2/11/04 1 of 27 www.xicor.com preliminary information real time clock/calendar with event/timestamp detection & alarms X1209 features real time clock/calendar ? racks time in hours, minutes, and seconds ? ay of the week, day, month, and year security and event functions ? amper detection with time stamp event alarm operation to 1.8v ? ow power operations. selectable sampling rates. selectable glitch ?ter on event monitor input pulse interrupt for periodic irq selectable dividers for various frequency out- put ? polled alarm settable on the second, minute, hour, day of the week, day, or month pulse interrupt for periodic irq battery switch or super cap input battery backup sram timing and alarm regis- ters ? o wer failure detection oscillator compensation on chip ? bytes general purpose sram 2-wire interface 400khz data transfer rate ? ow power cmos ? 1? operating current small package options 10-lead msop and fcp (flip chip) applications security or anti-tampering applications ? anel / enclosure status ? arranty reporting time stamping applications event recording / data logging ? atrol/security checkpoint management ? acility safety check (fire or light equipment) ? r oduction line check & management ? ending machine management other: utility meters, hvac equipment, audio / video components, set top box / television, modems, network routers, hubs, switches, bridges, cellular infrastructure equipment, fixed broadband wireless equipment, pagers / pda, pos equipment, test meters / fixtures, data acquisition systems, of?e automation (copiers, fax), home appliances, computer products, other industrial / medical / automotive low power, battery backup, 2-wire block diagram x1 x2 oscillator f requency timer logic divider calendar 32.768khz control registers time k eeping registers alarm regs compare mask irq / fout control decode logic alarm (sram*) (sram*) scl sda serial interface decoder interrupt registers status (sram*) alarm alarm (sram*) osc compensation *battery backup sram general purpose sram enable vbat vcc vss vcc / batt switch evin evdet event detector new features rtc with time stamp event detection to 1.8v
2 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 pin descriptions pin assignments pin number symbol brief description msop fcp 1x1 x1. the x1 pin is the input of an inverting amplifier. an external 32.768khz quartz crys- tal is used with the X1209 to supply a timebase for the real time clock. the device can also be driven directly from a 32.768khz source. internal compensation circuitry is includ- ed to form a complete oscillator circuit with accuracy over the operating temperature range from -40c to +85c. the oscillator compensation network can be used either calibrate the crystal pull-over accuracy over temperature during manufacturing calibration or used with external temperature sensor and microcontroller for active compensation. 2x2 x2. the x2 pin is the output of an inverting amplifier. an external 32.768khz quartz crystal is used with the X1209 to supply a timebase for the real time clock. the device can also be driven directly from a 32.768khz source. internal compensation circuitry is in- cluded to form a complete oscillator circuit with accuracy over the operating temperature range from -40c to +85c. the oscillator compensation network can be used either cali- brate the crystal pull-over accuracy over temperature during manufacturing calibration or used with external temperature sensor and microcontroller for active compensation. 3v bat v bat . this input provides a backup supply voltage to the device. v bat supplies power to the device in the event the v cc supply fails. this pin can be connected to a battery, a supercap or tied to ground if not used. 4v ss chip ground pin 5 evin event input (evin). the evin is an input pin that is used to detect an externally mon- itored event. when a high signal is present at the evin pin an ?vent?is detected. upon a valid detection, the X1209 has the option to 1) provide a flag signal at the ev- det pin (open drain, active low), 2) record a time stamp when the event occurred, 3) set a status bit (evt bit). note that on detection the evt bit is set then the evdet pin is pulled low. the evin pin can be optionally connected (see evineb bit) to an internal pull up cur- rent source that operates to 1ua (always on mode). user selectable event sampling modes are also available for low power applications with 1/4-hz, 1-hz and 2-hz sam- ple detection rates. the evin input is pulsed on/off when in sampling mode for pow- er savings advantages. 6 evdet 7 sda serial data (sda). sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collector outputs. the input buffer is always active (not gated). an open drain output requires the use of a pull-up resistor. the output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. the circuit is designed for 400khz 2-wire interface speeds. disabled when the backup power sup- ply on the v bat pin is activated. 10-pin msop X1209 nc = no internal connection 10-lead fcp bump chip scale tbd 1 2 3 4 9 10 8 7 x1 x2 v bat v cc irq / fout scl sda v ss 5 6 evin evdet
3 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 8 scl serial clock (scl). the scl input is used to clock all data into and out of the device. the input buffer on this pin is always active (not gated). disabled when the backup power supply on the v bat pin is activated. 9 irq / fout interrupt output ?irq , frequency output?fout. multi-functional pin set via configuration register that can be used as interrupt or frequency output pin. interrupt mode. this is an interrupt signal output. this signal notifies a host processor that an alarm has occurred and requests action. it is an open drain active low out- put.this mode is selected via the frequency out control bits. frequency output mode. this is an frequency output pin. the frequency output is user selectable and enabled via the 2-wire bus. this mode is selected via the frequency out control bits. 10 v cc chip supply pin. pin number symbol brief description msop fcp
preliminary information X1209 4 of 27 rev 3.0 2/11/04 www.xicor.com dc operating characteristics - rtc (temperature = -40? to +85?, unless otherwise stated.) operating characteristics - rtc symbol parameter conditions min typ max unit notes v cc main power supply 2.0 5.5 v vbat backup power supply 1.8 5.5 v v mw voltage trip memory write valid 2.0 v trip point for sup- ply switch over v cb switch to backup supply v cc < v mw vbat - 50 vbat + 50 mv v bc switch to main supply v cc > v mw vbat vbat + 50 mv v hyst1 voltage hysteresis ?0 mv vcc to vbat v hyst2 voltage hysteresis +50 mv vbat to vcc symbol parameter conditions min typ max unit notes i cc1 active supply current (sram read) v cc = 2.0v 1 a 1, 5, 7, 14 v cc = 2.7v 1 a v cc = 5.0v 1 a i cc2 active supply current (sram write) v cc = 2.0v 2 v cc = 2.7v 2 ma 2, 5, 7, 14 v cc = 5.0v 2 ma i cc3 main timekeeping current v cc = 2.0v 500 700 na v cc = 2.7v 500 700 na 3, 7, 8, 14, 15 v cc = 5.0v 500 700 na i back timekeeping current (during v bat supply on) vbat = 1.8v 250 500 na 3, 6, 9, 14, 15 vbat = 3.0v 250 500 na i lb vbat leakage current vbat = 1.8v 25 50 na vbat = 3.0v 25 50 i li input leakage current 10 ? 10 i lo output leakage current 10 ? 10 v il input low voltage -0.5 v cc x 0.2 or vbat x 0.2 v13 v ih input high voltage v cc x 0.7 or vbat x 0.7 v cc + 0.5 or vbat + 0.5 v13 v ol output low voltage for sda/irq v cc = 2.7v 0.4 v 11 v cc = 5.5v 0.4 absolute maximum ratings t emperature under bias ................... -65? to +135? storage temperature......................... -65? to +150? v oltage on v cc , vbat and irq pin (respect to ground) ............................-0.5v to 7.0v v oltage on scl, sda, x1 and x2 pin (respect to ground) ............... -0.5v to 7.0v or 0.5v lead temperature (soldering, 10 sec) ...............300? stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this spec- i?ation is not implied. exposure to absolute maximum r ating conditions for extended periods may affect device reliability.
5 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 dc operating characteristics - event detection circuits (temperature = -40? to +85?, unless otherwise stated.) operating characteristics - event detection circuits symbol parameter conditions min typ max unit notes v ih voltage input logic high for evin pin v v il voltage input logic low for evin pin v v oh voltage output logic high for evdet pin v v ol voltage output logic high for evdet pin v r sw switch resistance on evin pin ohm symbol parameter conditions min typ max unit notes i cc4 active supply current (sampled event detection) evin always on 1.25 ? evin: 1/4 hz ? evin: 1 hz ? evin: 2 hz ? i cc5 standby current (evin) evin disabled na i l input leakage current evdet pin t evt1 time evin valid high to evt bit valid high vcc = x + t hys vbat = y + t hys t evt2 time evt bit valid high to evdet pin valid low vcc = vbat = t evt3 time from evt bit valid high to rtc stamp valid vcc = vbat = t hys time based hysteresis on evin pin 0ms 3.9 15.625 31.25 % t pulse sample rate of evin pin 0 hz 0.25 1 2 %
6 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 notes: (1) the device enters the active state after any start, and remains active: for 9 clock cycles if the device select bits in the slave address byte are incorrect or until 200ns after a stop ending a read or write operation. (2) the device enters the program state 200ns after a stop ending a write operation and continues for t wc . (3) the device goes into the timekeeping state 200ns after any stop; or 9 clock cycles after any start that is not followed by t he correct device select bits in the slave address byte. (4) for reference only and not tested. (5) v il = v cc x 0.1, v ih = v cc x 0.9, f scl = 400khz (6) v cc = 0v (7) vbat = 0v (8) v sda = v scl =v cc , others = gnd or v cc (9) v sda =v scl =vbat, others = gnd or vbat, note sda and scl disabled internally when v bat supply is on (10) v sda = gnd or v cc , v scl = gnd or v cc (11) i ol = 3.0ma at 5v, 1ma at 2.7v (13) threshold voltages based on the higher of vcc or vbat. (14) using recommended crystal and oscillator network applied to x1 and x2 (25?). (15) typical values are for t a = 25? capacitance t a = 25?, f = 1.0 mhz, v cc = 5v notes: (1) this parameter is not 100% tested. (2) the input capacitance between x1 and x2 pins can be varied between 5pf and 19.75pf by using analog trimming registers ac characteristics - serial bus ac test conditions figure 1. standard output load for testing the device with v cc = 5.0v symbol parameter max. units test conditions c out (1) output capacitance (sda, irq )10pfv out = 0v c in (1) input capacitance (scl) 10 pf v in = 0v input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load sda 1533 ? 100pf 5.0v f or v ol = 0.4v and i ol = 3 ma equivalent ac output load circuit for v cc = 5v 1316 ? 5.0v irq 100pf 806 ?
7 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 ac specifications - serial bus (t a = -40? to +85?, v cc = +2.7v to +5.5v, unless otherwise specified.) notes: (1) this parameter is not 100% tested. (2) cb = total capacitance of one bus line in pf. timing diagrams bus timing symbol parameter min. max. units f scl scl clock frequency 400 khz t in pulse width suppression time at inputs 50 (1) ns t aa scl low to sda data out valid 0.9 s t buf time the bus must be free before a new transmission can start 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh data output hold time 50 ns t r sda and scl rise time 20 +.1cb (1)(2) 300 ns t f sda and scl fall time 20 +.1cb (1)(2) 300 ns cb capacitive load for each bus line 400 pf t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r
8 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 write cycle timing power up timing notes: (1) delays are measured from the time v cc is stable until the speci?d operation can be initiated. these parameters are not 100% tested. v cc slew rate should be between 0.2mv/?ec and 50mv/?ec. (2) typical values are for t a = 25? and v cc = 5.0v symbol parameter min. typ. (2) max. units t pur (1) time from power up to read 1 ms t puw (1) time from power up to write 5 ms scl sda t wc 8th bit of last byte ack stop condition start condition
9 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 description the X1209 device is a low power real time clock with crystal and timing compensation, tamper or event detection, clock/calendar, one polled alarm, power indi- cator, periodic and polled alarms and battery backup s witch. the oscillator uses an external, low-cost 32.768khz crystal. the real-time clock keeps track of time with separate registers for hours, minutes, and seconds. the calendar has separate registers for date, month, y ear and day-of-week. the calendar is correct through 2099, with automatic leap year correction. the powerful alarm can be set to any clock/calendar v alue for a match. for instance, every minute, every t uesday, or 5:23 am on march 21. the alarm can be polled in the status register or provide a hardware interrupt (irq pin). there is a repeat mode for the alarms allowing a periodic interrupt of 60-seconds, 1- hour, 1-day, once-a-week, etc. the device offers a backup power input pin. this vbat pin allows the device to be backed up by battery or supercap. the entire X1209 device is fully operational from 2.0v to 5.5 volts and the clock/calendar portion of the X1209 device remains fully operational down to 1.8 v olts (standby mode). the event detection function can be used for tamper detection, security or other chassis or generic system monitoring. upon a valid event detection, the X1209 provides the following options: 1) to issue an event out- put signal pin (evdet ), 2) to sets an event detection bit (evt bit) in the status register and 3) to store the timestamp when the event occured. the event monitor can function in both main vcc and battery backup modes. for low power savings the event monitor can be con?ured for various input detection rates. the ev ent input monitor pin (evin) also has a selectable glitch ?ter to avoid switch de-bouncing. pin description serial clock (scl) the scl input is used to clock all data into and out of the device. the input buffer on this pin is always active (not gated). disabled when the backup power supply on the v bat pin is activated. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collector outputs. the input buffer is always active (not gated). an open drain output requires the use of a pull-up resistor. the output circuitry controls the fall time of the output signal with the use of a slope controlled pull- down. the circuit is designed for 400khz 2-wire inter- f ace speeds. disabled when the backup power supply on the v bat pin is activated. v bat this input provides a backup supply voltage to the device. v bat supplies power to the device in the event the v cc supply fails. this pin can be connected to a battery, a supercap or tied to ground if not used. interrupt output ?irq , frequency output?fout multi-functional pin set via con?uration register that can be used as interrupt or frequency output pin. interrupt mode. this is an interrupt signal output. this signal noti?s a host processor that an alarm has occurred and requests action. it is an open drain active low output.this mode is selected via the frequency out control bits. f requency output mode. this is an frequency output pin. the frequency output is user selectable and enabled via the 2-wire bus. this mode is selected via the frequency out control bits. x1, x2 the x1 and x2 pins are the input and output, respec- tively, of an inverting ampli?r. an external 32.768khz quartz crystal is used with the X1209 to supply a time- base for the real time clock. the device can also be driven directly from a 32.768khz source. internal com- pensation circuitry is included to form a complete oscilla- tor circuit with accuracy over the operating temperature r ange from -40c to +85c. the oscillator compensation network can be used either calibrate the crystal pull-over accuracy over temperature during manufacturing calibra- tion or used with external temperature sensor and micro- controller for active compensation.
preliminary information X1209 10 of 27 rev 3.0 2/11/04 www.xicor.com event input (evin) the evin is an input pin that is used to detect an exter- nally monitored event. when a high signal is present at the evin pin an ?vent is detected. upon a valid detection, the X1209 has the option to 1) provide a ?g signal at the evdet pin (open drain, active low), 2) record a time stamp when the event occurred, 3) set a status bit (evt bit). note that on detection the evt bit is set then the evdet pin is pulled low. the evin pin can be optionally connected (see evineb bit) to an internal pull up current source that operates to 1ua (always on mode). user selectable ev ent sampling modes are also available for low power applications with 1/4-hz, 1-hz and 2-hz sample detec- tion rates. the evin input is pulsed on/off when in sampling mode for power savings advantages. the evin also has a user selectable time based hys- tersis ?ter (see ehys bits) to lter out circuit de- bouncing and noise during an event detection. the evin signal must be high for the duration of the time ?- ter. the time ?ter can be selected from 0 time delay (no time based hysteresis) to 3.9ms (2048hz), 15.625ms (512hz), or 31.25ms (256hz). the event detection circuit can be user enabled/dis- abled (see even bit) and has the option to be opera- tional in battery backup modes (see evbatb bit). when the event detection is disabled the evin pin is gated off. see functional description for more details. figure 2. recommended crystal connection vcc, vss chip supply and ground pins. pin out x1 x2 10-pin msop X1209 nc = no internal connection 10-lead fcp bump chip scale tbd 1 2 3 4 9 10 8 7 x1 x2 v bat v cc irq / fout scl sda v ss 5 6 evin evdet
11 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 functional description power control operation the power control circuit accepts a v cc and a vbat input. many types of batteries can be used with the xicor rtc products. 3.0v or 3.6v lithium batteries are appropriate, and sizes are available that can power a xicor rtc device for up to 10 years. another option is to use a supercapacitor for applications where vcc may disappear intermittently for short periods of time. see application for more information. normal mode (v cc ) to battery backup mode (v bat ). to transition from vcc to vbat source, the following conditions must exist: condition 1: v cc < v bat - v hys , where v hys1 is +/- 50mv. and condition 2: v cc < v mw , where v mw is ~1.8v. battery backup mode (v bat ) to normal mode (v cc ). to transition from vbat to vcc source, the following conditions must exist: v cc > v mw + v hys2 , where v hys2 is + 50mv. power failure detection. the X1209 provides a real time clock failure bit (rtcf) to detect total power failure low power modes. the X1209... other notes. the 2-wire bus is inactive in battery backup mode. the status register and the alarm registers are opera- tional during battery backup mode. all the inputs and outputs of the X1209 are active during battery backup mode unless disabled via the control register. the user sram is operational in battery backup mode down to 1.8v. power ramp rate the power ramp rate recommended is.... real time clock operation the real time clock (rtc) uses an external 32.768khz quartz crystal to maintain an accurate inter- nal representation of second, minute, hour, day, date, month, and year. the rtc has leap-year correction. the clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or am/pm fo r mat. when the X1209 powers up after the loss of both v cc and vbat, the clock will not operate until at least one byte is written to the clock register. accuracy of the real time clock the accuracy of the real time clock depends on the frequency of the quartz crystal that is used as the time base for the rtc. since the resonant frequency of a crystal is temperature dependent, the rtc perfor- mance will also be dependent upon temperature. the frequency deviation of the crystal is a function of the turnover temperature of the crystal from the crystals nominal frequency. for example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. these parameters are available from the crystal manufacturer. xicors rtc family provides on-chip crys- tal compensation networks to adjust load-capacitance to tune oscillator frequency from +185 ppm to ?4 ppm (calculated). for more detail information see the appli- cation notes. standard and pulse interrupt alarm modes the alarm mode is enabled via the alme bit. choos- ing standard and pulse (repetitive) interrupt alarm mode is selected via the im bit. note that when the fre- quency output function is enabled the alarm function is disabled. the standard alarm allows for time alarms for time, date, day of the week and year. when a time alarm occurs a irq pin will be pulled low and the alarm sta- tus bit (alm) will be set to ?? the pulsed interrupt mode allows for repetitive or recurring alarm functionality. hence an repetitive or recurring alarm can be set for every n th second, or n th minute, or n th hour, or n th date, or for the same day of the week. the pulsed interrupt mode can be consid- ered a repetitive interrupt mode, with the repetition rate set by the time setting of the alarm. during a pulsed interrupt mode, the irq pin will be pulled low for 250ms and the alarm status bit (alm) will be set to ??
preliminary information X1209 12 of 27 rev 3.0 2/11/04 www.xicor.com note the alm bit can be reset by the user or cleared automatically using the auto reset mode (see arst bit). the alarm function can be enabled / disable during battery backup mode using the fobatb bit. frequency output mode the X1209 has the option to provide a frequency out- put signal using the irq / fout pin. the frequency output mode is bit by con?uring the using the fo bits to select 16 possible output frequency values from 0 hz to 32 khz. the frequency output can enabled / dis- able during battery backup mode using the fobatb bit. general purpose user sram the X1209 provides 2 bytes of user sram. the sram will also operate in battery backup mode. however the 2-wire bus is disabled in battery backup mode. 2-wire serial interface the X1209 provides a 2-wire serial bus interface pro- vides access to the control and status registers, and the user sram. the 2-wire serial interface is compati- b le with other industry 2-wire serial bus protocols using a bi-directional data signal (sda) and a clock signal (scl). oscillator compensation the X1209 provides the option of timing correction due to temperature variation of the crystal oscillator for either manufacturing calibration or active calibration. the total possible compensation is +167ppm to -94ppm (calculated). compensation can be imple- mented using the following: 1) the X1209 provides a digital trimming register (dtr register) that can be used for adjust the timing counter by ?0 ppm. 2) in addition, the X1209 provides an analog trimming (atr) registers that can be used to adjust an on-chip digital capacitor for oscillator capacitance trimming. the digital capacitor is selectable from a range of 9pf to 40.5pf (based upon 32.758 khz) this translates to calculated compensation from approximately +127 ppm to -34 ppm. an optional circuit is provided to allow for capacitance adjustment of the crystal capacitance when the X1209 s witches from v cc to battery backup mode. event / tamper monitor and detection the X1209 provides a event detection and alarm func- tion to be used in a wide variety of applications ranging from security, warranty monitoring, data collection and recording. the tamper detect input pin, evin, can be used as a ev ent or tamper detection input of an external switch (mechanical or electronic). when the evin pin is a v alid high, the X1209 provides the following detection options: 1) record the time of the event detection, 2) issue a event detection alarm (via the evdet pin) and/ or 3) set an event detection bit (evt bit) in the status register. to allow for ?xibility of external switches used at the evin pin, the internal pullup (~1ua in full on mode) can be disabled/enabled. this will allow for external pullup currents and allow more ?xibility depending on the capacitive and resistive loading at the evin pin. a noise ?ter option is also provided for the event moni- tor circuit. the evin pin has a time base ?ter where the evin signal must be stable for the given time ?ter to trigger a valid detection. the time hysteresis ?ter can vary from 0, 3.9ms, 15.62ms or 31.25ms. f or low power applications, the event monitor can be sampled at a user selectable rate. the evin pin can be always on or periodically sampled every 1/4, 1, or 2 hz. the X1209 can operate independently or in conjunc- tion with a microcontroller for low power operation modes or in battery backup modes. the event detection circuits operate is either main vcc power or battery backup mode.
13 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 register description clock/control registers (ccr) the control/clock registers are located in an area accessible following a slave byte of ?101111x and reads or writes to addresses [0000h:0013h]. (note: 014:015h are reserved for manufacturing purposes) the de?ed addresses and default values are described in the table 1. writing to and reading from the unde?ed addresses are not recommended. ccr access the contents of the ccr can be modi?d by perform- ing a byte or a page write operation directly to any address in the ccr. prior to writing to the ccr (except the status register). the ccr is divided into 5 sections. these are: 1. real time clock (7 bytes): 00h to 06h addresses. 2. control and status (5 bytes): 07h to 0b addresses. 3. alarm (6 bytes): 0ch to 11h addresses. 4. user sram (2 bytes): 12h to 13h addresses. 5. reserved for manufacturing (2 byte): 14h to 15h addresses. each register is read and written through buffers. sram write capability is allowable into the rtc regis- ters (00h to 06h) only when the wrtc bit is set after a v alid write operation and stop bit. a sequential read or page write operation provides access to the contents of only one section of the ccr per operation. access to another section requires a new operation. continued reads or writes, once reaching the end of a section, will wrap around to the start of the section. a read or write can begin at any address in the ccr. it is not necessary to set the wrtc bit prior to writing into the control and status, alarm, and user sram reg- isters. the device supports a single byte read or write only. continued reads or writes from this section termi- nates the operation. table 1. register memory map - clock and control registers (ccr) addr. type reg name bit range default 76 543210 00 rtc (sram) sc 0 sc22 sc21 sc20 sc13 sc12 sc11 sc10 0-59 00h 01 mn 0 mn22 mn21 mn20 mn13 mn12 mn11 mn10 0-59 00h 02 hr mil 0 hr21 hr20 hr13 hr12 hr11 hr10 0-23 00h 03 dt 0 0 dt21 dt20 dt13 dt12 dt11 dt10 1-31 00h 04 mo 0 0 0 mo20 mo13 mo12 mo11 mo10 1-31 00h 05 yr yr23 yr22 yr21 yr20 yr13 yr12 yr11 yr10 0-99 00h 06 dw 0 0 0 0 0 dw2 dw1 dw0 0-6 00h 07 control / status sr arst xtoscb reserved wrtc evt alm bat rtcf n/a 01h 08 int im alme lpmode fobatb fo3 fo2 fo1 fo0 n/a 00h 09 ev evienb evbatb rtchlt even ehys1 ehys0 esmp1 esmp0 n/a 00h 0a atr bmatr1 bmatr0 atr5 atr4 atr3 atr2 atr1 atr0 n/a 00h 0b dtr reserved reserved reserved reserved reserved dtr2 dtr1 dtr0 n/a 00h 0c alarm sca esca asc22 asc21 asc20 asc13 asc12 asc11 asc10 00-59 00h 0d mna emna amn22 amn21 amn20 amn13 amn12 amn11 amn10 00-59 00h 0e hra ehra 0 ahr21 ahr20 ahr13 ahr12 ahr11 ahr10 0-23 00h 0f dta edta 0 adt21 adt20 adt13 adt12 adt11 adt10 0-31 00h 10 moa emoa 0 0 amo20 amo13 amo12 amo11 amo10 1-12 00h 11 dwa edwa 0 0 0 0 adw12 adw11 adw10 0-6 00h 12 user usr1 usr17 usr16 usr15 usr14 usr13 usr12 usr11 usr10 n/a 00h 13 usr2 usr27 usr26 usr25 usr24 usr23 usr22 usr21 usr20 n/a 00h 14 reserved for internal use only 15
preliminary information X1209 14 of 27 rev 3.0 2/11/04 www.xicor.com the state of the ccr can be read by performing a ran- dom read at any address in the ccr at any time. this returns the contents of that register location. additional registers are read by performing a sequential read. the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. a sequential read of the ccr will not result in the output of data from the memory array. at the end of a read, the master supplies a stop condition to end the operation and free the bus. after a read of the ccr, the address remains at the previous address +1 so the user can execute a current address read of the ccr and continue reading the next register. real time clock registers addresses [00 hex to 06hex] clock/calendar registers (sc, mn, hr, dt, mo, yr) these registers depict bcd representations of the time. as such, sc (seconds) and mn (minutes) range from 00 to 59, hr (hour) can be either a 12-hour or 24- hour mode, (mil bit = 0) the hr provides 1 to 12 with an am or pm indicator (h21 bit) or 0 to 23 (with mil bit = 1), dt (date) is 1 to 31, mo (month) is 1 to 12, yr (year) is 0 to 99. date of the week register (dw) this register provides a day of the week status and uses three bits dw2 to dw0 to represent the seven days of the week. the counter advances in the cycle 0- 1-2-3-4-5-6-0-1-2-?the assignment of a numerical v alue to a speci? day of the week is arbitrary and may be decided by the system software designer. the default value is de?ed as ?? 24 hour time if the mil bit of the hr register is 1, the rtc uses a 24-hour format. if the mil bit is 0, the rtc uses a 12- hour format and h21 bit functions as an am/pm indica- tor with a ? representing pm. the clock defaults to standard time with h21=0. leap years leap years add the day february 29 and are de?ed as those years that are divisible by 4. years divisible by 100 are not leap years, unless they are also divisible by 400. this means that the year 2000 is a leap year, the year 2100 is not. the X1209 does not correct for the leap year in the year 2100. control and status registers the control and status registers consist of the status register, interrupt and alarm register, event detec- tion, analog trimming and digital trimming registers. status register (sr) the status register is located in the ccr memory map at address 07h. this is a volatile register only and provides either control or status of rtc failure, battery mode, alarm trigger, event detection, write protection of clock counter, crystal oscillator enable and auto reset of status bits. table 2. status register (sr) rtcf: real time clock fail bit?olatile this bit is set to a ? after a total power failure. this is a read only bit that is set by hardware (X1209 internally) when the device powers up after having lost all power to the device. the bit is set regardless of whether v cc or vbat is applied ?st. the loss of only one of the sup- plies does not result in setting the rtcf bit. the ?st v alid write to the rtc after a complete power failure (writing one byte is suf?ient) resets the rtcf bit to ?? bat: battery supply?olatile this bit set to ? indicates that the device is operating from supply from the v bat pin and not the v cc pin. this bit can be reset either manually by the user (note this bit can only be manually cleared to 0) or automati- cally reset by enabling the auto-reset bit (see arst bit). al: alarm bit?olatile these bits announce if the alarm matches the real time clock. if there is a match, the respective bit is set to ?? this bit can be reset either manually by the user (note this bit can only be manually cleared to 0) or automati- cally reset by enabling the auto-reset bit (see arst bit). addr 76543210 07h arst xtoscb reserved wrtc evt alm bat rtcf default 0 0000001
15 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 an alarm bit that is set by an alarm occurring during an sr read operation will remain set after the read opera- tion is complete. evt: event detection bit ?olatile the event detection bit provides status of the event input pin (evin). when the evin pin is triggered the evt bit is set to 1 to indicate a detection of an event input. this bit can be reset either manually by the user (note this bit can only be manually cleared to 0) or automatically reset by enabling the auto-reset bit (see arst bit). when an high signal is present at the evin pin, an ?vent is detected. on detection a corresponding bit in the status register (evt bit) is set high and the evdet pin, open drain, is activated (pulled low). wrtc: write rtc enable bit?olatile the wrtc bit enables or disables write capability into the rtc timing registers. the factory default setting of this bit is ?? upon initialization or power up, the wrtc must be set to ? to enable the rtc. upon the completion of a valid write (stop), the rtc starts counting. the rtc internal 1 hz signal is synchronized to the stop condition during a valid write cycle. xtoscb: crystal oscillator enable bit ?olatile this bit enables / disables the internal crystal oscillator. when the xtoscb is set to ?? the oscillator is dis- abled. when the xtoscb is cleared to ?? the x1 pin allows for an external 32khz signal to drive the rtc. arst: auto reset enable bit ?olatile this bit enables / disables the automatic reset of the f ollowing status bits only: bat, alm, evt. when arst bit is set to ?? the participating status bits are reset to ? after a valid read of the status register (stop con- dition). when the arst is cleared to ? the user must manually reset the arst bit. interrupt control register (int) table 3. interrupt control register (int) fo<3:0>: frequency out control bits - volatile these bits enable / disable the frequency output func- tion and selects the output frequency at the irq / fout pin. see table 3 for frequency selection. when the frequency mode is enabled it will override the alarm mode at the irq / fout pin. table 4. frequency selection of fout pin fobatb: frequency output and interrrupt bit - volatile this bit enables / disables the fout / irq pin during battery backup mode (i.e. v bat power source active). when the fobatb is set to ? the fout / irq pin is disabled during battery backup mode. when the fobatb is cleared to ? the fout / irq pin is enabled during battery backup mode. addr 76543210 08h i m alme lpmode fobatb fo3 fo2 fo1 fo0 default 0 0000001 frequency, fout units fo3 fo2 fo1 fo0 default 0 0 0 0 0 0hz 0000 32 khz 0 0 0 1 4096 hz 0 0 1 0 1024 hz 0 0 1 1 64 hz 0 1 0 0 32 hz 0 1 0 1 16 hz 0 1 1 0 8hz 0111 4hz 1000 2hz 1001 1hz 1010 1/2 hz 1 0 1 1 1/4 hz 1 1 0 0 1/8 hz 1 1 0 1 1/16 hz 1 1 1 0 1/32 hz 1 1 1 1
preliminary information X1209 16 of 27 rev 3.0 2/11/04 www.xicor.com lpmode: low power mode bit - volatile this bit alme: alarm enable bit - volatile this bit enables / disables the alarm function. when the alme bit is set to ?? the alarm function is enabled. when the alme is cleared to ?? the alarm function is disabled. the alarm function can operate in either a single event alarm or a periodic interrupt alarm (see im bit). note: when the frequency output mode is enabled, the alarm function is disabled. im: interrupt / alarm mode bit - volatile this bit enables / disables the interrupt mode of the alarm function. when the im bit is set to ?? the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the irq / fout pin when the rtc is triggered by the alarm as de?ed by alarm registers (0ch to 11h). when the im bit is cleared to ?? the alarm will operate in standard mode, where the irq / fout pin will be tied low until the alm status bit is cleared to ?? event detection register (ev) the X1209 provides a simple event and tamper detec- tion circuit. the event detection register con?ures the functionality of the event detection circuits. esmp<1:0>: event input sampling selection bits - volatile these two bits select the rate of sampling of the evin pin to trigger an event detection. for example, a 1 hz sampling rate would con?ure the X1209 to check the status of the ev pin once a second. ehsy<1:0>: event input hysteresis selection bits - volatile these two bits select the amount of hysteresis (time based de-bouncing ?ter) of the evin pin to prevent de- bouncing or noise of external event detection circuits. the time hysteresis can be set between 0 to 31.25 ms. f or example, a 32.25ms would provide.... even: event mode enable bit - volatile this bit enables / disables the event detection mode of the X1209. when this bit is set to ?? the event mode is active. when this bit is cleared to ?? the event mode is disabled. rtchlt: rtc halt on event detection bit - volatile this bit selects whether the rtc is to continue of halt counting upon an event detection triggered by the ev pin. when rtchlt is set to ?? the rtc will discon- tinue incrementing if an event is detected. counting will resume when there is a valid write to the to the rtc registers (i.e. time set). when the rtchlt is cleared to ?? the rtc will continue counting if an event is detected. note 1: this function requires that the event detection is enabled (see even bit). note 2: in both cases, upon an event detection, the evdet pin will be pulled low and the ev detection bit will be set to ?? evbatb: event output battery mode enable bit - volatile this bit enables / disables the evdet pin during bat- tery backup mode (i.e. v bat pin supply on). when the evbatb is set to ?? the evdet pin will be disabled in battery backup mode. when the evbatb is cleared to ?? the evdet pin will be enabled in battery backup mode. im bit interrupt / alarm frequency 0 single time event set by alarm 1 repetitive / recurring time event set by alarm esmp1 esmp0 event sampling rate 00 always on 012 hz 101 hz 111 / 4 hz ehsy1 ehsy1 input hysteresis 00 0 (pullup always on) 01 3.9 ms 10 15.625 ms 11 32.25 ms
17 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 evienb: event current source enable bit - volatile this bit enables / disables the internal pullup current source used for the evin pin. when the evienb bit is set to ?? the pullup current source is always disabled. when the evienb bit is cleared to ?? the pullup cur- rent source is enabled (current source is approximately 1 ?). analog trimming register (atr) atr<5:0>: analog trimming register - volatile the X1209 contains two digitally controlled capacitors connected from both x1 pin and x2 pin to the ground pin. the amount capacitance can be selected via the a tr register. six analog trimming bits from a tr5 to a tr0 are pro- vided to adjust the on-chip loading capacitance range. the on-chip load capacitance ranges from 4.5 pf to 20.25 pf. each bit has a different weight for capaci- tance adjustment. in addition, using a citizen cfs-206 crystal with different atr bit combinations provides an estimated ppm range from +125 ppm to ?4 ppm to the nominal frequency compensation. the com bination of digital and analog trimming can give up to +185 to ?4 ppm adjustment. the on-chip capacitance can be calculated as follows: c at r = [(atr value, decimal) x 0.5pf] + 9.0pf note that the atr values are in twos complement, for e xample, atr(000000) = 25pf, atr(100000) = 9pf, and atr(011111) = 40.5pf. the entire range runs from 4.5pf to 20.25pf in 0.5pf steps. the effective load capacitance is the parallel combina- tion of the two capacitances at each pin. the values calculated above are typical, and total load capaci- tance seen by the crystal will include approximately 2pf of package and board capacitance in addition to the atr value. bmatr<1:0>: battery mode atr selection - volatile since accuracy of the crystal oscillator is dependent on the vcc/vbat operation, the X1209 provides the capa- bility to adjust the capacitance when the devices s witches between power sources. digital trimming register (dtr) dtr<2:0>: digital trimming register - volatile the digital trimming bits dtr2 , dtr1 and dtr0 adjust the number of counts per second and average the ppm error to achieve better accuracy. dtr2 is a sign bit. dtr2=0 means frequency compen- sation is > 0. dtr2=1 means frequency compensation is < 0. dtr1 and dtr0 are scale bits. dtr1 gives ____ ppm adjustment and dtr0 gives ____ ppm adjustment. a range from -60 ppm to +60 ppm can be represented by using three bits above. bmatr1 bmatr0 delta capacitance (cbat to cvcc) 000 pf 01 - 0.5 pf (~ + 2ppm) 10 + 0.5 pf (~ -2ppm) 11 + 1 pf (~ -4ppm)
preliminary information X1209 18 of 27 rev 3.0 2/11/04 www.xicor.com table 5. digital trimming registers alarm register addresses [0c hex to 11hex] the alarm register contents mimic the contents of the r tc register, but add enable bits and exclude the 24 hour time selection bit. the enable bits specify which registers to use in the comparison between the alarm and real time registers. for example: setting the enable month bit (emna) bit in combina- tion with other enable bits and a speci? alarm time, the user can establish an alarm that triggers at the same time once a year. when there is a match, an alarm ?g (alm) is set. the occurrence of an alarm can be determined by polling the alm bit or by enabling the irq output, using it as hardware ?g. the alarm enable bits are located in the msb of the particular register. when all enable bits are set to ?? there are no alarms. the user can set the X1209 to alarm every wednes- day at 8:00 am by setting the edwa, the ehra and emna enable bits to ? and setting the dwa, hra and mna alarm registers to 8:00am wednesday. ? daily alarm for 9:30pm results when the ehra and emna enable bits are set to ? and the hra and mna registers are set to 9:30pm. user register (user) addresses [12 hex to 13 hex] these registers are available for (2 bytes) user memory storage. dtr register estimated frequency ppm dtr2 dtr1 dtr0 00 00 (default) 001 +20 010 +40 011 +60 100 0 111 -20 110 -40 111 -60
19 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 serial communication interface conventions the device supports a bidirectional bus oriented proto- col. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this family operate as slaves in all applications. clock and data data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 3. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see figure 4. stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. see fig- ure 4. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 5. the device will respond with an acknowledge after rec- ognition of a start condition and if the correct device identi?r and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, e xcept for: the slave address byte when the device identi?r and/or select bits are incorrect all data bytes of a write when the wrtc in the write protect register is low the 2nd data byte of a status register write operation (only 1 data byte is allowed) figure 3. valid data changes on the sda bus figure 4. valid start and stop conditions scl sda data stable data change data stable scl sda start stop
preliminary information X1209 20 of 27 rev 3.0 2/11/04 www.xicor.com figure 5. acknowledge response from receiver device addressing f ollowing a start condition, the master must output a slave address byte. slave bits ?101 access the ccr. bit 3 through bit 1 of the slave byte specify the device select bits. these are set to ?11? the last bit of the slave address byte de?es the oper- ation to be performed. when this r/w bit is a one, then a read operation is selected. a zero selects a write operation. refer to figure 6. after loading the entire slave address byte from the sda bus, the X1209 compares the device identi?r and device select bits with ?101111? upon a correct compare, the device outputs an acknowledge on the sda line. f ollowing the slave byte is a two byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power up the internal address counter is set to address 0h, so a current address read of the ccr array starts at address 0. when required, as part of a random read, the master must supply the 2 word address bytes as shown in figure 6. in a random read operation, the slave byte in the ?ummy write portion must match the slave byte in the ?ead section. for a random read of the clock/control registers, the slave byte must be 1101111x in both places. figure 6. slave address, word address, and data bytes scl from master data output from transmitter data output from receiver 8 1 9 start acknowledge slave address byte byte 0 d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte byte 3 a6 a5 00 0000 0 1 10 1 1 1 r/w 1 0 w ord address 1 byte 1 w ord address 0 byte 2
21 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 writing or reading to the clock/control registers changing any of the volatile bits of the clock/control register requires the following steps: ? r ite one to 8 bytes to the clock/control registers with the desired clock, alarm, or control data. this sequence starts with a start bit, requires a slave byte of ?1011110 and an address within the ccr and is terminated by a stop bit. a write to the ccr changes v olatile register values. ? read operation occurring between any of the previ- ous operations will not interrupt the register write operation. the wrtc bit enables or disables write capability into the rtc timing registers. upon initialization or power up, the wrtc must be set to ? to enable the rt c. upon the completion of a valid write (stop), the rtc starts counting. ? r iting and reading capability is disable during bat- tery backup mode. write operations byte write f or a write operation, the device requires the slave address byte and the word address bytes. this gives the master access to any one of the words in the ccr. upon receipt of each address byte, the X1209 responds with an acknowledge. after receiving both address bytes the X1209 awaits the eight bits of data. after receiving the 8 data bits, the X1209 again responds with an acknowledge. the master then termi- nates the transfer by generating a stop condition. the X1209 then begins an internal write cycle of the data to the nonvolatile memory. during the internal write cycle, the device inputs are disabled, so the de vice will not respond to any requests from the master. the sda out- put is at high impedance. see figure 7. stop and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data b yte and its associated ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte + a ck is sent, then the X1209 resets itself without per- fo r ming the write. the contents of the array are not affected. acknowledge polling once the stop condition is issued to indicate the end of the masters byte load operation, the X1209 initiates the internal nonvolatile write cycle. acknowledge poll- ing can begin immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the X1209 is still b usy with the nonvolatile write cycle then no ack will be returned. when the X1209 has completed the write operation, an ack is returned and the host can pro- ceed with the read or write operation. refer to the ?w chart in figure 9. reading the real time clock the rtc is read by initiating a read command and specifying the address corresponding to the register of the real time clock. the rtc registers can then be read in a sequential read mode. since the clock runs continuously and a read takes a ?ite amount of time, there is the possibility that the clock could change dur- ing the course of a read operation. in this device, the time is latched by the read command (falling edge of the clock on the ack bit prior to rtc data output) into a separate latch to avoid time changes during the read operation. the clock continues to run. alarms occur- r ing during a read are unaffected by the read opera- tion. writing to the real time clock the time and date may be set by writing to the rtc registers. to avoid changing the current time by an uncompleted write operation, the current time value is loaded into a separate buffer at the falling edge of the clock on the ack bit before the rtc data input bytes, the clock continues to run. the new serial input data replaces the values in the buffer. this new rtc value is loaded back into the rtc register by a stop bit at the end of a valid write sequence. an invalid write operation aborts the time update procedure and the contents of the buffer are discarded. after a valid write operation the rtc will re?ct the newly loaded data beginning with the next ?ne second clock cycle after the stop bit is written. the rtc continues to update the time while an rtc register write is in progress and the r tc continues to run during any nonvolatile write sequences. a single byte may be written to the rtc without affecting the other bytes
preliminary information X1209 22 of 27 rev 3.0 2/11/04 www.xicor.com figure 7. byte write sequence read operations there are three basic read operations: current address read, random read, and sequential read. current address read internally the X1209 contains an address counter that maintains the address of the last word read incre- mented by one. therefore, if the last read was to address n, the next read operation would access data from address n+1. upon receipt of the slave address byte with the r/w bit set to one, the X1209 issues an acknowledge, then transmits eight data bits. the mas- ter terminates the read operation by not responding with an acknowledge during the ninth clock and issuing a stop condition. refer to figure 8 for the address, acknowledge, and data transfer sequence. figure 8. current address read sequence figure 9. acknowledge polling sequence it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. s t a r t s t o p slave address w ord address 1 data a c k a c k a c k sda bus signals from the slave signals from the master 0 a c k w ord address 0 1 1 1 1 00000000 101 s t a r t s t o p slave address data a c k sda bus signals from the slave signals from the master 1 1 1 1 1 1 0 1 ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes issue stop no continue normal read or write command sequence proceed yes write cycle complete. continue command sequence?
23 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 random read random read operations allow the master to access any location in the X1209. prior to issuing the slave address byte with the r/w bit set to zero, the master m ust ?st perform a ?ummy write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipt of each word address byte, the master immediately issues another start condition and the slave address b yte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit data word. the master terminates the read operation by not responding with an acknowledge and then issu- ing a stop condition. refer to figure 10 for the address, acknowledge, and data transfer sequence. in a similar operation called ?et current address, the device sets the address if a stop is issued instead of the second start shown in figure 10. the X1209 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. this operation loads the new address into the address counter. the next current address read operation will read from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. sequential read sequential reads can be initiated as either a current address read or random address read. the ?st data b yte is transmitted as with the other modes; however, the master now responds with an acknowledge, indi- cating it requires additional data. the device continues to output data for each acknowledge received. the mas- ter terminates the read operation by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. refer to figure 11 for the acknowledge and data trans- f er sequence. figure 10. random address read sequence figure 11. sequential read sequence 0 slave address w ord address 1 a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master a c k w ord address 0 1 1 1 1 1 1 11 0000000 1 0 1 1 0 1 data (2) s t o p slave address data (n) a c k a c k sda bus signals from the slave signals from the master 1 data (n-1) a c k a c k (n is any integer greater than 1) data (1)
preliminary information X1209 24 of 27 rev 3.0 2/11/04 www.xicor.com application section crystal oscillator and temperature compensation xicor has now integrated the oscillator compensation circuit layout considerations the crystal assembly most electronic oscillator measurements when a proper crystal i backup battery operation many types of batteries can be used with the xicor r tc products. 3.0v or 3.6v lithium batteries are appropriate, and sizes are available that can power a xicor rtc device for up to 10 years. another option is to use a supercapacitor for applications where vcc may disappear intermittently for short periods of time. depending on the value of supercapacitor used, backup time can last from a few days to two weeks (with >1f). a simple silicon or schottky barrier diode can be used in series with vcc to charge the superca- pacitor, which is connected to the vbat pin. do not use the diode to charge a battery (especially lithium batter- ies!). figure 12. supercapactor charging circuit since the battery switchover occurs at .... (see figure xx), .... the summary of conditions for backup battery opera- tion is given in table 6: table 6. battery backup operation 2.7-5.5v supercapacitor v ss v cc v back 1. example application, vcc=5v, vbat=3.0v condition vcc vbat vtrip iback notes a. normal operation b. vcc on with no battery c. backup mode 2. example application, vcc=3.3v,vbat=3.0v condition vcc vbat vtrip iback a. normal operation b. vcc on with no battery c. backup mode d. 3. example application, vcc=3.3v,vbat=5.0v a. normal operation b. vcc on with no battery c. backup mode
25 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 packaging information 10-lead miniature small outline gull wing package type m
26 of 27 rev 3.0 2/11/04 www.xicor.com preliminary information X1209 10 bump fcp package symbol min nominal max millimeters package width a package length b package height c body thickness d ball height e ball diameter f bump name x coordinate, ? y coordinate, ? 1 2 3 4 5 6 7 8 9 10
characteristics subject to change without notice. 27 of 27 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, e xpress, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, biaslo ck and xdcp are also trademarks of xicor, inc. all others belong to their respective owners. u .s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2003 patents pending rev 3.0 2/11/04 www.xicor.com preliminary information X1209

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