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1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 1 1, 2 meg x 32 dram simms obsolete dram module features ? jedec- and industry-standard pinout in a 72-pin, single in-line memory module (simm) ? 4mb (1 meg x 32) and 8mb (2 meg x 32) ? high-performance cmos silicon-gate process ? single +5v 10% power supply ? all inputs, outputs and clocks are ttl-compatible ? refresh modes: ras#-only, cas#-before-ras# (cbr) and hidden ? multiple ras# lines allow x16 or x32 width ? 1,024-cycle refresh distributed across 16ms ? fast page mode (fpm) operating mode or extended data-out (edo) page mode operating mode options marking ? timing 60ns access -6 ? packages 72 -pin simm m 72 -pin simm (gold) g ? operating modes fast page mode blank edo page mode x pin assignment (front view) 72-pin simm (dd-3) 1 meg x 32 (dd-4) 2 meg x 32 pin symbol pin symbol pin symbol pin symbol 1v ss 19 nc (a10) 37 nc 55 dq12 2 dq1 20 dq5 38 nc 56 dq28 3 dq17 21 dq21 39 v ss 57 dq13 4 dq2 22 dq6 40 cas0# 58 dq29 5 dq18 23 dq22 41 cas2# 59 v cc 6 dq3 24 dq7 42 cas3# 60 dq30 7 dq19 25 dq23 43 cas1# 61 dq14 8 dq4 26 dq8 44 ras0# 62 dq31 9 dq20 27 dq24 45 nc*/ras1# 63 dq15 10 v cc 28 a7 46 nc 64 dq32 11 nc 29 nc (a11) 47 we# 65 dq16 12 a0 30 v cc 48 nc 66 nc 13 a1 31 a8 49 dq9 67 prd1 14 a2 32 a9 50 dq25 68 prd2 15 a3 33 nc*/ras3# 51 dq10 69 prd3 16 a4 34 ras2# 52 dq26 70 prd4 17 a5 35 nc 53 dq11 71 nc 18 a6 36 nc 54 dq27 72 v ss *4mb version only mt8d132(x) mt16d232(x) 1363772 part numbers edo operating mode part number configuration plating MT8D132G-xx x 1 meg x 32 gold mt8d132m-xx x 1 meg x 32 tin/lead mt16d232g-xx x 2 meg x 32 gold mt16d232m-xx x 2 meg x 32 tin/lead xx = speed fpm operating mode part number configuration plating MT8D132G-xx 1 meg x 32 gold mt8d132m-xx 1 meg x 32 tin/lead mt16d232g-xx 2 meg x 32 gold mt16d232m-xx 2 meg x 32 tin/lead xx = speed note: symbols in parentheses are not used on these modules but may be used for other modules in this product family. they are for reference only. key timing parameters edo operating mode speed t rc t rac t pc t aa t cac t cas -6 110ns 60ns 26ns 30ns 17ns 13ns fpm operating mode speed t rc t rac t pc t aa t cac t rp -6 110ns 60ns 35ns 30ns 15ns 40ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 2 1, 2 meg x 32 dram simms obsolete general description the mt8d132(x) and mt16d232(x) are randomly ac- cessed 4mb and 8mb solid-state memories organized in a x32 configuration. during read or write cycles, each bit is uniquely addressed through the 20 address bits, which are entered 10 bits (a0 -a9) at a time. ras# is used to latch the first 10 bits and cas# the latter 10 bits. a read or write cycle is selected with the we# input. a logic high on we# dictates read mode while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we# or cas#, whichever occurs last. early write occurs when we# goes low prior to cas# going low, and the output pin(s) remain open (high-z) until the next cas# cycle. fast page mode fast page mode operations allow faster data opera- tions (read or write) within a row-address-defined (a0 -a9) page boundary. the fast page mode cycle is always initiated with a row address strobed-in by ras# followed by a column address strobed-in by cas#. cas# may be toggled-in by holding ras# low and strobing-in different column addresses, thus executing faster memory cycles. returning ras# high terminates the fast page mode operation. edo page mode edo page mode, designated by the x version, is an accelerated fast page mode cycle. the primary advan- tage of edo is the availability of data-out even after cas# goes back high. edo provides for cas# precharge time ( t cp) to occur without the output data going invalid. this elimination of cas# output control provides for pipeline reads. fast page mode modules have traditionally turned the output buffers off (high-z) with the rising edge of cas#. edo operates as any dram read or fast-page- mode read, except data will be held valid after cas# goes high, as long as ras# and oe# are held low and we# is held high. (reference mt4c4007j dram data sheet for additional information on edo functionality.) refresh returning ras# and cas# high terminates a memory cycle and decreases chip current to a reduced standby level. also, the chip is preconditioned for the next cycle during the ras# high time. memory cell data is retained in its correct state by maintaining power and executing any ras# cycle (read, write) or ras# refresh cycle (ras# only, cbr or hidden) so that all 1,024 combination of ras# addresses (a 0 -a9) are executed at least every 16ms, regardless of sequence. x16 configuration for x16 applications, the corresponding dq and cas# pins must be connected together (dq1 to dq17, dq2 to dq18 and so forth, and cas0# to cas2# and cas1# to cas3#). each ras# is then a bank select for the x16 memory organization.
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 3 1, 2 meg x 32 dram simms obsolete functional block diagram mt8d132(x) (4mb) dq1 - 4 u1 a0?9 dq1 - 4 a0?9 dq1 dq8 dq1 - 4 a0?9 dq1 - 4 a0?9 dq9 dq16 cas1# we# dq1 - 4 a0?9 dq1 - 4 a0?9 dq17 dq24 dq1 - 4 a0?9 dq1 - 4 a0?9 dq25 dq32 cas3# a0?9 10 10 10 10 10 10 10 10 u2 u5 u6 u3 u4 u7 u8 fast page mode u1-u8 = mt4c4001jdj edo page mode u1-u8 = mt4c4007jdj cas0# ras0# cas2# ras2# v cc v ss u1-u8 u1-u8 we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe#
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 4 1, 2 meg x 32 dram simms obsolete functional block diagram mt16d232(x) (8mb) dq1 - 4 u1 a0?9 dq1 - 4 a0?9 dq1 dq8 dq1 - 4 a0?9 dq1 - 4 a0?9 dq9 dq16 cas1# we# cas# ras# oe# dq1 - 4 a0?9 dq1 - 4 a0?9 dq17 dq24 dq1 - 4 a0?9 dq1 - 4 a0?9 dq25 dq32 cas3# a0?9 10 10 10 10 10 10 10 10 u2 u5 u6 u3 u4 u7 u8 fast page mode u1-u16 = mt4c4001j edo page mode u1-u16 = mt4c4007jdj dq1 - 4 u9 a0?9 dq1 - 4 a0?9 dq1 dq8 dq1 - 4 a0?9 dq1 - 4 a0?9 dq9 dq16 ras1# dq1 - 4 a0?9 dq1 - 4 a0?9 dq17 dq24 dq1 - 4 a0?9 dq1 - 4 a0?9 dq25 dq32 ras3# 10 10 10 10 10 10 10 10 u10 u13 u14 u11 u12 u15 u16 cas0# ras0# we# cas2# ras2# v cc v ss u1-u16 u1-u16 we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe# we# cas# ras# oe#
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 5 1, 2 meg x 32 dram simms obsolete truth table addresses data-in/out function ras# cas# we# t r t c dq1-dq32 standby h h ? x x x x high-z read l l h row col data-out early write l l l row col data-in edo/fast-page- 1st cycle l h ? l h row col data-out mode read 2nd cycle l h ? l h n/a col data-out any cycle l l ? h h n/a n/a data-out (x version) edo/fast-page- 1st cycle l h ? l l row col data-in mode early write 2nd cycle l h ? l l n/a col data-in ras#-only refresh l h x row n/a high-z hidden read l ? h ? l l h row col data-out refresh write l ? h ? l l l row col data-in cbr refresh h ? l l h x x high-z jedec-defined presence-detect C mt16d232(x) (8mb) symbol pin -6 prd1 67 nc prd2 68 nc prd3 69 nc prd4 70 nc jedec-defined presence-detect C mt8d132(x) (4mb) symbol pin -6 prd1 67 v ss prd2 68 v ss prd3 69 nc prd4 70 nc
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 6 1, 2 meg x 32 dram simms obsolete absolute maximum ratings* voltage on v cc supply relative to v ss .............. -1v to +7v operating temperature, t a (ambient) .......... 0 c to +70 c storage temperature (plastic) .................... -55 c to +125 c power dissipation ............................................................. 8w short circuit output current ..................................... 50ma *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1, 3, 6) (v cc = +5v 10%) parameter/condition symbol min max units notes supply voltage v cc 4.5 5.5 v input high (logic 1) voltage, all inputs v ih 2.4 v cc +1 v input low (logic 0) voltage, all inputs v il -1.0 0.8 v input leakage current cas0#-cas3# i i 1 -8 8 m a23 any input 0v v in v cc +1v a0-a9, we# i i 2 -32 32 m a23 (all other pins not under test = 0v) ras0#-ras3# i i 3 -8 8 m a output leakage current dq1-dq32 i oz -20 20 m a23 (dq is disabled; 0v v out 5.5v) output levels v oh 2.4 v high voltage (i out = -5ma) v ol 0.4 v low voltage (i out = 4.2ma) parameter/condition symbol size -6 units notes standby current: (ttl) i cc 1 4mb 16 ma (ras# = cas# = v ih ) 8mb 32 standby current: (cmos) i cc 2 4mb 8 ma (ras# = cas# = other inputs = v cc -0.2v) 8mb 16 operating current: random read/write 4mb 880 ma 2, 22 average power supply current i cc 3 (ras#, cas#, address cycling: t rc = t rc [min]) 8mb 896 operating current: fast page mode 4mb 640 ma 2, 22 average power supply current i cc 4 (ras# = v il , cas#, address cycling: t pc = t pc [min]) 8mb 656 operating current: edo page mode i cc 5 4mb 640 ma 2 average power supply current (ras# = v il , cas#, address cycling: t pc = t pc [min]) (x only) 8mb 656 refresh current: ras#-only 4mb 880 average power supply current i cc 6 ma 2, 22 (ras# cycling, cas# = v ih : t rc = t rc [min]) 8mb 896 refresh current: cbr 4mb 880 average power supply current i cc 7 ma 2, 17 (ras#, cas#, address cycling: t rc = t rc [min]) 8mb 896 max
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 7 1, 2 meg x 32 dram simms obsolete capacitance parameter symbol 4mb 8mb units notes input capacitance: a0-a9 c i 1 48 95 pf 15 input capacitance: we# c i 2 64 127 pf 15 input capacitance: ras0#-ras3# c i 4 32 32 pf 15 input capacitance: cas0#-cas3# c i 5 16 32 pf 15 input/output capacitance: dq1-dq32 c io 10 18 pf 15 max fast page mode ac electrical characteristics (notes: 3, 4, 5, 6, 7, 8, 9, 14) (v cc = +5v 10%) ac characteristics - fast page mode option -6 parameter symbol min max units notes access time from column address t aa 30 ns column-address hold time (referenced to ras#) t ar 45 ns column-address setup time t asc 0 ns row-address setup time t asr 0 ns access time from cas# t cac 15 ns column-address hold time t cah 10 ns cas# pulse width t cas 15 10,000 ns cas# hold time (cbr refresh) t chr 10 ns 17 cas# to output in low-z t clz 0 ns cas# precharge time t cp 10 ns 16 access time from cas# precharge t cpa 35 ns cas# to ras# precharge time t crp 10 ns cas# hold time t csh 60 ns cas# setup time (cbr refresh) t csr 10 ns 17 write command to cas# lead time t cwl 15 ns data-in hold time t dh 10 ns 13 data-in setup time t ds 0 ns 13 output buffer turn-off delay t off 3 15 ns 10, 21, 24 fast-page-mode read or write cycle time t pc 35 ns access time from ras# t rac 60 ns ras# to column-address delay time t rad 15 ns 20 row-address hold time t rah 10 ns ras# pulse width t ras 60 10,000 ns ras# pulse width (fast page mode) t rasp 60 100,000 ns random read or write cycle time t rc 110 ns ras# to cas# delay time t rcd 20 ns 11 read command hold time (referenced to cas#) t rch 0 ns 12 read command setup time t rcs 0 ns refresh period (1,024 cycles) t ref 16 ms ras# precharge time t rp 40 ns ras# to cas# precharge time t rpc 0 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 8 1, 2 meg x 32 dram simms obsolete fast page mode ac electrical characteristics (notes: 3, 4, 5, 6, 7, 8, 9, 14) (v cc = +5v 10%) ac characteristics - fast page mode option -6 parameter symbol min max units notes read command hold time t rrh 0 ns 12 ras# hold time t rsh 15 ns write command to ras# lead time t rwl 15 ns transition time (rise or fall) t t350ns write command hold time t wch 10 ns write command hold time (referenced to ras#) t wcr 45 ns we# command setup time t wcs 0 ns write command pulse width t wp 10 ns we# hold time (cbr refresh) t wrh 10 ns we# setup time (cbr refresh) t wrp 10 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 9 1, 2 meg x 32 dram simms obsolete edo page mode ac electrical characteristics (notes: 3, 4, 5, 6, 7, 8, 9, 14) (v cc = +5v 10%) ac characteristics - edo page mode option -6 parameter sym min max units notes access time from column address t aa 30 ns column-address setup to cas# precharge during write t ach 15 ns column-address hold time (referenced to ras#) t ar 45 ns column-address setup time t asc 0 ns row-address setup time t asr 0 ns access time from cas# t cac 17 ns column-address hold time t cah 10 ns cas# pulse width t cas 13 10,000 ns cas# hold time (cbr refresh) t chr 10 ns 17 cas# to output in low-z t clz 3 ns 21 data output hold after cas# low t coh 5 ns cas# precharge time t cp 10 ns 16 access time from cas# precharge t cpa 35 ns cas# to ras# precharge time t crp 10 ns cas# hold time t csh 50 ns cas# setup time (cbr refresh) t csr 10 ns 17 write command to cas# lead time t cwl 15 ns data-in hold time t dh 9 ns 13 data-in setup time t ds 0 ns 13 output buffer turn-off delay t off 3 15 ns 10, 21, 24 fast-page-mode read or write cycle time t pc 26 ns access time from ras# t rac 60 ns ras# to column-address delay time t rad 15 ns 20 row-address hold time t rah 10 ns ras# pulse width t ras 60 10,000 ns ras# pulse width (fast page mode) t rasp 60 100,000 ns random read or write cycle time t rc 110 ns ras# to cas# delay time t rcd 20 ns 11 read command hold time (referenced to cas#) t rch 0 ns 12 read command setup time t rcs 0 ns refresh period (1,024 cycles) t ref 16 ms ras# precharge time t rp 40 ns ras# to cas# precharge time t rpc 5 ns read command hold time t rrh 0 ns 12 ras# hold time t rsh 15 ns write command to ras# lead time t rwl 15 ns transition time (rise or fall) t t 1.5 50 ns 5, 14 write command hold time t wch 10 ns write command hold time (referenced to ras#) t wcr 45 ns we# command setup time t wcs 0 ns output disable delay from we# (cas# high) t whz 3 15 ns write command pulse width t wp 10 ns we# pulse width for output disable when cas# high t wpz 10 ns we# hold time (cbr refresh) t wrh 10 ns we# setup time (cbr refresh) t wrp 10 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 10 1, 2 meg x 32 dram simms obsolete notes 1. all voltages referenced to v ss . 2. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the output open. 3. an initial pause of 100 m s is required after power-up, followed by eight ras# refresh cycles (ras#-only or cbr with we# high), before proper device operation is ensured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 4. ac characteristics assume t t = 5ns for fast page mode and t t = 1.5ns for edo page mode. 5. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 6. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 c t a 70 c) is ensured. 7. measured with a load equivalent to two ttl gates and 100pf. 8. if cas# and ras# = v ih , data output is high-z. 9. if cas# = v il , data output may contain data from the last valid read cycle. 10. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 11. the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac ( t rac [min] no longer applied). with or without the t rcd (max) limit, t aa and t cac must always be met. 12. either t rch or t rrh must be satisfied for a read cycle. 13. these parameters are referenced to cas# leading edge in early write cycles. 14. in addition to meeting the transition rate specifica- tion, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 15. this parameter is sampled. capacitance is measured using mil-std-883c, method 3012.1 (1 mhz ac, v cc = 4.5v, dc bias = 2.4v at 15mv rms). 16. if cas# is low at the falling edge of ras#, data-out (q) will be maintained from the previous cycle. to initiate a new cycle and clear the data-out buffer, cas# must be pulsed high for t cp. 17. on-chip refresh and address counters are enabled. 18. a hidden refresh may also be performed after a write cycle. in this case, we# = low. 19. late write, read-write or read-modify- write cycles are not available due to oe# being grounded on u1-u8/u16. 20. the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa ( t rac and t cac no longer applied). with or without the t rad (max) limit, t aa, t rac and t cac must always be met. 21. the 3ns minimum is a parameter guaranteed by design. 22. column address changed once each cycle. 23. 4mb module values will be half of those shown. 24. for fast page mode option, t off is determined by the first ras# or cas# signal to transition high. in comparison, t off on an edo option is determined by the latter of the ras# and cas# signal to transition high. 25. applies to both edo and fast page modes.
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 11 1, 2 meg x 32 dram simms obsolete read cycle 25 t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t ach t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il cas# v v ih il addr v v ih il dq v v ioh iol v v ih il column we# don?t care undefined t csh (edo) 50 ns t off 3 15 ns t rac 60 ns t rad 15 ns t rah 10 ns t ras 60 10,000 ns t rc 110 ns t rcd 20 ns t rch 0 ns t rcs 0 ns t rp 40 ns t rrh 0 ns t rsh 15 ns -6 symbol min max units fast page mode and edo page mode timing parameters -6 symbol min max units t aa 30 ns t ach 15 ns t ar 45 ns t asc 0 ns t asr 0 ns t cac (fpm) 15 ns t cac (edo) 17 ns t cah 10 ns t cas (fpm) 15 10,000 ns t cas (edo) 13 10,000 ns t clz (fpm) 0 ns t clz (edo) 3 ns t crp 10 ns t csh (fpm) 60 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 12 1, 2 meg x 32 dram simms obsolete early write cycle 25 don? care undefined v v ih il valid data row column row t ds t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol ras# t dh we# cas# t ach -6 symbol min max units t ds 0 ns t rad 15 ns t rah 10 ns t ras 60 10,000 ns t rc 110 ns t rcd 20 ns t rp 40 ns t rsh 15 ns t rwl 15 ns t wch 10 ns t wcr 45 ns t wcs 0 ns t wp 10 ns fast page mode and edo page mode timing parameters -6 symbol min max units t ach (edo) 15 ns t ar 45 ns t asc 0 ns t asr 0 ns t cah 10 ns t cas (fpm) 15 10,000 ns t cas (edo) 13 10,000 ns t crp 10 ns t csh (fpm) 60 ns t csh (edo) 50 ns t cwl 15 ns t dh (fpm) 10 ns t dh (edo) 9 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 13 1, 2 meg x 32 dram simms obsolete fast-page-mode read cycle valid data valid data valid data column column column row row t rcs t cah t asc t cp t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rch t rch t rcs t rrh t rch t off t cac t cpa t aa t clz t off t cac t cpa t aa t clz t off t cac t rac t aa t clz open open v v ih il cas# v v ih il addr v v ih il we# v v ih il dq v v ioh iol ras# don?t care undefined t off 3 15 ns t pc 35 ns t rac 60 ns t rad 15 ns t rah 10 ns t rasp 60 100,000 ns t rcd 20 ns t rch 0 ns t rcs 0 ns t rp 40 ns t rrh 0 ns t rsh 15 ns -6 symbol min max units fast page mode timing parameters -6 symbol min max units t aa 30 ns t ar 45 ns t asc 0 ns t asr 0 ns t cac 15 ns t cah 10 ns t cas 15 10,000 ns t clz 0 ns t cp 10 ns t cpa 35 ns t crp 10 ns t csh 60 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 14 1, 2 meg x 32 dram simms obsolete edo-page-mode read cycle valid data valid data valid data column column column row row don?t care undefined t cah t asc t cp t rsh t cp t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t ach t ach t ach t asr t rcs t rrh t rch t off t cac t cpa t aa t clz t cac t cpa t aa t cac t rac t aa t clz open open v v ih il v v ih il addr v v ih il v v ih il dq v v oh ol ras# t cas t cas cas# we# t coh -6 symbol min max units t off 3 15 ns t pc 26 ns t rac 60 ns t rad 15 ns t rah 10 ns t rasp 60 100,000 ns t rcd 20 ns t rch 0 ns t rcs 0 ns t rp 40 ns t rrh 0 ns t rsh 15 ns edo page mode timing parameters -6 symbol min max units t aa 30 ns t ar 45 ns t asc 0 ns t asr 0 ns t cac 17 ns t cah 10 ns t cas 13 10,000 ns t clz 3 ns t coh 5 ns t cp 10 ns t cpa 35 ns t crp 10 ns t csh 50 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 15 1, 2 meg x 32 dram simms obsolete fast/edo-page-mode early-write cycle 25 t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t cah t asc t cah t asc t rah t asr t rad t ar column column column row row t cp t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp v v ih il cas# v v ih il addr v v ih il we# v v ih il dq v v ioh iol ras# don? care undefined t ach t ach t ach fast page mode and edo page mode timing parameters -6 symbol min max units t ar 45 ns t asc 0 ns t asr 0 ns t cah 10 ns t cas (fpm) 15 10,000 ns t cas (edo) 13 10,000 ns t cp 10 ns t crp 10 ns t csh (fpm) 60 ns t csh (edo) 50 ns t cwl 15 ns t dh (fpm) 10 ns t dh (edo) 9 ns t ds 0 ns -6 symbol min max units t pc (fpm) 35 ns t pc (edo) 26 ns t rad 15 ns t rah 10 ns t rasp 60 100,000 ns t rcd 20 ns t rp 40 ns t rsh 15 ns t rwl 15 ns t wch 10 ns t wcr 45 ns t wcs 0 ns t wp 10 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 16 1, 2 meg x 32 dram simms obsolete edo-page-mode read-early-write cycle (pseudo read-modify-write) v v ih il v v ih il ras# v v ih il addr v v ih il we# t rasp t rp row column (a) column (n) row v v ioh iol t crp t csh t cas t rcd t asr t rah t rad t asc t ar t cah t asc t cah t asc t cah t cp t rsh valid d in t rcs t rch t wcs valid d out valid d out t whz t cac t cpa t aa t cac t aa open dq t pc rac t t coh t wch t ds t dh t pc column (b) t ach cas# t cas t cas t cp t cp don?t care undefined edo page mode timing parameters -6 symbol min max units t aa 30 ns t ach 15 ns t ar 45 ns t asc 0 ns t asr 0 ns t cac 17 ns t cah 10 ns t cas 13 10,000 ns t coh 5 ns t cp 10 ns t cpa 35 ns t crp 10 ns t csh 50 ns t dh 9 ns -6 symbol min max units t ds 0 ns t pc 26 ns t rac 60 ns t rad 15 ns t rah 10 ns t rasp 60 100,000 ns t rcd 20 ns t rch 0 ns t rcs 0 ns t rp 40 ns t rsh 15 ns t wch 10 ns t wcs 0 ns t whz 3 15 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 17 1, 2 meg x 32 dram simms obsolete row valid data valid data open t crp t rcd t cas t rsh t rasp t rp t pc t asc t cah t ar t asr t rad t rah t wcs t wp t rwl t rcs t dh t ds t cac t off v v ih il cas# v v ih il addr v v ih il ras# dq v v oh ol we# v v ih il t csh column t cp t cp t asc t cah t cwl t wch t clz t aa rac don?t care undefined t note 1 row column t cas fast-page-mode read-early-write cycle (pseudo read-modify-write) note: 1. do not drive data prior to tristate. -6 symbol min max units fast page mode timing parameters -6 symbol min max units t aa 30 ns t ar 45 ns t asc 0 ns t asr 0 ns t cac 15 ns t cah 10 ns t cas 15 10,000 ns t clz 0 ns t cp 10 ns t crp 10 ns t csh 60 ns t cwl 15 ns t dh 10 ns t ds 0 ns t off 3 15 ns t pc 35 ns t rac 60 ns t rad 15 ns t rah 10 ns t rasp 60 100,000 ns t rcd 20 ns t rcs 0 ns t rp 40 ns t rsh 15 ns t rwl 15 ns t wch 10 ns t wcs 0 ns t wp 10 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 18 1, 2 meg x 32 dram simms obsolete edo read cycle (with we#-controlled disable) t clz t cac t rac t aa valid data open t rch t rcs t asc t rah t rad t ar t cah t rcd t cas t csh t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il column cas# we# t whz t wpz t cp t asc t rcs column t clz don?t care undefined -6 symbol min max units t csh 50 ns t rac 60 ns t rad 15 ns t rah 10 ns t rcd 20 ns t rch 0 ns t rcs 0 ns t whz 3 15 ns t wpz 10 ns edo page mode timing parameters -6 symbol min max units t aa 30 ns t ar 45 ns t asc 0 ns t asr 0 ns t cac 17 ns t cah 10 ns t cas 13 10,000 ns t clz 3 ns t cp 10 ns t crp 10 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 19 1, 2 meg x 32 dram simms obsolete ras#-only refresh cycle 25 row v v ih il v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open q v v oh ol t rpc casl#/cash# we# v v ih il t rp v v ih il ras# t ras open t chr t csr v v ih il v v oh ol cas# dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh we# t wrp t wrh don?t care undefined cbr refresh cycle 25 (addresses = dont care) -6 symbol min max units t rc 110 ns t rp 40 ns t rpc (fpm) 0 ns t rpc (edo) 5 ns t wrh 10 ns t wrp 10 ns fast page mode and edo page mode timing parameters -6 symbol min max units t asr 0 ns t chr 10 ns t cp 10 ns t crp 10 ns t csr 10 ns t rah 10 ns t ras 60 10,000 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 20 1, 2 meg x 32 dram simms obsolete hidden refresh cycle 18, 25 (we# = high) don? care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t crp t rcd t rsh t ras t rp t chr t ras dq v v oh ol v v ih il addr v v ih il v v ih il ras# cas# -6 symbol min max units t crp 10 ns t off 3 15 ns t rac 60 ns t rad 15 ns t rah 10 ns t ras 60 10,000 ns t rcd 20 ns t rp 40 ns t rsh 15 ns fast page mode and edo page mode timing parameters -6 symbol min max units t aa 30 ns t ar 45 ns t asc 0 ns t asr 0 ns t cac (fpm) 15 ns t cac (edo) 17 ns t cah 10 ns t chr 10 ns t clz 3 ns
1, 2 meg x 32 dram simms micron technology, inc., reserves the right to change products or specifications without notice. dm53.pm5 C rev. 3/97 ? 1997, micron technology, inc. 21 1, 2 meg x 32 dram simms obsolete 72-pin simm (4mb) 72-pin simm (8mb) .050 (1.27) typ 1.010 (25.65) .990 (25.15) pin 1 .200 (5.08) max .054 (1.37) .047 (1.19) 4.260 (108.20) 4.240 (107.70) .133 (3.38) typ .400 (10.16) typ .080 (2.03) .040 (1.02) typ .125 (3.18) typ .235 (5.97) min .250 (6.35) .250 (6.35) 1.75 (44.45) typ 3.75 (95.25) 1.010 (25.65) .990 (25.15) pin 1 .350 (8.98) max .054 (1.37) .047 (1.19) 4.260 (108.20) 4.240 (107.70) .133 (3.38) typ .400 (10.16) typ .125 (3.18) typ .235 (5.97) min .250 (6.35) .250 (6.35) 1.75 (44.45) typ 3.75 (95.25) .050 (1.27) typ .080 (2.03) .040 (1.02) typ note: 1. all dimensions in inches (millimeters) max or typical where noted. min 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.

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