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lxt908 universal 3.3v 10base-t and aui transceiver march 2000 data sheet general description features revision 1.6 refer to www.level1.com for most current information. ) mode select logic controller compatibility/ port select / loopback / link test squelch / link detect manchester decoder collision logic watchdog timer xtal osc manchester encoder select: pls only or pls / mau do autosel paui lbk li tclk clko clki ten txd cd ledl md0 tpopa tpona tponb tpip tpin pulse shaper and filter twisted pair interface collision/ polarity detect correct rc rc di lpbk collision receiver rxd rclk col ci md1 tpopb dop don dip din cip cin ledr ledt/pdn ledc/fde nth jab plr + - drop cable interface ecl tx amp rx slicer rx slicer cmos tx amp dsqe md2 the lxt908 universal 10base-t and aui transceiver is designed for ieee 802.3 physical layer applications. it provides all the active circuitry to interface most standard 802.3 controllers to either the 10base-t media or attachment unit interface (aui). in addition to standard 10 mbps ethernet, the lxt908 also supports full-duplex operation at 20 mbps. lxt908 functions include manchester encoding/decoding, receiver squelch and transmit pulse shaping, jabber, link testing and reversed polarity detection/correction. the lxt908 can be used to drive either the aui drop cable or the 10base-t twisted-pair cable with only a simple isolation transformer. integrated filters simplify the design work required for fcc-compliant emi performance. the lxt908 is fabricated with an advanced cmos process and requires only a single 3.3v power supply. applications ? 10base-t hub and switching products ? computer/workstation 10base-t lan adapter boards functional features ? improved filters - simplifies fcc compliance ? integrated manchester encoder/decoder ? 10base-t compliant transceiver ? aui transceiver ? supports standard and full-duplex ethernet convenience features ? automatic/manual aui/rj-45 selection ? automatic polarity correction ? sqe disable/enable function ? power down mode with tristated outputs ? four loopback modes ? single 3.3v operation ? available in 64-pin lqfp and 44-pin plcc package ? commercial (0 to +70c) and extended (-40 to +85c) temperature range diagnostic features ? four led drivers ? aui/rj-45 loopback lxt908 block diagram
lxt908 universal 3.3v 10base-t and aui transceiver 2 table of contents pin assignments and signal descriptions .......... 3 functional description .......................................... 7 introduction ......................................................... 7 controller compatibility modes ........................... 7 transmit function ............................................... 7 jabber control function ..................................... 8 receive function ................................................ 8 sqe function ..................................................... 8 polarity reverse function ................................... 9 loopback function ............................................ 9 collision detection function ............................... 9 link integrity test function .............................. 10 application information ....................................... 12 external components ....................................... 12 layout requirements ........................................ 12 auto port select with external loopback control .............................................................. 12 full - duplex support ........................................ 14 dual network support - 10base-t and token ring .................................................................. 15 manual port select & link test function .......... 16 three media application ................................... 18 aui encoder/decoder only ............................... 19 test specifications ...............................................20 absolute maximum values ................................20 recommended operating conditions ...............20 i/o electrical characteristics .............................21 aui electrical characteristics ............................21 twisted-pair electrical characteristics ..............22 switching characteristics ..................................23 rclk/start-of-frame timing .............................23 rclk/end-of-frame timing ..............................24 transmit timing .................................................24 collision, col/ci output and loopback timing 25 mode 1 timing diagrams ..................................26 mode 2 timing diagrams ..................................28 mode 3 timing diagrams ..................................30 mode 4 timing diagrams ..................................32 mode 5 timing diagrams ..................................34 mechanical specifications ...................................36 revision history ...................................................38
lxt908 lxt908 pin assignments and signal descriptions 3 lxt908 pin assignments and signal descriptions figure 1: lxt908 pin assignments 7 8 9 10 11 12 13 14 15 16 17 n/c li jab test tclk txd ten clko clki col autosel tpin tpip dsqe tponb tpona vcc2 gnd2 tpopa tpopb plr n/c 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 ledr ledt/pdn ledl ledc/fde lbk gnd1 rbias md2 rxd cd rclk md1 md0 nth cin cip vcc1 don dop din dip paui 6 5 4 3 2 1 44 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n/c n/c paui dip din n/c dop don vcca vcc1 cip cin nth md0 md1 n/c n/c n/c tpin tpip n/c dsqe tponb tpona vcc2 gnd2 tpopa tpopb plr n/c n/c n/c 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 n/c n/c li n/c jab test tclk txd ten clko clki col autosel n/c n/c n/c n/c rclk cd rxd md2 n/c rbias n/c gnda gnd1 lbk ledc/fde ledl ledt/pdn ledr n/c 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 xxxx xxxx lxt908pc/pe xxxxxx ( date code) (part#) (lot#) (trace code) xxxx xxxx LXT908LC/le xxxxxx (part#) (lot#) (trace code) (date code)
lxt908 universal 3.3v 10base-t and aui transceiver 4 table 1: lxt908 signal descriptions pin# symbol i/o description plcc lqfp 1 34 10 56 vcc1 vcc2 C C power 1 and 2. connect to positive power supply terminal (+3.3v dc). C9vccaC analog supply. (+3.3v) 2 3 11 12 cip cin i i aui collision pair. differential input pair connected to the aui transceiver ci circuit. the input is collision signaling or sqe. 413nthi normal threshold. when nth is high, the normal tp squelch threshold is in effect. when nth is low, the normal tp squelch threshold is reduced by 4.5 db. 5 6 25 14 15 44 md0 md1 md2 i i i mode select 0 (md0), mode select 1 (md1) and mode select 2 (md2). mode select pins determine the controller compatibility mode as specified in table 2 . 7, 29 1, 2, 6 16, 17 18, 20 30, 31 32, 33 41, 43 48, 49, 50, 51, 60, 63, 64 n/c C no connect. these pins may be left unconnected or tied to ground. 819 li i link test enable. controls link integrity test; enabled when high, disabled when low. 921jabo jabber indicator. output goes high to indicate jabber state. 10 22 test i test. this pin must be tied high. 11 23 tclk o transmit clock. a 10 mhz clock output. this clock signal should be directly connected to the transmit clock input of the controller. tclk goes to high impedance (tri-state) when ledt/pdn is pulled low externally. 12 24 txd i transmit data. input signal containing nrz data to be transmitted on the network. txd is connected directly to the transmit data output of the controller. 13 25 ten i transmit enable. enables data transmission and starts the watch-dog timer. synchronous to tclk (see test specifications for details). 14 15 26 27 clko clki o i crystal oscillator. a 20 mhz crystal must be connected across these pins, or a 20 mhz clock applied at clki with clko left open. 16 28 col o collision detect. output driving the collision detect input of the controller. col goes to high impedance (tri-state) when ledt/pdn is pulled low externally.
lxt908 lxt908 pin assignments and signal descriptions 5 17 29 autosel i automatic port select. when high, automatic port selection is enabled (the lxt908 defaults to the aui port only if tp link integrity = fail). when low, manual port selection is enabled (the paui pin determines the active port). 18 34 ledr o receive led. open drain driver for the receive indicator led. output is pulled low during receive, except when data is being looped back to din/ dip from a remote transceiver (external mau). led on time (low output) is extended by approximately 100 ms. 19 35 ledt/ pdn o i transmit led (ledt)/power down (pdn ). open drain driver for the transmit indicator led. output is pulled low during transmit. do not allow this pin to float. if unused, tie high. led on time (low output) is extended by approximately 100 ms. if externally tied low, the lxt908 goes to power down state. in power down state, tclk, col, rxd, cd, and rclk (pins 11, 16, 26, 27, and 28, respectively) are tri-stated. 20 36 ledl o i link led. open drain driver for link integrity indicator led. output is pulled low during link test pass. if externally tied low, internal circuitry is forced to link pass state and the lxt908 will continue to transmit link test pulses. 21 37 ledc/ fde o i collision led (ledc)/full duplex enable (fde ). open drain driver for the collision indicator led pulls low during collision. led on time (low output) is extended by approximately 100 ms. if externally tied low, the lxt908 disables the internal tp loopback and collision detection cir- cuits to allow full-duplex operation or external tp loopback. 22 38 lbk i loopback. enables internal loopback mode. refer to functional description and test specifications for details. 23 33 39 55 gnd1 gnd2 C C ground returns 1 and 2. connect to negative power supply terminal (ground). C 40 gnda C analog ground. ground for analog plane. 24 42 rbias i bias control. a 12.4 k w 1% resistor to ground at this pin controls operating circuit bias. 26 45 rxd o receive data. output signal connected directly to the receive data input of the controller. rxd goes to high impedance (tri-state) when ledt/pdn is pulled low externally. 27 46 cd o carrier detect. an output to notify the controller of activity on the network. cd goes to high impedance (tri-state) when ledt/pdn is pulled low externally. 28 47 rclk o receive clock. a recovered 10 mhz clock that is synchronous to the received data and connected to the controller receive clock input. rclk goes to high impedance (tri-state) when ledt/pdn is pulled low externally. 30 52 plr o polarity reverse. output goes high to indicate reversed polarity at the tp input. table 1: lxt908 signal descriptions C continued pin# symbol i/o description plcc lqfp
lxt908 universal 3.3v 10base-t and aui transceiver 6 32 35 31 36 54 57 53 58 tpopa tpona tpopb tponb o o o o twisted-pair transmit pairs a & b. two differential driver pair outputs (a and b) to the twisted-pair cable. the outputs are pre-equalized. each pair must be shorted together with an 11.5 w 1% resistor to match an impedance of 100 w . 37 59 dsqe i disable sqe. when dsqe is high, the sqe function is disabled. when dsqe is low, the sqe function is enabled. sqe must be disabled for normal operation in hub/switch applications. 38 39 61 62 tpip tpin i i twisted-pair receive pair. a differential input pair from the tp cable. receive filter is integrated on chip. no external filters are required. 40 3 paui i port/aui select. in manual port select mode (autosel low), paui selects the active port. when paui is high, the aui port is selected. when paui is low, the tp port is selected. in auto port select mode, paui must be tied to ground. 41 42 4 5 dip din i i aui receive pair. differential input pair from the aui transceiver di circuit. the input is manchester encoded. 43 44 7 8 dop don o o aui transmit pair. a differential output driver pair for the aui transceiver cable. the output is manchester encoded. table 1: lxt908 signal descriptions C continued pin# symbol i/o description plcc lqfp
lxt908 lxt908 functional description 7 lxt908 functional description introduction the lxt908 universal 10base-t and aui transceiver performs the physical layer signaling (pls) and media attachment unit (mau) functions as defined by the ieee 802.3 specification. it functions as an aui (pls-only device) for use with 10base-2 or 10base-5 coaxial cable networks, or as an integrated pls/mau for use with 10base-t twisted-pair (tp) networks. in addition to standard 10 mbps operation, the lxt908 also supports full-duplex 20 mbps operation. the lxt908 interfaces a back-end controller to either an aui drop cable or a tp cable. the controller interface includes transmit and receive clock and nrz data channels, as well as mode control logic and signaling. the aui interface comprises three circuits: data output (do), data input (di), and collision (ci). the tp interface comprises two circuits: twisted-pair input (tpi) and twisted-pair output (tpo). in addition to the three basic interfaces, the lxt908 contains an internal crystal oscillator and four led drivers for visual status reporting. functions are defined from the back end controller side of the interface. the lxt908 transmit function refers to data transmitted by the back end to the aui cable (pls-only mode) or to the tp network (integrated pls/mau mode). the lxt908 receive function refers to data received by the back end from the aui cable (pls-only) or from the tp network (integrated pls/mau mode). in the integrated pls/mau mode, the lxt908 performs all required mau functions defined by the ieee 802.3 10baseCt specification such as collision detection, link integrity testing, signal quality error messaging, jabber control, and loopback. in the pls-only mode, the lxt908 receives incoming signals from the aui di circuit with 18 ns of jitter and drives the aui do circuit. controller compatibility modes the lxt908 is compatible with most industry-standard controllers including devices produced by advanced micro devices (amd), motorola, intel, fujitsu, national semiconductor, seeq, and texas instruments, as well as custom controllers. five different control signal timing and polarity schemes (modes 1 through 5) are required to achieve this compatibility. mode select pins (md2:0) determine controller compatibility modes as listed in table 2 . refer to test specifications for a complete set of timing diagrams for each mode. transmit function the lxt908 receives nrz data from the controller at the txd input as shown in the block diagram on the first page of this data sheet, and passes it through a manchester encoder. the encoded data is then transferred to either the aui cable (the do circuit) or the tp network (the tpo circuit). the advanced integrated pulse shaping and filtering network produces the output signal on tpon and tpop, shown in figure 2 . the tpo output is pre-distorted and pre-filtered to meet the 10base-t jitter template. an internal continuous resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping circuitry. integrated filters simplify the design work required for fcc-compliant emi performance. during idle periods, the lxt908 transmits link integrity test pulses on the tpo circuit (if li is enabled and integrated pls/ mau mode is selected). external resistors control the termination impedance. fi g ure 2: lxt908 tpo output waveform 4v 2v 0v -2v -4v table 2: controller compatibilit y mode options controller mode md2 md1 md0 mode 1 - for amd am7990, motorola 68en360, mpc860 or compatible controllers low low low mode 2 - for intel 82596 or compatible controllers low low high mode 3 - for fujitsu mb86950, mb86960 or compatible controllers (seeq 8005) 1 low high low mode 4 - for national semiconductor 8390 or compatible controllers (ti tms380c26) low high high mode 5 - for custom controllers (mode 3 with tclk, rclk and col inverted) high high low 1. seeq controllers require inverters on clki, lbk, rclk, and col in mode 3; or on clki, lbk, and tclk in mode 5.
lxt908 universal 3.3v 10base-t and aui transceiver 8 jabber control function figure 3 is a state diagram of the lxt908 jabber control function. the lxt908 on-chip watch-dog timer prevents the dte from locking into a continuous transmit mode. when a transmission exceeds the time limit, the watch-dog timer disables the transmit and loopback functions, and activates the jab pin. once the lxt908 is in the jabber state, the txd circuit must remain idle for a period of 0.25 to 0.75 seconds before it will exit the jabber state. receive function the lxt908 receive function acquires timing and data from the tp network (the tpi circuit) or from the aui (the di circuit). valid received signals are passed through the on-chip filters and manchester decoder then output as decoded nrz data and recovered clock on the rxd and rclk pins, respectively. an internal rc filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. the receive function is activated only by valid data streams above the squelch level and with proper timing. if the differential signal at the tpi or the di circuit inputs falls below 75% of the threshold level (unsquelched) for 8 bit times (typical), the lxt908 receive function enters the idle state. if the polarity of the tpi circuit is reversed, lxt908 detects the polarity reverse and reports it via the plr output. the lxt908 automatically corrects reversed polarity. sqe function in the integrated pls/mau mode, the lxt908 supports the signal quality error (sqe) function as shown in figure 3 , although the sqe function can be disabled. after every successful transmission on the 10base-t network when sqe is enabled, the lxt908 transmits the sqe signal for 10bt 5bt over the internal ci circuit, which is indicated on the col pin of the device. sqe must be disabled for normal operation in hub and switch applications. in tp applications, the sqe function is disabled when dsqe is set high, and enabled when dsqe is low. when using the 10base-2 port of the lxt908, the sqe function is determined by the external mau attached. figure 3: jabber control function no output nonjabber output start_xmit_max_timer power on do=active jab xmit=disable lpbk=disable ci=sqe unjab wait start_unjab_timer xmit=disable lpbk=disable ci=sqe do=active * xmit_max_timer_done do=idle do=idle un j ab_ timer_done do=active * un j ab_timer_not_done figure 4: sqe function output idle output detected power on do=active sqe wait test start_sqe_test__wait_timer sqe test start_sqe_test_timer ci=sqe sqe_test__wait_timer_done * xmit=enable do=idle sqe_test_timer_done xmit=disable
lxt908 lxt908 functional description 9 polarity reverse function the lxt908 polarity reverse function uses both link pulses and end-of-frame data to determine polarity of the received signal. a reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. reversed polarity is also detected if four frames are received with a reversed start-of-idle. whenever a correct polarity frame or a correct link pulse is received, these two counters are reset to zero. if the lxt908 enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. if link integrity testing is disabled, polarity detection is based only on received data. polarity correction is always enabled. loopback function the lxt908 provides the normal loopback function specified by the 10base-t standard for the twisted-pair port. the loopback function operates in conjunction with the transmit function. data transmitted by the back-end is internally looped back within the lxt908 from the txd pin through the manchester encoder/decoder to the rxd pin and returned to the back-end. this normal loopback function is disabled when a data collision occurs, clearing the rxd circuit for the tpi data. normal loopback is also disabled during link fail and jabber states. the lxt908 also provides three additional loopback functions. an external loopback mode, useful for system- level testing, is controlled by pin 21 (ledc). when ledc is tied low, the lxt908 disables the collision detection and internal loopback circuits, to allow external loopback or full-duplex operation. normal tp loopback is controlled by pin 22 (lbk). when the tp port is selected and lbk is high, tp loopback is forced, overriding collisions on the tp circuit. when lbk is low, normal loopback is in effect. aui loopback is also controlled by the lbk pin. when the aui port is selected and lbk is high, data transmitted by the back-end is internally looped back from the txd pin through the manchester encoder/decoder to the rxd pin. when lbk is low, no aui loopback occurs. collision detection function the collision detection function operates on the twisted pair side of the interface. for standard (half-duplex) 10base-t operation, a collision is defined as the simultaneous presence of valid signals on both the tpi circuit and the tpo circuit. the lxt908 reports collisions to the back-end via the col pin. if the tpi circuit becomes active while there is activity on the tpo circuit, the tpi data is passed to the back-end over the rxd circuit, disabling normal loopback. figure 5 is a state diagram of the lxt908 collision detection function. refer to test specifications for collision detection and col/ci output timing note: for full-duplex operation, the collision detection circuitry must be disabled. figure 5: collision detection function idle power on collision tpo=do di=tpi ci=sqe output tpo=do di=do input di=tpi do=active * tpi=idle * xmit=enable do=active * tpi=active * xmit=enable do=active * tpi=active * xmit=enable do=active * tpi=idle do=idle + xmit=disable do=idle tpi=idle tpi=active a a a
lxt908 universal 3.3v 10base-t and aui transceiver 10 link pulse transmission the lxt908 transmits standard link pulses which meet the 10base-t specifications. figure 6 shows the link integrity pulse timing. figure 6: transmitted link integrity pulse timing 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms
lxt908 lxt908 functional description 11 link integrity test function figure 7 is a state diagram of the lxt908 link integrity test function. the link integrity test is used to determine the status of the receive side twisted-pair cable. link integrity testing is enabled when pin 8 (li) is tied high. when enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic. if no serial data stream or link integrity pulses are detected within 50 - 150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. the lxt908 ignores any link integrity pulse with interval less than 2 - 7 ms. the lxt908 will remain in the link fail state until it detects either a serial data packet or two or more link integrity pulses. figure 7: link integrity test function idle test start_link_loss_timer start_link_test_min_timer power on link test fail reset link_count=0 xmit=disable rcvr=disable lpbk=disable link_loss_timer_done * tpi=idle * link_test_rcvd=false tpi=active + (link_test_rcvd=true * link_test_min_timer_done) link test fail wait xmit=disable rcvr=disable lpbk=disable link_count=link_count + 1 link test fail start_link_test_min_timer start_link_test_max_timer xmit=disable rcvr=disable lpbk=disable link_test_rcvd=false * tpi=idle tpi=active tpi=active link_test_rcvd=idle * tpi=idle link test fail extended xmit=disable rcvr=disable lpbk=disable tpi=active + link_count=lc_max link_test_min_timer_done * link_test_rcvd=true (tpi=idle * link_test_max_timer_done) + (link_test_min_timer_not_done * link_test_rcvd=true) tpi=idle * do=idle
lxt908 universal 3.3v 10base-t and aui transceiver 12 application information figures 8 through 14 show some typical lxt908 applications. external components crystal information suitable crystals are available from various manufacturers. table 3 lists some suitable crystals based on limited evaluation. designers should test and validate all crystals before using them in production. magnetic information the tp interface requires a 1:1 ratio for the receive transformer and a 1:2 ratio for the transmit transformer. the aui interface requires a 1:1 ratio for the data-in, data- out, and collision-pair transformers. a cross-reference list of suitable magnetics and part numbers is available in application note 73, magnetic manufacturers , which can be found on the level one web site (www.level1.com). designers should test and validate all magnetics before committing to a specific component. layout requirements auto port select with external loopback control figure 8 is a typical lxt908 application. the diagram is arranged to group similar pins together; it does not represent the actual lxt908 pin-out. the controller interface pins (txd, rxd, ten, tclk, rclk, cd, col, and lbk) are shown at the top left. programmable option pins are grouped center left. the paui pin is tied low and all other option pins are tied high. this setup selects the following options: ? automatic port selection (paui low and autosel high) ? normal receive threshold (nth high) ? mode 4, compatible with national ns8390 controllers (md2:0 = low, high, high) ? sqe disabled (dsqe high) ? link testing enabled (li high) status outputs are grouped at lower left. line status outputs drive led indicators and the jabber and polarity status indicators are available as required. power and ground pins are shown at the bottom of the diagram. a single power supply is used for both vcc1 and vcc2 with a decoupling capacitor installed between the power and ground busses. an additional power and ground pin (vcca and gnda) is supported in designs using the 64-pin lqfp package. a single power supply is used for all three power and ground pins (vcc1, vcc2, vcca) and (gnd1, gnd2, gnda). install a decoupling capacitor between each power and ground buss. the tp and aui interfaces are shown at upper and lower right, respectively. impedance matching resistors for 100 utp are installed in each i/o pair but no external filters are required. table 3: suitable crystals manufacturer part number mtron mp-1 mp-2
lxt908 application information 13 figure 8: lan adapter board - auto port select with external loopback control lxt908 20 mhz 20 pf 20 pf clki txd tpin 100 w tpip 1 : 1 116 14 6 5 4 3 2 1 11 9 rj45 3 6 8 to 10 base-t twisted- pair network 1 2 4 5 7 89 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip rbias gnd2 gnd1 ten d - connector to aui drop cable chassis gnd fuse 78 w 78 w 78 w 12.4 k w tclk rclk rxd cd col lbk paui autosel nth md2 md1 dsqe li jab plr txd txe txc rxc rxd crs col lbk green red red red ns8390 back-end controller interface loopback enable programming options mode select line status 1 % +3.3v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clko 330 330 330 330 1 : 2 test tpona tponb tpopa tpopb 11.5 w 1% 11.5 w 1% md0 bias resistor rbias should be located close to the pin and isolated from other signals. 1 1 220pf
lxt908 universal 3.3v 10base-t and aui transceiver 14 full duplex support figure 9 shows the lxt908 with a texas instruments 380c24 commprocessor. the 380c24 is compatible with mode 4 (md2:0 = low, high, high). when used with the 380c24 or other full duplex-capable controller, the lxt908 supports full-duplex ethernet, effectively doubling the available bandwidth of the network. in this application the sqe function is enabled (dsqe tied low), and the lxt908 aui port is not used. figure 9: full-duplex operation 3 lxt908 clki txd tpin 100 w tpip 1 : 1 116 14 6 5 4 3 2 1 11 9 rj45 3 6 8 cin cip don dop din dip rbias gnd2 gnd1 ten 12.4 k w tclk rclk rxd cd col lbk ledc/fde txd txen txc rxc rxd csn coll lpbk 1 % +3.3 v vcc1 vcc2 clko tms380c24 1 : 2 to 10 base-t twisted- pair network 20 mhz 20 pf 20 pf *test0 1n914 10 k w autosel nth li md2 md1 md0 jab plr green red red programming options mode select line status ledr ledt/pdn ledl 330 330 outsel0 paui 330 1 4.7 k w test dsqe *open collector driver tpona tponb tpopa tpopb 11.5 w 1% 11.5 w 1% paui 1 half/full duplex selection controlled by tms380c24 pi n test0 and outsel0. bias resistor rbias should be located close to the pin and isolated from other signals. 2 3 the tms380c26 may be substituted for dual network support of 10base-t and token ring. 2 220pf
lxt908 application information 15 dual network support-10base t and token ring figure 10 shows the lxt908 with a texas instruments 380c26 commprocessor. the 380c26 is compatible with mode 4 (md2:0 = low, high, high). when used with the 380c26, both the lxt908 and a tms38054 token ring transceiver can be tied to a single rj-45 allowing dual network support from a single connector. the lxt908 aui port is not used. figure 10: lxt908/380c26 interface for dual network support of 10base-t and token ring lxt908 20 mhz 20 pf 20 pf clki txd tpin 100 w tpip 1 : 1 116 14 6 5 4 3 2 1 11 18 pf 9 tpona tponb tpopb tpopa rj45 3 6 8 from ti tms38054 token ring transceiver cin cip don dop din dip rbias gnd2 gnd1 ten 1 12.4 k w tclk rclk rxd cd col lbk paui autosel nth dsqe li md2 md1 md0 jab plr txd txe txc rxc rxd crs col lbk green red red red programming options mode select line status 1 % +3.3 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clko 330 330 330 330 380c26 2 to ti tms38054 token ring transceiver 1 : 2 to 10 base-t twisted- pair network bias resistor rbias should be located close to the pin and isolated from other signals. 1 2 additional magnetics and switching logic (not shown) is required to implement the dual network solution. test 11.5 w 1% 11.5 w 1% 220pf
lxt908 universal 3.3v 10base-t and aui transceiver 16 manual port select & link test function with md2:0 = low, high, low, the lxt908 logic and framing are set to mode 3 (compatible with fujitsu mb86950 and mb86960, and seeq 8005 controllers). figure 11 shows the setup for fujitsu controllers. figure 12 on page 17 shows the four inverters required to interface with the seeq 8005 controller. as in figure 8 on page 13 , both these mode 3 applications show the li pin tied high, enabling link testing; and the nth and dsqe pins are both tied high, selecting the standard receiver threshold and disabling sqe. however, in these applications autosel is tied low, allowing external port selection through the paui pin. figure 11: lan adapter board - manual port select with link test function lxt908 20 mhz 20 pf 20 pf clki txd tpin 100 w tpip 1 : 1 116 14 6 5 4 3 2 1 11 9 tpona tponb tpopb tpopa rj45 3 6 8 to 10 base-t twisted- pair network 1 2 4 5 7 89 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip rbias gnd2 gnd1 ten d - connector to aui drop cable chassis gnd fuse 1 78 w 78 w 78 w 12.4 k w tclk rclk rxd cd col lbk paui autosel nth md2 dsqe li jab plr txd ten tckn rckn rxd xcd lbc red red red mb86950 or mb86960 back-end/ controller interface programming options line status 1 % +3.3 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clko 330 330 330 1 : 2 green 330 port selection test 11.5 w 1% 11.5 w 1% xcol md1 md0 mode select bias resistor rbias should be located close to the pin and isolated from other signals. 1 220pf
lxt908 application information 17 figure 12: manual port select with seeq 8005 controller lxt908 clki lbk tpin 100 w tpip 1 : 1 116 14 6 5 4 3 2 1 11 9 tpona tponb tpopb tpopa rj45 3 6 8 to 10 base-t twisted- pair network 1 2 4 5 7 89 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip rbias gnd2 gnd1 cd d - connector to aui drop cable chassis gnd fuse 1 78 w 78 w 78 w 12.4 k w rxd rclk col ten tclk txd paui autosel nth dsqe li md2 jab plr red red red programming options line status 1 % +3.3v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 330 330 330 1 : 2 green 330 port selection clko 8005 clki lpbk csn rxd rxc coll txen txc txd external 20 mhz source left open test 11.5 w 1% 11.5 w 1% mode select md1 md0 bias resistor rbias should be located close to the pin and isolated from other signals. 1 220pf
lxt908 universal 3.3v 10base-t and aui transceiver 18 three media application figure 13 shows the lxt908 in mode 2 (compatible with intel 82596 controllers) with additional media options for the aui port. two transformers are used to couple the aui port to either a d-connector or a bnc connector. (a dp8392 coax transceiver with pm6044 power supply are required to drive the thin coax network through the bnc.) figure 13: three media application lxt908 clki txd tpin 100 w tpip 1 : 1 116 14 11.5 w 1% 11.5 w 1% 6 5 4 3 2 1 11 9 tpona tponb tpopb tpopa rj45 3 6 8 to 10 base-t twisted- pair network 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop dip rbias gnd2 gnd1 ten d - connector to aui drop cable (thick coax) chassis gnd fuse 1 78 w 78 w tclk rclk rxd cd col lbk paui autosel nth li md2 md1 md0 jab plr txd rts txc rxc rxd crs cdt lbk 82566 back-end/ controller interface programming options mode select line status 1 % +3.3 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clko 1 : 2 20 mhz system clock clk link test enable power down left open 1 2 4 5 7 89 10 12 13 15 16 78 w 1 2 4 5 7 89 10 12 13 15 16 din cd- cd+ tx- vee tx+ rx- rx+ vee cds txd rxi vee rr- rr+ gnd hbe 1n916 0v bhc to thin coax network 1 k w 1% -9v v+ n/c v- 5v 5v en gnd gnd 12 13 9 1 +5 v 2 3 23 1 m w 1/2 w 24 test 0.1 m f 1.5 k w 0.01 m f75 m f / 1 kv pm6044 dp8392 10 k w dsqe 10 k w 12.4 k w
lxt908 application information 19 aui encoder/decoder only in the application shown in figure 14 , the dte is connected to a coaxial network through the aui. autosel is tied low and paui is tied high, manually selecting the aui port. the twisted-pair port is not used. with md2:0 all tied low, the lxt908 logic and framing are set to mode 1 (compatible with amd and motorola controllers). the li pin is tied low, disabling the link test function. the dsqe pin is also low, enabling the sqe function. the lbk input controls loopback. a 20 mhz system clock is supplied at clki with clko left open. figure 14: aui encoder/decoder only application lxt908 txd rbias gnd2 gnd1 ten 1 tclk rclk rxd cd col lbk autosel nth dsqe li md2 md1 md0 jab plr tx tena tclk rclk rx rena clsn lbk red red red am7990 back-end/ controller interface loopback control programming options mode select line status 1 % green +3.3 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clki 330 330 330 330 1 2 4 5 7 89 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip d - connector to aui drop cable chassis gnd fuse 78 w 78 w 78 w 12.4 k w clko paui 20 mhz left open system clock test bias resistor rbias should be located close to the pin and isolated from the other signals 1
lxt908 universal 3.3v 10base-t and aui transceiver 20 test specifications note tables 4 through 13 and figures 15 through 44 represent the performance specifications of the lxt908. these specifications are guaranteed by test except where noted by design. minimum and maximum values listed in tables 6 through 13 apply over the recommended operating conditions specified in table 5 . . table 4: absolute maximum values parameter symbol min max units supply voltage v cc -0.3 6 v ambient operating temperature (commercial) t a 0+70oc ambient operating temperature (extended) t a -40 +85 oc storage temperature t stg -65 +150 oc caution exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 5: recommended operating conditions parameter symbol min typ max units recommended supply voltage 1 v cc 3.13 3.3 3.47 v recommended operating temperature (commercial) t op 0C+70oc recommended operating temperature (extended) t op -40 C +85 oc 1. voltages with respect to ground unless otherwise specified.
lxt908 test specifications 21 table 6: i/o electrical characteristics parameter sym min typ 1 max units test conditions input low voltage 2 v il CC0.8v input high voltage 2 v ih 2.0 C C v output low voltage v ol CC0.4vi ol = 1.6 ma v ol CC10%v cc i ol < 10 a output low voltage (open drain led driver) v oll CC0.7vi oll = 10 ma output high voltage v oh 2.4 C C v i oh = 40 a v oh 90 C C %v cc i oh < 10 a output rise time tclk & rclk cmos C C 3 12 ns c load = 20 pf ttl C C 2 8 ns output fall time tclk & rclk cmos C C 3 12 ns c load = 20 pf ttl C C 2 8 ns clki rise time (externally driven) C C C 10 ns clki duty cycle (externally driven) C C 40/60 % supply current normal mode i cc C 65 85 ma idle mode i cc C 95 120 ma transmitting on tp i cc C 90 120 ma transmitting on aui power down mode i cc C0.752ma 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. limited functional tests are performed at these input levels. the majority of functional tests are performed at levels of 0v and 3v. table 7: aui electrical characteristics parameter symbol min typ 1 max units test conditions input low current i il CC-700 a input high current i ih CC500 a differential output voltage v od 550 C 1200 mv differential squelch threshold v ds 150 260 350 mv 5 mhz square wave input 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
lxt908 universal 3.3v 10base-t and aui transceiver 22 table 8: twisted-pair electrical characteristics parameter symbol min typ 1 max units test conditions transmit output impedance z out C5C w transmit timing jitter addition 2 C C 6.4 10 ns 0 line length for internal mau transmit timing jitter added by the mau and pls sections 2, 3 C C 3.5 5.5 ns after line model specified by ieee 802.3 for 10base-t internal mau receive input impedance z in C20C k w between tpip/tpin, cip/ cin & dip/din differential squelch threshold normal threshold nth = high v ds 300 395 585 mv 5 mhz square wave input reduced threshold nth = low v ds 180 250 345 mv 5 mhz square wave input 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing. 3. ieee 802.3 specifies maximum jitter additions at 1.5 ns for the aui cable, 0.5 ns from the encoder, and 3.5 ns from the mau.
lxt908 test specifications 23 table 9: switching characteristics parameter symbol minimum typical 1 maximum units jabber timing maximum transmit time C 20 C 150 ms unjab time C 250 C 750 ms link integrity timing time link loss receive C 50 C 150 ms link min receive C 2 C 7 ms link max receive C 50 C 150 ms link transmit period C 8 10/20 24 ms 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 10: rclk/start-of-frame timing parameter symbol minimum typical 1 maximum units decoder acquisition time aui t data C 900 1100 ns tp t data C 1200 1500 ns cd turn-on delay aui t cd C 25 200 ns tp t cd C 420 550 ns receive data setup from rclk mode 1 t rds 60 70 C ns modes 2 through 5 t rds 30 45 C ns receive data hold from rclk mode 1 t rdh 10 20 C ns modes 2 through 5 t rdh 30 45 C ns rclk shut off delay from cd assert (mode 3 and mode 5) tsws C 100 C ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
lxt908 universal 3.3v 10base-t and aui transceiver 24 table 11: rclk/end-of-frame timing parameter type sym mode 1 mode 2 mode 3 mode 4 mode 5 units rclk after cd off min t rc 51 C 5 Cbt rxd throughput delay max t rd 400 375 375 375 375 ns cd turn off delay 2 max t cdoff 500 475 475 475 475 ns receive block out after ten off typ 1 t ifg 550 C C Cbt rclk switching delay after cd off (mode 3 and 5) typ 1 t swe C C 120(80) C 120(80) ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. cd turn-off delay measured from middle of last bit: timing specification is unaffected by the value of the last bit. table 12: transmit timing parameter symbol minimum typical 1 maximum units ten setup from tclk t ehch 22 C C ns txd setup from tclk t dsch 22 C C ns ten hold after tclk t chel 5CCns txd hold after tclk t chdu 5CCns transmit start-up delay - aui t stud C 220 450 ns transmit start-up delay - tp t stud C 430 450 ns transmit through-put delay - aui t tpd CC300ns transmit through-put delay - tp t tpd C 305 350 ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
lxt908 test specifications 25 table 13: collision, col/ci output and loopback timing parameter symbol minimum typical 1 maximum units col turn-on delay t cold C 40 500 ns col turn-off delay t coloff C 420 500 ns col (sqe) delay after ten off t sqed 0.65 1.2 1.6 m s col (sqe) pulse duration t sqep 500 1000 1500 ns lbk setup from ten t kheh 10 25 C ns lbk hold after ten t khel 10 0 C ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
lxt908 universal 3.3v 10base-t and aui transceiver 26 timing diagrams for mode 1 (md2, 1, 0 = low, low, low) figures 15 through 20 figure 15: mode 1 rclk/start-of-frame timing 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t data tpip/tpin or dip/din cd rclk rxd t rds t rdh 0 1 0 0 0 1 0 1 0 note: rxd chan g es 25 ns after the risin g ed g e of rclk . figure 16: mode 1 rclk/end-of-frame timing 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd t cdoff tpip/tpin or dip/din cd rclk rxd t rc note: rxd chan g es 25 ns after the risin g ed g e of rclk .
lxt908 test specifications 27 figure 17: mode 1 transmit timing t chel t ehch t chdu ten tclk txd tpo t tpd t dsch t stud figure 18: mode 1 collision detect timing t coloff t cold ci col figure 19: mode 1 col/sqe output timing/ci output timing t sqep t sqed ten col figure 20: mode 1 loopback timing t khel t kheh lbk ten
lxt908 universal 3.3v 10base-t and aui transceiver 28 timing diagrams for mode 2 (md2, 1, 0 = low, low, high) figures 21 through 26 figure 21: mode 2 rclk/start-of-frame timing 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t rds t rdh cd rclk rxd t data tpip/tpin or dip/din 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 note: rxd chan g es at the risin g ed g e of rclk. the controller should sample at the fallin g ed g e. figure 22: mode 2 rclk/end-of-frame timing 1 0 1 0 1 0 1 0 0 t rd tpip/tpin or dip/din cd rclk rxd 1 0 1 0 1 0 1 0 0 t cdoff note: rxd chan g es at the risin g ed g e of rclk. the controller should sample at the fallin g ed g e.
lxt908 test specifications 29 figure 23: mode 2 transmit timing t chel t ehch t chdu ten tclk txd tpo t dsch t tpd t stud figure 24: mode 2 collision detect timing t coloff t cold ci col figure 25: mode 2 col/sqe output timing t sqed ten col t ifg t sqep figure 26: mode 2 loopback timing t khel t kheh lbk ten
lxt908 universal 3.3v 10base-t and aui transceiver 30 timing diagrams for mode 3 (md2, 1, 0 = low, high, low) figures 27 through 32 figure 27: mode 3 rclk/start-of-frame timing 1 0 1 0 1 0 1 1 1 0 1 0 1 t rds t rdh t data cd rclk rxd tpip/tpin or dip/din 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 t cd t sws recovered from input data stream generated from tclk note: rxd changes at the rising edge of rclk. the controller should sample at the falling edge. figure 28: mode 3 rclk/end-of-frame timing t rd t cdoff cd rclk rxd t swe recovered clock generated from tclk 1 0 1 0 1 0 1 0 0 tpip/tpin or dip/din 1 0 1 0 1 0 1 0 0 note: rxd changes at the rising edge of rclk. the controller should sample at the falling edge.
lxt908 test specifications 31 figure 29: mode 3 transmit timing t chel t ehch t chdu ten tclk txd tpo t stud t dsch t tpd figure 30: mode 3 collision detect timing t coloff t cold ci col figure 31: mode 3 col/sqe output timing t sqed ten col t sqep figure 32: mode 3 loopback timing t khel t kheh lbk ten
lxt908 universal 3.3v 10base-t and aui transceiver 32 timing diagrams for mode 4 (md2, 1, 0 = low, high, high) figures 33 through 38 figure 33: mode 4 rclk/start-of-frame timing 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t data cd rclk rxd tpip/tpin or dip/din t rds t rdh 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 note: rxd changes at the rising edge of rclk. the controller should sample at the falling edge. figure 34: mode 4 rclk/end-of-frame timing 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd tpip/tpin or dip/din cd rclk rxd t cdoff note: rxd changes at the rising edge of rclk. the controller should sample at the falling edge.
lxt908 test specifications 33 figure 35: mode 4 transmit timing t chel t ehch t chdu ten tclk txd tpo t dsch t stud t tpd figure 36: mode 4 collision detect timing t coloff t cold ci col figure 37: mode 4 col/sqe output timing t sqep t sqed ten col figure 38: mode 4 loopback timing t khel t kheh lbk ten
lxt908 universal 3.3v 10base-t and aui transceiver 34 timing diagrams for mode 5 (md2, 1, 0 = high, high, low) figures 39 through 44 figure 39: mode 5 rclk/start-of-frame timing 1 0 1 0 1 0 1 1 1 0 1 0 1 t rds t rdh t data cd rclk rxd tpip/ tpin 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 t cd t sws recovered from input data stream generated from tclk note: rxd changes at the rising edge of rclk. the controller should sample at the falling edge. figure 40: mode 5 rclk/end-of-frame timing t rd t cdoff cd rclk rxd t swe recovered clock generated from tclk 1 0 1 0 1 0 1 0 0 tpip/ tpin 1 0 1 0 1 0 1 0 0 note: rxd changes at the rising edge of rclk. the controller should sample at the falling edge.
lxt908 test specifications 35 figure 41: mode 5 transmit timing t chel t ehch t chdu ten tclk txd tpo t stud t dsch t tpd figure 42: mode 5 collision detect timing t coloff t cold ci col figure 43: mode 5 col/sqe output timing t sqed ten col t sqep figure 44: mode 5 loopback timing t khel t kheh lbk ten
lxt908 universal 3.3v 10base-t and aui transceiver 36 mechanical specifications figure 45: 44-pin plcc package specifications a 2 a d f a 1 c b d 1 d c l 44-pin plastic leaded chip carrier ? part number lxt908pc - commercial temperature range (0 c to +70 c) ? part number lxt908pe - extended temperature range (-40 c to +85 c) dim inches millimeters min max min max a 0.165 0.180 4.191 4.572 a 1 0.090 0.120 2.286 3.048 a 2 0.062 0.083 1.575 2.108 b 0.050 C 1.270 C c 0.026 0.032 0.660 0.813 d 0.685 0.695 17.399 17.653 d 1 0.650 0.656 16.510 16.662 f 0.013 0.021 0.330 0.533
lxt908 mechanical specifications 37 figure 46: 64-pin lqfp package specifications d d 1 a 1 a 2 l a b l 1 q 3 q 3 q e e 1 e / 2 e dim inches millimeters min max min max a C 0.063 C 1.60 a1 0.002 0.006 0.05 0.15 a2 0.053 0.057 1.35 1.45 b 0.007 .011 0.17 0.27 d 0.472 bsc 12.00 bsc d1 0.394 bsc 10.00 bsc e 0.472 bsc 12.00 bsc e1 0.394 bsc 10.00 bsc e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 l1 0.039 ref 1.00 ref q 3 11 o 13 o 11 o 13 o q 0 o 7 o 0 o 7 o 64-pin low-profile quad flat package ? part number LXT908LC (commercial temperature range) ? part number lxt908le (extended temperature range)
lxt908 universal 3.3v 10base-t and aui transceiver 38 revision history table 14: changes from revision 1.5 to revision 1.6 (03/00) section page change text table 1 lxt908 signal descriptions 4 modify add to ledt/pdn description: do not allow this pin to float. if unused, tie high. table 15: changes from revision 1.4 to revision 1.5 (01/99) section page change text front page 1 update delete 5v reference in general description and features list. table 1 signal descriptions 4 update delete 5v reference to supply pins. table 4 magnetics 12 update delete magnetics table 4 (renumber all subsequent tables) and reference application note 73. layout requirements 12 update add power and ground pins (vcca and gnda) for 64- pin lqfp package. figures 13, 14 application diagrams 18, 19 update correct rbias value to 12.4 k w in diagrams. delete note 1 in figure 13 (duplication rbias place- ment). figures 8 - 14 application diagrams 13 - 19 update delete 5v supply reference (3.3v only). table 6 recommended operating conditions 20 update change recommended supply voltage: (min to max respectively) from: 3.135 5.0 5.25v to: 3.13 3.3 3.47v all all edit various minor editing. table 16: changes from revision 1.3 to revision 1.4 (09/98) section page change text product title 1 update change product name to universal 10base-t and aui transceiver . table 1 signal descriptions 4 update correct pin 9 of the lqfp package to include 3.3v supply. test specifications 20-25 update replace test spec note with updated version and delete (over recommended range) note on all test spec tables. backpage 40 update update backpage.
lxt908 revision history 39 table 17: changes from revision 1.2 to revision 1.3 (04/98) section page change text front page 1 update add 64-pin lqfp to features list. figure 1 pin assignments 3 update add 64-pin lqfp pin assignment diagram. table 1 signal descriptions 4 update add lqfp package column and pins. figure 46 package diagram 35 update add 64-pin lqfp package diagram. table 18: changes from revision 1.1 to revision 1.2 (03/98) section page change text front page 1 update add commercial (0 to +70c) and extended (-40 to +85c) temperature range to features list. figure 1 pin assignments 3 update add pe to package designator for extended temperature. tables 5 and 6 absolute max values operating conditions 18 update add extended temperature (-40 to +85c). figure 45 package diagram 34 update add part number lxt908pe and extended temperature range (-40 to +85c). revision history 35 update add revision history section. table 19: changes from revision 1.0 to revision 1.1 (10/97) section page change text table 1 signal descriptions 4 & 5 update change note for no connect pins #7 and #29. this pin may be left unconnected or tied to ground. table 4 suitable magnetics 10 update change belfuse aui magnetic part number from s553-1006-ae to s553-1006-d0.
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