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hms87c5216 sep. 2001 ver 1.0 1 hms87c5216 cmos single-chip 8-bit microcontroller for ur(universal remocon) & wireless keyboard 1. overview 1.1 description the hms87c5216 is an advanced cmos 8-bit microcontroller with 16k bytes of rom. the device is one of gms800 fam- ily. the hynix semicon hms87c5216 is a powerful microcontroller which provides a highly flexible and cost effective solution to many ur & keyboard applications. the hms87c5216 provides the following standard features: 16k bytes of rom, 320 bytes of ram, 8-bit timer/counter, on-chip oscillator,clock circuitry and rc wake up function. 4 chanel adc, in addition, the hms87c5216 series supports power saving modes to reduce power consumption 1.2 features ? instruction cycle time: - 1us at 4mhz ? programmable i/o pins ? operating voltage - 2.0 ~ 5.5 v @ 4mhz ?timer - timer / counter ......... 16bit * 1ch ........ 16bit * 2ch - basic interval timer ...... 8bit * 1ch - watch dog timer ............ 6bit * 1ch ? 8 interrupt sources * nested interrupt control is available. - external input: 2 - keyscan input - basic interval timer - watchdog timer - timer : 3 ? power on reset ? power saving operation modes - stop - sleep ? low voltage detection circuit ? watch dog timer auto start (during 1second after power on reset) ? 4 chanel adc ? rc timer wake up device name rom size eprom size ram size operatind voltage package hms87c5216 - 16k byte 320bytes 2.0 ~ 5.5v 28 sop 40 pdip 44 plcc 44 qfp 28 pin 40 pin 44 pin input 2 2 2 output 2 2 2 i/o 22 34 38
hms87c5216 2 sep. 2001 ver 1.0 1.3 development tools the hms87c5216 and hms87c5216 are supported by a full-featured macro assembler, an in-circuit emulator choice-dr tm . in circuit emulators choice-dr. assembler hme macro assembler otp writer single writer : sigma 4-gang writer : dr.gang otp devices hms87c5216
hms87c5216 sep. 2001 ver 1.0 3 2. block diagram alu accumulator stack pointer interrupt controller data memory 8-bit converter a/d 8-bit counter timer/ program memory data table pc 8-bit basic timer interval watch-dog instruction r1 r2 r3 rc watch timer psw system controller timing generator system clock controller clock generator reset xin xout r10 / int1 r11 / int2 r12 / t0 r13 / t1 r14 / an0 r15 / an1 r16 / an2 r17 / an3 r20 r21 r22 r23 r24 /t2 v dd v ss power supply decoder carrier r25 / ec0 r26 r27 r4 lvd/por r0 r00 / ks0 r01 / ks1 r02 / ks2 r03 / ks3 r04 / ks4 r05 / ks5 r06 / ks6 r07 / ks7 key wake up generator remout r30 r31 r32 r33 r34 r35 r36 r37 r40 r41 r42 r43 r44
hms87c5216 4 sep. 2001 ver 1.0 3. pin assignment 28pin 40pdip r00 1 r01 2 r02 3 r03 4 r04 5 r05 6 r06 7 r07 8 r34 9 r35 10 vdd 11 r36 12 r37 13 xout 14 xin 15 r10 16 r11 17 r12 18 r15 19 resetb 20 r14 remout r26 r25 r24 r23 r22 r21 r20 vss 40 39 38 37 36 35 34 33 32 31 r33 r32 r31 r30 r17 r16 30 29 28 27 26 25 24 23 22 21 r13 r40 41 40 r00 r01 r24 r25 r26 r02 r03 r23 r04 r27 44plcc resetb remout r15 r12 r11 39 38 37 36 35 34 33 32 31 30 29 r40 r45 r10 r35 r34 r07 r06 18 19 20 21 22 23 24 25 26 27 28 vdd r36 r37 xout xin r44 r05 7 8 9 10 11 12 13 14 r14 15 16 17 r42 r33 r20 r21 6 5 4 3 2 1 44 43 42 r32 r31 r30 r17 r22 vss r16 r41 r13 r43 33 32 31 30 29 28 27 26 25 24 23 44qfp 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 38 39 40 41 42 43 44 r35 r34 r07 r06 vdd r36 r37 xout xin r44 r05 r42 r33 r20 r21 r32 r31 r30 r17 r22 vss r16 resetb remout r15 r12 r11 r40 r45 r10 r14 r41 r13 r00 r01 r24 r25 r26 r02 r03 r23 r04 r27 r43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 r01 r02 r03 r04 r05 r06 r07 vdd xout xin r10 r11 r12 r13 r00 remout r25 r24 r23 r22 r21 r20 vss r17 r16 r15 r14 resetb r41 r27
hms87c5216 sep. 2001 ver 1.0 5 4. pin diagram
hms87c5216 6 sep. 2001 ver 1.0 2.045 2.075 0.065 0.015 0.022 0.200 max. 0.530 0.550 0.045 0.100 bsc 0.600 bsc 0.140 0.120 min 0.015 0.012 0.008
hms87c5216 sep. 2001 ver 1.0 7
hms87c5216 8 sep. 2001 ver 1.0 5. pin function v dd : supply voltage. v ss : circuit ground. reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal main clock operating circuit. x out : output from the inverting oscillator amplifier. r00~r07 : r0 is an 8-bit cmos bidirectional i/o port. r0 pins 1 or 0 written to the port direction register can be used as outputs or inputs. r10~r17 : r1 is an 8-bit cmos bidirectional i/o port. r1 pins 1 or 0 written to the port direction register can be used as outputs or inputs. in addition, r1 serves the functions of the various follow- ing special features. r20~r22 , r30~r37 : r2 & r3 is a 8-bit cmos bidirec- tional i/o port. each pins 1 or 0 written to the their port di- rection register can be used as outputs or inputs. in addition, r2 serves the functions of the various follow- ing special features. r40~r43 : r4 is 1-bit cmos bidirectional i/o port. this pin 1 or 0 written to the its port direction register can be used as outputs or inputs. port pin alternate function r10 r11 r12 r13 r14 r15 r16 r17 int1 (external interrupt input 1) int2 (external interrupt input 2) t0 (timer / counter inpit 0) t1 (timer / counter inpit 1) an0 (adc input 0) an1 (adc input 1) an2 (adc input 2) an3 (adc input 3) port pin alternate function r24 r25 t2 (timer / counter inpit 2) /ec (event counter input )
hms87c5216 sep. 2001 ver 1.0 9 6. @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
hms87c5216 10 sep. 2001 ver 1.0 7. port structures ? reset
hms87c5216 sep. 2001 ver 1.0 11 ? xin, xout t ?
hms87c5216 12 sep. 2001 ver 1.0 ? ra0/ec0 t ?
hms87c5216 sep. 2001 ver 1.0 13 ? ra1/an1 ~ ra7/an7 xin xout
hms87c5216 14 sep. 2001 ver 1.0 8. electrical characteristics (hms87c5216/gms81c1408) 8.1 absolute maximum ratings supply voltage ........................................... -0.3 to +7.0 v storage temperature ................................-40 to +125 c aximum current out of v ss pin..........................tbd ma maximum current into v dd pin ........................tbd ma maximum current sunk by (i ol per i/o pin) ....tbd ma maximum output current sourced by (i oh per i/o pin) ...........................................................................tbd ma maximum current ( s i ol ) ...................................tbdma maximum current ( s i oh ) ...................................tbdma note: stresses above those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional op- eration of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8.2 recommended operating conditions 8.3 a/d converter characteristics (t a =25 c, v ss =0v, v dd =3.072v @ f xin =4mhz) 8.4 dc electrical characteristics (t a =-20~85 c for hms87c5216/1408 or t a =-40~85 c for hms87c5216e/1408e, v dd =2.2~5.5v , v ss =0v) , parameter symbol condition specifications unit min. max. supply voltage v dd f xin =4mhz 2.0 5.5 v operating frequency f xin v dd =2.0~5.5v 14mhz operating temperature t opr v dd =2.0~5.5v -20 85 c parameter symbol condition specifications unit min. typ. max. analog input voltage range v ain - v ss- 0.3 - v dd +0.3 v current following between avdd and avss iavdd - - - 200 ua overall accuracy n acc -- 1.0 2.0 lsb non-linearity error n nle -- 1.0 2.0 lsb differential non-linearity error n dnle -- 1.0 2.0 lsb zero offset error n zoe - 0.5 1.5 lsb full scale error n fse - 0.25 0.5 lsb gain error n nle - 1.0 1.5 lsb conversion time t conv f xin =4mhz --30us parameter symbol pin condition specifications unit min. typ. max. input high voltage v ih1 x in , reset 0.8 v dd - v dd v
hms87c5216 sep. 2001 ver 1.0 15 input high voltage v ih1 reset,xin,int1,in t2,ec0,r1<7:4> 0.8v dd - v dd v v ih2 r0,r1,r2,r3,r4 0.7v dd - v dd v input low voltage v il1 reset,xin,int1,in t2,ec0,r1<7:4> 0 - 0.2v dd v v il2 r0,r1,r2,r3,r4 0 - 0.3v dd v input high leakage current i ih r0,r1,r2,r3,r4 resetb v ih =vdd --1.0 m a input low leakage current i il r0,r1,r2,r3,r4 v il =0v ---1.0 m a output high voltage v oh1 r0,r1<3:0>,r2,r3, r4 ioh1=-0.8ma,vdd=3v vdd-0.4 - - v v oh2 r1<7:0>, i oh2=-2.0ma,vdd=3v vdd-0.4 - - v v oh3 xout ioh3=-50ua,vdd=3v vdd-0.5 - - v output low voltage v ol1 r0,r1<3:0>,r2,r3, r4 i ol =5ma,v dd =3v - -0.8v v ol2 xout i ol =50ua,v dd =3v - -0.5v output high leakage current i iohl r0,r1,r2,r3,r4 v oh =vdd --1.0 m a output low leakage current i ioll r0,r1,r2,r3,r4 v ol =0v ---1.0 m a output high current i oh remout vdd=3v,voh=2.0v -20 - -5 ma output low current i ol remout vdd=3v,vol=1.0v -0.5 - 3 ma input pull-up i p r0,r1,r2,r3,r4 resetb v dd =3v 50 100 200 k hysteresis | v t | hysteresis input 1 v dd =5v 0.5 - - v feed back resistor rf! main osc feedback resistor v dd =3.0v, f xin =4mhz 0.2 - 1.0 supply currnet i dd active mode v dd =4.0v -4.010ma v dd =2.0v -2.46ma i sleep sleep mode v dd =4.0v -2.03.0ma v dd =2.0v -1.02.0ma i stop stop mode,osc stop v dd =4.0v -5.030 m a v dd =2.0v -3.025 m a parameter symbol pin condition specifications unit min. typ. max.
hms87c5216 16 sep. 2001 ver 1.0 8.5 ac characteristics (t a =-20~85 c for hms87c5216/1408 or t a =-40~85 c for hms87c5216e/1408e, v dd =5v 10% , v ss =0v) figure 8-1 timing chart parameter symbol pins specifications unit min. typ. max. operating frequency f mcp x in 1-4mhz systemp clock cycle time t sys - 0.5 - 2.0 us oscillation stabilizing time(4mhz) t mst! x in , x out --20ms external clock h or l pulse width t cpw x in 80 ns external clock transition time t rcp, t fcp x in - - 20 ns interrupt input pulse width t lw int1,int2 2 - t sys resetb input pulse l width t rst resetb 8 - - t sys event couter input h or l pulse width t tcw eco 2 - - t sys event couter transition time t rec, t fec eco 0 - 20 ns
hms87c5216 sep. 2001 ver 1.0 17 9. memory organization the hms87c5216 have separate address spaces for pro- gram memory and data memory. program memory can only be read, not written to. it can be up to 16k bytes of program memory. data memory can be read and written to up to 320 bytes including the stack area. 9.1 registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 9-1 configuration of registers accumulator: the accumulator is the 8-bit general pur- pose register, used for data operation such as transfer, tem- porary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. figure 9-2 configuration of ya 16-bit register x, y registers : in the addressing mode which uses these index registers, the register contents are added to the spec- ified address, which becomes the actual address. these modes are extremely effective for referencing subroutine tables and memory tables. the index registers also have in- crement, decrement, comparison and data transfer func- tions, and they can be used as simple accumulators. stack pointer : the stack pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be accessed (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. the stack can be located at any position within 100 h to 17f h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the loca- tion with which the use of the stack starts) by using the ini- tialization routine. normally, the initial value of 17f h is used. note: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #07fh txsp ; sp ? 7f h program counter : the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset rou- tine address (pc h :0ff h , pc l :0fe h ). program status word : the program status word (psw) contains several bits that reflect the current state of the cpu. the psw is described in figure 9-3 . it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared by any other result. a accumulator x register y register stack pointer program counter program status word x y sp pcl pch psw two 8-bit registers can be used as a ya 16-bit register y a y a sp 1 stack address (100 h ~17f h ) 15 0 87 hardware fixed
hms87c5216 18 sep. 2001 ver 1.0 figure 9-3 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all inter- rupts are disabled when cleared to 0. this flag immedi- ately becomes 0 when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector ad- dress. [overflow flag v] this flag is set to 1 when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction ex- ceeds +127(7f h ) or -128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. when the bit in- struction is executed, bit 7 of memory is copied to this flag. [direct page flag g] this flag assigns ram page for direct addressing mode. in the direct addressing mode, addressing area is from zero page 00 to ff when this flag is 0. if it is set to 1, addressing area is 1 page. it is set by instruction and cleared by clrg. n negative flag v g b h i z c msb lsb reset value: 00 h psw overflow flag select direct page flag carry flag receives zero flag interrupt enable flag carry out half carry flag receives carry out from bit 1 of addition operlands brk flag
hms87c5216 sep. 2001 ver 1.0 19 9.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but these devices have 16k bytes program memory space only physically implemented. accessing a location above ffff h will cause a wrap-around to 0000 h . figure 9-4 , shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h and ffff h as shown in figure 9-5 . as shown in figure 9-4 , each area is assigned a fixed lo- cation in program memory. program memory area con- tains the user program. figure 9-4 program memory map page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall in- stead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. the table call service area spaces 2-byte for every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 9-6 . example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 0, for example, is assigned to loca- tion 0fffa h . the interrupt service locations spaces 2-byte interval: 0fff8 h and 0fff9 h for external interrupt 1, 0fffa h and 0fffb h for external interrupt 0, etc. as for the area from 0ff00 h to 0ffff h , if any area of them is not going to be used, its service location is avail- able as general purpose program memory. figure 9-5 interrupt vector area program memory tcall area interrupt vector area c000h feffh ff00h ffc0h ffdfh ffe0h ffffh pcall area f000h lda #5 tcall 0fh ; 1byte instruction :; instead of 3 bytes :; normal call ; ;table call routine ; func_a: lda lrg0 ret ; func_b: lda lrg1 ret ; ;table call add. area ; org 0ffc0h ; tcall address area dw func_a dw func_b 1 2 0ffe0 h e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe - - adc interrupt vector area rc wt interrupt vector area wdt interrupt vector area - timer/counter 2 interrupt vector area timer/counter 0 interrupt vector area - ext2 interrupt vector area key scan interrupt vector area - reset vector area ext1 interrupt vector area timer/counter 1 interrupt vector area bit interrupt vector area - means reserved area. note:
hms87c5216 20 sep. 2001 ver 1.0 figure 9-6 pcall and tcall memory area pcall ? rel 4f35 pcall 35h tcall ? n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffff h pcall area (256 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ next 35 0ff35h 0ff00h 0ffffh 11111111 11010110 01001010 pc: f h f h d h 6 h 4a ~ ~ ~ ~ 25 0ffd6h 0ff00h 0ffffh f1 next 0ffd7h t ? 0f125h reverse
hms87c5216 sep. 2001 ver 1.0 21 example: the usage software example of vector address and the initialize part. org 0ffe0h dw not_used ; (0ffeo) dw not_used ; (0ffe2) dw adc_int ; (0ffe4) a/d interface dw rc_wt_int ; (0ffe6) rc wake up timer dw bit_int ; (0ffe8) bit timer dw wdt_int ; (0ffea) wdt dw not_used ; (0ffec) dw tmr2_int ; (0ffee) timer-2 dw tmr1_int ; (0fff0) timer-1 dw tmr0_int ; (0fff2) timer-0 dw not_used ; (0fff4) dw ext2_int ; (0fff6) external2 dw ext1_int ; (0fff8) external1 dw key_scan ; (0fffa) key scan dw not_used ; (0fffc) dw reset ; (0fffe) reset org 0f000h ;******************************************** ; main program * ;******************************************* ; reset: di ;disable all interrupts ldx #0 ram_clr: lda #0 ;ram clear(!0000h->!00bfh) sta {x}+ cmpx #0c0h bne ram_clr ; ldx #07fh ;stack pointer initialize txsp ; call initial ; ; ldm r1, #0 ;normal port a ldm r1dd,#1000_0010b ;normal port direction ldm r2, #0 ;normal port b ldm r2dd,#1000_0010b ;normal port direction : : : :
hms87c5216 22 sep. 2001 ver 1.0 9.3 data memory figure 9-7 shows the internal data memory space availa- ble. data memory is divided into two groups, a user ram (including stack) and control registers. figure 9-7 data memory map user memory the hms87c5216 has 330 8 bits for the user memory (ram). control registers the control registers are used by the cpu and peripheral function blocks for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. more detailed informations of each register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruction. use byte manipulation instruction. example; to write at ckctlr ldm ckctlr,#09h ;divide ratio ? 16 note: several names are given at same address. refer to- user memory control registers 0000h 00bfh 00c0h 00ffh page0 user memory (including stack) 0100h 017fh page2 address symbol r/w reset value addressin g mode table 9-1 control registers
hms87c5216 sep. 2001 ver 1.0 23 below table. stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents of the pro- gram counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save. address symbol r/w reset value addressin g mode 0c0h 0c1h 0c2h 0c3h 0c4h 0c5h 0c6h 0c7h 0c7h 0c8h 0c9h 0cah 0cbh 0cch 0cdh 0ceh 0cfh r0 r0dr r1 r1dr r2 r2dr tmr1 ckctlr bitr wdtr psr rcwtr iesr ienl irql ienh irqh r/w w r/w w r/w w w w r w w w w r/w r/w r/w r/w undefined 0000_0000 undefined 0000_0000 undefined 0000_0000 0000_0000 --11_0111 0000_0000 -000_1111 --00_0000 ----_1000 --00_00-- -000_-0-- -000_-0-- 000-_000- 000-_000- byte, bit 1 byte 2 byte, bit byte byte, bit byte byte byte byte byte byte byte,bit byte,bit byte,bit byte,bit byte,bit byte,bot 0d0h 0d1h 0d2h 0d3h 0d4h 0d5h 0d5h 0d6h 0d6h 0d7h 0d8h 0d8h 0d9h 0d9h 0dah 0dch 0ddh 0deh 0dfh tm0 tm1 tm2 t0hmd t0hld t0mc t0lmd t0lc t0lld t1hd t1c t1ld t2c t2d tm01 ksr0 ksr1 r10d r2od r/w r/w r/w w w r w r w w r w r w r/w w w w w 0000_0000 0000_-000 ---0_0000 undefined undefined 0000_0000 undefined 0000_0000 undefined undefined 0000_0000 undefined 0000_0000 undefined 0000_0000 00000_000 0000_0000 0000_0000 0000_0000 byte, bit byte, bit byte, bit byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte,bit 0e0h 0e1h 0e4h 0e5h 0e6h 0e7h 0e8h 0eeh 0efh r3od r4od r0od r3 r3dr r4 r4dr tmr2 lvdr w w w r/w w r/w w r r 0000_0000 --00_0000 0000_0000 undefined 0000_0000 undefined tt 00_0000 0000_0000 ttt _ t 00 t byte byte byte byte s bit byte byte,bit byte byte byte table 9-1 control registers 0f0h 0f4h 0f5h 0f6h 0f7h 0f8h 0f9h 0fah 0fbh 0fch smr admr addr krl0 krl1 r0pu r1pu r2pu r3pu r4pu w r/w r w w w w w w w ----_---0 -000_0001 undefined 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 --00_0000 byte byte, bit byte byte byte byte byte byte byte byte 1. byte, bit means that register can be addressed by not only bit but byte manipulation instruction. 2. byte means that register can be addressed by only byte manipulation instruction. on the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. table 9-1 control registers
hms87c5216 24 sep. 2001 ver 1.0 9.4 addressing mode the hms87c5216 and gms81c1408 uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing ? #imm in this mode, second byte (operand) is accessed as a data immediately. example: 0435 adc #35h e45535 ldm 35h,#55h (3) direct page addressing ? dp in this mode, a address is specified within direct page. example; c535 lda 35h ;a ? ram[35h] (4) absolute addressing ? !abs absolute addressing sets corresponding memory data to data, i.e. second byte(operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; 0735f0 adc !0f035h ;a ? rom[0f035h] 35 a+35h+c ? a 04 memory e4 0f100 h data ? 55h ~ ~ ~ ~ data 0035 h t 35 0f102 h 55 0f101 h data 35 0035 h 0f551 h data ? a t ~ ~ ~ ~ c5 0f550 h 07 0f100 h ~ ~ ~ ~ data 0f035 h t f0 0f102 h 35 0f101 h a+data+c ? a address: 0f035
hms87c5216 sep. 2001 ver 1.0 25 the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0135 h . 983500 inc !0035h ;a ? ram[035h] (5) indexed addressing x indexed direct page (no offset) ? {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h d4 lda {x} ;acc ? ram[x]. x indexed direct page, auto increment ? {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; x=35 h db lda {x}+ x indexed direct page (8 bit offset) ? dp+x this address value is the second byte (operand) of com- mand plus the data of -register. and it assigns the mem- ory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; x=015 h c645 lda 45h+x 98 0f100 h ~ ~ ~ ~ data 0035 h t 00 0f102 h 35 0f101 h data+1 ? data ? address: 0035 data d4 15 h 0e550 h data ? a t ~ ~ ~ ~ data db 35 h data ? a t ~ ~ ~ ~ 36h ? x data 45 5a h 0e551 h data ? a t ~ ~ ~ ~ c6 0e550 h 45h+15h=5ah ?
hms87c5216 26 sep. 2001 ver 1.0 y indexed direct page (8 bit offset) ? dp+y this address value is the second byte (operand) of com- mand plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute ? !abs+y sets the value of 16-bit absolute address plus y-register data as memory. this addressing mode can specify mem- ory in whole area. example; y=55 h d500fa lda !0fa00h+y (6) indirect addressing direct page indirect ? [dp] assigns data address to use for accomplishing command which sets memory data(or pair memory) by operand. also index can be used with index register x,y. jmp, call example; 3f35 jmp [35h] x indexed indirect ? [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; x=10 h 1625 adc [25h+x] d5 0f100 h data ? a t ~ ~ ~ ~ data 0fa55 h 0fa00h+55h=0fa55h ? fa 0f102 h 00 0f101 h 0a 35 h jump to address 0e30a h t ~ ~ ~ ~ 35 0fa00 h e3 36 h 3f 0e30a h next ~ ~ ~ ~ 05 35 h 0e005 h ~ ~ ~ ~ 25 0fa00 h e0 36 h 16 0e005 h data ~ ~ ~ ~ ? a + data + c ? a 25 + x(10) = 35 h t
hms87c5216 sep. 2001 ver 1.0 27 y indexed indirect ? [dp]+y processes memory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in di- rect page plus y-register data. adc, and, cmp, eor, lda, or, sbc, sta example; y=10 h 1725 adc [25h]+y absolute indirect ? [!abs] the program jumps to address specified by 16-bit absolute address. jmp example; 1f25e0 jmp [!0c025h] 05 25 h 0e005 h + y(10) = 0e015 h t ~ ~ ~ ~ 25 0fa00 h e0 26 h 17 0e015 h data ~ ~ ~ ~ ? a + data + c ? a 25 0e025 h jump to ~ ~ ~ ~ e0 0fa00 h e7 0e026 h 25 0e725 h next ~ ~ ~ ~ 1f program memory t address 0e30a h
hms87c5216 28 sep. 2001 ver 1.0 10. i/o ports the gms87c5216 has 38 i/o ports which are port0(8 i/ o), port1 (8 i/o), port2 (8 i/o), port3 (8 i/o), port4 (6 i/o). pull-up resistor of each port can be select- able by program. each port contains data direction register which controls i/o and data register which stores port data 10.1 r0 ports r0 is an 8-bit cmos bidirectional i/o port (address 0c0 h ). each i/o pin can independently used as an input or an output through the r0dd register (address 0c1 h ). r0 has internal pull-ups that is independently connected or disconnected by r0pc. the control registers for r0 are shown below. (1) r0 i/o data direction register (r0dd) r0 i/o data direction register (r0dd) is 8-bit register, and can assign input state or output state to each bit. if r0dd is ``1``, port r0 is in the output state, and if ``0``, it is in the input state. r0dd is write-only register. since r0dd is initialized as ``00 h`` in reset state, the whole port r0 becomes input state. (2) r0 data register (r0) r0 data register (r0) is 8-bit register to store data of port r0. when set as the output state by r0dd, and data is writ- ten in r0, data is outputted into r0 pin. when set as the in- put state, input state of pin is read. the initial value of r0 is unknown in reset state. (3) r0 open drain assign register (r0odc) r0 open drain assign register (r0odc) is 8bit register, and can assign r0 port as open drain output port each bit, if corresponding port is selected as output. if r0odc is selected as ``1``, port r0 is open drain output, and if select- ed as ``0``, it is push-pull output. r0odc is write-only register and initialized as ``00 h`` in reset state. (4) r0 pull-up resistor control register (r0pc) r0 pull-up resistor control register (r0pc) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. if r0pc is selected as ``1``, pull- up ia disabled and if selected as ``0``, it is enabled. r0pc is write-only register and initialized as ``00 h`` in reset state. the pull-up is automatically disabled, if correspond- ing port is selected as output. 10.2 r1 ports r1 is an 8-bit cmos bidirectional i/o port (address 0c2 h ). each i/o pin can independently used as an input or an output through the r1dd register (address 0c3 h ). r1 has internal pull-ups that is independently connected or disconnected by register r1pc. the control registers for r1 are shown below. r0 data register (r/w) r0 address : 0c0 h reset value : undefined r07 r06 r05 r04 r03 r02 r01 r00 port direction r0 direction register (w) r0dd address : 0c1 h reset value : 00 h 0: input 1: output pull-up select r0 pull-up selection register (w) r0pc address :0f8 h reset value : 00 h 1: without pull-up 0: with pull-up open drain select r0 open drain assign register (w) r0odc address :0e4 h reset value : 00 h 0: push-pull 1: open drain
hms87c5216 sep. 2001 ver 1.0 29 (1) r1 i/o data direction register (r1dd) r1 i/o data direction register (r1dd) is 8-bit register, and can assign input state or output state to each bit. if r1dd is ``1``, port r1 is in the output state, and if ``0``, it is in the input state. r1dd is write-only register. since r1dd is initialized as ``00 h`` in reset state, the whole port r1 becomes input state. (2) r1 data register (r1) r1 data register (r1) is 8-bit register to store data of port r1. when set as the output state by r1dd, and data is writ- ten in r1, data is outputted into r1 pin. when set as the in- put state, input state of pin is read. the initial value of r1 is unknown in reset state. (3) r1 mode register (pmr1) r1 port mode register (pmr1) is 8-bit register, and can assign the selection mode for each bit. when set as ``0``, corresponding bit of pmr1 acts as port r1 selection mode, and when set as ``1``, it becomes function selection mode. pmr1 is write-only register and initialized as ``00 h`` in reset state. therefore, becomes port selection mode. port r1 can be i/o port by manipulating each r1dd bit, if cor- responding pmr1 bit is selected as ``0``. table 10-1 selection mode of pmr1 (4) r1 pull-up resistor control register (r1pc) r1 pull-up resistor control register (r1pc) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. if r1pc is selected as ``1``, pull- up ia disabled and if selected as ``0``, it is enabled. r1pc is write-only register and initialized as ``00 h`` in reset state. the pull-up is automatically disabled, if correspond- ing port is selected as output. 10.3 r2 port r2 is an 8-bit cmos bidirectional i/o port (address 0c4 h ). each i/o pin can independently used as an input or an output through the r2dd register (address 0c5 h ). r1 data register (r/w) r1 address : 0c2 h reset value : undefined r17 r16 r15 r14 r13 r12 r11 r10 port direction r1 direction register (w) r1dd address : 0c3 h reset value : 00 h 0: input 1: output pull-up select r1 pull-up selection register (w) r1pc address : 0f9 h reset value : 00 h 1: without pull-up 0: with pull-up open drain select r1 open drain assign register (w) p1odc address : 0de h reset value : 00 h 0: push-pull 1: open drain mode select r1 port mode register (w) pmr1 address : 0c9 h reset value : 00 h 0: port r1 selection 1: function selection pin name pmr1 selection mode remarks - - ec0 0 r25(i/o) - 1 ec0(i) event count0 t2 0 r24(i/o) - 1t2(o) timer2 t1 0 r13 (i/o) - 1t1(o) timer1 t0 0 r12 (i/o) - 1t0(o) timer0 int2 0 r11 (i/o) - 1 int2(i) ext int2 int1 0 r10(i/o) - 1 int1(i) ext int1
hms87c5216 30 sep. 2001 ver 1.0 r2 has internal pujll-ups that is independently connected or disconnected by r2pc (address 0fa h ). the control reg- isters for r2 are shown as below. (1) r2 i/o data direction register (r2dd) r2 i/o data direction register (r2dd) is 8-bit register, and can assign input state or output state to each bit. if r2dd is ``1``, port r2 is in the output state, and if ``0``, it is in the input state. r2dd is write-only register. since r2dd is initialized as ``00 h`` in reset state, the whole port r2 becomes input state. (2) r2 data register (r2) r2 data register (r2) is 8-bit register to store data of port r2. when set as the output state by r2dd, and data is writ- ten in r2, data is outputted into r2 pin. when set as the in- put state, input state of pin is read. the initial value of r2 is unknown in reset state. (3) r2 open drain assign register (r2odc) r2 open drain assign register (r2odc) is 8bit register, and can assign r2 port as open drain output port each bit, if corresponding port is selected as output. if r2odc is selected as ``1``, port r2 is open drain output, and if select- ed as ``0``, it is push-pull output. r2odc is write-only register and initialized as ``00 h`` in reset state. (4) r2 pull-up resistor control register (r2pc) r2 pull-up resistor control register (r2pc) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. if r2pc is selected as ``1``, pull- up ia disabled and if selected as ``0``, it is enabled. r2pc is write-only register and initialized as ``00 h`` in reset state. the pull-up is automatically disabled, if correspond- ing port is selected as output. r2 data register (r/w) r2 address : 0c4 h reset value : undefined r27 r26 r25 r24 r23 r22 r21 r20 port direction r2 direction register (w) r2dd address : 0c5 h reset value : 00 h 0: input 1: output pull-up select r2 pull-up selection register (w) r2pc address :0fa h reset value : 00 h 1: without pull-up 0: with pull-up open drain select r2 open drain assign register (w) r2odc address :0df h reset value : 00 h 0: push-pull 1: open drain
hms87c5216 sep. 2001 ver 1.0 31 r3 port r3 is an 8-bit cmos bidirectional i/o port (address 0e5 h ). each i/o pin can independently used as an input or an output through the r3dd register (address 0e6 h ). r3 has internal pull-ups that is independently connected or disconnected by r3pc (address 0fb h ). the control regis- ters for r3 are shown as below. (1) r3 i/o data direction register (r3dd) r3 i/o data direction register (r3dd) is 8-bit register, and can assign input state or output state to each bit. if r3dd is ``1``, port r3 is in the output state, and if ``0``, it is in the input state. r3dd is write-only register. since r3dd is initialized as ``00 h`` in reset state, the whole port r3 becomes input state. (2) r3 data register (r3) r3 data register (r3) is 8-bit register to store data of port r3. when set as the output state by r3dd, and data is writ- ten in r3, data is outputted into r3 pin. when set as the in- put state, input state of pin is read. the initial value of r3 is unknown in reset state. (3) r3 open drain assign register (r3odc) r3 open drain assign register (r3odc) is 8bit register, and can assign r3 port as open drain output port each bit, if corresponding port is selected as output. if r3odc is selected as ``1``, port r3 is open drain output, and if select- ed as ``0``, it is push-pull output. r3odc is write-only register and initialized as ``00 h`` in reset state. (4) r3 pull-up resistor control register (r3pc) r3 pull-up resistor control register (r3pc) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. if r3pc is selected as ``1``, pull- up ia disabled and if selected as ``0``, it is enabled. r3pc is write-only register and initialized as ``00 h`` in reset state. the pull-up is automatically disabled, if correspond- ing port is selected as output. r3 data register (r/w) r3 address : 0e5 h reset value : undefined r37 r36 r35 r34 r33 r32 r31 r30 port direction r3 direction register (w) r3dd address : 0e6 h reset value : 00 h 0: input 1: output pull-up select r3 pull-up selection register (w) r3pc address :0fb h reset value : 00 h 1: without pull-up 0: with pull-up open drain select r3 open drain assign register (w) r3odc address :0e0 h reset value : 00 h 0: push-pull 1: open drain
hms87c5216 32 sep. 2001 ver 1.0 r4 port r4 is an 1-bit cmos bidirectional i/o port (address 0e7 h ). each i/o pin can independently used as an input or an output through the r4dd register (address 0e8 h ). r3 has internal pull-ups that is independently connected or disconnected by r4pc (address 0fc h ). the control regis- ters for r4 are shown as below. (1) r4 i/o data direction register (r4dd) r4 i/o data direction register (r4dd) is 1-bit register, and can assign input state or output state to each bit. if r4dd is ``1``, port r4 is in the output state, and if ``0``, it is in the input state. r4dd is write-only register. since r4dd is initialized as ``00 h`` in reset state, the whole port r4 becomes input state. (2) r4 data register (r4) r4 data register (r4) is 1-bit register to store data of port r4. when set as the output state by r4dd, and data is writ- ten in r4, data is outputted into r4 pin. when set as the in- put state, input state of pin is read. the initial value of r4 is unknown in reset state. (3) r4 open drain assign register (r4odc) r4 open drain assign register (r4odc) is 1-bit register, and can assign r4 port as open drain output port each bit, if corresponding port is selected as output. if r4odc is selected as ``1``, port r4 is open drain output, and if select- ed as ``0``, it is push-pull output. r4odc is write-only register and initialized as ``00 h`` in reset state. (4) r4 pull-up resistor control register (r4pc) r4 pull-up resistor control register (r4pc) is 1-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. if r4pc is selected as ``1``, pull- up ia disabled and if selected as ``0``, it is enabled. r4pc is write-only register and initialized as ``00 h`` in reset state. the pull-up is automatically disabled, if correspond- ing port is selected as output. r4 data register (r/w) r4 address : 0e7 h reset value : undefined port direction r4 direction register (w) r4dd address : 0e8 h reset value : 00 h 0: input 1: output pull-up select r4 pull-up selection register (w) r4pc address :0fc h reset value : 00 h 1: without pull-up 0: with pull-up open drain select r4 open drain assign register (w) r4odc address :0e1 h reset value : 00 h 0: push-pull 1: open drain r44 r43 r42 r41 r40
hms87c5216 sep. 2001 ver 1.0 33 11. clock generator clock generating circuit consists of clock pulse generator (c.p.g), prescaler, basic interval timer (b.i.t) and watch dog timer. the clock applied to the xin pin divided by two is used as the internal system clock. figure 11-1 block diagram of clock generator prescaler consists of 12-bit binary counter. the clock sup- plied from oscillation circuit is input to prescaler (fex). the divided output from each bit of prescaler is provided to peripheral hardware. figure 11-2 block diagram of prescaler 9 prescaler c.p.g mux wdt (6) comparator internal data bus 01234 056 6 wdton to reset circuit ifwdt wdtcl ifbit 5 0 7 0 fcpu fex ps1 enpck peripheral ckctlr btcl 3 8 osc circuit b.i.t (8) 6 wdtr internal system clock 5 b.i.t peripheral ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12 fex enpck fcpu ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12
hms87c5216 34 sep. 2001 ver 1.0 table 11-1 ps output period lock to peripheral hardware can be stopped by bit4 (en- pck) of ckctlr register. enpck is set to ``1`` in reset state. fex (mhz) 4 mhz 2 mhz frequency period frequency period ps 0 ps 1 ps 2 ps 3 ps 4 ps 5 ps 6 ps 7 ps 8 ps 9 ps 10 ps 11 ps 12 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 31.25 khz 15.63 khz 7.183 khz 3.906 khz 1.953 khz 0.976 khz 250 ns 500 ns 1 us 2 us 4 us 8 us 16 us 32 us 64 us 128 us 256 us 512 us 1024 us 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 31.25 khz 15.63 khz 7.183 khz 3.906 khz 1.953 khz 0.976 khz 0.488 khz 500 ns 1 us 2 us 4 us 8 us 16 us 32 us 64 us 128 us 256 us 512 us 1024 us 2048 us
hms87c5216 sep. 2001 ver 1.0 35 12. timer 12.1 basic interval timer the gms81c5016/24/32 has one 8-bit basic interval tim- er that is free-run and can not stop. block diagram is shown in figure 12-1 . the basic interval timer generates the time base for key scanning, watchdog timer counting, and etc. it also pro- vides a basic interval timer interrupt (ifbit). as the count overflow from ff h to 00 h , this overflow causes the inter- rupt to be generated. -8bit binary counter -use the bit output of prescaler as input to secure the oscil- lation stabilization time after power-on -secures the oscillation stabilization time in standby mode (stop mode) release -contents of b.i.t can be read -provides the clock for watch dog timer. figure 12-1 block diagram of basic interval timer (1) control of b.i.t the basic interval timer is controlled by the clock control register (ckctlr) shown in figure 12-2 . if bit3(btcl) of ckctlr is set to ``1``, b.i.t is cleared, and then, after one machine cycle, btcl becomes ``0``, and b.i.t starts counting. btcl is set to ``0`` in reset state. mux bitr ifbit ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 data bus data bus -- wdton enpck btcl bts2 bts1 bts0 ckctlr bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
hms87c5216 36 sep. 2001 ver 1.0 figure 12-2 btcl mode of b.i.t (2) input clock selection of b.i.t the input clock of b.i.t can be selected from the prescaler within a range of 2us to 256us by clock input selection bits (bts2~bts0). (at fex = 4mhz). in reset state, or power on reset, bts2=``1``, bts1=``1``, bts0=``1`` to secure the longest oscillation stabilization time. b.i.t can gener- ate the wide range of basic interval time interrupt request (ifbit) by selecting prescaler output. interrupt interval can be selected to kinds of interval time as shown in figure 12-3 . figure 12-3 basic interval timer interrupt time (3) reading basic interval timer by reading of the basic interval timer register (bitr), we can read counter value of b.i.t. because b.i.t can be cleared or read, the spending time up to maximum 65.5ms can be available. b.i.t is read-only register. if b.i.t reg- 0 -- wdton enpck btcl bts2 bts1 bts0 7 w <00c7 h> ckctlr clock control register btcl periphral clock 0 1 free-run automatically cleared, after one cycle 512 us 1,024 us 2,048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us 0 -- wdton enpck btcl bts2 bts1 bts0 7 w <00c7 h> ckctlr clock control register bts0 b.i.t. input clock 0 1 bts1 0 0 bts2 0 0 standby release time 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 ps3 (2us) ps4 (4us) ps5 (8us) ps6 (16us) ps7 (32us) ps8 (64us) ps9 (128us) ps10 (256us)
hms87c5216 sep. 2001 ver 1.0 37 ister is written, then ckctlr register with same address is written. 12.2 timer0, timer1, timer2 (1) timer operation mode timer consists of 16bit binary counter timer0 (t0), 8bit binary timer1 (t1), timer2 (t2), timer data register, timer mode register (tm01, tm0, tm1, tm2) and con- trol circuit. timer data register consists of timer0 high- msb data register (t0hmd), timer0 high-lsb data register (t0hld), timer0 low-msb data register (t0lmd), timer0 low-lsb data register (t0lld), timer1 high data register (t1hd), timer1 low data register (t1ld), timer2 data register (t2dr). any of the ps0 ~ ps5, ps11 and external event input ec can be selected as clock source for t0. any of the ps0 ~ ps3, ps7 ~ ps10 can be selected as clock t1. any of the ps5 ~ ps12 can be selected as clock source for t2. * relevant port mode register (pmr1 : 00c9 h) value should be assigned for event counter, 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 7 r <00c7 h> bitr basic interval timer register timer0 - 16-bit interval timer - 16-bit event counter - 16-bit input capture - 16-bit rectangular-wave output - single/modulo-n mode - timer output initial value setting - timer0~timer1 combination logic output - one interrupt generating every 2nd counter overflow timer1 - 8-bit interval timer - 8-bit rectangular-wave output timer2 - 8-bit interval timer - 8-bit rectangular-wave output - modulo-n mode
hms87c5216 38 sep. 2001 ver 1.0 figure 12-4 timer / counter block diagram (2) function of timer & counter t2 out / r15 timer0 (16 bit) polarity selection t0hmd t0hld t0lmd t0lld tout logic t1hd t1ld timer1 (8 bit) edge selection t1 out / r16 remout t0 out / r17 ec / r14 int2 / r12 (capture signal) 16 8888 88 16 timer2 (8 bit) t2dr ps0 ( 0.25 us) 16,384 us ps0 ( 0.25 us) 64 us ps5 ( 8 us) 2.048 us ps1 ( 0. 5 us) 32,768 us ps1 ( 0.5 us) 128 us ps6 ( 16 us) 4,096 us ps2 ( 1 us) 65,536 us ps2 ( 1 us) 256 us ps7 ( 32 us) 8,192 us ps3 ( 2 us) 131,072 us ps3 ( 2 us) 512us ps8 ( 64 us) 16,384 us ps4 ( 4 us) 262,144 us ps7 ( 32 us) 8,192 us ps9 ( 128 us) 32,768 us ps5 ( 8 us) 524,288 us ps8 ( 64 us) 16,384 us ps10 ( 256 us) 65,536 us ps11 ( 512 us) 33,554,432 us ps9 ( 128 us) 32,768 us ps11 ( 512 us) 131,072 us ec - ps10 ( 256 us) 65,536 us ps12 (1,024 us) 262,144 us fex = 4mhz 16bit timer (t0) 8bit timer (t1) 8bit timer (t2) resolution (ck) max. count resolution (ck) max. count resolution (ck) max. count
hms87c5216 sep. 2001 ver 1.0 39 figure 12-5 block diagram of timer0 internal data bus timer0 h count reg timer0 l count reg timer0 hm data reg timer0 hl data reg timer0 lm data reg timer0 ll data reg single/ modulo-n selection mux ck t0 counter (16 bit) clear ps0 ps1 ps2 ps3 ps4 ps5 ps11 ec m u x d e l a y edge selection mux int. gen. output gen. tm0 r / w <00d0 h> <00d5 h> <00d6 h> <00d3 h> <00d4 h> <00d5 h> <00d6 h> 16 16 16 int2 t0int t0 out ift0 data read 76543210
hms87c5216 40 sep. 2001 ver 1.0 figure 12-6 block diagram of timer1 internal data bus 7 6 5 4 3 2 1 0 timer1 count reg timer1 h data reg timer1 l data reg single/ modulo-n selection mux ck t1 counter (8 bit) ps0 ps1 ps2 ps3 ps7 ps8 ps9 ps10 int. gen. output gen. tm1 r/w <00d1h> <00d7 h> <00d8 h> t1out ift1 output gen. x <00d8 h> t1int
hms87c5216 sep. 2001 ver 1.0 41 figure 12-7 block diagram of timer2 internal data bus 7 6 5 4 3 2 1 0 timer2 count reg mux ck t2 counter (8 bit) ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12 output gen. tm2 r/w <00d2 h> <00d9 h> t2 out <00d9 h> timer2 data reg ift2
hms87c5216 42 sep. 2001 ver 1.0 figure 12-8 timer0 / timer1 mode register 0 touts toutb - t0outp t0init t1init tout1 tout0 7 r / w <00da h> tm01 timer0 / timer1 mode register tout0 tout1 tout logic 00 01 10 11 t1init timer1 output initial value 0 1 t0init 0 1 t0outp t0out polarity selection 0 1 toutb remout port bit control 0 1 touts remout port output selection (tout logic or toutb) 0 1 and of t0 output and t1 output nand of t0 output and t1 output or of t0 output and t1 output nor of t0 output and t1 output timer1 output low timer1 output high timer0 output initial value timer0 output low timer0 output high t0out polarity equal to tout logic input signal t0out polarity reverse to tout logic input signal remout output low remout output high bit (toutb) output through remout tout logic output through remout
hms87c5216 sep. 2001 ver 1.0 43 figure 12-9 timer0 mode register 0 cap0 t0st t0cn t0mod t0ifs t0sl2 t0sl1 t0sl0 7 r / w <00d0 h> tm0 timer0 mode register t0sl2 t0sl1 input clock selection 00 00 01 01 t0ifs timer0 interrupt selection 0 1 10 10 11 11 t0sl0 0 1 0 1 0 1 0 1 notes ps0 (250ns) ps1 (500ns) ps2 ( 1us) ps3 ( 2us) ps4 ( 4us) ps5 ( 8us) ps11 (512us) ec event counter * interrupt every counter overflow interrupt every 2nd counter overflow t0mod timer0 single/modulo-n selection 0 1 modulo-n single t0cn timer0 counter continuation/pause control 0 1 count pause count contination t0st timer0 start/stop control 0 1 timer0 stop timer start after clear cap0 timer0 interrupt selection 0 1 timer/counter input capture * * ps1 : not supporting input capture.
hms87c5216 44 sep. 2001 ver 1.0 figure 12-10 timer1 mode register 0 t1st t1cn t1mod t1ifs - t1sl2 t1sl1 t1sl0 7 r / w <00d1 h> tm1 timer1 mode register t1sl2 t1sl1 input clock selection 00 00 01 01 t1ifs timer1 interrupt selection 0 1 10 10 11 11 t1sl0 0 1 0 1 0 1 0 1 ps0 (250ns) ps1 (500ns) ps2 ( 1us) ps3 ( 2us) ps7 ( 32us) ps8 ( 64us) ps9 (128us) interrupt every counter overflow interrupt every 2nd counter overflow t1mod timer1 single/modulo-n selection 0 1 modulo-n single t1cn timer1 counter continuation/pause control 0 1 count pause count contination t1st timer1 start/stop control 0 1 timer1 stop timer1 start after clear ps10 (256us)
hms87c5216 sep. 2001 ver 1.0 45 figure 12-11 timer2 mode register figure 12-12 external interrupt signal edge selection register 0 - - - t2st t2cn t2sl2 t2sl1 t2sl0 7 r / w <00d2 h> tm2 timer2 mode register t2sl2 t2sl1 input clock selection 00 00 01 01 10 10 11 11 t2sl0 0 1 0 1 0 1 0 1 ps5 ( 8us) ps6 ( 16us) ps7 ( 32us) ps8 ( 64us) ps9 ( 128us) ps10 ( 256us) ps11 ( 512us) t2cn timer2 counter continuation/pause control 0 1 count pause count contination t2st timer2 start/stop control 0 1 timer2 stop timer2 start after clear ps12 (1024us) ied*h ied*l int* 0 - - ied2h ied2l ied1h ied1l - - 7 w <00cb h> ieds external interrupt signal edge selection register 00 01 1 1 0 1 - falling edge selection rising edge selection both edge selection
hms87c5216 46 sep. 2001 ver 1.0 (3) timer0, timer1 timer0 and timer1 have an up-counter. when value of the up-counter reaches the content of timer data register (tdr), the up-counter is cleared to ``00 h``, and interrupt (ift0, ift1) is occured at the next clock. figure 12-13 operatiion of timer0 for timer0, the internal clock (ps) and the external clock (ec) can be selected as counter clock. but timer1 and timer2 use only internal clock. as internal clock. timer0 can be used as internal-timer which period is determined by timer data register (tdr). chosen as external clock, timer0 executes as event-counter. the counter ex- ecution of timer0 and timer1 is controlled by t0cn, t0st, cap0, t1cn, t1st, of timer mode register tm0 and tm1. t0cn, t1cn are used to stop and start timer0 and timer1 without clearing the counter. t0st, t1st is used to clear the counter. for clearing and starting the counter, t0st or t1st should be temporarily set to ``0`` and then set to ``1``. t0cn, t1cn, t0st and t1st should be set ``1``, when timer counting-up. controlling of cap0 enables timer0 as input capture. by program- ming of cap0 to ``1``, the period of signal from int2 can be measured and then, event counter value for int2 can be read. during counting-up, value of counter can be read. timer execution is stopped by the reset signal (reset = ``l``) note: in the process of reading 16-bit timer data, first read the upper 8-bit data. then read the lower 8-bit data, and read the upper 8-bit data again. if the earlier read up- per 8-bit data are matched with the later read upper 8-bit data, read 16-bit data are correct. if not, caution should be taken in the selection of upper 8-bit data. (example) 1) upper 8-bit read 0a 0a 2) lower 8-bit read ff 01 3) upper 8-bit read 0b 0b ===================== - - 0aff 0b01 concurrence concurrence concurrence clear clear clear 0 t0 data registers value t0 value interrupt interrupt interrupt interval period ift0
hms87c5216 sep. 2001 ver 1.0 47 figure 12-14 start/stop operation of timer0 figure 12-15 input capture operation of timer0 concurrence clear interrupt concurrence clear interrupt ift0 t0st t0cn 0 01 01 counter count stop clear & count stop count continue clear & start t0 data register value t0 value clear & start t0 t1 t2 t3 int2
hms87c5216 48 sep. 2001 ver 1.0 * single/modulo-n mode timer0 (timer1) can select initial (t0init, t1init of tm01) output level of timer output port. if initial level is ``l``, low-data register value of timer data register is transferred to comparator and t0out (t1out) is to be ``low``, if initial level is high? high -data register is transferred and to be ``high``. single mode can be set by mode select bit (t0mod, t1mod) of timer mode reg- ister (tm0, tm1) to ``1`` when used as single mode, timer counts up and compares with value of data regis- ter. if the result is same, time out interrupt occurs and level of timer output port toggle, then counter stops as re- set state. when used as modulo-n mode, t0mod (t1mod) should be set ``0``. counter counts up until the value of data register and occurs time-out interrupt. the level of timer output port toggle and repeats process of counting the value which is selected in data register. during modulo-n mode, if interrupt select bit (t0ifs, t1ifs) of mode register is ``0``, interrupt occurs on ev- ery time-out. if it is ``1``, interrupt occurs every second time-out. note: (*note. timer output is toggled whenever time out happen) figure 12-16 operation diagram for single/modulo-n mode (4) timer 2 timer2 operates as a up-counter. the content of t2dr are compared with the contents of up-counter. if a match is found. timer2 interrupt (ift2) is generated and the up- counter is cleared to ``00 h``. therefore, timer2 executes as a interval timer. interrupt period is determined by the count source clock for the timer2 and content of t2dr. when t2st is set to ``1``, count value of timer 2 is cleared and starts counting-up. for clearing and starting the timer2. t2st have to set to ``1`` after set to ``0``. in order to write a value directly into the t2dr, t2st should be set to ``0``. count value of timer2 can be read at any time. 8bit / 16bit counting 8bit / 16bit counting timer enable initial. value toggle. timer-output toggle. interrupt occurs. count stop. timer enable initial. value toggle. timer-output toggle. int occurs (ifs = 1) each 2nd time out. int occurs (ifs = 0) when time out. [ single mode ] [ modulo-n mode ]
hms87c5216 sep. 2001 ver 1.0 49 figure 12-17 operation of timer2 figure 12-18 start/stop of timer2 concurrence concurrence concurrence clear clear clear 0 t2 data registers value t2 value interrupt interrupt interrupt interval period ift0 concurrence clear interrupt concurrence clear interrupt ift2 t2st 0 count stop by 0 count start clear by 1 counter count up count continue count up after clear t2 data register value t2 value count stop
hms87c5216 50 sep. 2001 ver 1.0 13. interrupts the gms81c5016/24/32 interrupt circuits consist of in- terrupt mode register (mod), interrupt enable register (ienh, ienl), interrupt request flags of irqh, irql, priority circuit and master enable flag ("i" flag of psw). 8 interrupt sources are provided. the configuration of inter- rupt circuit is shown in figure 13-1 . the gms81c5016/24/32 contains 8 interrupt sources; 3 externals and 5 internals. nested interrupt services with priority control is also possible. software interrupt is non- maskable interrupt, the others are all maskable interrupts. - 8 interrupt source (2ext, 3timer, bit, wdt and key scan) - 8 interrupt vector - nested interrupt control is possible - programmable interrupt mode - hardware accept mode - software selection accept mode - read and write of interrupt request flag are possible. - in interrupt accept, request flag is automatically cleared. figure 13-1 block diagram of interrupt 13.1 interrupt priority and sources. each interrupt vector is independent and has its own prior- ity. software interrupt (brk) is also available. interrupt source classification is shown in table 13-1. internal data bus kscnr int1r int2r t0r t1r t2r wdtr bitr priority control ienl ienh imod irq kscn int1 int2 ift0 ift1 ift2 ifwdt ifbit int. vector addr. brk standby mode release 7 0 -- 7 0 -- 7 0 -- - - - -
hms87c5216 sep. 2001 ver 1.0 51 table 13-1 interrupt priority & source 13.2 interrupt control register i flag of psw is a interrupt mask enable flag. when i flag = ``0``, all interrupts become disable. when i flag = ``1``, interrupts can be selectively enabled and disabled by con- tents of corresponding interrupt enable register. when in- terrupt is occured, interrupt request flag is set, and interrupt request is detected at the edge of interrupt signal. the accepted interrupt request flag is automatically cleared during interrupt cycle process. the interrupt request flag maintains ``1`` until the interrupt is accepted or is cleared in program. in reset state, interrupt request flag register (irqh, irql) is cleared to ``0``. it is possible to read the state of interrupt register and to mainpulate the contents of register and to generate interrupt. (refer to software inter- rupt). mask priority interrupt source int vector high int vector low hardwar e interrupt int2r (external interrupt2) non-maskable maskable - 0 1 2 3 4 5 6 7 - int1r (external interrupt1) - wdtr (watctdog timer) bitr (basic interval timer) rst (reset pin) kscnr (key scan) t0r (timer0) t1r (timer1) t2r (timer2) brk instruction ffff fffe fffb fffa fff9 fff8 fff7 fff6 fff3 fff2 fff1 fff0 ffef ffee ffe9 ffe8 ffe7 ffe6 ffdf ffde -wdtrbite----- kscne int1e int2e - t0e t1e t2e - -wdtrbite----- kscne int1r int2r - t0r t1r t2r - irql irqh r/w <00cfh> r/w <00cdh> r/w <00ceh> r/w <00cch> ienh ienl ienl : interrupt enable register low ienh : interrupt enable register high irql : interrupt request register low irqh : interrupt request register high
hms87c5216 52 sep. 2001 ver 1.0 13.3 interrupt accept mode the interrupt priority order is determined by bit (im1, im0) of imod register. (1) selection of interrupt by ip3-ip0 the condition allow for accepting interrupt is set state of the interrupt mask enable flag and the interrupt enable bit must be ``1``. in reset state, these ip3 - ip0 registers become all ``0``. table 13-2 interrupt selection by ip3 - ip0 0 - - im1 im0 ip3 ip2 ip1 ip0 7 r/w <00ca h> imod interrupt mode register im1 im0 00 01 1* priority fixed by hardware changeable by ip3~ ip0 interrupt is inhibited assigning by interrupt accept mode bit 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 kscnr (key scan) int1r (external interrupt 1) int2r (external interrupt 2) reserved t0r (timer 0) t1r (timer 1) t2r (timer 2) reserved reserved wdtr (watch dog timer) bitr (basic interval timer) reserved ip3 ip2 ip1 ip0 selection interrupt
hms87c5216 sep. 2001 ver 1.0 53 (2) interrupt timing figure 13-2 interrupt enable accept timing *interrupt request sampling time -maximum 12 machine cycle (when execute div instruction) -minimum 0 machine cycle *interrupt preprocess step is 8 machine cycle *interrupt overhead -maximum 1 + 12 + 8 = 21 machine cycle -minimum 1 + 0 + 8 = 9 machine cycle (3) the valid timing after executing interrupt control instructions i flag is valid just after executing of ei/di on the contrary. interrupt enable register is valid one instruction after con- trolling interrupt enable register. 13.4 interrupt processing sequence when an interrupt is accepted, the on-going process is stopped and the interrupt service routine is executed. after the interrupt service routine is completed it is necessary to restore everything to the state before the interrupt oc- cured.as soon as an interrupt is accepted, the content of the program counter and psw are savedin the stack area. at the same time, the content of the vector address corre- sponding to the accepted interrupt, which is in the interrupt vector table, enters into the program counter and interrupt service is executed. in order to execute the interrupt ser- vice routine, it is necessary to write the jump addresses in the vector table (ffe0 h ~ ffff h) corresponding to each interrupt * interrupt processing step 1) store upper byte of program counter, sp <= sp 2) store lower byte of program counter, sp <= sp - 1 3) store program status word, sp <= sp - 2 4) after resetting of i-flag, clear accepted interrupt re- quest flag. (set b-flag for brk instruction) 5) call interrupt service routine clock sync a command before interrupt interrupt process step interrupt request sampling
hms87c5216 54 sep. 2001 ver 1.0 figure 13-3 interrupt procesing step timing 13.5 software interrupt (interrupt by break (brk) instruction) software interrupt is available just by writing ``break(brk)`` instruction. the values of pc and psw is stacked by brk instruction and then b flag of psw is set and i flag is reset. interrupt vector of brk instruction is shared by vector of table call (tcall0). when both instruction of brk and tcall0 are used, as shown in figure 13-4 each process- ing routine is judged by contents of b flag. there is no in- struction to reset directly b flag. *1 isr : interrupt service routine *2 lva : low vector address *3 hva : high vector address pc ? op code interrupt process step isr sp sp-1 sp-2 lva hva new pc *2 *3 *1 ? op code ? pch ? pcl ? psw ? ``l`` vector ? ``h`` vector clock sync r/w internal addr bus internal data bus internal read internal write set reset (right after brk execution) nvgbh i zc psw flag change by brk execution nvg1h0 zc psw
hms87c5216 sep. 2001 ver 1.0 55 figure 13-4 execution of brk or tcall0 13.6 multiple interrupt if there is an interrupt, interrupt mask enable flag is auto- matically cleared before entering the interrupt service routine. after then, no interrupt is accepted. if ei instruc- tion is executed, interrupt mask enable bit becomes ``1``, and each enable bit can accept interrupt request. when two or more interrupts are generated simultaneously, the high- est priority interrupt set by interrupt mode register is ac- cepted. 13.7 key scan input processing (1) standby mode release register (smrr) key scan interrupt is generated by detecting low or high input from each input pin (r0, r1) is one of the sources which release standby (sleep, stop) mode. key scan ports are all 16bit which are controlled by standby mode release register (smrr0, smrr1). key input is consid- ered as interrupt, therefore, kscne bit of iehn should be set for correct interrupt executing, sleep mode and stop mode, the rest of executing is the same as that of external interrupt. each smrr register bit is allowed for each port (for bit= ``0``, no key input, for bit= ``1``, key input available). at reset, smrr becomes ``00 h``. so, there is no key input source. b flag brk interrupt routine tcall0 routine reti ret brk or tcall0 0 1
hms87c5216 56 sep. 2001 ver 1.0 figure 13-5 key scan block r00 r01 . . . r07 r10 r11 . . . r17 r0 port selection logic smrr0 w <00dc h> internal key scan interrupt 7 0 smrr1 w <00dd h> 7 0 r0 port selection logic 0 kr07 kr06 kr05 kr04 kr03 kr02 kr01 kr00 7 w <00dc h> smrr0 smrr0 register 0 kr17 kr16 kr15 kr14 kr13 kr12 kr11 kr10 7 w <00dd h> smrr1 smrr1 register
hms87c5216 sep. 2001 ver 1.0 57 (2) standby release level control register (srlc) standby release level control register (srlc) can select the key scan input level ``l`` or ``h`` for standby release by each bit pin (r0, r1). standby release level control reg- ister (srlc) is write-only register and initialized as ``00 h`` in reset state. smrr0 kr07 key input selection 0 1 no select select smrr1 kr17 0 1 kr06 0 1 no select select kr16 0 1 kr05 0 1 no select select kr15 0 1 kr04 0 1 no select select kr14 0 1 kr03 0 1 no select select kr13 0 1 kr02 0 1 no select select kr12 0 1 kr01 0 1 no select select kr11 0 1 kr00 0 1 no select select kr10 0 1 0 klr07 klr06 klr05 klr04 klr03 klr02 klr01 klr00 7 w <00f6 h> srlc0 srlc0 register 0 klr17 klr16 klr15 klr14 klr13 klr12 klr11 klr10 7 w <00f7 h> srlc1 srlc1 register
hms87c5216 58 sep. 2001 ver 1.0 srlc0 klr07 key input level 0 1 low high srlc1 klr17 0 1 klr06 0 1 klr16 0 1 klr05 0 1 klr15 0 1 klr04 0 1 klr14 0 1 klr03 0 1 klr13 0 1 klr02 0 1 klr12 0 1 klr01 0 1 klr11 0 1 klr00 0 1 klr10 0 1 low high low high low high low high low high low high low high
hms87c5216 sep. 2001 ver 1.0 59 14. watch dog timer watch dog timer (wdt) consists of 6-bit binary counter, 6-bit comparator, and watch dog timer register (wdtr). figure 14-1 block diagram of watch dog timer 14.1 control of wdt watch dog timer can be used 6-bit general timer or spe- cific watch dog timer by setting bit5 (wdton) of clock control register (ckctlr). by assigning bit6(wdtcl) of wdtr, 6-bit counter can be cleared. ifbit 05 6bit comparator wdtr w <00c8 h> if wdt clr wdton to reset circuit internal data bus wdt0 wdt1 wdt2 wdt3 wdt4 wdt5 wdtr0 wdtr1 wdtr2 wdtr3 wdtr4 wdtr5 wdtcl 06 0 -- wdton enpck btcl bts2 bts1 bts0 7 w <00c7 h> ckctlr clock control register wdton watch dog timer function control 0 1 6-bit timer watch dog timer
hms87c5216 60 sep. 2001 ver 1.0 14.2 wdt interrupt interval wdt interrupt (ifwdt) interval is determined by the in- terrupt ifbit interval of basic interval timer and the val- ue of wdt register. -interval of ifwdt = (ifbit interval) * (wdtr value) -interval of ifwdt : 512 us * 1 = 512 us (min>) -65,536us * 63 = 4,128,768 us (max>) as ifbit (basic interval timer interrupt request) is used for input clock of wdt, input clock cycle is possible from 512 us to 65,536 us by bts. (at fex = 4mhz) *at hardware reset time ,wdt starts automatically. therefore, the user must select the ckctlr, wdtr be- fore wdt overflow. -reset wdtr value = 0f h,15 -interval of wdt = 65,536 * 15 = 983040 us (about 1second ) determine interval of ifwdt interval of ifwdt = value of wdtr y interval of ifbit 0 - wdtcl wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 7 w <00c8 h> wdtr watch dog timer register wdtcl watch dog timer operation 0 1 free-run automatically cleared, after one machine cycle
hms87c5216 sep. 2001 ver 1.0 61 note: when wdtr register value is 63 (3f h) (caution) : do not use ``0`` for wdtr register value. device come into the reset state by wdt 32,756 us 64,512 us 129,024 us 258,048 us 516,096 us 1,032,192 us 2,064,384 us 4,128,768 us 0 -- wdton enpck btcl bts2 bts1 bts0 7 w <00c7 h> ckctlr clock control register bts0 wdt input clock 0 1 bts1 0 0 bts2 0 0 max. interval of wdt output (*note1) 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 512 us 1,024 us 2,048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us
hms87c5216 62 sep. 2001 ver 1.0 15. standby function to save power consumption, there is stop modes. in this modes, the execution of program stops. 15.1 sleep mode sleep mode can be entered by setting the bit of sleep mode register (slpm). in the mode, cpu clock stops but oscillator keeps running. b.i.t and a part of peripheral hardware execute, but prescalers output which provide clock to peripherals can be stopped by program. (except, ps10 cant stopped.) in sleep mode, more consuming power can be saved by not using other peripheral hardware except for b.i.t. by setting enpck (peripheral clock con- trol bit) of ckctlr (clock control register) to ``0``, pe- ripheral hardware halted, and sleep mode is entered. to release sleep mode by bitr (basic interval timer inter- rupt), bit10 of prescaler should be selected as b.i.t input clock before entering sleep mode. ``nop`` instruction should be follows setting of sleep mode for rising pre- charge time of data bus line. (ex) setting of sleep mode : set the bit of sleep ; mode register (slpm) nop : nop instruction 15.2 stop mode stop mode can be entered by stop instruction during program. in stop mode, oscillator is stopped to make all clocks stop, which leads to less power consumption. all registers and ram data are preserved. ``nop`` instruction should be follows stop instruction for rising precharge time of data bus line. (ex) stop : stop instruction execution nop : nop instruction 0 - -slpm0 7 w <00f0 h> slpm sleep mode control register slpm0 0 1 condition sleep mode release sleep mode - - - -- 0 - - wdton enpck btcl bts2 bts1 bts0 7 w <00c8 h> ckctlr colck control register encpk 0 1 peripheral clock stopped provided
hms87c5216 sep. 2001 ver 1.0 63 figure 15-1 block diagram of standby circuit figure 15-2 enpck and basic interval timer clock osc. circuit clock pulse gen clr mux prescaler clr s q r s q r overflow detection basic interval timer clr cpu clock b.i.t 7 stop release signal from interrupt circuit reset control signal selector prescaler enpck basic interval timer ps10 peripheral
hms87c5216 64 sep. 2001 ver 1.0 15.3 standby mode release release of standby mode is executed by reset input and interrupt signal. register value is defined when reset. when there is a release signal of stop mode (interrupt, reset input), the instruction execution starts after stabi- lization oscillation time is set by value of bts2 ~ bts0 and set enpck to ``1``. table 15-1 standby mode register table 15-2 standby mode release release signal kscn (key input) sleep reset int1 , int2 b.i.t stop o o o o o o o x release factor kscn (key input) release method reset int1 int2 basic interval timer (ifbit) standby mode is released by low input of selected pin by key scan input (smrr0, smrr1) in case of interrupt mask enable flag = ``0``, program executes just after standby instruction, if flag = ``1``, enters each interrupt service routine. when external interrupt (int1, int2) enable flag is ``1``, standby mode is released at the rising edge of each terminal. when standby mode is released at interrupt. mask enable flag = ``0``, program executes from the next instruction of standby instruction. when ``1``, enters each interrupt service routine. when b.i.t is executed only by bit10 of prescaler (ps10), sleep mode can be release. interrupt release sleep mode, when bit interrupt enable flag is ``1``. when standby mode is released at interrupt. mask enable flag = ``0``, program executes from the next instruction of sleep instruction. when ``1``, enters each interrupt service routine. by reset pin = low level, standby mode is release and system is initialized
hms87c5216 sep. 2001 ver 1.0 65 figure 15-3 release timing of standby mode 15.4 release operation of standby mode after standby mode is released, the operation begins ac- cording to content of related interrupt register just before standby mode start (figure 15-4 ) (1) interrupt enable flag(i) of psw = ``0`` release by only interrupt which interrupt enable flag = ``1``, and starts to execute from next to standby instruction (sleep or stop). (2) interrupt enable flag(i) of psw = ``1`` released by only interrupt which each interrupt enable flag = ``1``, and jump to the relevant interrupt service routine. note: when stop instruction is used, b.i.t should guar- antee the stabilization oscillation time. thus, just before en- tering stop mode, clock of bit10 (ps10) of prescaler is selected or peripheral hardware clock control bit (enpck) to ``1``, therefore the clock necessary for stabilization os- cillation time should be input into b.i.t. otherwise, standby mode is released by reset signal. in case of interrupt re- quest flag and interrupt enable flag are both ``1``, standby mode is not entered. stop mode stable osc. time program setting time by ckctlr longer than stable osc. time xin longer than 2 machine cycle sleep mode sleep command [ sleep mode ] [ stop mode ] release by interrupt reset clock release by interrupt reset
hms87c5216 66 sep. 2001 ver 1.0 figure 15-4 standby mode release flow table 15-3 operation state in standby mode stop command standby mode interrupt request gen. ie flag standby mode release psw ie flag interrupt service routine standby next command execution 0 1 0 1 internal circuit stop mode sleep mode oscillator internal cpu clock register ram i/o port prescaler basic interval timer watch dog timer timer address bus, data bus active stop retained retained retained active ps10 selected : active others : stop stop stop retained stop stop retained retained retained retained stop stop stop retained
hms87c5216 sep. 2001 ver 1.0 67 16. oscillation circuit oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. fig. 4.2-(a) shows circuit diagrams using a crystal (or ceramic) oscillator. as shown in the diagram, oscillation circuits can be construct- ed by connecting a oscillator between xout and xin. clock from oscillation circuit makes cpu clock via clock pulse generator, and then enters prescaler to make periph- eral hardware clock. alternately, the oscillator may be driven from an external source as shown is fig. 4.2.-(b). in the standby (stop) mode, oscillatiion stop, xout state goes to ``hiigh``, xin state goes to ``low``, and built-in feed back resistor is disabled. figure 16-1 oscillator configurations * recommendable resonator * mc type is building in load capacitior.ccr type is chip type. cout cin xin xout (b) external clock input circuit xin xout external clock (a) external crystal (ceramic) oscillator circuit frequency resonator maker part name load capacitor operating voltage 4.0 mhz cq zta4.00mg cin=cout=30pf 2.2 ~ 4.0v tdk fcr4.0mc5 cin=cout=open 2.2 ~ 4.0v tdk fcr4.0m5 cin=cout=33pf 2.2 ~ 4.0v tdk ccr4.0mc3 2.2 ~ 4.0v
hms87c5216 68 sep. 2001 ver 1.0 17. reset function 17.1 external reset the reset pin should be held at low for at least 2machine cycles with the power supply voltage within the operating voltage range and must be connected 0.1uf capacitor for stable system initialization. the reset pin contains a schmitt trigger with an internal pull-up resistor. figure 17-1 17.2 power on reset power on reset circuit automatically detects the rise of power voltage (the rising time should be within 50ms) the power voltage reaches a certain level, reset terminal is maintained at ?l? level until a crystal ceramic oscillator oscillates stably. after power applies and starting of oscil- lation, this reset state is maintained for about oscillation cycle of 219 (about 65.5ms : at 4mhz).the execution of built-in power on reset circuit is as follows : (1) latch the pulse from power on detection pulse gener- ator circuit, and reset prescaler, b.i.t and b.i.t overflow detection circuit. (2) once b.i.t overflow detection circuit is reset. then, prescaler starts to count. (3) prescaler output is inputted into b.i.t and ps10 of prescaler output is automatically selected. if overflow of b.i.t is detected, overflow detection circuit is set. (4) reset circuit generates maximum period of reset pulse from prescaler and b.i.t. figure 17-2 block diagram of power on reset circuit reset 0.1 uf capacitor reset power on det pulse gen. osc. clr prescaler clr basic interval tiemr clr basic interval tiemr xtal ps10 msb internal reset vdd vss 0.1uf internal ic
hms87c5216 sep. 2001 ver 1.0 69 note: notice ; when power on reset, oscillator stabiliza- tion time doesn`t include osc. start time. figure 17-3 oscillator stabilization diagram figure 17-4 reset timing by diagram 17.3 low voltage detection mode (1) low voltage detection condition an on board voltage comparator checks that vdd is at the required level to ensure correct operation of the device. if vdd is below a certain level, low voltage detector forces the device into low voltage detection mode. (2) low voltage detection mode there is no power consumption except stop current, stop mode release function is disabled. all i/o port is config- ured as input mode and data memory is retained until volt- age through external capacitor is worn out. in this mode, all port can be selected with pull-up resistor by mask op- tion. if there is no information on the mask option sheet ,the default pull up option (all port connect to pull-up resis- }kk vzju z{hy{ {ptpun wylzjhsly jv|u{ z{hy{ reset addr. bus internal data bus sp sp-1 sp-2 fffe ffff new pc fe lsb vector msb vector internal reset
hms87c5216 70 sep. 2001 ver 1.0 tor ) is selected. (3) release of low voltage detection mode reset signal result from new battery(normally 3v) wakes the low voltage detection mode and come into normal reset state. it depends on user whether to execute ram clear routine or not. figure 17-5 low voltage vs temperature (4) sram back-up after low voltage detection. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0 10 20 30 40 50 60 70 {??????????o p s?? }?????? o}p 2.6 2.8 3.0
hms87c5216 sep. 2001 ver 1.0 71 figure 17-6 low voltage detection and protection (5) s/w flow chart example after reset using sram back-up figure 17-7 s/w flow chart example for sram back-up 3.0v 1.8v(typ) ( 20 p * sram data backup user removes batteries user replace batteries interrupt : disable stop release : disable all i/o port : input mode remout port : low level osc : stop all i/o port pull-up on (mask option ) sram data retention * the operation after low voltage detection about hours depend on vcc-gnd capacitor 0v low voltage detection point mcu opr. voltage power on reset ( sram unstable ) power on reset ( sram retention) 0.7v(v ret ) reset stack pointer initialize sram data is valid? check the sram value (ram pattern, check sum..) n y clear all ram area use saved sram value
hms87c5216 72 sep. 2001 ver 1.0 17.4 low voltage indicator register (lvir) low voltage indication register (lvir) is read only reg- ister. it is useful to display the consumption of batteries. if vdd power level is below a cirtain level which is higher than low voltage detection level ( refer to figure 17-6 ) , the bit of lvir register could be set according to the vdd level sequentially. the vdd dection levels for indication are two , that is , bit1 and bit0 of lvir register. the de- tection level of bit0 is higer than bit1. ------lvir1lvir0 <00ef h> lvir bit7 6543210 initial value - - - - - 00 r / w- ---- rr - -
hms87c5216 sep. 2001 ver 1.0 73 18. clock generator clock generating circuit consists of clock pulse generator (c.p.g), prescaler, basic interval timer (b.i.t) and watch dog timer. the clock applied to the xin pin divided by two is used as the internal system clock. figure 18-1 block diagram of clock generator prescaler consists of 12-bit binary counter. the clock sup- plied from oscillation circuit is input to prescaler (fex). the divided output from each bit of prescaler is provided to peripheral hardware. figure 18-2 block diagram of prescaler 9 prescaler c.p.g mux wdt (6) comparator internal data bus 01234 056 6 wdton to reset circuit ifwdt wdtcl ifbit 5 0 7 0 fcpu fex ps1 enpck peripheral ckctlr btcl 3 8 osc circuit b.i.t (8) 6 wdtr internal system clock 5 b.i.t peripheral ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12 fex enpck fcpu ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 ps11 ps12
hms87c5216 74 sep. 2001 ver 1.0 table 18-1 ps output perio basic interval timer the hms87c5216 and gms81c1408 has one 8-bit basic interval timer that is free-run, can not stop. block diagram is shown in figure 18-3 .the 8-bit basic interval timer reg- ister (bitr) is increased every internal count pulse which is divided by prescaler. since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. as the count overflows from ff h to 00 h , this overflow causes to generate the basic interval timer inter- rupt. the bitf is interrupt request flag of basic interval timer. when write 1 to bit btcl of ckctlr, bitr register is cleared to 0 and restart to count-up. the bit btcl be- comes 0 after one machine cycle by hardware. if the stop instruction executed after writing 1 to bit wakeup of ckctlr, it goes into the wake-up timer mode. in this mode, all of the block is halted except the os- cillator, prescaler (only fxin ? 2048) and timer0. if the stop instruction executed after writing 1 to bit rcwdt of ckctlr, it goes into the internal rc oscillat- ed watchdog timer mode. in this mode, all of the block is halted except the internal rc oscillator, basic interval timer and watchdog timer. more detail informations are explained in power saving function. the bit wdton de- cides watchdog timer or the normal 7-bit timer note: all control bits of basic interval timer are in ckctlr register which is located at same address of bitr (address ec h ). address ec h is read as bitr, writ- ten to ckctlr. therefore, the ckctlr can not be accessed by bit manipulation instruction. . figure 18-3 block diagram of basic interval timer fex (mhz) 4 mhz 2 mhz frequency period frequency period ps 0 ps 1 ps 2 ps 3 ps 4 ps 5 ps 6 ps 7 ps 8 ps 9 ps 10 ps 11 ps 12 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 31.25 khz 15.63 khz 7.183 khz 3.906 khz 1.953 khz 0.976 khz 250 ns 500 ns 1 us 2 us 4 us 8 us 16 us 32 us 64 us 128 us 256 us 512 us 1024 us 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 31.25 khz 15.63 khz 7.183 khz 3.906 khz 1.953 khz 0.976 khz 0.488 khz 500 ns 1 us 2 us 4 us 8 us 16 us 32 us 64 us 128 us 256 us 512 us 1024 us 2048 us ? 8 ? 16 ? 128 ? 256 ? 512 ? 1024 ? 32 ? 64 0 1 mux 8 3 fxin bitr (8bit) bitif bts[2:0] rcwdt internal rc osc basic interval timer interrupt btcl clear to watchdog timer
hms87c5216 sep. 2001 ver 1.0 75 figure 18-4 ckctlr: clock control register clock control register ckctlr address : ech reset value : -0010111 - wakeup rcwdt wdton btcl bts2 bts1 bts0 basic interval timer clock selection 000 : fxin ? 8 001 : fxin ? 16 100 : fxin ? 128 101 : fxin ? 256 110 : fxin ? 512 111 : fxin ? 1024 010 : fxin ? 32 011 : fxin ? 64 symbol function description wakeup 1 : enables wake-up timer 0 : disables wake-up timer rcwdt 1 : enables internal rc watchdog timer 0 : disables internal rc watchdog time wdton 1 : enables watchdog timer 0 : operates as a 7-bit timer btcl 1 : bitr is cleared and btcl becomes 0 automatically after one machine cycle, and bitr continue to count-up bit manipulation not available
hms87c5216 76 sep. 2001 ver 1.0 19. analog to digital converter the analog-to-digital converter (a/d) allows conversion of an analog input signal to a corresponding 8-bit digital value. the a/d module has eight analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which gen- erates the result via successive approximation. the analog reference voltage is v dd . the a/d module has two registers which are the control register admr and a/ d result register addr. the admr register, shown in figure 19-2 , controls the operation of the a/d converter module. the port pins can be configure as analog inputs or digital i/o. to use analog inputs, each port is assigned analog input port by setting the bit ansel[7:0] in rafunc register. and selected the corresponding channel to be converted by setting ads[2:0]. the processing of conversion is start when the start bit adst is set to 1. after one cycle, it is cleared by hard- ware. the register adcr contains the results of the a/d conversion. when the conversion is completed, the result is loaded into the adcr, the a/d conversion status bit adsf is set to 1, and the a/d interrupt flag adif is set. the block diagram of the a/d module is shown in figure 19-1 . the a/d status bit adsf is set automatically when a/d conversion is completed, cleared when a/d conver- sion is in process. the conversion time takes maximum 30 us (at fxin=4 mhz). figure 19-1 a/d converter block diagram r1[4]/an0 aden r1[5]/an1 aden r1[6]/an2 aden r1[7]/an3 aden 00 01 10 11 s/h successive approximation circuit adif resistor ladder circuit addr(8-bit) sample & hold a/d interrupt address : edh reset value : undefined a/d result register avdd aden adan[1:0]
hms87c5216 sep. 2001 ver 1.0 77 figure 19-2 a/d converter registers figure 19-3 a/d converter operation flow a/d converter cautions (1) input range of an0 to an3 the input voltage of an0 to an3 should be within the specification range. in particular, if a voltage above vdd or below vss is input (even if within the absolute maximum rat- ing range), the conversion value for that channel can not be inde- terminate. the conversion values of the other channels may also be affected. (2) noise countermeasures in order to maintain 8-bit resolution, attention must be paid to noise on pins vdd and an0 to an3. since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 19-4 in order to reduce noise. figure 19-4 analog input pin connecting capacitor (3) pins an0/r1[4] and an1/r1[5] to an3/r1[7] admr address : f4h reset value : --000001 - anen adan3 adan2 adan1 adan0 adst adf analog channel select a/d status bit 0 : a/d conversion is in process 1 : a/d conversion is completed a/d start bit 1 : a/d conversion is started after 1 cycle, cleared to 0 0 : bit force to zero 0000 : channel 0 (r1[4]/an0) 0001 : channel 1 (r1[5]/an1) 0010 : channel 2 (r1[6]/an2) 0011 : channel 3 (r1[7]/an3) a/d enable bit 1 : a/d conversion is enable 0 : a/d converter module shut off and consumes no operation current a/d control register adcr address : f5h reset value : undefined adcr7 adcr6 adcr5 adcr4 adcr3 adcr2 adcr1 adcr0 a/d result data register enable a/d converter a/d start (adst = 1) nop adsf = 1 a/d input channel select analog reference select read adcr yes no an0~an3 100~1000pf analog input
hms87c5216 78 sep. 2001 ver 1.0 the analog input pins an0 to an3 also function as input/ output port (port r1 ) pins. when a/d conversion is per- formed with any of pins an0 to an3 selected, be sure not to execute a port input instruction while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion.

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