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ds05-11316-1e fujitsu semiconductor data sheet memory cmos 4 m 4 bits fast page mode dynamic ram MB8117400B-50/-60 cmos 4,194,304 4 bits fast mode dynamic ram n description the fujitsu mb8117400b is a fully decoded cmos dynamic ram (dram) that contains 16,777,216 memory cells accessible in 4-bit increments. the mb8117400b features a ?ast page mode of operation whereby high- speed random access of up to 1,024-bits of data within the same row can be selected. the mb8117400b dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. since the standby current of the mb8117400b is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb8117400b is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon and two- layer aluminum process. this process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb8117400b are not critical and all inputs are ttl compatible. n product line & features parameter MB8117400B-50 mb8117400b-60 ras access time 50 ns max. 60 ns max. randam cycle time 90 ns min. 110 ns min. address access time 25 ns min. 30 ns max. cas access time 15 ns max. 15 ns max. fast page mode cycle time 35 ns min. 40 ns min. low power dissipation operating current 660 mw max. 550 mw max. standby current 11 mw max. (ttl level) / 5.5 mw max. (cmos level) 4,194,304 words 4 bits organization silicon gate, cmos, advanced capacitor cell all input and output are ttl compatible 2048 refresh cycles every 32 ms early write or oe controlled write capability ras only, cas -before-ras , or hidden refresh fast page mode, read-modify-write capability on chip substrate bias generator for high performance
2 MB8117400B-50/-60 n package (lcc-26p-m09) plastic soj package (fpt-26p-m05) (normal bend) plastic tsop (ll) package package and ordering information ?26-pin plastic (300 mil) tsop (ii) with normal bend leads, order as mb8117400b- pftn ?26-pin plastic (300 mil) soj, order as mb8117400b- pj marking side
3 MB8117400B-50/-60 fig. 1 mb8117400b dynamic ram - block diagram a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 ras cas we dq 1 to v cc v ss clock gen #1 write clock gen mode control clock gen #2 column decoder sense ampl & i/o gate 16,777,216 bit storage cell data in buffer data out buffer address buffer pre- decoder refresh address counter row decoder substrate bias gen & dq 4 oe
4 MB8117400B-50/-60 n pin assignments and descriptions we ras n.c. dq 2 dq 1 v cc 1 2 3 4 5 19 14 15 8 9 10 11 12 26 25 24 23 22 17 16 621 13 18 1 2 3 4 5 8 9 10 11 12 15 16 17 26 25 24 23 22 19 18 6 13 14 21 designator function dq 1 to dq 4 v cc a 0 to a 10 v ss data input/ output write enable row address strobe address inputs +5 volt power supply column address strobe circuit ground output enable (marking side) 1 pin index n.c. no connection we ras cas oe cas cas we ras n.c. dq 2 dq 1 v cc a 10 a 0 a 1 a 2 a 3 v cc oe v ss dq 3 dq 4 a 8 a 7 a 6 a 5 a 4 v ss a 9 oe a 9 a 8 a 7 a 6 a 5 a 4 v ss a 10 a 0 a 1 a 2 a 3 v cc v ss dq 4 dq 3 26-pin soj (top view) 26-pin tsop (ll) (top view)
5 MB8117400B-50/-60 n functional truth table x : ? or ? * : it is impossible in fast page mode. n functional operation address inputs twenty-two input bits are required to decode any four of 16,777,216 cell addresses in the memory matrix. since only eleven address bits (a 0 to a 10 ) are available, the row and column inputs are separately strobed by ras and cas as shown in figure 1. first, eleven row address bits are input on pins a 0 -through-a 10 and latched with the row address strobe (ras ) then, ten column address bits are input and latched with the column address strobe (cas ). both row and column addresses must be stable on or before the falling edges of ras and cas , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min)+ t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data inputs input data is written into memory in either of three basic ways?n early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or cas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data (dq 1 to dq 4 ) is strobed by cas and the setup/hold times are referenced to cas because we goes low before cas . in a delayed write or a read-modify-write cycle, we goes low after cas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. operation mode clock input address input input data refresh note ras cas we oe row column input output standby h h x x high-z read cycle l l h l valid valid valid yes * t rcs 3 t rcs (min) write cycle (early write) l l l x valid valid valid high-z yes * t wcs 3 t wcs (min) read-modify- write cycle llh ? ll ? h valid valid valid valid yes * ras -only refresh cycle l h x x valid high-z yes cas -before- ras refresh cycle l l h x high-z yes t csr 3 t csr (min) hidden refresh cycle h ? llh ? x l valid yes previous data is kept.
6 MB8117400B-50/-60 data outputs the three-state buffers are ttl compatible with a fan out of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max) is satis?d. t cac : from the falling edge of cas when t rcd is greater than t rcd (max). t aa : from column address input when t rad is greater than t rad (max). t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . the data remains valid until either cas or oe returns to a high logic level. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. fast page mode of operation the fast page mode of operation provides faster memory access and lower power dissipation. the fast page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each fast page of memory, any of 1,024 4-bits can be accessed and, when multiple mb 8117400bs are used, cas is decoded to select the desired memory fast page. fast page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted.
7 MB8117400B-50/-60 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n capacitance (t a = 25 c, f = 1 mhz) parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.5 to +7 v voltage of v cc supply relative to v ss v cc ?.5 to +7 v power dissipation p d 1.0 w short circuit output current ?0 to +50 ma operating temperature t ope 0 to +70 c storage temperature t stg ?5 to +125 c parameter notes symbol min. typ. max. unit ambient operating temp supply voltage *1 v cc 4.5 5.0 5.5 v 0 c to +70 c v ss 000 input high voltage, all inputs *1 v ih 2.4 6.5 v input low voltage, all inputs/outputs* *1 v il ?.3 0.8 v parameter symbol typ. max. unit input capacitance, a 0 to a 10 c in1 ?pf input capacitance, ras , cas , we , oe c in2 ?pf input/output capacitance, dq 1 to dq 4 c dq ?pf
8 MB8117400B-50/-60 n dc characteristics (at recommended operating conditions unless otherwise noted.) note 3 parameter notes symbol conditions value unit min. typ. max. output high voltage v oh i oh = ? ma 2.4 v output low voltage v ol i ol = 4.2 ma 0.4 input leakage current (any input) i i(l) 0v v in v cc ; 4.5v v cc 5.5v; v ss = 0v; all other pins under test = 0v ?0 10 m a output leakage current i o(l) 0 v v out v cc ; data out disabled ?0 10 operating current (average power supply current) *2 MB8117400B-50 i cc1 ras & cas cycling; t rc = min 120 ma mb8117400b-60 100 standby current (power supply current) *2 ttl level i cc2 ras = cas = v ih 2.0 ma cmos level ras = cas 3 v cc ?.2 v 1.0 refresh current #1 (average power supply current) *2 MB8117400B-50 i cc3 cas = v ih , ras cycling; t rc = min 120 ma mb8117400b-60 100 fast page mode current *2 MB8117400B-50 i cc4 ras =v il , cas cycling; t pc = min 80 ma mb8117400b-60 70 refresh current #2 (average power supply current) *2 MB8117400B-50 i cc5 ras cycling; cas -before-ras ; t rc = min 120 ma mb8117400b-60 100
9 MB8117400B-50/-60 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 (continued) no. parameter notes symbol MB8117400B-50 mb8117400b-60 unit min. max. min. max. 1 time between refresh t ref ?2?2ms 2 random read/write cycle time t rc 90 110 ns 3 read-modify-write cycle time t rwc 126 150 ns 4 access time from ras *6,9 t rac ?0?0ns 5 access time from cas *7,9 t cac ?5?5ns 6 column address access time *8,9 t aa ?5?0ns 7 output hold time t oh 3?ns 8 output buffer turn on delay time t on 0?ns 9 output buffer turn off delay time *10 t off ?3?5ns 10 transition time t t 350350ns 11 ras precharge time t rp 30?0ns 12 ras pulse width t ras 50 100000 60 100000 ns 13 ras hold time t rsh 15?5ns 14 cas to ras precharge time t crp 5?ns 15 ras to cas delay time *11,12 t rcd 17 35 20 45 ns 16 cas pulse width t cas 15?5ns 17 cas hold time t csh 50?0ns 18 cas precharge time (normal) *19 t cpn 7 10 ns 19 row address set up time t asr 0?ns 20 row address hold time t rah 7 10 ns 21 column address set up time t asc 0?ns 22 column address hold time t cah 7 10 ns 23 column address hold time from ras t ar 24?0ns 24 ras to column address delay time *13 t rad 12 25 15 30 ns 25 column address to ras lead time t rel 25?0ns 26 column address to cas lead time t cal 25?0ns 27 read command set up time t rcs 0?ns 28 read command hold time referenced to ras *14 t rrh 0?ns 29 read command hold time referenced to cas *14 t rch 0?ns
10 MB8117400B-50/-60 (continued) no. parameter notes symbol MB8117400B-50 mb8117400b-60 unit min. max. min. max. 30 write command set up time *15 t wcs 0?ns 31 write command hold time t wch 7 10 ns 32 write hold time from ras t wcr 24?0ns 33 we pulse width t wp 7 10 ns 34 write command to ras lead time t rwl 13?5ns 35 write command to cas lead time t cwl 15?5ns 36 din set up time t ds 0?ns 37 din hold time t dh 7 10 ns 38 data hold time from ras t dhr 24?0ns 39 ras to we delay time *20 t rwd 68?0ns 40 cas to we delay time *20 t cwd 33?5ns 41 column address to we delay time *20 t awd 43?0ns 42 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 43 cas set up time for cas -before-ras refresh t csr 0?ns 44 cas hold time for cas -before-ras refresh t chr 10?0ns 45 we set up time from ras t wsr 0?ns 46 we hold time from ras t whr 10?0ns 47 access time from oe *9 t oea ?5?5ns 48 output buffer turn off delay form oe *10 t oez ?3?5ns 49 oe to ras lead time for valid data t oel 5?ns 50 oe hold time referenced to we *16 t oeh 5?ns 51 oe to data in delay time t oed 13?5ns 52 cas to data in delay time t cdd 13?5ns 53 din to cas delay time *17 t dzc 0?ns 54 din to oe delay time *17 t dzo 0?ns 55 fast page mode ras pulse width t rasp 100000 100000 ns 60 fast page mode read/write cycle time t pc 35?0ns
11 MB8117400B-50/-60 (continued) no. parameter notes symbol MB8117400B-50 mb8117400b-60 unit min. max. min. max. 61 fast page mode read-modify-write cycle time t prwc 73?0ns 62 access time from cas precharge *9,18 t cpa ?0?5ns 63 fast page mode cas precharge time t cp 7 10 ns 64 fast page mode ras hold time from cas precharge t rhcp 30?5ns 65 fast page mode cas precharge to we delay time t cpwd 48?5ns
12 MB8117400B-50/-60 notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il , cas = v ih and v il > ?.3v. i cc1 , i cc3 , i cc4 and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih . i cc2 is speci?d during ras = v ih and v il > ?.3 v. *3. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras -only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. *4. ac characteristics assume t t = 5 ns. *5. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also transition times are measured between v ih (min) and v il (max). *6. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig. 2 and 3. *7. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa ?t cac ?t t , access time is t cac . *8. if t rad 3 t rad (max) and t asc t aa ?t cac ?t t , access time is t aa . *9. measured with a load equivalent to two ttl loads and 100 pf. *10. t off and t oez is speci?d that output buffer change to high-impedance state. *11. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *12. t rcd (min) = t rah (min)+ 2 t t + t asc (min). *13. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max) limit, access time is controlled exclusively by t cac or t aa . *14. either t rrh or t rch must be satis?d for a read cycle. *15. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *16. assumes that t wcs < t wcs (min). *17. either t dzc or t dzo must be satis?d. *18. t cpa is access time from the selection of a new column address (that is caused by changing cas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max). *19. assumes that cas -before-ras refresh. *20. t wcs , t cwd , t rwd and t awd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs > t wcs (min), the cycle is an early write cycle and dq pin will maintain high-impedance state thoughout the entire cycle. if t cwd > t cwd (min), t rwd > t rwd (min), and t awd > t awd (min), the cycle is a read modify-write cycle and data from the selected cell will appear at the dq pin. if neither of the above conditions is satis?d, the cycle is a delayed write cycle and invalid data will appear the dq pin , and write operation can be executed by satisfying t rwl , t cwl , and t ral speci?ations.
13 MB8117400B-50/-60 fig. 2 ?t rac vs. t rcd fig. 4 ?t cpa vs. t cp fig. 3 ?t rac vs. t rad t rcd (ns) t rad (ns) t cp (ns) t rac (ns) t rac (ns) t cpa (ns) 60 50 80 70 90 20 040 30 60 50 50 ns version 60 ns version 100 70 60 50 80 70 90 20 040 30 60 50 50 ns version 60 ns version 100 70 40 30 60 50 70 10 030 20 50 40 50 ns version 60 ns version 80 60
14 MB8117400B-50/-60 we cas ras description to implement a read operation, a valid address is latched in by the ras and cas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. the access time is determined by ras (t rac ), cas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max.), access time = t cac . if t rad > t rad (max.), access time = t aa . if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea . however, if either ca s or oe goes high, the output returns to a high-impedance state after t oh is satisfied. ? or ? level (excluding address and dq) row add valid data high-z high-z column add oe t cah a 0 to a 10 t rc t ras t crp t rcd t csh t rp t rsh t rad t rah t asc t asr t oh t rch t aa t cac t rac t off t on t rrh t cas t ral t cal t oel t rcs t dzc t dzo t oea t on t oed t oh t oez t cdd fig. 5 ?read cycle ? or ? level, ? ? l or ? ? h transition (address and dq) dq (output) dq (input) v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il
15 MB8117400B-50/-60 fig. 6 ?early write cycle (oe = ??or ?? description a write cycle is similar to a read cycle except we is set to a low state and oe is a ??or ??signal. a write cycle can be implemented in either of three ways-early write, oe write (delayed write), or read-modify-write. during all write cycles, timing parameters t rwl , t cwl and t ral must be satisfied. in the early write cycle shown above t wcs satisfied, data on the dq pin is latched with the falling edge of cas and written into memory. row valid data i n add column add high-z we cas ras a 0 to a 10 v oh t rc t ras t crp t rad t rcd t csh t rsh t asc t rah t asr t cal t ral t cah t rp t wch t wcs t ds t dh t cas t ar t cwl t wcr t wp t rwl t dhr ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) dq (output) dq (input) v ol v ih v il v ih v il v ih v il v ih v il v ih v il
16 MB8117400B-50/-60 fig. 7 ?oe (delayed write cycle) cas ras invalid data valid data i n col row add add high-z high-z high-z description in the oe (delayed write) cycle, t wcs is not satisfied ; thus, the data on the dq pins is latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t ds ). oe a 0 to a 10 we t rc t ras t crp t rad t rcd t csh t cas t rsh t asc t rah t asr t cwl t ral t cah t rp t wch t dzc t aa t rwl t rwd t cwd t awd t ds t dh t oed t rac t dzo t oea t oez t oeh t cac t wp ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) v oh dq (output) dq (input) v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il
17 MB8117400B-50/-60 fig. 8 ?read-modify-write cycle ras cas a 0 to a 10 valid data i n col row add add high-z high-z valid high-z description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. we oe t rwc t ras t csh t rp t rsh t cas t rcd t rad t rah t asc t awd t wp t rwd t cwl t cah t rwl t ral t rcs t ds t dh t cwd t dzc t aa t on t crp t asr t oed t cac t rac t oea t dzo t oez t oeh ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) v oh dq (output) dq (input) v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il
18 MB8117400B-50/-60 fig. 9 ?fast page mode read cycle ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) description the fast page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. valid data col row add add col add col add high-z high-z high-z high-z t dzc t rasp t rhcp t rsh t pc t csh t cp t cas t crp t rcd t asr t rad t rah t asc t cah t asc t cah t cah t rcs t rch t rcs t rch t dzc t oh t oh t oel t cpa t ral t ar t asc t rp t cas t rrh t rch t rcs t dzc t dzo t dzo t dzo t rac t cac t on t off t cac t on t off t aa t aa t oea t oez t oea t oez t oed t oed ras a 0 to a 10 cas we oe v oh dq (input) dq (output) v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il
19 MB8117400B-50/-60 fig. 10 ?fast page mode early write cycle (oe = ??or ?? we ras cas high-z valid data valid data valid data col row add add col add col add description the fast page mode write cycle is executed in the same manner as the fast page mode read cycle except the states of we and oe are reversed. data appearing on the dq pins is latched on the falling edge of cas and written into memory. during the fast page mode write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satisfied. t rasp t rhcp t rsh t rp t cas t cp t pc t csh t crp t rcd t cas t rah t asr t asc t cah t asc t cah t asc t cah t ral t wcs t wch t cwl t wch t wcs t wcl t wcs t wch t cwl t wp t ds t dh t ds t dh t dh t ds t wp t wp t rwl t rad t ar t wcr a 0 to a 10 t dhr ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) v oh dq (input) dq (output) v ol v ih v il v ih v il v ih v il v ih v il v ih v il
20 MB8117400B-50/-60 fig. 11 ?fast page mode oe write cycle oe ras invalid data col row add. add col add col add valid valid valid high-z description the fast page mode oe (delayed) write cycle is executed in the same manner as the fast page mode write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the fast page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t ds ). t rasp t rsh t rp t pc t csh t crp t rcd t cas t cas t asr t cah t rcs t cah t dh t rwl t wp t wp t aa t cwl t cpwd t cwl t cwl t ral t rhcp t asc t cah t asc t ar t rah t asc t cp t wp t ds t ds t dh t ds t dh t dzc t aa t aa t cac t oed t oed t rac t oeh t cac t oeh t cac t oed t oeh t oez t oea t oez t oea t oez t oea t dzo a 0 to a 10 cas we t rad ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) v oh dq (input) dq (output) v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il data data data
21 MB8117400B-50/-60 fig. 12 ?fast page mode read-modify-write cycle ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) valid data valid valid valid col row add add col add col add description during the fast page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input date appears at the dq pins during a normal cycle. high-z oe t rasp t rp t csh t crp t prwc t cas t cah t cwl t cwd t ral t rad t rcd t cp t rsh t cas t asc t cah t asc t cah t asc t asr t rah t rcs t cwl t wp t rcs t cpwd t wp t rcs t cwl t rwl t wp t dh t ds t dh t ds t dh t ds t dzc t oed t cac t aa t aa t cac t oed t on t dzo t oeh t oez t cpa t oea t oea t on ras a 0 to a 10 cas we t oez v oh dq (input) dq (output) v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il data data data
22 MB8117400B-50/-60 fig. 13 ?ras -only refresh (we = oe = ??or ?? ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) high-z row address t rc t ras t asr t rah t rpc t rp t crp t oh t off description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 2048 row addresses every 32-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and cas high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras . during ras -only refresh, dq pins are kept in a high-impedance state. ras a 0 to a 10 cas dq (input) v ih v il v ih v il v ih v il v oh v ol fig. 14 ?cas -before-ras refresh (addresses = we = oe = ??or ?? high-z description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if cas is held low for the specified setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next cas - before-ras refresh operation. ras cas we t wsr t oh t off t whr t cpn t csr t chr t ras t rc t rp t rpc ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) v ih v il v ih v il v ih v il v oh v ol dq (input)
23 MB8117400B-50/-60 fig. 15 ?hidden refresh cycle ras column row address address valid data out high-z high-z description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of cas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. we oe t rc t ras t chr t ras t rp t rp t rc t crp t oel t rcd t rad t rah t rah t asr t asc t ral t ar t cah t rcs t rrh t wsr t whr t aa t rac t dzc t cac t on t dzo t oea t oed t oez t off t cdd t oh a 0 to a 10 cas ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) v oh dq (input) dq (output) v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il
24 MB8117400B-50/-60 fig. 16 ?test mode set cycle (a0 to a10, oe = ??or ?? ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) description test mode ; the purpose of this test mode is to reduce device test time to one sixteenth of that required to test the device conventionally. the test mode function is entered by performing a we and cas -before-ras (wcbr) refresh for the entry cycle. in the test mode, read and write operations are executed in units of sixteenth bits which are selected by the address combination of ca 0 and ca 1 . in the write mode, data is written into sixteenth cells simultaneously. but the data must be input from dq 1 only. in the read mode, the data of sixteenth cells at the selected addresses are read out from dq and checked in the following manner. when the sixteenth bits are all ??or all ?? an ??level is output. when the sixteenth bits show a combination of ??and ?? an ??level is output. the test mode function is exited by performing a ras -only refresh or a cas -before-ras refresh for the exit cycle. in test mode operation, the following parameters are delayed approximately 10 ns from the specified value in the data sheet. t rc , t rwc , t rac , t cac , t aa , t ras , t rsh , t cas , t csh , t ral , t cal , t rwd , t cwd , t awd , t cpwd , t rhcp high-z ras we cas t ras t rp t rc t chr t csr t cpn t whr t wsr t oh t off v oh dq (output) v ol v ih v il v ih v il v ih v il
25 MB8117400B-50/-60 fig. 17 ?cas -before-ras refresh counter test cycle valid data high-z high-z high-z valid data in column address we cas ras oe t fcas t rp t chr t frsh t cp t csr t asc t fcah t ral t wsr t whr t rcs t fcwd t cwl t rwl t wp t dh t ds t dzc t oed t fcac t on t oea t dzo t oez t oeh description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the functionality of cas -before-ras refresh circuitry. if, after a cas -before-ras refresh cycle cas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are de?ed as follows: row address: bits a 0 through a 10 are de?ed by the on-chip refresh counter. column address: bits a 0 through a 10 are de?ed by latching levels on a 0 -a 10 at the second falling edge of cas . the cas -before-ras counter test procedure is as follows ; 1) initialize the internal refresh address counter by using 8 ras only refresh cycles. 2) use the same column address throughout the test. 3) write ? to all 2048 row addresses at the same column address by using normal write cycles. 4) read ? written in procedure 3) and check; simultaneously write ? to the same addresses by using cas - before-ras refresh counter test (read-modify-write cycles). repeat this procedure 2048 times with addresses generated by the internal refresh address counter. 5) read and check data written in procedure 4) by using normal read cycle for all 2048 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). ? or ? level (excluding address and dq) ? or ? level, ? ? l or ? ? h transition (address and dq) v oh dq (input) dq (output) v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a 0 to a 10 mb8117400b-60 MB8117400B-50 unit parameter min . max. ns no . min. max. 90 50 45 symbol (at recommended operating conditions unless otherwise noted.) cas to we delay time 91 35 ns 35 column address hold time cas pulse width 70 ns 63 50 ns 45 ns 45 50 access time from cas t fcac t fcah t fcwd t fcas t frsh ras hold time 92 93 94 note: assumes that cas -before-ras refresh counter test cycle only.
26 MB8117400B-50/-60 n package dimensions 26-lead plastic flat package (case no.: fpt-26p-m05) dimensions in mm (inches) 1.150.05(.045.002) lead no. (.005.002) 0.1250.05 8.220.20 (.324.008) (.020.004) 0.500.10 (.363.008) 9.220.20 (.300.004) 7.620.10 (stand off) 0.05(.002)min * 0.21(.008) m ref 15.24(.600) 0.10(.004) typ 1.27(.050) (.675.004) 17.140.10 (.016.004) 0.400.10 details of "a" part 0.25(.010) 0.15(.006) max 0.50(.020) max 0.15(.006) index "a" 1 6 8 13 14 19 21 26 1994 fujitsu limited f26005s-2c-1 c dimensions in mm (inches)
27 MB8117400B-50/-60 n package dimensions 26-lead plastic leaded chip carrier (case no.: lcc-26p-m09) +0.25 C0.20 +.010 C.008 C0.02 +0.05 C.001 +.002 * details of "a" part 0.81(.032)max 0.430.10 (.017.004) 0.10(.004) 2.60(.102)nom r0.81(.032)typ 3.50 .138 (.270.010) 6.860.25 0.20 .008 index (.339.005) 8.600.13 nom (.300) 7.62 13 8 6 1 14 19 21 26 1.270.13 (.050.005) 17.150.13(.675.005) 15.24(.600)ref 0.64(.025)min 2.80(.110)nom lead no. "a" 1994 fujitsu limited c26059s-3c-1 c dimensions in mm (inches)
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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