GS9000S serial data in serial data in serial clock in serial clock in level shift sp sync correction enable standards select control sync warning control descrambler level shift osc 2 bit counter parallel timing generator parallel clock out parallel data out (10 bits) sync word boundary sync error hsync reset 15 11 8 7 6 5 14 i clk hsync output ss0 ss1 sync warning flag 30 - bit shift reg sync detect (3ff 000 000 hex) sync correction sync warning (schmitt trigger comparator) auto standard select document no. 521 - 80 - 02 data sheet genlinx GS9000S serial digital decoder functional block diagram device description the GS9000S is a cmos integrated circuit specifically designed to deserialize smpte 259m serial digital signals at data rates to 300mbps. the device incorporates a descrambler, serial to parallel convertor, sync processing unit, sync warning unit and automatic standards select circuitry. differential pseudo-ecl inputs for both serial clock and data are internally level shifted to cmos levels. digital outputs such as parallel data, parallel clock, hsync, sync warning and standard select are all ttl compatible. the GS9000S is designed to directly interface with the gs9005a reclocking receiver to form a complete smpte-serial-in to cmos level parallel-out deserializer. the GS9000S may also be used with the gs9010a and the gs9005a to form an adjustment-free receiving system which automatically adapts to all serial digital data rates. the gs9015a can replace the gs9005a in GS9000S applications where cable equalization is not required. the GS9000S is packaged in a 28 pin plcc and operates from a single 5 volt, 5% power supply. features fully compatible with smpte 259m decodes 8 and 10 bit serial digital signals for data rates to 300 mb/s pin and function compatible with gs9000b and gs9000 250 mw power dissipation at 270 mhz clock rates incorporates an automatic standards selection function with the gs9005a receiver or gs9015a reclocker operates from single +5 or -5 volt supply enables an adjustment-free deserializer system when used with gs9010a and gs9005a or gs9015a 28 pin plcc packaging applications ? sc and 270 mb/s , 4:2:2 serial digital interfaces automatic standards select controller for serial routing and distribution applications using gs9005a receiver or gs9015a reclocker revision date: december 1999 gennum corporation p.o. box 489, stn a, burlington, ontario, canada l7r 3y3 tel. (905) 632-2996 fax: (905) 632-5946 gennum japan corporation a-302 miyamae village, 2-10-42 miyamae, suginami-ku, tokyo 168, japan tel. (03) 3334-7700 fax (03) 3247-8839 not recommended for new designs GS9000S
2 521 - 80 - 02 GS9000S not recommended for new designs parameter symbol conditions min typ max units notes supply voltage v s operating range 4.75 5.00 5.25 v power consumption p c ?= 270 mhz (see fig. 8) - 250 - mw input resistance r in - 10 - m ? input capacitance c in - 5 10 pf cmos input voltage vih min t a = 25 o c 3.4 - - v vil max - - 1.5 v output voltage voh min t a = 25 o c 2.4 4.5 - v vol max ioh = 4 ma - 0.2 0.5 v input leakage current i in v in = v dd or v ss -- 10 a serial clock & data inputs signal swing v in 700 800 1000 mv p-p signal offset v inos 3.0 - 4.2 v v dd = 5v, t a = 0 c to 70 c unless otherwise shown GS9000S decoder - dc electrical characteristics centre of swing parameter symbol conditions min typ max units notes serial input clock frequency sc i 100 300 mhz serial input data rate dr sd i 100 300 mb/s serial data & clock inputs: t a = 25 c risetime t r t clkl - - 1.0 ns setup t su 1.0 - - ns hold t hold 1.0 - - ns parallel clock: jitter t jclk t a = 25 c - 1.0 - ns p-p parallel data: risetime t r-pdn t a = 25 c, c l = 10pf - 1.0 - ns 20% to 80% pdn to pclk delay tolerance t d -- 3ns v dd = 5v, t a = 0 c to 70 c unless otherwise shown GS9000S decoder - ac electrical characteristics absolute maximum ratings parameter value/units supply voltage (v s =v dd -v ss )7 v input voltage range (any input) -0.3 to (v dd +0.3) v dc input current (any one input)25 mw 10 a power dissipation 400 mw operating temperature range 0 c to 70 c storage temperature range -65 c to +150 c lead temperature (soldering, 10 seconds) 260 c ordering information part number package temperature GS9000Scpj 28 pin plcc 0 c to 70 c GS9000Sctj 28 pin plcc tape 0 c to 70 c rising edge of pclk to bit period centre
3 521 - 80 - 02 not recommended for new designs GS9000S GS9000S pin descriptions pin no. symbol type description 1 hsync output horizontal sync output. cmos (ttl compatible) output that toggles for each trs detected. 2v ss power supply. most negative power supply connection. 3 swf output sync error warning flag. cmos (ttl compatible) active high output that indicates the preselected hsync error rate (her). the her is set with an rc time constant on the swc input. 4v ss power supply. most negative power supply connection. 5,6 sdi/sdi inputs differential, pseudo-ecl serial data inputs . ecl voltage levels with offset of 3v to 4.2v for operation up to 300 mhz. see ac characteristics for details. 7,8 sci/sci inputs differential, pseudo-ecl serial clock inputs. ecl voltage levels with offset of 3v to 4.2v for operation up to 300 mhz. see ac characteristics for details. 9,10 ss1/ss0 output standard select outputs . cmos (ttl compatible) outputs used with the gs9005a receiver in order to perform an automatic standards select function. these outputs are generated by a 2 bit internal binary counter which stops cycling when there is no carrier present at the gs9005a receiver input or when a valid trs is detected by the GS9000S. 11 ssc input standards select control. analog input used to set a time constant for the standards select hunt period. an external rc sets the time constant. when a gs9005a receiver is used, the open collector carrier detect output also connects to this pin in order to enable or disable the internal 2 bit binary counter which controls the hunting process. 12 v dd power supply . most positive power supply connection. 13 v dd power supply. most positive power supply connection. 14 sce input sync correction enable. active high cmos input which enables sync correction by not resetting the GS9000S? internal parallel timing on the first sync error. if the next incoming sync is in error, internal parallel timing will be reset. this is to guard against spurious hsync errors. when sce is low, a valid sync will always reset the GS9000S? parallel timing generator. fig. 1 GS9000S pin outs, 28 pin plcc package pd7 pd6 pd5 pd4 pd3 pd2 pd1 sd1 sd1 sc1 sc1 ss1 ss0 ssc (msb) v ss swf v ss hsync pd9 pd8 v ss GS9000S top view v dd v dd sce swc pclk pd0 v dd (lsb) 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 28 27 26
4 521 - 80 - 02 GS9000S not recommended for new designs sdi sci bias sdi sci v dd v dd sce v dd v dd r ext external components ssc v dd v dd r ext c ext swc external components v dd v dd 6800 GS9000S pin descriptions pin no. symbol type description 15 swc input sync warning control . analog input used to set the hsync error rate (her). this is accomplished by an external rc time constant connected to this pin. 16 pclk output parallel clock output. cmos (ttl compatible) clock output where the rising edge of the clock is located at the centre of the parallel data window within a given tolerance. see fig. 2. 17 pd0 output parallel data output - bit 0 (lsb) . cmos (ttl compatible) descrambled parallel data output from the serial to parallel convertor representing the least significant bit (lsb). 18 v dd power supply . most positive power supply connection. 19 - 25 pd1 - pd7 outputs parallel data outputs - bit 1 to bit 7. cmos (ttl compatible) descrambled parallel data outputs from the serial to parallel convertor representing data bit 1 through data bit 7. 26 v ss power supply. most negative power supply connection. 27 pd8 output parallel data output. cmos (ttl compatible) descrambled parallel data output from the serial to parallel convertor representing data bit 8. 28 pd9 output parallel data output - bit 9 (msb). cmos (ttl compatible) descrambled data output from the serial to parallel convertor representing the most significant bit (msb). input / output circuits fig. 4 pins 5 - 8 sdi - sci fig. 2 pin 11 ssc fig. 3 pin 14 sce fig. 5 pin 15 swc fig. 6 pins 3, 16, 17, 19 - 25, 27, 28 swf, hsync, ssi, ssd, pclk, pd0-9 gnd output v dd
5 521 - 80 - 02 not recommended for new designs GS9000S fig. 7 waveforms in order to maintain very short interconnections when interfacing with the gs9005a receiver, the critical high speed inputs such as serial data (pins 5 and 6) and serial clock (pins 7 and 8) are located along one side of the device package. if the automatic standard select function is not used, the standard select bits (pins 9 and 10) do not need to be connected, however the control input (pin 11) should be grounded. test set-up & application information figure 9 shows the test set-up for the GS9000S operating from a v dd supply of +5 volts. the differential pseudo ecl inputs for data and clock (pins 5,6,7 and 8) must be biased between +3 and +4.2 volts. in the circuit shown, these inputs with the resistor values shown, can be directly driven from the outputs of the gs9005a reclocking receiver. in other cases, such as true ecl level driver outputs, two biasing resistors are needed on the data and clock inputs and the signals must be ac coupled. it is critical that the decoupling capacitors connected to pins 12,13 and 18 be chip types and be located as close as possible to the device pins. frequency (mhz) fig. 8 power consumption 1 10 100 300 10 100 200 300 500 typical performance curves (v s = 5v, t a = 25 c unless otherwise shown) t su t hold t clkl = t clkh serial clock (sci) serial data (sdi) 50% parallel data (pdn) 50% parallel clock (pclk) 1 / 2 t 1 / 2 t t d
6 521 - 80 - 02 GS9000S not recommended for new designs xxx 3ff 000 000 xxx xxx 3ff 000 000 xxx pclk pdn hsync decoder GS9000S 1 4 3 6 5 7 sdi sdi sci sci ss1 ss0 ssc 9 8 10 2 parallel data bit 0 parallel data bit 1 parallel data bit 2 parallel data bit 3 parallel data bit 4 parallel data bit 5 parallel data bit 6 parallel data bit 7 parallel data bit 8 parallel data bit 9 parallel clock out sync correction enable hsync output standards select bit 1 standards select bit 0 3x0.22 f ** 17 18 19 20 15 16 14 12 13 *11 +5v pd0 pdi pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pclk sce vss vss vss swc swf vdd vdd vdd hsync 82 ? (+3v) 4x100 ? 21 22 23 24 25 27 28 26 22nf * this pin receives a carrier detect signal from the gs9005a receiver. when the line is low, the internal counter is stopped and the outputs ss0 and ss1 retain their logic levels sync warning flag control time constant 500k ? +5v ** locate the three 0.22 f decoupling capacitors as close as possible to the corresponding pins on the GS9000S. chip capacitors are recommended. sync warning flag 100nf sdi in sdi in sci in sci in fig. 9 GS9000S test set-up with correctly synchronized serial data and clock connected to the GS9000S, the hsync output (pin 1) will toggle for each hsync detected. the parallel data bits pd0 through pd9 along with the parallel clock can be observed on an oscilloscope or fed to a logic analyzer. these outputs can also be fed through a suitable ttl to ecl converter to directly drive parallel inputs to receiving equipment such as monitors or digital to analog converters. in operation, the hsync output from the GS9000S decoder toggles on each occurrence of the timing reference signal (trs). the state of the hsync output is not significant, just the time at which it toggles. e a v s a v 4 sc data stream active video & h blanking t r s hsync out active video t r s t r s active video & h blanking 4:2:2 data stream e a v s a v h blnk h blnk hsync out the hsync output toggles to indicate the presence of the trs on the falling edge of pclk, one data symbol prior to the output of the first word in the trs. in the following diagram, data is indicated in 10 bit hex.
7 521 - 80 - 02 not recommended for new designs GS9000S standard truth table /2 p/n standard 0 0 4:2:2 - 270 0 1 n/a 1 0 4 sc - ntsc 1 1 4 sc - pal p/n out in- comp lf /2 v cc swf 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 parallel data bit 9 parallel data bit 8 parallel data bit 7 parallel data bit 6 parallel data bit 5 parallel data bit 4 parallel data bit 3 parallel data bit 2 parallel data bit 1 parallel data bit 0 parallel clock out sync correction enable hsync output sync warning flag input selection stdt v cc cd hsync gnd osc dly fvcap 10 10 10 + + + v cc +5v +5v v cc v cc v cc 0.1 100 100 100 100 390 390 390 390 0.1 0.1 0.1 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 12 13 14 15 16 17 18 910 22n (1) (2) (2) (2) (3) 75 113 75 47p 5.6p 10n 0.1 0.1 3.3n 82n 180n 0.68 0.1 22n dgnd dgnd dgnd dgnd 47p 0.1 dgnd gnd 1.2k 1.2k 68k 100 100 120 50k 0.1 100k swf swf gs9010a input ecl data input dd i dd i vcc2 sd i sd i /2 vee3 sdo sdo sco sco ss1 ss0 cd vcc1 vee1 agc a/d ss i vee2 vcc4 loop rvco0 rvco1 rvco2 eyeout rvco3 vcc3 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 0.1 dgnd dgnd ssi 100 100 100 3.3k 100 100 100 100 100 100 100 GS9000S sd i sd i sc i sc i ss1 ss0 sst pd7 pd6 pd5 pd4 pd3 pd2 pd1 vss swf vss hsync pd9 pd8 vss vdd vdd sce swc pclk pdo vdd star routed 12 13 14 15 16 17 18 v cc v cc v cc v cc 6.8 6.8 + + gs9005a v cc v cc dv cc dv cc dv cc v cc dv cc v cc figure 10 shows an application of the GS9000S in an adjustment free, multi-standard serial to parallel convertor. this circuit uses the gs9010a automatic tuning sub-system ic and a gs9005a serial digital receiver. the gs9005a may be replaced with a gs9015a reclocker ic if cable equalization is not required. the gs9010a ats eliminates the need to manually set or externally temperature compensate the receiver or reclocker vco. the gs9010a can also determine whether the incoming data stream is 4 sc ntsc,4 sc pal or component 4:2:2. the gs9010a includes a ramp generator/oscillator which repeatedly sweeps the receiver/reclocker vco frequency over a set range until the system is correctly locked. an automatic fine tuning (aft) loop maintains the vco control voltage at it's centre point through continuous, long term adjustments of the vco centre frequency. during normal operation, the GS9000S decoder provides continuous hsync pulses which disable the ramp/oscillator of the gs9010a. this maintains the correct r eceiver/ reclocker vco frequency. when an interruption to the incoming data stream is detected by the receiver/reclocker, the carrier detect goes low and tri-states the aft loop in order to maintain the correct vco frequency for a period of about 2 seconds. this allows the receiver/reclocker to rapidly relock when the signal is re-established. GS9000S, gs9005a and gs9010a interconnections fig. 10 application circuit - adjustment free multistandard serial to parallel convertor (1) typical value for input return loss matching (2) to reduce board space, the two anti-series 6.8 f capacitors (connected across pins 2 and 3 of the gs9010a) may be replaced with a 1.0 f non-polarized capacitor provided that: (a) the 0.68 f capacitor connected to the osc pin (11) of the gs9010a is replaced with a 0.33 f capacitor and (b) the gs9005a /15a loop filter capacitor is 10nf. (3) remove this potentiometer if p/n function is not required, and ground pin 16 of the gs9010a.
8 521 - 80 - 02 GS9000S not recommended for new designs gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ? copyright january 1997 gennum corporation. all rights reserved. printed in canada. caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation sync warning flag operation fig. 11 sync warning flag circuit sync error sync warning control v dd comparator 15 v dd sync warning flag (swf) 3 - + 6.8k each time hsync is not correctly detected, the sync warning flag output (pin 3 ) will go high. the rc network connected to the sync warning control input (pin 15) sets the number of sync errors that will cause the swf pin to go high. the component values of the rc network shown in figure 10 set the swf error rate to approximately one hsync error in 10 lines. these component values are chosen for optimum performance of the swf pin, and should not be adjusted. typically, hsync errors will become visible on a monitor before the swf will provide an indication of hsync errors. as a result, the swf function can be used in applications where the detection of significant signal degradation is desired. a high swf will go low as soon as the input error rate decreases below the set rate. this response time is determined by c, as mentioned earlier. a small amount of hysterisis in the comparator ensures noise immunity. revision notes: not recommended watermark added to all pages. document identification: data sheet the product is in production. gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
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