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preliminary data sheet august 2000 TTRN012G5 (2.5 gbits/s) and ttrn012g7 (2.5 gbits/s and 2.7 gbits/s) clock synthesizer, 16:1 data multiplexer features n TTRN012G5 supports oc-48/stm-16 data rate n ttrn012g7 supports: oc-48/stm-16 data rate rs (255, 239) forward error correction (fec) oc-48/stm-16 data rate n fully integrated clock synthesizer and 16:1 data multiplexer n supports clockless data transfer into the 16:1 multiplexer n parity checking and valid data indication n data inversion option n additional high-speed cml serial data output for system loopback n loss of lock indication n single 3.3 v supply n available in either mbic 025 bicmos technology or lower-power mbic 025 silicon germanium bicmos technology n lvpecl 155.52 mbits/s digital i/o n jitter generation and jitter transfer compliant with the following: telcordia technologies * gr-253 itu-t g.825 itu-t g.958 applications n sonet/sdh line origination equipment n sonet/sdh add/drop multiplexers n sonet/sdh cross connects n sonet/sdh test equipment n digital video transmission * telcordia technologies is a registered trademark of bell com- munications research, inc. description the lucent technologies microelectronics group TTRN012G5 operates at the oc-48/stm-16 data rate of 2.5 gbits/s. the ttrn012g7 device operates at either 2.5 gbits/s or the rs fec oc-48/stm-16 data rate of 2.7 gbits/s. for clarity, this data sheet refers to the TTRN012G5 serial data rate as 2.5 gbits/s and the parallel data and reference clock frequency as 155 mhz. (the precise rates are 2.48832 gbits/s and 155.52 mhz.) when using the ttrn012g7 at the fec rate, the 2.5 gbits/s data rate should be interpreted as 2.7 gbits/s and the par- allel and clock frequency should be interpreted as 166 mhz. (the precise rates are 2.66606 gbits/s and 166.62 mhz.) the devices provide a 16:1 multiplexer and clock multiplier unit. both a high-speed serial clock and data output are generated. the devices accept 16 differential pecl data inputs and a low-speed refer- ence clock. a unique feature of the multiplexer is that no clock is required to feed in the 16 data lines, as long as the upstream data chip clock is synchronous with the device refclkp/n input. alternatively, contra-clocking may be used, whereby the device provides one of four phases of a 155.52 mhz or 166.62 mhz clock output back upstream to the data chip. other features include a parity bit input and parity check on the 16 input data lines, a second 2.5 gbits/s or 2.7 gbits/s data output for loopback toward the trcv012g5 or trcv012g7 device, and a user-configurable pll bandwidth. both devices are available in either bicmos or in sige bicmos tech- nology for lower power operation.
TTRN012G5 and ttrn012g7 preliminary data sheet clock synthesizer, 16:1 data multiplexer august 2000 2 lucent technologies inc. table of contents contents page features ....................................................................................................................... ............................................. 1 applications ................................................................................................................... ............................................ 1 description.................................................................................................................... .............................................1 pin information ................................................................................................................ ..........................................4 functional overview ............................................................................................................ ...................................... 9 clock synthesizer operation .................................................................................................... .............................. 9 multiplexer operation.......................................................................................................... ..................................11 clocking modes and timing adjustments .......................................................................................... .....................12 clockless transfer mode (clkmode, extadjn, monapap/n) .......................................................................12 contra-directional clocking mode (clkmode, phadj[1:0]) ......................................................................... .....13 cml output structure (used on pins d2g5p/n, ck2g5p/n).......................................................................... .......14 choosing the value of the external cml reference resistors (rref1, rref2) ...............................................14 absolute maximum ratings....................................................................................................... ..............................15 handling precautions ........................................................................................................... ...................................15 operating conditions........................................................................................................... ....................................15 electrical characteristics ..................................................................................................... ....................................16 reference frequency (refclkp/n) specifications................................................................................. ............16 lvpecl, cmos, cml input and output pins ........................................................................................ ..............17 timing characteristics ......................................................................................................... ....................................19 transmit timing ................................................................................................................ ....................................19 outline diagram................................................................................................................ .......................................21 128-pin qfp .................................................................................................................... .....................................21 ordering information........................................................................................................... .....................................22 ds00-375hspl replaces ds00-155hspl to incorporate the following updates.................................................22
preliminary data sheet TTRN012G5 and ttrn012g7 august 2000 clock synthesizer, 16:1 data multiplexer 3 lucent technologies inc. description (continued) 5-8060(f)r.3 note: diagram is representative of device functionality and conceptual signal flow. internal implementation details may be diff erent than shown. figure 1. functional block diagram ck155p ck155n 16:1 multiplexer parity d0p d0n phase/ vco parity charge lfp lfn d1p d1n d15p d15n divide ck2g5p ck2g5n enck2g5 data validp validn d2g5p d2g5n invdatn resetn to digital logic tstckp tstckn testn refclkp refclkn phadj[1:0] manual clkmode 01 invdat test 0 1 acquisition lcklossn extadjn load monapap monapan 1 0 rref2 0 1 lbdp lbdn enlbdn vcp vcn rref1 parityp parityn check phase adjust indicator auto phase adjust freq. detector pump by 16 register retime
TTRN012G5 and ttrn012g7 preliminary data sheet clock synthesizer, 16:1 data multiplexer august 2000 4 lucent technologies inc. pin information 5-8066(f)r.3 figure 2. pin diagram of 128-pin qfp (top view) 1 2 3 5 4 6 7 9 8 18 10 11 13 12 14 15 17 16 19 20 22 21 23 24 26 25 35 27 28 30 29 31 32 34 33 36 37 38 39 41 40 42 43 45 44 54 46 47 49 48 50 51 53 52 55 56 58 57 59 60 62 61 63 64 100 99 98 96 97 95 94 92 93 83 91 90 88 89 87 86 84 85 82 81 79 80 78 77 75 76 66 74 73 71 72 70 69 67 68 65 128 127 126 124 125 123 122 120 121 111 119 118 116 117 115 114 112 113 110 109 107 108 106 105 103 104 102 101 nc v ccd v ccd lcklossn gnd gnd enlbdn v ccd gnd lbdp lbdn gnd v ccd rref1 rref2 enck2g5 v ccd gnd ck2g5n ck2g5p gnd d2g5n d2g5p gnd v ccd invdatn testn v ccd tstckn v ccd tstckp v ccd gnd v ccd v ccd gnd gnd gnd d2n d2p d3n d3p v ccd d4n d4p d5n d5p gnd d6n d6p d7n d7p v ccd d8n d8p d9n d9p gnd d10n d10p d11n d11p v ccd d12n d12p d13n d13p gnd d14n d14p d15n d15p v ccd gnd d1n d1p d0p d0n parityp gnd gnd parityn v ccd ck155p v ccd ck155n validn validp v ccd monapap nc monapan phadj1 phadj0 clkmode extadjn gnd resetn gnd gnd gnd gnd v ccd gnd refclkp refclkn v cca v ccd vcn v cca lfn lfp v cca vcp nc nc gnd gnd gnd gnd gnd gnd gnd gnd v cca nc gnd v cca
preliminary data sheet TTRN012G5 and ttrn012g7 august 2000 clock synthesizer, 16:1 data multiplexer 5 lucent technologies inc. pin information (continued) table 1. pin descriptions2.5 gbits/s and related signals note: in table 1, when operating the ttrn012g7 device at the oc-48/stm-16 rate, 2.5 gbits/s should be inter- preted as 2.48832 gbits/s. when operating the ttrn012g7 device at the rs fec oc-48/stm-16 rate, 2.5 gbits/s should be interpreted as 2.66606 gbits/s. (a similar interpretation should be made for 2.5 ghz.) * differential pairs are indicated by p and n suffixes. for nondifferential pins, n at the end of the symbol name designates act ive-low. ? i = input, o = output. i u indicates an internal pull-up resistor on this pin. pin symbol * type ? level name/description 14 d2g5p o cml data output (2.5 gbits/s nrz). 2.5 gbits/s differential data output. 15 d2g5n 27 lbdp o cml loopback data output. additional 2.5 gbits/s differential data output for system loopback. 26 lbdn 17 ck2g5p o cml clock output (2.5 ghz). 2.5 ghz differential clock output. 18 ck2g5n 23 rref1 i analog resistor reference 1. cml current bias reference resistor. (see table 15, page 18 for values.) 22 rref2 i analog resistor reference 2. cml bias reference resistor. connect a 1.5 k w resistor to v ccd . 21 enck2g5 i u cmos enable ck2g5p/n clock output. 0 = ck2g5p/n buffer powered off 1 or no connection = ck2g5p/n buffer enabled 30 enlbdn i u cmos enable lbdp/n data output (active-low). 0 = lbdp/n buffer enabled 1 or no connection = lbdp/n buffer powered off 11 invdatn i u cmos invert d2g5p/n data output (active-low). 0 = invert 1 or no connection = noninvert
TTRN012G5 and ttrn012g7 preliminary data sheet clock synthesizer, 16:1 data multiplexer august 2000 6 lucent technologies inc. pin information (continued) table 2. pin descriptions155.52 mbits/s and related signals note: in table 2, when operating the ttrn012g7 device at the oc-48/stm-16 rate, 155 mbits/s should be inter- preted as 155.52 mbits/s. when operating the ttrn012g7 device at the rs fec oc-48/stm-16 rate, 155 mbits/s should be interpreted as 166.62 mbits/s. (a similar interpretation should be made for 155 mhz.) * differential pairs are indicated by p and n suffixes. for nondifferential pins, n at the end of the symbol name designates act ive-low. ? i = input, o = output. i u indicates an internal pull-up resistor on this pin. pin symbol * type ? level name/description 99 d15p i lvpecl data input (155 mbits/s). 155 mbits/s differential data input. d15 is the most significant bit and is transmitted first on the d2g5p/n output. 98 d15n 97 d14p lvpecl 96 d14n 94 d13p lvpecl 93 d13n 92 d12p lvpecl 91 d12n 89 d11p lvpecl 88 d11n 87 d10p lvpecl 86 d10n 84 d9p lvpecl 83 d9n 82 d8p lvpecl 81 d8n 79 d7p lvpecl 78 d7n 77 d6p lvpecl 76 d6n 74 d5p lvpecl 73 d5n 72 d4p lvpecl 71 d4n 69 d3p lvpecl 68 d3n 67 d2p lvpecl 66 d2n 62 d1p lvpecl 61 d1n 60 d0p lvpecl 59 d0n
preliminary data sheet TTRN012G5 and ttrn012g7 august 2000 clock synthesizer, 16:1 data multiplexer 7 lucent technologies inc. pin information (continued) table 2. pin descriptions155.52 mbits/s and related signals (continued) * differential pairs are indicated by p and n suffixes. for nondifferential pins, n at the end of the symbol name designates act ive-low. ? i = input, o = output. i u indicates an internal pull-up resistor on this pin. pin symbol * type ? level name/description 53 ck155p o lvpecl clock output (155 mhz). 155 mhz differential clock output. 52 ck155n 43 44 phadj1 phadj0 i u cmos phase adjust. adjusts phase of ck155p/n in 90 degree steps. 42 clkmode i u cmos clock mode select. selects clockless data transfer mode. 0 = clockless transfer 1 or no connection = contra clock 57 parityp i lvpecl parity input over data (d[15:0]). 56 parityn 50 validp o lvpecl parity check output. validates the input of parityp/n. 0 = parity check does not agree with input parityp/n pins 1 = parity check agrees 49 validn 33 lcklossn o cmos loss of lock (active-low). 0 = pll out of lock. 41 extadjn i u cmos external automatic phase adjust (active-low). adjusts the 155 mhz clock output, ck155p/n. 0 = adjust phase of 155 mhz clock to data upon next transition of the d0p/n input signal 1 = no adjust must be held low until the first rising transition of d0p/n. 47 monapap o lvpecl monitor automatic phase adjust. indicates when a phase adjustment in the automatic phase adjust block occurs. 46 monapan 105 refclkp i lvpecl reference clock input (155 mhz). this clock is required. when applying the refclkp/n, set the refclkp/n to one of the following frequencies: n 155.52 mhz if using the trcv012g5, or the trcv012g7 at the 0c-48/stm-16 rate of 2.48832 ghz. n 166.62 mhz if using the trcv012g7 at the rs fec 0c-48/stm-16 rate of 2.66606 ghz. 106 refclkn 112 lfp i analog loop filter pll. connect lfp to vcp, and lfn to vcn. 111 lfn 113 vcp i analog vco control. connect vcp to lfp, and vcn to lfn. 110 vcn
TTRN012G5 and ttrn012g7 preliminary data sheet clock synthesizer, 16:1 data multiplexer august 2000 8 lucent technologies inc. pin information (continued) table 3. pin descriptionsreset and test signals * differential pairs are indicated by p and n suffixes. for nondifferential pins, n at the end of the symbol name designates act ive-low. ? i = input, o = output. i u indicates an internal pull-up resistor on this pin. table 4. pin descriptionspower and no-connect signals note: v cca and v ccd have the same dc value, which is represented as v cc unless otherwise specified. however, high-frequency filtering is suggested between the individual supplies. * differential pairs are indicated by p and n suffixes. for nondifferential pins, n at the end of the symbol name designates act ive-low. ? i = input, o = output. i u indicates an internal pull-up resistor on this pin. pin symbol * type ? level name/description 40 resetn i u cmos reset (active-low). resets all synchronous logic. during a reset, the true data outputs are in the low state and the barred data outputs are in the high state. 0 = reset 1 or no connection = normal operation 6 tstckp i cml test clock input. buffer is powered down when testn = 1. 8tstckn 10 testn i u cmos test clock select (active-low). 0 = select test clock 1 or no connection = select internal vco pin symbol * type ? level name/description 108, 109, 114, 126, 127 v cca ipower analog power supply (3.3 v). 2, 3, 5, 7, 9, 12, 20, 24, 29, 34, 35, 48, 51, 54, 63, 70, 80, 90, 104, 107 v ccd ipower digital power supply (3.3 v). 1, 4, 13, 16, 19, 25, 28, 31, 32, 3739, 55, 58, 64, 65, 75, 85, 95, 100103, 117124, 128 gnd i ground ground. 36, 45, 115, 116, 125 nc no connection. pin 45 has an internal pull-up resistance of approximately 25 k w . all of these pins must be left open.
preliminary data sheet TTRN012G5 and ttrn012g7 august 2000 clock synthesizer, 16:1 data multiplexer 9 lucent technologies inc. functional overview the lucent technologies microelectronics group TTRN012G5 operates at the oc-48/stm-16 data rate of 2.5 gbits/s.* the ttrn012g7 device operates at either 2.5 gbits/s or the rs fec oc-48/stm-16 data rate of 2.7 gbits/s. the device performs the clock synthesis and 16:1 data multiplexing operations required to support 2.5 gbits/s applications compliant with telcordia technologies and itu standards. parallel 155 mbits/s data is clocked into an input register and checked for valid parity. both clockless data transfer and contra-directional clock- ing modes are supported. the data is then multiplexed into a 2.5 gbits/s serial stream and output buffered for inter- facing to a laser driver. a 2.5 ghz clock is synthesized from a reference clock and is used to retime the serial data. the 2.5 ghz clock is optionally available as an output. the serial data stream polarity can be inverted under pin control to make interfacing easier. clock synthesizer operation the clock synthesizer uses a pll to synthesize a 2.5 ghz clock from a reference frequency. a 155 mhz clock derived from the 2.5 ghz synthesized clock may be used to clock in the parallel data. clock synthesizer loop filter a typical loop filter that provides adequate damping for less than 0.1 db of jitter peaking is shown in figure 3. con- nect the filter components and also connect lfp to vcp and connect lfn to vcn. the component values can be varied to adjust the loop dynamic response (see table 5). table 5. clock synthesizer loop filter component values * capacitor c1 should be either ceramic or nonpolar. 5-8061(f) figure 3. clock synthesizer loop filter components clock synthesizer settling time the clock synthesizer will acquire phase/frequency lock after a valid reference clock is applied to the refclkp/n input pins. the actual time to acquire lock is a function of the loop bandwidth selected. the loop will acquire lock within 5 ms when using the external loop bandwidth components corresponding to 2 mhz. loss of lock indicator (lcklossn) the lcklossn pin indicates (active-low) when the clock synthesizer has exceeded phase-lock limits with the incoming refclkp/n phase. the lock detect function compares the phases of the input 155 mhz clock at the refclkp/n pins with the internally generated 155 mhz output clock at the ck155p/n pins. when the phase dif- ference in the two signals is close to zero as determined by a second internal phase detector and filter, the lock detect signal lcklossn is set to the logic high state. when the phase difference between the two signals is changing with time at a rate exceeding the filter's cutoff frequency, the device is declared out of lock and lock detect signal lcklossn is set to a logic low. if a set of highly damped phase-locked loop parameters is chosen for the device, lcklossn may exhibit more than one positive edge transition during the acquisition process before a steady logic high state is achieved. * the oc-48/stm-16 data rate of 2.48832 gbits/s is typically approximated as 2.5 gbits/s in this document when referring to the application rate. the rs fec oc-48/stm-16 data rate is 2.66606 gbits/s and is approximated as 2.7 gbits/s in this document. similarly, the oc-3/ stm-1 data rate of 155.52 mbits/s is typically approximated as 155 mbits/s, and the rs fec oc-3/stm-1 data rate of 166.62 mbits /s is approximated as 166 mbits/s. the exact frequencies are used only when necessary for clarity. components values for 2 mhz loop bandwidth c1* 0.10 m f 10% c2, c3 10 pf 20% r1 680 w 5% c 3 c 2 c 1 r 1 lfn/vcn lfp/vcp
TTRN012G5 and ttrn012g7 preliminary data sheet clock synthesizer, 16:1 data multiplexer august 2000 10 lucent technologies inc. functional overview (continued) clock synthesizer operation (continued) clock synthesizer generated jitter the clock synthesizers generated jitter performance meets the requirements shown in table 6. these specifica- tions apply to the jitter generated at the 2.5 ghz clock pins (ck2g5p/n) when the jitter on the reference clock (refclkp/n) is within the specifications given in table 9 on page 16, and the loop filter components are chosen to provide a loop bandwidth of 2 mhz. table 6. clock synthesizer generated jitter specifications * this denotes the device specification for system sonet/sdh compliance when the loop filter in table 5 and figure 3 is used. clock synthesizer jitter transfer the clock synthesizers jitter transfer performance meets the requirement shown in figure 4 when the loop filter values shown in table 5 are used. 5-8062(f)r.1 figure 4. clock synthesizer jitter transfer parameter typical max (device) * unit generated jitter (p-p): measured with 12 khz to 20 mhz bandpass filter 0.02 0.09 uip-p generated jitter (rms): measured with 12 khz to 20 mhz bandpass filter 0.002 0.009 uirms 60 40 20 0 1k 10k 100k 1m 10m 50 30 10 100m frequency (hz) jitter out/jitter in (db) (2 mhz, 0.1 db)
preliminary data sheet TTRN012G5 and ttrn012g7 august 2000 clock synthesizer, 16:1 data multiplexer 11 lucent technologies inc. functional overview (continued) multiplexer operation the parallel 155 mbits/s data is clocked into an input buffer by a 155 mhz clock derived from the synthesized 2.5 ghz clock. the data is checked for parity and then clocked into a 16:1 multiplexer. the relationship between the parallel d[15:0] input data and the serial output data (d2g5p/n) is given in figure 5. the d15 bit is the most significant bit (msb) and is shifted out first in time in the serial output stream. 5-8063(f) figure 5. parallel input to serial output data relationship high-speed serial clock output enable (enck2g5) a separate output enable is provided for the 2.5 ghz clock output (ck2g5p/n). the enable is an active-high cmos input with an internal pull-up resistor. the default condition will enable the ck2g5p/n output, and applying a ground or setting the enable pin (enck2g5) to logic low will disable the ck2g5p/n output. when disabled, the ck2g5p/n output pins should be either left floating, or be connected to a load which returns to v cc . the output must not be connected directly to ground when it is disabled. loopback 2.5 ghz data output (lbdp/n, enlbdn) an alternate 2.5 gbits/s cml data output is available on the lbdp/n pin. this pin is provided for use in system loopback testing and avoids the need for off-chip signal splitting of the data signal path. the alternate 2.5 gbits/s loopback data output may be enabled by setting the enlbdn pin to logic low. enlbdn enable is an active-low cmos input with an internal pull-up resistor so the default condition will disable the lbdp/n output, and a ground or logic-low signal must be applied to enable the loopback output. when disabled, the lbdp/n pin should be either left floating, or be connected to a load which returns to v cc . the output must not be connected directly to ground when it is disabled. parity validation (validp/n) the parity signal is expected to be a logic 0 when the number of 1s in the 16-bit input register is an even number, and the parity signal is expected to be a logic 1 when the number of 1s in the input register is an odd number. if the parity bit agrees with the parity in the input register, then the validp/n signal will be logic high. if the parity signal is not generated, the validp/n pin should be left open without termination to avoid meaningless signal swings and avoid unnecessary power dissipation. d15 d14 d1 d0 d15 time (d15 serially shifted out first) (d0 serially shifted out last) (msb) (lsb)
TTRN012G5 and ttrn012g7 preliminary data sheet clock synthesizer, 16:1 data multiplexer august 2000 12 lucent technologies inc. clocking modes and timing adjustments clockless transfer mode (clkmode, extadjn, monapap/n) the device supports two timing modes for the 155 mbits/s data input. in clockless transfer mode (clkmode = 0), data may be sent to the device without a clock. after phase/frequency lock has been obtained by the clock synthesizer, the device automatically finds the correct phase of the internal 155 mhz clock by sampling the rising edge of the d0p/n data bit. the skew of any data bit d[15:0]p/n must be less than 500 ps relative to d0p/n. if the phase of the incoming data shifts more than 2400 ps from the time the automatic phase adjustment occurred, the device will automatically readjust its internal clocking phase. data integrity may not be obtained at the instant of phase adjustment, and an error burst of up to 16 data bits may occur. the user may optionally force the automatic phase adjustment to occur by toggling the extadjn pin (active-low) and keeping it low for at least 12.8 ns after the next rising edge of the d0p/n input. the phase will be adjusted one time upon the first occurrence of a low-to-high transition of the d0p/n data bit while the extadjn pin is in the logic-low state. to externally adjust the phase again, the resetn pin must be brought low then high to enable another phase adjustment. when clkmode = 0, the 155 mhz output clock (ck155p/n) is active but should be left unconnected to conserve power. monapap/n can be used for the monitoring and reporting of phase adjustments. the monapap/n output will go high in the following sequence: n extadjn pin transitions to logic-low state n a rising edge of the d0p/n input occurs n monapap/n transitions to logic 1 three ck2g5 cycles (1.2 ns) later n monapap/n will stay high for 12 ck2g5 cycles (4.8 ns) the first sixteen d2g5 data output bits after the rising edge of monapap/n are invalid.
preliminary data sheet TTRN012G5 and ttrn012g7 august 2000 clock synthesizer, 16:1 data multiplexer 13 lucent technologies inc. clocking modes and timing adjustments (continued) contra-directional clocking mode (clkmode, phadj[1:0]) in the contra-directional clocking mode (clkmode = 1), the data is sampled with the internal 2.5 ghz clock at the time of the falling edge of ck155p (see figure 8 on page 19 for timing details). the device sends a 155 mhz clock with one of four user-selectable phases out to the upstream device for clocking the data toward the device. the user can program phadj[1:0] to adjust the phase of ck155 as a function of pwb layout and upstream device propagation delay in order to meet the setup and hold time of the 155 mbits/s data to the device. with a phadj[1:0] = [11], the data is sampled by the internal ck2g5 clock at the falling edge of ck155p. phadj[1:0] changes the phase of the ck155p clock without changing the input data sampling time. phadj[1:0] setting infor- mation is given in table 7, and the phase relationship of ck155 for each phadj[1:0] setting is shown in figure 6. table 7. phadj settings for ck155 output clock (contra-clocking mode) 5-8064(f)r.2 figure 6. ck155 phase relation vs. phadj setting input pins phase phadj1 phadj0 1 1 (see part a of figure 6.) 1 0 (see part b of figure 6.) 0 1 (see part c of figure 6.) 0 0 (see part d of figure 6.) a. (0 deg.) b. (C90 deg.) c. (C180 deg.) d. (C270 deg.) time
TTRN012G5 and ttrn012g7 preliminary data sheet clock synthesizer, 16:1 data multiplexer august 2000 14 lucent technologies inc. cml output structure (used on pins d2g5p/n, ck2g5p/n) the cml architecture is essentially a current-steering mechanism combined with an amplifier. this makes the out- put swing of the signal a function of the termination resistor and the programmable output current. the user should connect external termination resistors from the cml output pins to v cc . the on-chip, 100 w pull-up resistors pro- vide a dc path when using an ac-coupled load. the voltage swing of a cml signal is typically 400 mv, half that of ecl/pecl. the lower pulse amplitude reduces noise transients, crosstalk, and emi. it also uses half the amount of current through the termination resistors. the schematic of a typical cml output structure is shown in figure 7. 5-8065(f)r.2 figure 7. typical cml output structure choosing the value of the external cml reference resistors (rref1, rref2) the flexibility of the cml interface permits certain parameters to be customized for a particular application. the rref1 resistor controls the cml output driver current source. adjusting this tail current and termination resistors will allow signal amplitude control (see the cml output specifications for limitations, page 18 and page 20) and flexibility in termination schemes. with rref2 set to 1.5 k w , the equation for the cml output current is the following: iout = (18)*(1.21)/rref1 the cml outputs have on-chip 100 w load resistors to v cc to accommodate capacitive ac coupling. with a 50 w 1% load, the effective load resistance will be 33.33 w 6%. for a 400 mv voltage swing into the 50 w load, set rref1 to 1.8 k w . for a 600 mv voltage swing, set rref1 to 1.2 k w . in both cases, rref2 remains fixed at a value of 1.5 k w. device-internal cml output buffer circuit external output termination v cc v cc 50 w 50 w v cc v cc 100 w 100 w vref 18x v cc rref1 rref2 + C i out i out
preliminary data sheet TTRN012G5 and ttrn012g7 august 2000 clock synthesizer, 16:1 data multiplexer 15 lucent technologies inc. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used in the defined model. no industrywide standard has been adopted for the cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes: operating conditions table 8. recommended operating conditions parameter min max unit power supply voltage (v cc ) 4.0 v storage temperature C40 125 c pin voltage gnd C 0.5 v cc + 0.5 v device voltage TTRN012G5 3 200 v ttrn012g7 3 200 v parameter symbol min typ max unit power supply (dc voltage) 3.135 3.3 3.465 v ground v input voltage: low high v il v ih see table 10, table 12, table 14. see table 10, table 12, table 14. see table 10, table 12, table 14. v v temperature: ambient t a C40 85 c power dissipation: mbic 025 bicmos mbic 025 sige bicmos p d p d 1.5 0.9 tbd 1.14 w w
TTRN012G5 and ttrn012g7 preliminary data sheet clock synthesizer, 16:1 data multiplexer august 2000 16 lucent technologies inc. electrical characteristics reference frequency (refclkp/n) specifications the device requires a differential lvpecl reference clock input. n when using the TTRN012G5 device, a 155.52 mhz differential lvpecl clock must be applied to the refclkp/n input. n when using the ttrn012g7 device at the oc-48/stm-16 rate, a 155.52 mhz differential lvpecl clock must be applied to the refclkp/n input. n when using the ttrn012g7 device at the rs fec oc-48/stm-16 rate, a 166.62 mhz differential lvpecl clock must be applied to the refclkp/n input. table 9 provides the characteristics of the refclkp/n input. table 9. reference frequency characteristics * includes effects of power supply variation, temperature, electrical loading, and aging. the 20 ppm tolerance is required to meet sonet/sdh requirements. for non-sonet/sdh compliant systems, looser tolerances may apply. ? measured under one 3.3 v lvpecl load. includes frequency components up to 2 mhz. ? specified range is to be compatible with environmental specification of TTRN012G5 or ttrn012g7. applications requiring a reduced temperature range may specify the reference frequency oscillator accordingly. parameter min typ max unit reference frequency (refclkp/n) 155.52 mhz 166.62 mhz reference frequency tolerance* C20 20 ppm duty cycle 40 60 % phase jitter ? 3 ps(rms) temperature ? C40 85 c supply voltage ? 3.10 3.60 v
preliminary data sheet TTRN012G5 and ttrn012g7 august 2000 clock synthesizer, 16:1 data multiplexer 17 lucent technologies inc. electrical characteristics (continued) lvpecl, cmos, cml input and output pins notes: 1. for table 10 through table 17, v cc = 3.3 v 5%, t a = C40 c to +85 c; these tables apply to both mbic 025 bicmos and mbic 025 sige bicmos technologies. 2. for more information on interpreting cml specifications, see the cml output structure (used on pins d2g5p/n, ck2g5p/n) section on page 14. table 10. lvpecl input pin characteristics table 11. lvpecl output pin characteristics table 12. cmos input pin characteristics table 13. cmos output pin characteristics applicable pins symbol parameter conditions min typ max unit d[15:0]p/n, parityp/n, refclkp/n v ih input voltage high referred to v cc C1165 C880 mv v il input voltage low referred to v cc C1810 C1475 mv i ih input current high leakage v in = v ih (max) 20 m a i il input current low leakage v in = v il (min) 5 m a applicable pins symbol parameter conditions min typ max unit ck155p/n, validp/n, monapap/n v oh output voltage high load = 50 w connected to v cc C 2.0 v v cc C 1.31 v cc C 1.20 v cc C 0.90 v v ol output voltage low load = 50 w connected to v cc C 2.0 v v cc C 1.95 v cc C 1.88 v cc C 1.80 v applicable pins symbol parameter conditions min max unit resetn, phadj[1:0], extadjn, invdatn, testn, clkmode, enck2g5, enlbdn v ih input voltage high v cc C 1.0 v cc v v il input voltage low gnd 1.0 v i ih input current high leakage v in = v cc 10 m a i il input current low leakage v in = gnd C225 m a applicable pins symbol parameter conditions min max unit lcklossn v oh output voltage high i oh = C4.0 ma v cc C 0.5 v cc v v ol output voltage low i ol = 4.0 ma gnd 0.5 v c l output load capacitance 15 pf
TTRN012G5 and ttrn012g7 preliminary data sheet clock synthesizer, 16:1 data multiplexer august 2000 18 lucent technologies inc. electrical characteristics (continued) lvpecl, cmos, cml input and output pins (continued) table 14. cml input pin dc characteristics table 15. cml output pin dc characteristics * applies when rref1 = 1 k w. ? applies when rref1 = 1.8 k w. ? applies when rref1 = 6 k w. applicable pins symbol parameter conditions min typ max unit tstckp/n v il input voltage low v cc C 0.4 v v ih input voltage high v cc v applicable pins symbol parameter conditions min * typ ? max ? unit d2g5p/n, lbdp/n, ck2g5p/n v ol output voltage low rref2 = 1.5 k w, r l = 50 w, all signals differential v cc C 1.2 v cc C 0.4 v v oh output voltage high v cc v cc + 0.3 v i ol output current low 3.6 12 18 ma i oh output current high 0 1 m a
preliminary data sheet TTRN012G5 and ttrn012g7 august 2000 clock synthesizer, 16:1 data multiplexer 19 lucent technologies inc. timing characteristics transmit timing figure 8 shows the timing relationships between the 155.52 mhz or 166.62 mhz output clock (ck155p/n) and the 155.52 mbits/s or 166.62 mbits/s input data (d[15:0]p/n) and the input parity valid check (parityp/n). also shown is the relationship of the validp/n output signal to ck155p/n; this relationship is true for both the contra- clocking mode and the clockless transfer mode. 5-7726(f).hr.2 note: t su and t hold only apply in contra-clocking mode when clkmode = 1. figure 8. transmit timing waveform the 155 mhz or 166 mhz output clock and data signals from figure 8 are characterized in table 16. table 16. lvpecl input/output pin ac timing characteristics applicable pins symbol parameter conditions min typ max unit ck155p/n duty cycle all signals differential 40 50 60 % t period 155.52 mhz clock period 6.43 ns 166.62 mhz clock period 6.00 ns input timing d[15:0]p/n, parityp/n, ck155p/n t su setup from clock edge to d[15:0]p/n or to parityp/n edge clkmode = 1, all signals differential 2.0 ns t hold hold from clock edge to d[15:0]p/n or to parityp/n edge clkmode = 1, all signals differential 0.5 ns t rise , t fall rise, fall times: 20%80% all signals differential 200 500 800 ps t skew transition skew rise to fall C100 0 100 ps output timing validp/n, ck155p/n t dd time delay from clock edge to validp/n edge all signals differential C300 800 1500 ps t rise , t fall rise, fall times: 20%80% 200 500 800 ps t skew transition skew rise to fall C100 0 100 ps output ck155p ck155n inputs d[15:0]p/n, parityp/n t su data 1 t period data 2 t hold output validp/n valid 1 valid 2 t dd
TTRN012G5 and ttrn012g7 preliminary data sheet clock synthesizer, 16:1 data multiplexer august 2000 20 lucent technologies inc. timing characteristics (continued) transmit timing (continued) figure 9 shows the timing relationship between the 2.5 ghz or 2.7 ghz output clock (ck2g5p/n) and the 2.5 gbits/s or 2.7 gbits/s output data (d2g5p/n). 5-7726(f).er.4 figure 9. transmit timing waveform with 2.5 ghz or 2.7 ghz clock the 2.5 ghz or 2.7 ghz output clock and data signals from figure 9 are characterized in table 17. table 17. cml output pin ac timing characteristics applicable pins symbol parameter conditions min typ max unit ck2g5p/n duty cycle rref1 = 1.8 k w rref2 = 1.5 k w r l = 50 w all signals differential 40 50 60 % t period 2.48832 ghz clock period 402 ps 2.66606 ghz clock period 375 ps d2g5p/n, ck2g5p/n, lbdp/n t dd time delay from clock edge to data edge 151 201 251 ps t rise , t fall rise, fall times: 20%80% 50 80 120 ps t skew transition skew rise to fall C10 0 10 ps output ck2g5p ck2g5n output d2g5p/n data 1 t period data 2 data 3 t dd
preliminary data sheet TTRN012G5 and ttrn012g7 august 2000 clock synthesizer, 16:1 data multiplexer 21 lucent technologies inc. outline diagram 128-pin qfp dimensions are in millimeters. 5-8416(f)r.2 3.30 (ref) 0.50 (typ) 2.80 (ref) 1 38 65 102 103 128 17.20 0.20 19.86 0.10 64 39 0.800 0.150 1.600 0.150 detail a 1 lucent code name yywwl xxxxxknv 0.38 (ref) detail a 11.43 0.18 23.20 0.20 13.89 0.10 8.13 (ref) 2.89 (ref) 17.52 0.18 8.13 (ref) 0.20 0.06 0.000 to 0.100 8.13 (ref) 2.89 (ref) (8.13) 2 x 0.305 heat sink 5.87 (ref)
TTRN012G5 and ttrn012g7 preliminary data sheet clock synthesizer, 16:1 data multiplexer august 2000 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 2000 lucent technologies inc. all rights reserved august 2000 ds00-375hspl (replaces ds00-155hspl) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 3507670 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) ordering information ds00-375hspl replaces ds00-155hspl to incorporate the following updates 1. added a second technolo gy , mbic 025 sige bicmos, to the data sheet. 2. pa g e 7, refclkp/n pins, corrected definition. 3. pa g e 15, absolute maximum ratin g s, added maximum power suppl y value of 4.0 v. 4. pa g e 15, handlin g precautions, corrected esd threshold value from tbd to 3 200 v. 5. pa g e 15, table 8, added mbic 025 sige bicmos power dissipation values. 6. pa g e 17, table 11, updated lvpecl output pin characteristics. 7. pa g e 22, orderin g information, added mbic 025 sige bicmos comcodes. device code package temperature comcode (ordering number) TTRN012G5: TTRN012G5 ( bicmos ) TTRN012G53xe1 ( sige bicmos ) 128-pin qfp 128-pin qfp C40 c to +85 c C40 c to +85 c 108419961 108700709 ttrn012g7: ttrn012g7 ( bicmos ) ttrn012g73xe1 ( sige bicmos ) 128-pin qfp 128-pin qfp C40 c to +85 c C40 c to +85 c 108560335 108700717

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