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preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 1 - rev 0.1 aug. 1998 km718v949 document title 256kx36 & 512kx18-bit pipelined n t ram tm the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to c hange the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters. revision history rev. no. 0.0 0.1 remark preliminary preliminary history 1. initial document. 1. changed dc parameters i cc ; from 450ma to 420ma at 150mhz. i sb1 ; from 10ma to 20ma, i sb2 ; from 10ma to 20ma. draft date june. 09. 1998 aug. 19. 1998
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 2 - rev 0.1 aug. 1998 km718v949 256kx36 & 512kx18-bit n t ram tm the KM736V849 and km718v949 are 9,437,184 bits synchro- nous static srams. the n t ram tm , or no turnaround random access memory uti- lizes all the bandwidth in any combination of operating cycles. address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. burst order control must be tied "high or low". asynchronous inputs include the sleep mode enable(zz). output enable controls the outputs at any given time. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incomming signals. for read cycles, pipelined sram output data is temporarily stored by an edge trigered output register and then released to the output bufferes at the next rising edge of clock. the KM736V849 and km718v949 are implemented with sam- sung s high performance cmos technology and is available in 100pin tqfp packages. multiple power and ground pins minimize ground bounce. general description features logic block diagram ? 3.3v+0.165v/-0.165v power supply. ? i/o supply voltage 3.3v+0.165v/-0.165v for 3.3v i/o or 2.5v+0.4v/-0.125v for 2.5v i/o. ? byte writable function. ? enable clock and suspend operation. ? single read/write control pin. ? self-timed write cycle. ? three chip enable for simple depth expansion with no data contention ? a interleaved burst or a linear burst mode. ? asynchronous output enable control. ? power down mode. fast access times parameter symbol -67 -75 -10 unit cycle time t cyc 6.7 7.5 10 ns clock access time t cd 3.8 4.0 5.0 ns output enable access time t oe 3.8 4.0 5.0 ns we bw x clk cke cs 1 cs 2 cs 2 adv oe zz dqa 0 ~ dqd 7 or dqa 0 ~ dqb 8 address address register c o n t r o l l o g i c a 0 ~a 1 36 or 18 dqpa ~ dqpd output buffer register data-in register data-in register k k k register burst address counter write address register write control logic c o n t r o l r e g i s t e r k a [0:17]or a [0:18] lbo a 2 ~a 17 or a 2 ~a 18 a 0 ~a 1 (x=a,b,c,d or a,b) 256kx36/512kx18 memory array n t ram tm and no turnaround ram are trademarks of samsung electronics co.,ltd.
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 3 - rev 0.1 aug. 1998 km718v949 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 pin tqfp (20mm x 14mm) dqpc dqc 0 dqc 1 v ddq v ssq dqc 2 dqc 3 dqc 4 dqc 5 v ssq v ddq dqc 6 dqc 7 v dd v dd v dd v ss dqd 0 dqd 1 v ddq v ssq dqd 2 dqd 3 dqd 4 dqd 5 v ssq v ddq dqd 6 dqd 7 dqpd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqpb dqb 7 dqb 6 v ddq v ssq dqb 5 dqb 4 dqb 3 dqb 2 v ssq v ddq dqb 1 dqb 0 v ss v dd v dd zz dqa 7 dqa 6 v ddq v ssq dqa 5 dqa 4 dqa 3 dqa 2 v ssq v ddq dqa 1 dqa 0 dqpa 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 a 6 a 7 c s 1 c s 2 b w d b w c b w b b w a c s 2 v d d v s s c l k w e c k e o e a d v n . c . a 1 7 a 8 8 1 a 9 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 n . c . n . c . v d d v s s n . c . n . c . a 0 a 1 a 2 a 3 a 4 a 5 3 1 l b o pin name symbol pin name tqfp pin no. symbol pin name tqfp pin no. a 0 - a 17 adv we clk cke cs 1 cs 2 cs 2 bw x oe zz lbo address inputs address advance/load read/write control input clock clock enable chip select chip select chip select byte write inputs output enable power sleep mode burst mode control 32,33,34,35,36,37, 44,45,46,47,48,49, 50,81,82,83,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 v dd v ss n.c. dqa 0 ~a 7 dqb 0 ~b 7 dqc 0 ~c 7 dqd 0 ~d 7 dqpa~p d v ddq v ssq power supply(+3.3v) ground no connect data inputs/outputs output power supply (3.3v or 2.5v) output ground 14,15,16,41,65,66,91 17,40,67,90 38,39,42,43,84 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 KM736V849(256kx36)
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 4 - rev 0.1 aug. 1998 km718v949 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 pin tqfp (20mm x 14mm) n.c. n.c. n.c. v ddq v ssq n.c. n.c. dqb 8 dqb 7 v ssq v ddq dqb 6 dqb 5 v dd v dd v dd v ss dqb 4 dqb 3 v ddq v ssq dqb 2 dqb 1 dqb 0 n.c. v ssq v ddq n.c. n.c. n.c. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a 18 n.c. n.c. v ddq v ssq n.c. dqa 0 dqa 1 dqa 2 v ssq v ddq dqa 3 dqa 4 v ss v dd v dd zz dqa 5 dqa 6 v ddq v ssq dqa 7 dqa 8 n.c. n.c. v ssq v ddq n.c. n.c. n.c. 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 a 6 a 7 c s 1 c s 2 b w b b w a c s 2 v d d v s s c l k w e c k e o e a d v n . c . a 1 7 a 8 8 1 a 9 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 a 1 6 a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 n . c . n . c . v d d v s s n . c . n . c . a 0 a 1 a 2 a 3 a 4 a 5 3 1 l b o km718v949(512kx18) n . c . n . c . pin name symbol pin name tqfp pin no. symbol pin name tqfp pin no. a 0 - a 18 adv we clk cke cs 1 cs 2 cs 2 bw x oe zz lbo address inputs address advance/load read/write control input clock clock enable chip select chip select chip select byte write inputs output enable power sleep mode burst mode control 32,33,34,35,36,37, 44,45,46,47,48,49,50, 80,81,82,83,99,100 85 88 89 87 98 97 92 93,94 86 64 31 v dd v ss n.c. dqa 0 ~a 8 dqb 0 ~b 8 v ddq v ssq power supply(+3.3v) ground no connect data inputs/outputs output power supply (3.3v or 2.5v) output ground 14,15,16,41,65,66,91 17,40,67,90 1,2,3,6,7,25,28,29,30, 38,39,42,43,51,52,53, 56,57,75,78,79,84,95,96 8,9,12,13,18,19,22,23,24 58,59,62,63,68,69,72,73, 74 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 5 - rev 0.1 aug. 1998 km718v949 function description the KM736V849 and km718v949 are n t ram tm designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, or vice versa. all inputs (with the exception of oe , lbo and zz) are synchronized to rising clock edges. all read, write and deselect cycles are initiated by the adv input. subsequent burst addresses can be internally generated as co n- trolled by the burst advance pin (adv). adv should be driven to low once the device has been deselected in order to load a new address for next operation. clock enable( cke ) pin allows the operation of the chip to be suspended as long as necessary. all synchronous inputs are ignored when cke is high and the internal device registers will hold their previous values. when cke is active asserted, adv is disasserted and all three chip enables( cs 1 , cs 2 , cs 2 ) are asserted, n t ram tm latches external address and initiates a cycle. output enable( oe ) can be used to disable the output at any given time. read operation is initiated when the following conditions are satisfied at the rising edge of clock, cke is asserted low, all three chip enables( cs 1 , cs 2 , cs 2 ) are active, the write enable input signals we is deasserted high, and adv is asserted low. the address presented to the address inputs are latched in to address register and presented to the memory core and control logic. the contr ol logic determines that a read access is in progress and allows the requested data a propagate to the input of the output register . at the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus w ithin provided oe is active low. write operation occurs when we is sampled low at the rising edge of clock. bw [d:a] can be used for byte write operation. the pipe- lined n t ram tm uses a late-late write cycle to utilize 100% of the bandwidth. at the first rising edge of clock, we and address are registered, and the data associated with that address is required two cycles later. subsequent addresses are generated by adv high for the burst access as shown below. the starting point of the burst sequence is provided by the external address. the burst address counter wraps around to its initial state upon completion. the burst sequence is determined by the state of the lbo pin. when this pin is low, linear burst sequence is selected. and this pin is high, interleaved burst sequence is selected. during normal operation, zz must be pulled low. when zz is pulled high, the sram will enter a power sleep mode after 2 cycles. at this time, internal state of the sram is preserved. when zz returns to low, the sram normally operates after 2 cycles of wake up time. burst sequence table (interleaved burst, lbo =high) lbo pin high case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 bq table (linear burst, lbo =low) note : 1. lbo pin must be tied to high or low, and floating state must not be allowed . lbo pin low case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 6 - rev 0.1 aug. 1998 km718v949 state diagram for n t ram tm begin write burst write begin read write d s r e a d burst read d s w r i t e d s read d s r e a d d s w r i t e b u r s t deselect b u r s t r e a d b u r s t w r i t e read write burst burst command action ds deselect read begin read write begin write burst begin read begin write continue deselect note 1. an ignore clock edge cycle is not shown is the above diagram. this is because cke high only blocks the clock(clk) input and does not change the state of the device. 2. states change on the rising edge of the clock(clk)
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 7 - rev 0.1 aug. 1998 km718v949 synchronous truth table note : 1. x means "don t care". 2. the rising edge of clock is symbolized by ( - ). 3. a continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. write = l means write operation in write truth table. write = h means read operation in write truth table. 5. operation finally depends on status of asynchronous input pins(zz and oe ). cs 1 cs 2 cs 2 adv we bw x oe cke clk address accessed operation h x x l x x x l - n/a not selected x l x l x x x l - n/a not selected x x h l x x x l - n/a not selected x x x h x x x l - n/a not selected continue l h l l h x l l - external address begin burst read cycle x x x h x x l l - next address continue burst read cycle l h l l h x h l - external address nop/dummy read x x x h x x h l - next address dummy read l h l l l l x l - external address begin burst write cycle x x x h x l x l - next address continue burst write cycle l h l l l h x l - n/a nop/write abort x x x h x h x l - next address write abort x x x x x x x h - current address ignore clock write truth table (x36) we bw a bw b bw c bw d operation h x x x x read l l h h h write byte a l h l h h write byte b l h h l h write byte c l h h h l write byte d l l l l l write all bytes l h h h h write abort/nop truth tables write truth table (x18) note : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( - ). we bw a bw b operation h x x read l l h write byte a l h l write byte b l l l write all bytes l h h write abort/nop
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 8 - rev 0.1 aug. 1998 km718v949 asynchronous truth table (see notes 1 and 2) : operation zz oe i/o status sleep mode h x high-z read l l dq l h high-z write l x din, high-z deselected l x high-z note 1. x means "don t care". 2. for write cycles that following read cycles, the output buffers must be disabled with oe , otherwise data bus contention will be occur. 3. sleep mode means power sleep mode of which stand-by current does not depend on cycle time. 4. deselected means power sleep mode of which stand-by current depends on cycle time. absolute maximum ratings* *note : stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on v dd supply relative to v ss v dd -0.3 to 4.6 v voltage on any other pin relative to v ss v in -0.3 to 4.6 v power dissipation p d 1.6 w storage temperature t stg -65 to 150 c operating temperature t opr 0 to 70 c storage temperature range under bias t bias -10 to 85 c operating conditions at 3.3v i/o (0 c t a 70 c) parameter symbol min typ. max unit supply voltage v dd 3.135 3.3 3.465 v v ddq 3.135 3.3 3.465 v ground v ss 0 0 0 v capacitance* (t a =25 c, f=1mhz) *note : sampled not 100% tested. parameter symbol test condition min max unit input capacitance c in v in =0v - 6 pf output capacitance c out v out =0v - 8 pf operating conditions at 2.5v i/o (0 c t a 70 c) parameter symbol min typ. max unit supply voltage v dd 3.135 3.3 3.465 v v ddq 2.375 2.5 2.9 v ground v ss 0 0 0 v
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 9 - rev 0.1 aug. 1998 km718v949 dc electrical characteristics (v dd =3.3v+0.165v/-0.165v , t a =0 c to +70 c) * v il (min)=-2.0(pulse width t cyc / 2) ** v ih (max)=4.6(pulse width t cyc / 2) ** in case of i/o pins, the max. v ih =v ddq +0.5v parameter symbol test conditions min max unit input leakage current i il v dd =max ; v in =v ss to v dd -2 +2 m a output leakage current i ol output disabled, -2 +2 m a operating current i cc v dd =max i out =-0ma cycle time 3 t cyc min -67 - 420 ma -75 - 370 -10 - 300 standby current i sb device deselected, i out =0ma, zz v il , f=max, all inputs 0.2v or 3 v dd -0.2v -67 - 80 ma -75 - 70 -10 - 60 i sb1 device deselected, i out =0ma, zz 0.2v, f=0, all inputs=fixed (v dd -0.2v or 0.2v) - 20 ma i sb2 device deselected, i out =0ma, zz 3 v dd -0.2v, f=max, all inputs v il or 3 v ih - 20 ma output low voltage(3.3v i/o) v ol i ol =8.0ma - 0.4 v output high voltage(3.3v i/o) v oh i oh =-4.0ma 2.4 - v output low voltage(2.5v i/o) v ol i ol =1.0ma - 0.2 v output high voltage(2.5v i/o) v oh i oh =-1.0ma 2.0 - v input low voltage(3.3v i/o) v il -0.3* 0.8 v input high voltage(3.3v i/o) v ih 2.0 v dd +0.5** v input low voltage(2.5v i/o) v il -0.3* 0.7 v input high voltage(2.5v i/o) v ih 1.7 v dd +0.5** v (v dd =3.3v+0.165v/-0.165v , v ddq =3.3v+0.165/-0.165v or v dd =3.3v+0.165v/-0.165v , v ddq =2.5v+0.4v/-0.125v, t a =0to70 c) test conditions parameter value input pulse level(for 3.3v i/o) 0 to 3.0v input pulse level(for 2.5v i/o) 0 to 2.5v input rise and fall time(measured at 20% to 80% for 3.3v i/o) 1.0v/ns input rise and fall time(measured at 20% to 80% for 2.5v i/o) 1.0v/ns input and output timing reference levels for 3.3v i/o 1.5v input and output timing reference levels for 2.5v i/o v ddq /2 output load see fig. 1
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 10 - rev 0.1 aug. 1998 km718v949 ac timing characteristics note : 1. all address inputs must meet the specified setup and hold times for all rising clock(clk) edges when adv is sampled low an d cs is sampled low. all other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. chip selects must be valid at each rising edge of clk(when adv is low) to remain enabled. 3. a write cycle is defined by we low having been registered into the device at adv low, a read cycle is defined by we high with adv low, both cases must meet setup and hold times. 4. to avoid bus contention, at a given voltage and temperature t clz is more than t hzc. the specs as shown do not imply bus contention because t clz is a min. parameter that is worst case at totally different test conditions (0 c,3.465v) than t chz , which is a max. parameter(worst case at 70 c,3.135v) it is not possible for two srams on the same board to be at such different voltage and temperature. 5. adv must not be asserted for at least 2 clocks after leaving zz state. parameter symbol -67 -75 -10 unit min max min max min max cycle time t cyc 6.7 - 7.5 - 10.0 - ns clock access time t cd - 3.8 - 4.0 - 5.0 ns output enable to data valid t oe - 3.8 - 4.0 - 5.0 ns clock high to output low-z t lzc 1.5 - 1.5 - 1.5 - ns output hold from clock high t oh 1.5 - 1.5 - 1.5 - ns output enable low to output low-z t lzoe 0 - 0 - 0 - ns output enable high to output high-z t hzoe - 3.0 - 3.5 - 3.5 ns clock high to output high-z t hzc - 3.0 - 3.5 - 3.5 ns clock high pulse width t ch 2.5 - 3.0 - 3.0 - ns clock low pulse width t cl 2.5 - 3.0 - 3.0 - ns address setup to clock high t as 1.5 - 1.5 - 1.5 - ns cke setup to clock high t ces 1.5 - 1.5 - 1.5 - ns data setup to clock high t ds 1.5 - 1.5 - 1.5 - ns write setup to clock high ( we , bw x ) t ws 1.5 - 1.5 - 1.5 - ns address advance setup to clock high t advs 1.5 - 1.5 - 1.5 - ns chip select setup to clock high t css 1.5 - 1.5 - 1.5 - ns address hold from clock high t ah 0.5 - 0.5 - 0.5 - ns cke hold from clock high t ceh 0.5 - 0.5 - 0.5 - ns data hold from clock high t dh 0.5 - 0.5 - 0.5 - ns write hold from clock high ( we , bwe x ) t wh 0.5 - 0.5 - 0.5 - ns address advance hold from clock high t advh 0.5 - 0.5 - 0.5 - ns chip select hold from clock high t csh 0.5 - 0.5 - 0.5 - ns zz high to power down t pds 2 - 2 - 2 - cycle zz low to power up t pus 2 - 2 - 2 - cycle (v dd =3.3v+0.165v/-0.165v, t a =0 to 70 c) output load(b), (for t lzc , t lzoe , t hzoe & t hzc ) dout 353 w / 1538 w 5pf* +3.3v for 3.3v i/o 319 w / 1667 w fig. 1 * including scope and jig capacitance output load(a) dout zo=50 w rl=50 w vl=1.5v for 3.3v i/o v ddq /2 for 2.5v i/o /+2.5v for 2.5v i/o
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 11 - rev 0.1 aug. 1998 km718v949 sleep mode sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb2 . the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an asynchronous, active high input that causes the device to enter sleep mode. when the zz pin becomes a logic high, i sb2 is guaranteed after the time t zzi is met. any operation pending when entering sleep mode is not guaranteed to successful complete. therefore, sleep mode (read or write) must not be initiated until valid pend- ing operations are completed. similarly, when exiting sleep mode during t pus , only a deselect or read cycle should be given while the sram is transitioning out of sleep mode. sleep mode electrical characteristics description conditions symbol min max units current during sleep mode zz 3 v ih i sb2 10 ma zz active to input ignored t pds 2 cycle zz inactive to input sampled t pus 2 cycle zz active to sleep current t zzi 2 cycle zz inactive to exit sleep current t rzzi 0 k t pds zz setup cycle t rzzi zz isupply all inputs (except zz) outputs (q) t zzi t pus zz recovery cycle deselect or read only high-z don t care i sb2 sleep mode waveform normal operation cycle deselect or read only
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 12 - rev 0.1 aug. 1998 km718v949 c l o c k c k e a d d r e s s w r i t e c s a d v o e d a t a o u t t i m i n g w a v e f o r m o f r e a d c y c l e n o t e s : w r i t e = l m e a n s w e = l , a n d b w x = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l t c h t c l t c e s t c e h t a s t a h a 1 a 2 a 3 t w s t w h t c s s t c s h t o e t h z o e t l z o e t c d t o h t h z c q 3 - 4 q 3 - 3 q 3 - 2 q 3 - 1 q 2 - 4 q 2 - 3 q 2 - 2 q 2 - 1 q 1 - 1 d o n t c a r e u n d e f i n e d t c y c t a d v s t a d v h
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 13 - rev 0.1 aug. 1998 km718v949 t i m i n g w a v e f o r m o f w r t e c y c l e c l o c k a d d r e s s w r i t e c s a d v d a t a i n t c h t c l a 2 a 3 d 2 - 1 d 1 - 1 d 2 - 2 d 2 - 3 d 2 - 4 d 3 - 1 d 3 - 2 d 3 - 3 q 0 - 4 o e d a t a o u t t d s t d h t h z o e d o n t c a r e u n d e f i n e d t c y c c k e a 1 q 0 - 3 d 3 - 4 t c e s t c e h n o t e s : w r i t e = l m e a n s w e = l , a n d b w x = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 14 - rev 0.1 aug. 1998 km718v949 t i m i n g w a v e f o r m o f s i n g l e r e a d / w r i t e c l o c k a d d r e s s w r i t e c s a d v o e d a t a i n t c h t c l t d s t d h d a t a o u t w a 2 r a 4 w a 5 d 2 t o e t l z o e q 1 d o n t c a r e u n d e f i n e d t c y c c k e t c e s t c e h r a 1 r a 3 r a 7 r a 6 q 3 q 4 q 7 q 6 d 5 n o t e s : w r i t e = l m e a n s w e = l , a n d b w x = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 15 - rev 0.1 aug. 1998 km718v949 t i m i n g w a v e f o r m o f c k e o p e r a t i o n c l o c k a d d r e s s w r i t e c s a d v o e d a t a i n t c h t c l d a t a o u t r a 1 w a 2 r a 3 r a 4 w a 5 t c e s t c e h d o n t c a r e u n d e f i n e d t c y c c k e t d s t d h d 2 q 3 q 4 q 1 n o t e s : w r i t e = l m e a n s w e = l , a n d b w x = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l t c d t l z c t h z c
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 16 - rev 0.1 aug. 1998 km718v949 t i m i n g w a v e f o r m o f c s o p e r a t i o n c l o c k a d d r e s s w r i t e c s a d v o e d a t a i n t c h t c l d a t a o u t r a 1 r a 2 w a 3 r a 4 w a 5 d o n t c a r e u n d e f i n e d t c y c c k e d 5 q 4 t c e s t c e h q 1 q 2 t o e t l z o e d 3 t c d t l z c n o t e s : w r i t e = l m e a n s w e = l , a n d b w x = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l t h z c t d h t d s
preliminary KM736V849 256kx36 & 512kx18 pipelined n t ram tm - 17 - rev 0.1 aug. 1998 km718v949 package dimensions 0.10 max 0~8 22.00 0.30 20.00 0.20 16.00 0.30 14.00 0.20 1.40 0.10 1.60 max 0.05 min (0.58) 0.50 0.10 #1 (0.83) 0.50 0.10 100-tqfp-1420a 0.65 0.30 0.10 0.10 max + 0.10 - 0.05 0.127 units ; millimeters/inches

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