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test and measurement products 1 www .semtech.com edge720 500 mhz pin electronics driver, window comparator, and load description features functional block diagram applications revision 4 / october 3, 2002 the edge720 is a totally monolithic ate pin electronics solution manufactured in a high-performance complementary bipolar process. the three-statable driver is capable of generating 9v swings over a ?v to +12v range. in addition, 13v super voltage may be obtained under certain operating conditions. an input power down mode allows extremely low leakage current in hiz. thus, the edge720 can help to eliminate relays that are typically used to isolate devices such as per pin measurement units from the driver/ comparator/load. the load supports programmable source and sink currents of 35 ma over a ?v to +12v range, or it can be completely disabled. in addition, the load is configurable and may be used as a programmable voltage clamp. the window comparator spans a 13v common mode range, tracks input signals with edge rates greater than 6 v/ns and passes sub-ns pulses. an input power down mode allows for extremely low leakage measurements. the inclusion of all pin electronics building blocks into a 52 lead qfp (10 mm body w/ exposed heat sink) offers a highly integrated solution that is traditionally implemented with multiple integrated circuits or discretes. the edge720 is a variant of the edge710, with the following improvements: reduced d+c+l leakage current increased super voltage range additional vcm_in buffer reduces the need for an external buffer when using the load circuit as a programmable clamp. flash memory test vlsi test equipment mixed-signal test equipment memory testers (bidirectional channels) asic verifiers fully integrated three-statable driver, window comparator, and dynamic active load 13v driver, load, compare range +13v super voltage capable 35 ma programmable load comparator input tracking >6v/ns leakage (l+d+c) < 2 a (normal mode, typical) leakage (l+d+c) < 30 na (power-down mode, guaranteed) small footprint (52 lead exposed pad qfp) bias dvh dhi dhi* dvr_en dvr_en* dvl ipd_d qa* qa pecl superv ipd_c qb qb* isc_in vcm_in_a vcm_out_a vcm_out_b vcm_in_b isk_in ld_en ld_en* radj dvh_cap dvl_cap dout fadj cva vinp cvb load bridge_sc bridge_sk vcc vee isc isk
2 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 pin description # n i pe m a n n i pn o i t p i r c s e d r e v i r d 0 3t u o d. t u p t u o r e v i r d 3 1 , 2 1* i h d / i h d h g i h r e v i r d e h t e n i m r e t e d h c i h w s n i p l a t i g i d t u p n i l a i t n e r e f f i d e g a t l o v e d i w . l e v e l w o l r o 5 1 , 4 1* n e _ r v d / n e _ r v d g n i e b r e v i r d e h t l o r t n o c h c i h w s n i p l a t i g i d t u p n i l a i t n e r e f f i d e g a t l o v e d i w . e t a t s e c n a d e p m i h g i h a n i r o e v i t c a 9 1 , 0 2l v d , h v d h g i h r e v i r d e h t e n i m r e t e d h c i h w s t u p n i e g a t l o v g o l a n a e c n a d e p m i h g i h . l e v e l w o l d n a 4 2p a c _ h v d o t d e t c e n n o c e b d l u o h s r o t i c a p a c f p 0 0 1 a . n i p n o i t a s n e p m o c p m a p o . h v d 5 2p a c _ l v d o t d e t c e n n o c e b d l u o h s r o t i c a p a c f p 0 0 1 a . n i p n o i t a s n e p m o c p m a p o . l v d 6 1 , 7 1j d a f , j d a r . s e m i t n o i t i s n a r t r e v i r d e h t e n i m r e t e d h c i h w s t n e r r u c t u p n i 8 1s a i b . y l n o r e v i r d e h t r o f t n e r r u c s a i b l a n r e t n i n a s t e s h c i h w t u p n i t n e r r u c g o l a n a 4 3d _ d p i d n a n w o d r e v i r d e h t s w o l s h c i h w l o r t n o c n w o d r e w o p t u p n i r e v i r d l t t . t n e r r u c e g a k a e l z i h r e v i r d e h t s e c u d e r r o t a r a p m o c 3 3p n i v. s r o t a r a p m o c f o t u p n i e v i t i s o p e h t o t t u p n i e g a t l o v g o l a n a 1 5 , 0 5b v c , a v c. s d l o h s e r h t r o t a r a p m o c e h t t e s h c i h w s t u p n i g o l a n a 5 , 6 1 1 , 0 1 * a q / a q * b q / b q . b d n a a s r o t a r a p m o c f o s t u p t u o l a t i g i d ) l c e p r o ( l c e l a i t n e r e f f i d 8 , 7l c e p h c i h w s e g a t s t u p t u o r o t a r a p m o c e h t r o f l e v e l y l p p u s r e w o p d e r e f f u b n u . s l e v e l l a t i g i d l c e p r o l c e r e h t i e s e h s i l b a t s e 5 3c _ d p i l a n o i t c n u f - n o n , n w o d - r e w o p a n i d a o l d n a r o t a r a p m o c s t u p t a h t t u p n i l t t . e d o m 3 2v r e p u s l a n o i t c n u f - n o n , n w o d - r e w o p a n i d a o l d n a r o t a r a p m o c s t u p t a h t t u p n i l t t . e d o m
3 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 pin description (continued) # n i pe m a n n i pn o i t p i r c s e d d a o l 8 3d a o l. t u p t u o d a o l 3 , 2* n e _ d l / n e _ d l . d a o l e h t e l b a s i d d n a e t a v i t c a h c i h w s t u p n i l a t i g i d l a i t n e r e f f i d e g a t l o v e d i w 7 4 4 4 a _ n i _ m c v b _ n i _ m c v g n i t a t u m m o c e h t m a r g o r p t a h t s t u p n i e g a t l o v g o l a n a e c n a d e p m i h g i h . s e g a t l o v 5 4 , 8 4n i _ k s i , n i _ c s i . s t n e r r u c k n i s d n a e c r u o s d a o l e h t m a r g o r p h c i h w s t u p n i t n e r r u c g o l a n a 3 4 6 3 a _ p a c _ m c v b _ p a c _ m c v d n u o r g o t r o t i c a p a c f 1 0 . a ( n i p n o i t a s n e p m o c p m a p o r e f f u b g n i t a t u m m o c . ) d e d n e m m o c e r s i 2 4 1 4 a _ t u o _ m c v b _ t u o _ m c v . ) d e d n e m m o c e r s i d n u o r g o t r o t i c a p a c f 1 0 . a ( s n i p e g a t l o v g n i t a t u m m o c 0 4 9 3 c s _ e g d i r b k s _ e g d i r b t n e r r u c l a n r e t n i e h t s s a p y b t a h t e g d i r b t u p t u o e h t o t s n o i t c e n n o c e g d i r b e d o i d . s e c r u o s / s e i l p p u s r e w o p s u o e n a l l e c s i m 7 2 6 2 e d o h t a c e d o n a . g n i r t s e d o i d l a m r e h t p i h c - n o e h t f o s l a n i m r e t 9 4 , 2 3 , 1 3 , 4c c v d a o l e h t r o f c c v d e t a n g i s e d e h t s i 9 4 n i p ( . l e v e l y l p p u s r e w o p e v i t i s o p ) . t i u c r i c 2 5 , 9 2 , 8 2 , 1e e v. l e v e l y l p p u s r e w o p e v i t a g e n 6 4 , 7 3 , 2 2 , 1 2 , 9d n g. d n u o r g e c i v e d
4 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 pin description (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 52 pin exposed pad qfp (edquad) 10 mm x 10 mm top side (exposed pad on bottom) (die up) vee cvb cva vcc (load circuit) isc_in vcm_in_a gnd isk_in vcm_in_b vcm_cap_a vcm_out_a vcm_out_b bridge_sc bridge_sk load gnd vcm_cap_b ipd_c ipd_d vinp vcc vcc dout vee vee cathode dvr_en dvr_en* fadj radj bias dvl dvh gnd gnd superv dvh_cap dvl_cap anode vee ld_en ld_en* vcc qa* qa pecl pecl gnd qb qb* dhi dhi*
5 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 circuit description driver circuit description introduction the edge720 features a driver circuit that can be used to drive voltage levels over a 1v to +12v range at frequencies of up to 500 mhz at the dout pin. in addition, the driver can be used to force a super voltage level of up to 13v and can also be placed in a high impedance state. the driver circuit of the edge720 is a variant of the driver circuit of the edge710, and was specifically designed to offer a low leakage solution to flash tm memory testing.. a block diagram of the driver can be seen in figure 1. figure 1. block diagram of the edge720 driver driver digital ?lex-in?inputs the edge720 driver circuit features flex-in control inputs for the driver enable (drv-en(*)) and driver data (dhi(*)) inputs that allow the driver to receive ecl, ttl, cmos, or custom signal levels. these flex-in inputs are wide voltage differential inputs whose operation is described in table 1. table 1. ?lex-in?input characteristics single-ended operation of these inputs can be accomplished by connecting the inverting input (dhi* or drv_en*) to the desired dc threshold level. driver enable inputs (drv_en(*)) the driver enable inputs, drv_en(*), control whether the driver is forcing a voltage at dout, or is placed in a high impedance state. if the voltage applied to drv_en is more positive than that applied to drv_en*, the driver, will force the dout voltage to either dvh or dvl (determined by dhi(*)). if the voltage applied to drv_en is less than that applied to drv_en*, the driver will force the dout pin to a high impedance state (see table 2 for drv_en(*) functionality). it is important to note that for predictable operation, drv_en(*) pins must not be left floating. table 2. drv_en(*) and dhi(*) control input functionality input power down the driver input power down pin, ipd_d, is a ttl compatible input that can be used to place the driver in input power down (ipd) mode. ipd_d functionality is described below in table 3. table 3. ipd_d functionality ipd mode should be invoked when the driver is in high impedance mode (drv_en < drv_en*). when in ipd mode, the driver output leakage will be minimized. it is important to note that ipd_d should not be left floating. if ipd_d is not being used, it should be connected to gnd. e l b a n e r e v i r da t a d r e v i r dt u o d * n e _ v r d > n e _ v r d * n e _ v r d > n e _ v r d * n e _ v r d < n e _ v r d * i h d > i h d * i h d < i h d x h v d l v d z i h n i mx a ms t i n u e g n a r t u p n i e d o m n o m m o c5 7 . 2 + e e v0 . 5v e g n a r t u p n i l a i t n e r e f f i d5 2 . 0 0 . 4 v d _ d p in o i t a r e p o 0l a m r o n 1e d o m d p i bias dvh dhi dhi* dvr_en dvr_en* dvl ipd_d radj dvh_cap dout fadj dvl_cap
6 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 pin descriptions circuit description (continued) driver level inputs the dvl and dvh pins are high impedance analog voltage inputs that establish the driver output levels of a logical 1 or 0 at dout. due to possible offsets inherent in the driver, it may be necessary to apply a voltage to dvh or dvl that is slightly larger in magnitude than the desired dout voltage. driver stability/compensation in order to ensure stability, 100 pf chip capacitors (with good high frequency characteristics) should be connected between the dvh and dvh_cap, as well as between dvl and dvl_cap pins. the connectivity of these external components can be seen in figure 2. figure 2. driver external compensation component connectivity these capacitors are intended to improve the driver output response to fast changes in the dvl(h) input voltage levels. using 100 pf capacitors will allow the dout voltage to track dvl(h) level changes at slew rates up to 400v/ s. if it is desired to operate the edge720 in an application that can tolerate dvl(h) level changes (with the driver circuit enabled) of less than 100v/ s, these capacitors can be omitted without any reduction in part performance. super voltage operation the edge720 may be used to drive a super voltage level of up to 13v at the driver output, dout. in order to ensure that the desired super voltage level is driven, a slightly higher voltage will need to be switched onto the dvh or dvl pins to account for possible offsets in the driver. one solution that can be used to implement super voltage functionality is included as a feature on the edge4707. the edge4707b features an analog mux, which was designed to switch the driver input voltages between super voltage and standard levels. analog mux connectivity can be seen below in figure 3. figure 3. analog mux connectivity for super voltage operation it is important to note that when driving a super voltage level, the driver differential input voltage (dvh dvl) must be in compliance with the specified range. connecting the super voltage inputs (vihh and vill) of each analog mux to the same super voltage source will ensure this. in addition, if the edge720 s comparator and load are connected to the driver output, as in typical relay-less test system architecture, they will need to be protected during super voltage operation as follows: 1. comparator must be placed in input power down mode (ipd_c = 1 or superv = 1) 2. differential load voltage specification (vload vcm_in_a(b)) must be met 3. load should be disabled (isk_in, isc_in = 0 ma, ld_en < ld_en*) compliance with the precautions above will ensure that the edge720 is not inadvertently damaged during super voltage operation. 1 0 1 0 dvh dvl dout vihh vih vill vil sv_sel edge720 (driver section) edge4707 (analog mux section) high level voltage low level voltage dvh_cap dout dvl_cap dvh dvl 100 pf 100 pf
7 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 circuit description (continued) driver current inputs the edge720 driver also features a trio of current controlled inputs (bias, radj, and fadj) that can be used to optimize the driver circuit s power consumption and ac characteristics to allow the edge720 to be custom tailored to a broad spectrum of applications. driver bias input the bias pin is an analog current input that establishes the internal driver bias current. this current, to some degree, also establishes the overall power consumption and ac performance of the driver. an external current source, such as a group f dac on the edge6420, can be used to provide a programmable current supply as well as minimize part-to-part performance variation within a test system to optimize performance. in lieu of using an edge6420 group f dac for a programmable current source, a precision external resistor can be used to set the bias current as seen in figure 4. bias input current can range from 0.5 ma to 1.25 ma. in general, increasing the bias input current will result in faster ac swings and increased power consumption. however, optimum bias input current will be a function of radj and fadj input currents and thus bias cannot be set independently. figure 4. using an external resistor to establish the input current at bias, radj, and fadj driver slew rate adjustment the radj and fadj pins are current input pins that can be used to adjust the driver rising edge and falling edge slew rates, thus determining driver rise and fall times. the rising edge adjust pin, radj, controls the rate at which an output signal at dout transitions from low to high while the falling edge adjust pin, fadj, controls the rate at which an output signal transitions from high to low. similar to the bias input, it is recommended that an edge6420 group f dac provide these inputs. the edge6420 is designed to facilitate all of the necessary inputs to operate the edge720. however, in lieu of using the edge6420, an external precision resistor can be connected as shown in figure 4 to provide the radj and fadj input currents. driver dc accuracy in the ideal case, the voltages applied to the driver level inputs (dvl and dvh) will correspond 1:1 with the driver output voltage appearing at dout as can be seen in figure 5. figure 5. ideal driver dc transfer characteristic in reality, the transfer characteristic of the driver circuit is non-ideal and thus the driver level input voltages do not correspond 1:1 with the driver output voltage. there are three parameters that can be used to quantify the deviation of the non-ideal driver transfer characteristic from the ideal one. these parameters are all specified in the driver dc accuracy section of the datasheet and are as follows: 1. offset voltage 2. gain error 3. linearity error 1.5k rext radj, fadj, bias vcc vee the established bias current follows the equation: bias = (vcc C 0.7) / (rext + 1.5k ? ) 12v 12v C1v C1v v dout v dvl, dvh ideal
8 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 the final parameter that is used when quantifying the deviation of the non-ideal transfer characteristic from the ideal one is linearity error. linearity error is used to account for the fact that the driver dc transfer characteristic may not be completely linear, but guaranteed to fall within a window defined by the driver linearity specification (see figure 8). figure 8. the effect of linearity error on the ideal driver dc transfer characteristic of the three parameters that quantify the non-ideal behavior of the driver dc transfer characteristic, both offset voltage and gain error can be accounted for in software calibration and thus overall driver dc accuracy is governed by the linearity error of the device. circuit description (continued) the first parameter that will be discussed is offset voltage. offset voltage is defined as the difference between the driver level input voltage and the driver output voltage when the input is programmed to 0v. offset voltage manifests itself as a dc shift of the ideal driver transfer characteristic as can be seen in figure 6. figure 6. the effect of offset voltage on the ideal driver dc transfer characteristic the second parameter that will be discussed is gain error. gain error is due to the fact that the gain of the driver circuit may not be unity (constant) as in the ideal case. this can have an effect on the slope of the ideal driver dc transfer characteristic as can be seen in figure 7. figure 7. the effect of gain error on the ideal driver dc transfer characteristic 12v 12v C1v C1v v dout v dvl, dvh id e a l v o s v o s 12v 12v C1v C1v v dout v dvl, dvh id e a l s lo p e = m a x g a in slope = 1 slope = min gain 12v 12v C1v C1v v dout v dvl, dvh id e a l in l in l
9 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 comparator circuit description introduction the edge720 features two on-chip comparators that are connected to form a window comparator. this window comparator can be used to determine whether an input signal at vinp is within a threshold window determined by the cva and cvb pins. the comparator on the edge720 is a variant of the comparator on the edge710 and has been specifically designed to improve resistance to breakdown at super voltage levels. a block diagram of the edge720 s window comparator circuit can be seen in figure 9. figure 9. block diagram of the edge720? window comparator comparator inputs the comparator circuit features two digital, three analog, and three power supply inputs. the digital inputs, ipd_c and superv, can be used to place the comparator into input power down mode. the analog inputs are cva, cvb, and vinp. cva and cvb set the comparator thresholds, while vinp is the comparator input voltage signal. the comparator output power supply input is pecl. the functionality of all of these inputs is described later in this section. comparator input power down the ipd_c and superv pins are ttl compatible inputs that can be used to place the edge720 s window comparator circuit into input power down mode. ipd_c and superv functionality is described in table 4. table 4. ipd_c functionality when the comparator is placed in ipd mode, the comparator input, vinp, can be safely exposed to super voltage levels. since the comparator circuit is not functional in this mode, it is recommended that ipd_c be connected to gnd when not in use. in addition to the input power down characteristics of vinp, superv and ipd_c control switches that internally connect the isk_in and isc_in inputs to protect the load circuit. comparator analog inputs vinp is a high impedance analog voltage input pin that is used to read a desired voltage signal. vinp is internally connected to the non-inverting inputs of both on-chip comparators (as seen in figure 9). vinp is also connected to two internal over-voltage diodes that are connected to vcc and vee. these diodes are sized to handle up to 100 ma of current. cva and cvb are high impedance analog voltage inputs that are used to set the threshold levels of the window comparator. although cva(b) are high speed inputs, they do not require bypassing as long as the source impedance is not inductive (which can happen with a long, narrow pcb trace). if needed, small ( 100 pf) capacitors can be connected between the cva(b) pins and gnd to ensure stability and low noise. circuit description (continued) cva vinp cvb qa* qa ipd_c superv pecl qb qb* vee vcc v r e p u sc _ d p in o i t a r e p o 00 l a m r o n 01 e d o m d p i 10 e d o m d p i 11 e d o m d p i
10 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 when operating pecl at voltage levels above gnd, pins 7 and 8 should be bypassed with 0.1 f capacitors to gnd to ensure stability of the comparator inputs. comparator dc accuracy the dc accuracy of the edge720 s comparator circuitry is quantified by the following datasheet specified parameters: 1. comparator input offset voltage 2. comparator hysteresis comparator input offset voltage quantifies the region around the programmed threshold voltage applied to cva(b) at which the voltage applied to vinp will cause the comparator output to transition states. or more simply, it describes how far the actual threshold voltage of the comparator may deviate from the value which has been programmed at cva(b). comparator hysteresis quantifies the difference in the comparator threshold level when the comparator is triggered by a signal with a positive slope as opposed to one with a negative slope when the programmed threshold voltage at cva(b) is held constant. in order words, hysteresis is a measure of the change in threshold voltage as a function of the comparator output state (see figure 11). typically, hysteresis is used to prevent multiple comparator output transitions due to slow input slew rates in a noisy environment. these slower inputs remain in the transition region for longer periods of time, allowing noise present to cause repeated threshold crossings. figure 11. hysteresis circuit description (continued) comparator outputs the comparator outputs qa(*) and qb(*) are open emitter outputs that can be used to determine where the input voltage measured at the vinp input is located in relation to the comparator thresholds, cva and cvb. these outputs are normally terminated through a 50 ? resistor connected to pecl 2v. other possible termination schemes are discussed in an1003-ecl output termination techniques. comparator output functinality is described in table 5. table 5. window comparator truth table comparator power supplies pecl is the comparator output power supply input that determines the logic levels of the comparator circuit s differential outputs qa(*) and qb(*). when connected to gnd, the comparator outputs will function as standard ecl outputs. however, by increasing the value of the pecl input voltage, qa(*) and qb(*) will track the pecl input voltage and also increase as shown below in figure 10. figure 10. the influence of the pecl input on comparator outputs ) v ( p n i va qb q ) b ( a v c < p n i v00 ) b ( a v c > p n i v11 b v c < p n i v < a v c10 b v c > p n i v > a v c01 pecl = gnd a pecl = +3.3v b pecl = +5v c +5v +4v +3v +2v +1v 0v q q* q q* q q* v pecl actual threshold voltage comparator input signal programmed threshold voltage hysteresis
11 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 circuit description (continued) load circuit description introduction the edge720 features a programmable load circuit which is capable of sourcing or sinking up to 35 ma over a 1v to +12v range, or being placed in a high impedance state. this circuit also features split commutating voltage inputs that allow it to be configured as a programmable voltage clamp. in addition, the bridge_sc and bridge_sk pins allow the load circuit s diode bridge to be connected to external current sources for increased low current accuracy. a functional schematic of the edge720 s load circuit can be seen below in figure 12. figure 12. functional schematic of the edge720? load circuit load enable the edge720 load circuit features a differential flex in input labeled ld_en(*). this input can be used to isolate the diode bridge from the on-chip current supplies, leaving the load pin in a high impedance state. flex in inputs are wide voltage inputs which allow the ld_en(*) pin to be used with ecl, ttl, cmos, or custom level inputs, and whose characteristics are described in table 1. ld_en(*) functionality is described in table 6. table 6. load enable input functionality single-ended operation can be attained by connecting the inverting input, ld_en* to the desired dc threshold level. t u p n i e l b a n e d a o ln o i t a r e p o * n e _ d l < n e _ d le c n a d e p m i h g i h * n e _ d l > n e _ d le v i t c a current programming inputs isc_in and isk_in are independently adjustable analog current inputs that control the amount of current being supplied to the diode bridge by the on-chip current supplies (see figure 12). consequently, these inputs can be used to program the amount of current being sourced (isc_in) or sunk (isk_in) at the load circuit output pin (load). the on-chip current supplies have been designed to have a nominal gain of 20. therefore, the magnitude of current sourced or sunk is equal to the magnitude of the control current scaled by a factor of 20. the isk_in and isc_in current programming inputs should be routed on a pcb such that coupling between the control inputs and the load, vcm_out_a and vcm_out_b pins is minimized. finally, it is also recommended that 1 k ? of external series resistance be connected between these inputs and the source controlling them. a group e dac on the edge6420 offers a nice solution to controlling these inputs. commutating voltage inputs vcm_in_a(b) are high impedance analog voltage inputs to on-chip buffers that are used to set the voltage level at which the diode bridge switches from sourcing to sinking current when the load is connected as a standard active load (see figure 15). if the voltages applied to vcm_in_a(b) are more positive than that on the load pin, the bridge will source current from the load pin (see figure 13). if the voltage applied to vcm_in_a(b) is less than that at the load pin, the bridge will sink current through the load pin (see figure 14). figure 13. edge720 load circuit sources current figure 14. edge720 load circuit sinks current isc_in ipd_c superv vcm_in_a vcm_in_b vcm_out_a vcm_out_b isk_in ld_en ld_en* load bridge_sc bridge_sk vcc vee 1 k ? 1 k ? isc isk vcm_in_a load vcm_in_b external connection vcm_in_a(b) > load vcm_in_a load vcm_in_b external connection vcm_in_a(b) < load
12 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 commutating voltage compensation the vcm_cap_a(b) pins are internal commutating buffer compensation pins that require a fixed 0.01 f chip capacitor (with good high frequency characteristics) connected to gnd. commutating buffer outputs vcm_out_a(b) are connected to the outputs of the on- chip commutating buffer, whose output voltages are determined by vcm_in_a(b) (see figure 12). the connection scheme of these pins will determine the configuration of the edge720 load circuit. this allows the edge720 s load circuit to be quite versatile in that it can be configured in multiple ways. standard active load configuration one way to configure the load circuit of the edge720 is as a standard active load. in order to operate the load as a standard active load, vcm_in_a can be connected to vcm_in_b and driven with the same source as shown in figure 15. the 0.01 f bypass capacitors shown in figure 15 are needed to supply current to the diode bridge during fast transients. these capacitors should be placed as close to the vcm_out_a(b) pins as possible to ensure stability and quick response to fast transitions on the load output pin. figure 15. edge720 load circuit connected as a standard active load programmable clamp configuration another way to configure the load circuit of the edge720 is as a programmable voltage clamp. using this configuration allows the edge720 load circuitry to be used as a transmission line termination scheme to minimize the reflections caused by an unmatched line. using the edge720 load circuit in this configuration offers a superior clamping solution to the more traditional voltage controlled diode clamp method. to configure the edge720 load circuit as a programmable clamp, the load circuit should be configured as in figure 16. the 0.01 f bypass capacitors shown in figure 16 are needed to supply current to the diode bridge during fast transients. these capacitors should be placed as close to the vcm_out_a(b) pins as possible to ensure stability and quick response to fast transitions on the load output pin. figure 16. edge720 load circuit connected as a programmable voltage clamp with the load configured in this manner, the voltage at the load pin will be clamped within a range determined by the voltage at vcm_out_a and vcm_out_b. the voltage at vcm_out_a determines the low voltage- clamping limit, while the voltage at vcm_out_b determines the high voltage-clamping limit. it is important to note that when using the load circuit in this manner, isc_in and isk_in should be set to their maximum values. external diode bridge connections the edge720 features two pins, bridge_sc and bridge_sk, which allow access to the top and bottom of the diode bridge through 1 k ? series resistors (see figure 12). these pins can be connected to external current sources whenever it is desired to use sources that are more accurate than the on-chip sources. connecting these pins may degrade the high impedance characteristics of the load when it is not enabled unless isolation relays are used to isolate the external current sources from the diode bridge. circuit description (continued) vcm_in_a vcm_in_b vcm_out_a vcm_out_b load + + 0.01 f 0.01 f isc isk edge720 vcm_in_a vcm_in_b vcm_out_a vcm_out_b load + + 0.01 f 0.01 f isc isk edge720
13 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 load circuit current accuracy in the ideal case, the current that the load circuit will source or sink at the load pin will be equal to the magnitude of the current input applied to the current programming input pin (isc_in, isk_in) scaled by a factor of 20. this results in the ideal load circuit transfer characteristic seen in figure 17. figure 17. ideal load circuit current transfer characteristic in reality, the transfer characteristic of the load circuit current is non-ideal and thus the current being sourced or sunk at the load pin will not be equal to the magnitude of the programming input currents at isc_in or isk_in scaled by a factor of 20. to account for these non-ideal effects, the accuracy of the on-chip current sources (isc, isk) is quantified by three parameters. these parameters are all specified in the programmable load current accuracy section of the datasheet and are as follows: 1. source/sink current offset 2. source/sink current gain 3. source/sink current linearity error the source/sink offset current specification quantifies the amount of current that may be needed at the programming inputs (isc_in and isk_in) before the current being sourced or sunk at the load pin will actually turn on (see figure 18). this allows for the offset to be calibrated to ensure that zero input current results in zero output current. circuit description (continued) figure 18. source/sink current offset the source/sink current gain specification accounts for the fact that the gain of the actual on-chip current source (isc, isk) may not be 20 as in the ideal case. this may result in the possibility of a deviation in the slope of the load circuit transfer characteristic when it is in the linear region as shown in figure19. figure 20. source/sink current gain the source/sink current linearity specification quantifies the amount the load transfer characteristic deviates from a predicted ideal transfer characteristic in the linear region as shown in figure 20. figure 20. source/sink current linearity max current min current ideal ideal isc isk i load i isc_in, isk_in max current min current ideal ideal isc isk i load i os i isc_in, isk_in max current min current ideal isc ideal isk i load i isc_in, isk_in m ax gain min gain m in g a in max gain max current min current ideal isc inl inl ideal isk i load i isc_in, isk_in inl inl
14 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 circuit description (continued) load circuit commutating voltage accuracy the accuracy of the load circuit commutating voltage is dependent upon the commutating buffer. the accuracy of this buffer is quantified by three parameters. these parameters are all specified in the commutating voltage accuracy section of the datasheet and are as follows: 1. offset voltage 2. gain error 3. linearity error these parameters affect the ideal voltage transfer characteristic of the commutating buffer in the same manner as they affect the ideal transfer characteristic of the driver circuit. please refer to the driver dc accuracy section for a detailed description of these effects. additional features thermal monitor the edge720 features an on-chip string of five thermal diodes that allow for a method of accurate die temperature measurement (see figure 21). using an external bias current of 100 a injected through the string, the edge720 junction temperature follows the equation: tj[ ? c] = {anode cathode )/ 5 .7752} / ( .0018) figure 21. edge720 thermal diode string low leakage pin electronics implementation the edge720 is capable of supporting a total dcl (driver + comparator + load) leakage of less than 100 na. this extremely low leakage current capability enables the edge720 to be ideally suited for relay-less ate system architecture. in order to realize low leakage functionality, the following conditions must be met: 1. driver circuit must be in ipd mode (ipd_d = 1) 2. comparator circuit must be in ipd mode (ipd_c = 1) 3. load circuit must be disabled (high impedance mode: ld_en < ld_en*, isc_in = isk_in = 0 ma) connectivity the edge720 can be easily combined with other edge devices to create simple, yet high performance solutions to many challenges in ate. one possible ate solution that consists of the edge6420 dac, edge4707b pmu, and edge720 dcl is shown in figure 24. power sequencing in order to avoid the possibility of latch-up, the following power-up requirements must be satisfied: 1. vee gnd vcc at all times 2. vee all inputs vcc the following power sequencing can be used as a guideline when using the edge720: power up sequence 1. vee 2. vcc 3. analog inputs 4. digital inputs power down sequence 1. digital inputs 2. analog inputs 3. vcc 4. vee anode cathode temperature coefficient = C9 mv / ?c bias current
15 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 application information driver/comparator/load output circuit the recommended circuit for combining the driver, comparator, and load outputs to a single dut pin is shown in figure 1. the inductors in the circuit compensate for the parasitic capacitance of the load and comparator pins, minimizing the imaginary part of the impedance to both incoming and outbound signals. this yields the fastest driver rise times as well as the smallest amount of distortion of the signal going into the comparator. the amount of distortion caused by this compensation network is small compared to the other sources of distortion. figure 22. optimum circuit for combined edge720 outputs computing output voltage range the output voltage range of the driver and load and the input range of the comparator are a function of vcc and vee and their individual voltage overheads, offset, and gains specified for each. for example, the driver s output high range (no load) is shown below. figure 23. driver output high range (no load) vinp dut pin load dout 33 38 40.2 0603 48.7 0805 30 8.2 nh 0603 3.3 nh 0603 transmission line for dout(high) of +11.75v, dvh may need to be overdrived as follows: + offset (of dout vs. dvh) i.e. + 125 mv = 12.05v = dvh hence, vcc(min) needs to be: +12.05v + overhead i.e. +12.05 + 3.5v = 15.55v for the application of doutmax = +11.75v, vcc must be greater than 15.55v. similar is true for all input/ output ranges specified. power supply bypassing each section of the edge720 has separate vcc and gnd pins which are not connected to each other internally, so each ground pin must be connected to analog ground by the shortest possible path, and each of the vcc pins must have power and a bypass capacitor provided. these bypass capacitors should be placed as close to the power pin as possible for optimum filtering and stability. pins 31 and 32 provide vcc to the driver circuit. pins 21 and 22 connect the driver gnd. pin 4 is vcc, and pin 9 is gnd for the comparator circuit. pin 49 provides vcc and pins 37 and 46 provide gnd to the load circuit. all of the vee pins are connected together via the exposed heat slug on the bottom of the part. each of these go to separate sections of the part, so should be bypassed separately for best noise filtering and stability. pin 21 and 22 provide vee to the driver circuit, pin 1 provides it to the comparator, and pin 52 connects vee to the load circuit. +11.75v 0.985 ( ) ) +11.75v gain ( dvh dvl dout vcc vee overhead = +3.5v overhead = +3.5v
16 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 figure 24. connectivity of edge6420 dac, edge4707b pmu, and edge720 dcl dvh dvh_out dvl_out dhi dhi* dvr_en dvr_en* supervoltage sv_sel ipd_d qa* qa pecl ipd_c superv qb qb* vcm_out_a vcm_out_b ld_en ld_en* dut pin vinp bias radj isc_in vcm_in_a isk_in vinp ivin i/v max i/v min cva fadj cvb load vcc vee mux dvl mux e720 driver, comparator, load (single channel device) edge6420 dac (64-channel device) edge4707b ppmu (quad channel device) note: figure depicts one of four channels of the edge4707 sense force fv / fi* mi / mv* e_sn_in e_fc_in disable dutgtl dutlth ivmon comparators detector logic voltage monitor 100? 30 ? 1k ? low leakage features of the edge720 and low capacitance edge4707b allow for elimination of isolation relays one analog mux per channel is included in the edge4707b (4 channels total) used for connection to a system pmu 64 level dac chip ate chipset connections actual implementation of chipset may differ. the diagram above is conceptual only. bridge_sc bridge_sk application information (continued)
17 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 application information (continued) required external components dvh (note 1) dvh_cap dvl_cap dvl (note 1) 100 pf 100 pf anode cathode vinp dout load vcm_out_a(b) cva, cvb, vcm_in_a, vcm_in_b (note 2) radj, fadj, bias (note 1) isk_in, isc_in (note 1) a silicon diode with 150 ma of forward current capability is used to limit the vcc power supply voltage to the load circuit. its purpose is to ensure that the vcc vcm_in_a(b) breakdown voltage of 16v is not exceeded. edge720 vcc pecl vee + + v meter + 0.1 f 0.1 f 0.01 f 0.1 f 0.1 f vcc 0.1 f device under test(dut) 47 ? 1k ? vcc (pin 4) vcc (pin 49) vcc (pin 32) vcc (pin 31) gnd pecl vee note 1: the dvh, dvl, radj, fadj, and bias inputs do not normally require bypass capacitors for the edge720 to operate correctly. however, it is important that the signals supplied to these inputs be routed carefully to avoid noise pick-up or feedback from the driver output signal. if needed, bypass capacitors can be placed in front of these inputs to reduce the amount of pick-up. note 2: the iskin, iscin, vcm_in_b and vcm_in_a inputs do not require bypass capacitors if the input traces are routed to avoid noise pick-up and feedback from the output stage. it is especially important that the isk input be routed away from the output stage since this signal is the inverse of the applied output signal and can feed back to itself, causing oscillations. if needed, bypass capacitors can be placed before any of these pins without degrading part performance.
18 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 package information edge720bxf 10 mm x 10 mm x 1.4 mm exposed pad qfp d e d 1 e 1 a b d n 1 heatsink intrusion .0127 max exposed heatsink 5.00 mm sq. top view bottom view
19 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 footprint dims. tolerance body + 2.00 mm a max. 1.60 a1 .05 min. / .15 max a2 .05 1.40 d .20 12.00 d1 .10 10.00 e .20 12.00 e1 .10 10.00 l +.15 / .10 .60 e basic .65 b .05 .30 q0 o - 7 o ddd max. .13 ccc max. .10 package thickness 1.40 12 typ. ? 12 typ. ? a a 2 a 1 standoff a 1 seating plane ? ? 6 4 lead coplanarity c l .25 a 0.17 max. ddd m s s cd a b ccc c 0.20 rad. typ. package information (continued) edge720bxf 10 mm x 10 mm x 1.4 mm exposed pad qfp
20 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 recommended operating conditions r e t e m a r a pl o b m y sn i mp y tx a ms t i n u y l p p u s r e w o p e v i t i s o pc c v5 2 . 5 1 +5 . 5 1 +5 7 . 5 1 +v y l p p u s r e w o p e v i t a g e ne e v5 7 . 4 5 . 4 5 2 . 4 v y l p p u s g o l a n a l a t o te e v c c v5 . 9 10 . 0 25 . 0 2v y l p p u s t u p t u o r o t a r a p m o cl c e p03 . 30 . 5v e r u t a r e p m e t n o i t c n u jt j 0 60 8c ? e g a k c a p f o e c n a t s i s e r l a n m r e h t ) e s a c o t n o i t c n u j ( c j 1 . 4 1w / c ?
21 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 absolute maximum ratings r e t e m a r a pl o b m y sn i mx a ms t i n u ) d n g o t e v i t a l e r ( c c vc c v05 . 6 1v ) d n g o t e v i t a l e r ( e e ve e v0 1 0v y l p p u s r e w o p l a t o te e v c c v0 . 1 2v ) d n g o t e v i t a l e r ( l c e pl c e p1 . 0 5 . 5v s e g a t l o v t u p n i l a t i g i d ) * ( n e _ d l , ) * ( n e _ r v d , ) * ( i h de e v0 . 7 +v s e g a t l o v t u p n i l t t l a t i g i dv r e p u s , c _ d p i , d _ d p i5 . 2 0 . 6v s e g a t l o v t u p n i g o l a n a d a o l , p n i v , l v d , h v d , b v c , a v ce e vc c vv ) * n e _ v r d < n e _ v r d ( e g a t l o v t u o d g o l a n at u o d0 . 2 + e e v5 . 1 c c vv s t n e r r u c t u p n i g o l a n an i _ k s i , n i _ c s i j d a f , j d a r s a i b 5 2 1 . 0 0 0 5 2 . 2 5 4 . 1 5 4 . 1 a m a m a m s t n e r r u c t u p t u o l a t i g i d* b q / b q ; * a q / a q00 5a m t n e r r u c t u p t u o r e v i r d c i t a t st u o i0 4 0 4 +a m g n i w s r e v i r dl v d h v d5 . 0 3 1v e g a t l o v r o t a r a p m o c l a i t n e r e f f i d ) 0 = c _ d p i d n a 0 = v r e p u s ( ) b ( a v c p n i v3 1 9 +v e g a t l o v r o t a r a p m o c l a i t n e r e f f i d ) 1 = c _ d p i r o 1 = v r e p u s ( ) b ( a v c p n i v5 1 5 1 +v e g a t l o v t u p n i d a o l) b ( a _ n i _ m c v d a o l3 1 3 1 +v t i m i l n w o d k a e r b e g a t l o v g n i t a t u m m o c) b ( a _ n i _ m c v5 2 . 6 1 c c vc c vv e r u t a r e p m e t e g a r o t ss t5 6 0 5 1 +c ? ) 1 e t o n ( e r u t a r e p m e t n o i t c n u jj t5 2 1 +c ? e r u t a r e p m e t g n i r e d l o s ) n i p e h t m o r f " 5 2 . , s d n o c e s 5 ( l o s t0 6 2 +c ? stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. exposure to absolute maximum conditions for extended periods may affect device reliability. note 1: this device does not contain internal thermal limiting; external cooling is required.
22 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 dc characteristics dc test conditions (unless otherwise specified): over the full "recommended operating conditions". r e t e m a r a pl o b m y sn i mp y tx a ms t i n u ) t n e c s e i u q ( r e v i r d + r o t a r a p m o c + d a o l y l p p u s e v i t i s o p y l p p u s e v i t a g e n c c i e e i0 9 1 5 5 1 5 7 1 5 7 1a m a m ) t n e c s e i u q ( l c e pl c e p i5 20 3a m ) p i h c r e p ( n o i t a p i s s i d r e w o p t n e c s e i u qs s i d p2 . 3w power supply consumption
23 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 dc characteristics (continued) driver circuit r e t e m a r a pl o b m y sn i mp y tx a ms t i n u s e g a t l o v t u p n i g o l a n a s e g a t l o v t u p n i l e v e l r e v i r d l e v e l e g a t l o v t u p n i " l e v e l h g i h " h v d l e v e l e g a t l o v t u p n i " l e v e l w o l " l v d l e v e l e g a t l o v t u p n i " e g a t l o v r e p u s " h v d l e v e l e g a t l o v t u p n i " e g a t l o v r e p u s " l v d e g n a r e g a t l o v t u p n i l a i t n e r e f f i d h v d v l v d v h h v d v h l v d v l v d v h v d v 0 . 4 + e e v 5 . 3 + e e v 0 . 4 + e e v 5 . 3 + e e v 0 5 . 3 c c v 5 . 4 c c v 5 7 . 1 c c v 5 7 . 1 c c v 9 v v v v v s t n e r r u c t u p n i g o l a n a t n e r r u c t u p n i l v d , h v d t n e r r u c t u p n i j d a f , j d a r t n e r r u c t u p n i s a i b l v d i , h v d i j d a f i , j d a r i s a i b i 0 5 4 . 0 5 . 0 0 5 5 2 . 1 5 2 . 1 a a m a m , j d a f i , j d a r i r o f e g n a r e g a t l o v e c n a i l p m o c s a i b i a m 5 2 . 1 , j d a f v , j d a r v s a i b v 00 . 3v s c i t s i r e t c a r a h c t u p t u o r e v i r d ) e g a t l o v r e p u s - n o n ( t n e r r u c t u p t u o c i t a t s c d ) e g a t l o v r e p u s - n o n ( t n e r r u c t u p t u o c i m a n y d c d ) e g a t l o v r e p u s ( t n e r r u c t u p t u o c d ) a m 5 3 @ ( e c n a d e p m i t u p t u o i t u o i t u o c i m a n y d v s t u o i r t u o 5 3 0 5 . 0 0 9 3 . 1 5 3 6 5 . 3 a m a m a m ? e g a k a e l t u o d v 8 ( e d o m z i h ) b ( a v c t u o d ) v 8 v 2 1 < t u o d < ) 5 . 3 + e e v ( @ 5 . 3 + e e v ( e d o m d p i ) b ( a v c , v 8 ) 1 = c d p i = d d p i ) v 5 . 3 + e e v ( @ v 0 < t u o d v 0 @ t u o d v 8 + t u o d < v 8 @ v 2 1 t u o d < v 2 1 @ v 3 1 k a e l _ i k a e l _ i k a e l _ i k a e l _ i k a e l _ i 1 0 0 3 5 1 0 3 0 0 1 1 0 0 3 5 1 0 3 0 0 1 a a n a n a n a n y c a r u c c a c d r e v i r d ) v 5 . 3 c c v o t v 0 . 4 + e e v : e g n a r h v d ( h g i h r e v i r d ) v 0 = h v d ( e g a t l o v t e s f f o n i a g y t i r a e n i l v 5 . 3 c c v o t v 0 . 4 + e e v = h v d v 0 1 o t v 5 2 . 0 = h v d ) v 5 7 . 1 c c v = h v d ( t e s f f o e g a t l o v r e p u s t n e i c i f f e o c e r u t a r e p m e t e g a t l o v t e s f f o t u o d v h v d v h v d v / t u o d v l n i h v d t u o d v h h v d v ? / t u o d v ? t 5 2 1 8 9 . 0 0 2 0 1 5 2 . 0 5 2 1 1 0 2 0 1 0 5 7 v m v / v v m v m v m c ? / v m ) v 5 . 4 c c v o t v 5 . 3 + e e v : e g n a r l v d ( w o l r e v i r d ) v 0 = l v d ( e g a t l o v t e s f f o n i a g y t i r a e n i l v 5 . 4 c c v o t v 5 . 3 + e e v = l v d v 0 1 o t v 5 7 . 0 = l v d ) v 5 7 . 1 c c v = l v d ( t e s f f o e g a t l o v r e p u s t n e i c i f f e o c e r u t a r e p m e t e g a t l o v t e s f f o t u o d v l v d l v d v / t u o d v l n i l v d t u o d v h l v d v ? / t u o d v ? t 5 2 1 8 9 . 0 0 2 0 1 5 2 . 0 5 2 1 1 0 2 0 1 0 0 0 2 v m v / v v m v m v m c ? v m s e g a t l o v t u p n i l a t i g i d e g n a r e g a t l o v t u p n i ) * ( n e _ r v d , ) * ( i h d g n i w s t u p n i l a i t n e r e f f i d e g a t l o v w o l t u p n i v r e p u s , d _ d p i e g a t l o v h g i h t u p n i v r e p u s , d _ d p i v t u p n i x e l f * t u p n i t u p n i l i v h i v 5 7 . 2 + e e v 5 2 . 0 0 . 2 5 0 . 4 5 . 0 v v v v d _ d p i , ) * ( n e _ r v d , ) * ( i h d t n e r r u c t u p n i l a t i g i d ) * ( n e _ r v d , ) * ( i h d v r e p u s , d _ d p i i t u p n i x e l f i d _ d p i 0 5 3 0 0 1 0 5 3 0 0 1 a a dc test conditions (unless otherwise specified): over the full recommended operating conditions".
24 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 dc test conditions (unless otherwise specified): over the full recommended operating conditions". r e t e m a r a pl o b m y sn i mp y tx a ms t i n u s e g a t l o v t u p n i g o l a n a e g n a r e g a t l o v t u p n i r o t a r a p m o c e g n a r e g a t l o v d l o h s e r h t r o t a r a p m o c e g n a r e g a t l o v r o t a r a p m o c l a i t n e r e f f i d p n i v b v c , a v c ) b ( a v c p n i v 5 . 3 + e e v 5 . 3 + e e v 8 5 . 3 c c v 5 . 3 c c v 8 v v v s t n e r r u c t u p n i g o l a n a t n e r r u c t u p n i d l o h s e r h t t n e r r u c t u p n i p n i v e d o m l a m r o n ) 0 = v r e p u s , 0 = c _ d p i = d _ d p i ( ) 5 . 3 + e e v ( @ v 2 1 < p n i v e d o m d p i , 1 = v r e p u s r o 1 = c _ d p i = d _ d p i ( 5 . 3 + e e v ) b ( a v c ) v 8 + ) 5 . 3 + e e v ( @ v 0 < p n i v v 0 @ p n i v v 8 p n i v < v 8 @ v 2 1 p n i v < v 2 1 @ v 3 1 ) b ( a v c _ i p n i v i p n i v i p n i v i p n i v i p n i v i 0 5 3 0 0 1 5 2 0 5 0 5 0 5 3 0 0 1 5 2 0 5 0 5 a a a n a n a n a n y c a r u c c a c d s i s e r e t s y h r o t a r a p m o c t e s f f o r o t a r a p m o c e r u t a r e p m e t t e s f f o r o t a r a p m o c t n e i c i f f e o c ) 1 e t o n ( e c n a d e p m i t u p n i p n i v ) s y h ( v s o v ? / s o v ? t r n i 0 2 2 0 1 4 0 . 0 0 2 v m v m c ? / v m m ? e g a t l o v t u p n i l a t i g i d e g a t l o v w o l t u p n i c _ d p i e g a t l o v h g i h t u p n i c _ d p i l i v h i v0 . 2 5 . 0v v t n e r r u c t u p n i l a t i g i d e g n a r t n e r r u c t u p n i c _ d p i c _ d p i _ i0 0 1 0 0 1a e g a t l o v t u p t u o l a t i g i d g n i w s t u p t u o l a i t n e r e f f i d e g n a r e d o m n o m m o c t u p t u o | * b q v b q v | , | * a q v a q v | 2 / | * b q v + b q v | , 2 / | * a q v + a q v | 0 0 4 5 . 1 l c e p2 . 1 l c e p v m v comparator circuit dc characteristics (continued)
25 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 dc characteristics (continued) r e t e m a r a p l o b m y sn i mp y tx a ms t i n u s t u p n i g o l a n a d a o l e l b a m m a r g o r p ) n i _ k s i , n i _ c s i ( s t u p n i g n i m m a r g o r p t n e r r u c e g n a r e g a t l o v e c n a i l p m o c t u p n i e g n a r t n e r r u c t u p n i n i _ k s i v , n i _ c s i v n i _ k s i i , n i _ c s i i 1 . 0 0 5 . 2 3 9 . 1 v a m ) n i _ m c v ( t u p n i r e f f u b g n i t a t u m m o c e g n a r e g a t l o v t u p n i r e f f u b g n i t a t u m m o c e g n a r t n e r r u c t u p n i r e f f u b g n i t a t u m m o c ) b ( a _ n i _ m c v v ) b ( a _ n i _ m c v i 6 1 c c v 0 0 1 5 . 7 c c v 0 0 1 v a s t u p n i e c r u o s t n e r r u c y r a i l l i x u a e c n a t s i s e r t u p n i k s _ e g d i r b , c s _ e g d i r bn i r1k ? s t u p n i l a t i g i d d a o l e l b a m m a r g o r p ) ) * ( n e _ d l ( s t u p n i e l b a n e d a o l e g n a r e g a t l o v t u p n i l a t i g i d g n i w s t u p n i l a i t n e r e f f i d t n e r r u c t u p n i l a t i g i d ) * ( n e _ d l v * n e _ d l v n e _ d l v ) * ( n e d l i 5 7 . 2 + e e v 5 2 . 0 0 5 3 5 0 . 4 0 5 3 v v a t u p t u o d a o l e l b a m m a r g o r p e g n a r e g a t l o v t u p t u o d a o l e g n a r t n e r r u c t u p t u o d a o l e g a t l o v d a o l l a i t n e r e f f i d e c n a d e p m i t u p t u o d a o l d a o l v d a o l i n i _ m c v d a o l v t u o z 5 . 3 + e e v 5 3 1 1 5 5 . 3 c c v 5 3 1 1 8 v a m v ? e g a k a e l e c r u o s t n e r r u c p i h c - n o v 8 ( d e l b a n e t i u c r i c d a o l ) b ( a v c d a o l , v 8 ) a m 0 = n i _ c s i = n i _ k s i , 0 = v r e p u s , 0 = c _ d p i = d _ d p i ( e d o m z i h < n e _ d lv 8 , * n e _ d l ) b ( a v c d a o l ) v 8 5 . 3 + e e v @ d a o l v 2 1 , 1 = d _ d p i , 1 = v r e p u s r o 1 = c _ d p i ( e d o m d p i 5 . 3 + e e v , * n e _ d l < n e _ d l ) b ( a v c ) v 8 v 0 < d a o l < 5 . 3 + e e v @ v 0 @ d a o l v 8 v 2 1 < d a o l < v 8 @ d a o l < v 2 1 @ v 3 1 d a o l i d a o l i d a o l i d a o l i d a o l i d a o l i 0 0 3 1 0 5 2 5 1 0 3 0 0 1 0 0 3 1 0 5 2 5 1 0 3 0 0 1 a n a a n a n a n a n load circuit dc test conditions (unless otherwise specified): over the full recommended operating conditions".
26 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 dc conditions (unless otherwise specified): over the full "recommended operating conditions". note 1: not production tested. guaranteed by design and characterization. dc characteristics (continued) r e t e m a r a pl o b m y sn i mp y tx a ms t i n u y c a r u c c a t n e r r u c d a o l e l b a m m a r g o r p t e s f f o t n e r r u c k n i s / e c r u o s n i a g t n e r r u c k n i s / e c r u o s r o r r e y t i r a e n i l t n e r r u c k n i s / e c r u o s s o i i a 1 8 1 4 1 2 2 a a m / a m n i _ k s i , n i _ c s i s t n i o p n o i t a r b i l a c a 0 3 , a 5 1 a 0 3 1 , a 0 3 a 0 0 5 , a 0 3 1 a 0 5 7 , a 0 0 5 a m 1 , a 0 5 7 a m 2 . 1 , a m 1 a m 4 . 1 , a m 2 . 1 a m 6 . 1 , a m 4 . 1 a m 3 9 . 1 , a m 6 . 1 t n i o p t s e t a 5 . 2 2 a 0 8 a 5 1 3 a 5 2 6 a 5 7 8 a m 1 . 1 a m 3 . 1 a m 5 . 1 a m 7 . 1 d e m m a r g o r p l a u t c a 5 5 1 0 5 0 5 0 5 0 5 0 5 0 5 0 0 1 5 5 1 0 5 0 5 0 5 0 5 0 5 0 5 0 0 1 a a a a a a a a a t n e r r u c d a o l f o o c p m e t ? / d a o l i ? t ) 1 + % 1 . 0 ( c ? / a y c a r u c c a e g a t l o v g n i t a t u m m o c ) v 0 = n i _ m c v @ e g a t l o v t e s f f o r e f f u b g n i t a t u m m o c e g a t l o v t u p t u o r e f f u b f o o c p m e t s o v ? / ) b ( a _ t u o m c v ? t 0 0 1 2 0 . 0 0 0 1v m c ? / v m load circuit (continued) r e t e m a r a pl o b m y sn i mp y tx a ms t i n u t n e r r u c e g a k a e l 5 . 3 + e e v @ v 0 < d a o l + p n i v + t u o dk a e l i0 5 4 0 5 4a n v 0 @ d a o l + p n i v + t u o d v 8k a e l i0 3 0 3a n d a o l + p n i v + t u o d < v 8 @ v 2 1k a e l i0 5 0 5a n d a o l + p n i v + t u o d < v 2 1 @ v 3 1k a e l i0 0 3 0 0 3a n driver + comparator + load combined leakage ipd mode (ipd_d = 1, ipd_c = 1 or superv = 1, drv_en < drv_en*, ld_en < ld_en*, vee + 3.5 cva(b) +8v)
27 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 r e t e m a r a pl o b m y sn i mp y tx a ms t i n u y a l e d n o i t a g a p o r p r e v i r d t u p t u o o t a t a d ) 2 e t o n ( z i h o t e l b a n e ) 2 e t o n ( e v i t c a t u p t u o o t e l b a n e ) 1 e t o n ( o c p m e t o t y a l e d n o i t a g a p o r p d p t d p t d p t ? / d p t ? t 5 . 1 5 . 1 5 . 1 0 . 1 0 . 3 0 . 3 0 . 3 s n s n s n c ? / s p ) 1 e t o n ( s e m i t l l a f / e s i r r e v i r d ) % 0 8 - % 0 2 ( v m 0 0 8 ) % 0 9 - % 0 1 ( v 3 ) % 0 9 - % 0 1 ( v 5 f t / r t f t / r t f t / r t 0 0 8 2 . 1 0 . 2 0 0 0 1 3 . 1 1 . 2 s p s n s n ) 1 e t o n ( n o i t a i r a v e m i t l l a f / e s i r r e v i r d| f t r t |0 5 s p ) 1 e t o n ( ) n o i t c u d e r e d u t i l p m a % 0 1 ( x a m f v m 0 0 8 v 3 v 5 x a m f x a m f x a m f 0 0 5 0 5 3 0 5 1 z h m z h m z h m e d u t i l p m a % 0 1 ( h t d i w e s l u p m u m i n i m r e v i r d ) 1 e t o n ( ) n o i t c u d e r v m 0 0 8 v 3 v 5 1 2 3 s n s n s n ) 1 e t o n ( e c n a t i c a p a c t u p t u o r e v i r dt u o c2f p ac characteristics ac test conditions (unless otherwise specified): "recommended operating conditions". iradj = ifadj = 1.1 ma. ibias = 0.8 ma, vinp terminated with 50 ? to gnd, qa(*), qb(*) terminated with 50 ? to pecl 2v, isc_in - isk_in = 1.93 ma. r e t e m a r a pl o b m y sn i mp y tx a ms t i n u y a l e d n o i t a g a p o r p r o t a r a p m o cd p t5 . 10 . 3s n ) 1 e t o n ( y a l e d n o i t a g a p o r p f o o c p m e t ? / d p t ? t 0 . 7c ? / s p ) 1 e t o n ( g n i k c a r t e t a r w e l s t u p n i r o t a r a p m o ct r s0 . 4s n / v ) 1 e t o n ( e c n a t i c a p a c t u p n i r o t a r a p m o cn i c0 . 2f p ) 1 e t o n ( ) % 0 8 - % 0 2 ( s e m i t l l a f d n a e s i r t u p t u o l a t i g i df t , r t0 0 5s p ) 1 e t o n ( h t d i w e s l u p m u m i n i m r o t a r a p m o cw p m2 . 1s n comparator circuit driver circuit
28 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 ac characteristics (continued) r e t e m a r a pl o b m y sn i mp y tx a ms t i n u ) 3 e t o n ( y a l e d n o i t a g a p o r p d a o l t u o i o t t i b i h n i t i b i h n i o t t u o i n o _ d p t f f o _ d p t 8 . 3 8 . 3 0 . 5 0 . 6 s n s n ) 1 e t o n ( e c n a t i c a p a c t u p t u o d a o l e v i t c a d a o l f f o d a o l t u o c t u o c 5 . 3 0 . 2 f p f p load circuit ld_en* ld_en load (source case) tpd_on isc_in = 1 ma isk_in = 1 ma load (sink case) 0.9v 0.9v +1v 0v 0v 0v 1v ld_en ld_en* load (source case) load (sink case) tpd_off 0.1v 0.1v isc_in 1 ma isk_in 1 ma 0v 0v 0v +1v 1v ac test conditions (unless otherwise specified): "recommended operating conditions". iradj = ifadj = 1.1 ma. ibias = 0.8 ma, vinp terminated with 50 ? to gnd, qa(*), qb(*) terminated with 50 ? to pecl 2v, isc_in - isk_in = 1.93 ma. note 1: not production tested. guaranteed by design and characterization. note 2: driver enable/disable tpd is depicted below: load propagation delay drv_en drv_en* dout 0v 0v 2.7v tpd_dhz dvh = 3v, dvl = 0v conditions: 1. data = high drv_en* drv_en dout tpd_den dvh = 3v, dvl = 0v conditions: 1. data = high 0v 0.3v 0v note 3: load propagation delay is defined below: driver enable/disable tpd
29 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 ordering information contact information semtech corporation test and measurement division 10021 willow creek rd., san diego, ca 92131 phone: (858)695-1808 fax (858)695-2633 r e b m u n l e d o me g a k c a p f x b 0 2 7 ep f q d a p d e s o p x e d a e l 2 5 ) g u l s t a e h m m 5 x 5 ( f x b 0 2 7 m v ed r a o b n o i t a u l a v e 0 2 7 e g d e
30 www .semtech.com edge720 test and measurement products revision 4 / september 24, 2002 revision history current revision date: september 24, 2002 previous revision date: july 25, 2002 e g a p # e m a n n o i t c e sn o i s i v e r s u o i v e r p n o i s i v e r t n e r r u c l l a " y r a n i m i l e r p " e v o m e r " l a n i f " o t " y r a n i m i l e r p " m o r f d e g n a h c s u t a t s 6 r e v i r d n o i a t s n e p m o c / y t i l i b a t s : d d a h p a r g a r a p d n 2 9s t u p n i g o l a n a r o t a r a p m o c : d d a . h p a r g a r a p t s 1 f o d n e o t s e c n e t n e s 2 0 1 r e w o p r o t a r a p m o c s e i l p p u s : d d a h p a r g a r a p d n 2 2 1 e g a t l o v g n i t a t u m m o c n o i t a s n e p m o c r e f f u b g n i t a t u m m o c l a n r e t n i n a s i n i p p a c _ m c v e h t . . . d e x i f a s e r i u q e r t a h t n i p n o i t a s n e p m o c r e f f u b g n i t a t u m m o c l a n r e t n i e r a s n i p ) b ( a _ p a c _ m c v e h t . . . d e x i f a e r i u q e r t a h t s n i p n o i t a s n e p m o c 2 1 d a o l e v i t c a d r a d n a t s n o i t a r u g i f n o c : d d a . 1 h p a r g a r a p f o d n e o t s e c n e t n e s 1 2 1 p m a l c e l b a m m a r g o r p n o i t a r u g i f n o c : d d a . 1 h p a r g a r a p f o d n e o t s e c n e t n e s 1 4 1y t i v i t c e n n o c. 2 2 e r u g i f n i n w o h s s i l c d 0 2 7 e g d e . . . . 4 2 e r u g i f n i n w o h s s i l c d 0 2 7 e g d e . . . 5 1n o i t a m r o f n i n o i t a c i l p p a : d d a n o i t c e s t i u c r i c t u p t u o d a o l / r o t a r a p m o c / r e v i r d : d d a n o i t c e s g n i s s a p y b y l p p u s r e w o p 6 14 2 e r u g i fe c i v e d l e n n a h c d a u q e c i v e d l e n n a h c - 4 6 7 1n o i t a m r o f n i n o i t a c i l p p a . s e t o n d d a , e r u g i f e t a d p u 3 2s c i t s i r e t c a r a h c c d v 8 - ( e g a k a e l t u o d ) b ( a v c t u o d ) v 8 e d o m z i h e g a k a e l t u o d v 8 - ( e d o m z i h ) b ( a v c t u o d ) v 8 5 2s c i t s i r e t c a r a h c c de g a k a e l e c r u o s t n e r r u c p i h c - n o n e t t i r w e r s r e t e m a r a p l l a
31 www .semtech.com test and measurement products edge720 revision 4 / september 24, 2002 revision history current revision date: july 25, 2002 previous revision date: april 24, 2002 e g a p # e m a n n o i t c e sn o i s i v e r s u o i v e r p n o i s i v e r t n e r r u c 1n o i t p i r c s e d. . . e g a t l o v r e p u s v 5 7 . 3 1 , n o i t i d d a n i : a r a p d n 2 . . . e g a t l o v r e p u s v 3 1 , n o i t i d d a n i : a r a p d n 2 1s e r u t a e fe l b a p a c e g a t l o v r e p u s v 5 7 . 3 1 + e l b a p a c e g a t l o v r e p u s v 3 1 + 5n o i t c u d o r t n i. . . v 5 7 . 3 1 o t p u f o l e v e l e g a t l o v r e p u s . . . . . . v 3 1 o t p u f o l e v e l e g a t l o v r e p u s . . . 6n o i t a r e p o e g a t l o v r e p u s . . . v 5 7 . 3 1 o t p u f o l e v e l e g a t l o v r e p u s . . . . . . v 3 1 o t p u f o l e v e l e g a t l o v r e p u s . . . 8n o i t p i r c s e d t i u c r i c . v 0 = t u o d t a e g a t l o v t u p t u o . . . : e c n e t n e s d n 2 , a r a p t s 1 . v 0 o t d e m m a r g o r p s i t u p n i e h t n e h w e g a t l o v t u p t u o . . . 6 1n o i t a m r o f n i s p p a : d d a e r u g i f o t ) b ( a _ t u o _ m c v 7 1n o i t a m r o f n i e g a k c a p s g n i w a r d e t a d p u 8 1 n o i t a r e p o d e d n e m m o c e r s n o i t i d n o c 0 5 : n i m , e r u t a r e p m e t n o i t c n u j 0 6 : n i m , e r u t a r e p m e t n o i t c n u j 1 2 y l p p u s r e w o p n o i t p m u s n o c 0 1 2 : n i m , y l p p u s e v i t a g e n 0 9 1 : n i m , y l p p u s e v i t a g e n 2 2t i u c r i c r e v i r d5 . 4 : x a m , 2 : p y t , ) a m 5 2 @ ( e c n a d e p m i t u p t u o 5 . 3 : x a m , 3 . 1 : p y t , ) a m 5 3 @ ( e c n a d e p m i t u p t u o y t i r a e n i l s e g n a r t u o d o t n i k a e r b d _ d p iv r e p u s / d _ d p i e g n a r t u o d " = h v d " o t e g n a h c 0 0 5 : x a m , ) 5 . 2 c c v = t u o d ( t e s f f o e g a t l o v r e p u s 0 5 7 : x a m , ) v 5 7 . 1 c c v = h v d ( t e s f f o e g a t l o v r e p u s 3 2t i u c r i c r o t a r a p m o c 0 = v r e p u s , 0 = c _ d p i 1 = v r e p u s r o 1 = c _ d p i 1 . 1 l c e p : x a m , e g n a r e d o m n o m m o c t u p t u o 0 = v r e p u s , 0 = c _ d p i = d _ d p i 1 = v r e p u s r o 1 = c _ d p i = d _ d p i 2 . 1 l c e p : x a m , e g n a r e d o m n o m m o c t u p t u o 4 2t i u c r i c d a o ln i _ m c v i , n i _ m c v v : m y s ) b ( a _ n i _ m c v i , ) b ( a _ n i _ m c v v . . . , 0 = c _ d p i ( e d o m z i h * n e _ d l < n e _ d l , 1 = v r e p u s r o 1 = c _ d p i ( e d o m d p i . . . , 0 = c _ d p i = d _ d p i ( e d o m z i h < n e _ d l , 1 = d _ d p i , 1 = v r e p u s r o 1 = c _ d p i ( e d o m d p i * n e _ d l 5 2t i u c r i c d a o l s c e p s r o r r e y t i r a e n i l t n e r r u c k n i s / e c r u o s e t a d p u current revision date: april 24, 2002 previous revision date: august 13, 2002 e g a p # e m a n n o i t c e sn o i s i v e r s u o i v e r p n o i s i v e r t n e r r u c l l as n o i t c e s l l a n e t t i r w e r s n o i t c e s l l a " y r a n i m i l e r p " o t " t e g r a t " m o r f d e g n a h c s u t a t s

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