this document is for maintenance purposes only and is not recommended for new designs
cla70000v low voltage specification 1.0 m cmos gate arrays august 1992 features n operates at 3.3v n 1.0 m (0.8 m leff) twin well, epitaxial cmos process n 5,000 to 250,000 available gates on a chanelless array architecture n low current and power (<1 m a/gate/mhz) n slew controlled outputs with drivers up to 12ma for bus driving and other applications. n esd protection in excess of 2kv n comprehensive cell library including dsp and compiled memory cells (rom blocks to 64k bits and ram blocks to 16k bits) n supports jtag/bist test philosophies (ieee 1149-1 test procedures) n fully supported on industry standard workstations and in-house software description page process technology 2 core design 2 i/o design 2 ac characteristics 3 dc characteristics 4 design tools 5 packaging 6 array raw gates pads cla70000 5000 44 cla71000 12000 68 cla72000 19000 84 cla73000 27000 100 cla74000 39000 120 cla75000 70000 160 CLA76000 110000 200 cla77000 182000 256 cla78000 256000 304 cla70000 family contents general description advances in processing technology have led to the development of an array family which can operate at 3 volts. this series of arrays may be used with the lower voltage power supply rails which are becoming increasingly common. applications include battery portable such as laptop computers where low power consumption is essential as well as pagers and consumer applications like hand held language translators and games. this summary datasheet gives information on the cla70000 series ac and dc characteristics at low voltage. ds3535 - 1.0
cla70000v 2 vss supply vss supply programmable contacts figure 1 : process ?q?process cross section core cell design a four transistor group (2 nmos and 2pmos) (fig 2.) forms the basic cell of the core array. this array element is repeated in a regular fashion over the complete core area to give a homogeneous ?ull field?(sea of gates) array. this lends itself to hierarchical design, allowing pre-routed user defined subcircuits to be repeated anywhere on the array. the core cell structure has been carefully designed to maximise the number of nets which may be routed through the cell. this enables optimal routing for both data flow and control signal distribution schemes thus giving very high overall utilisation figures. this feature is of particular benefit in designs using highly structured blocks such as memory or arithmetic functions. figure 2 : diagrammatic representation of array core cell ip op1 op2 ib1 ib2 bonding pad i/o block ib3 ib4 ib5 vdd supply cmos process technology the cla70000 arrays are based on gec plessey semiconductors well proven 1 m cmos process, manufactured at gps? advanced , class 10, six-inch wafer fabrication facility. the process (fig.1) is a twin well, self aligned oxide-isolated technology, with an effective channel length of 0.8 m m (1.0 m m drawn ), giving a low defect density, high reliability, and inherently low power dissipation. the process has excellent immunity to latch-up, and esd, and exhibits stable performance characteristics. input/output buffer design the peripheral cells (fig.3) are fully programmable as input, output, vdd or gnd, and they are designed to offer several interfacing options, ttl and cmos for example. the cells already contain input ?ull-up?and ?ull-down?resistors and electro static discharge protection elements. components for implementing schmitt triggers, ttl threshold detectors, tristate control, and flip-flops for signal re-timing are also included. a range of output buffers is available with various output drive currents to match system requirements. noise transients due to a large number of simultaneously switching outputs are an increasing problem as bus widths widen (the supply pad location, and the inductance of the bond wires and package leads are also factors). cla70000 arrays offer several i/o buffers with the capability to control the output slew (di/dt) (fig.4) which are invaluable in controlling these transients when driving large capacitive loads such as busses. pin opt3 p n p n d input data 2.5 volts 2.5 volts 50 pf ibsk1, ibsk2 and ibsk3 have been characterised to g ive the correct timin g when connected to the opt* cells. slew rate controlled driver slew rate control figure 3 figure 4
cla70000v 3 ac characteristics the performance of the cla70000v device depends on numerous factors including: supply voltage ambient temperature, and temperature of the devices active junctions gate front, i.e. the logic loading on the gate outputs interconnection loading on the gates processing tolerance, i.e. the manufacturing spreads the cla70000 technology library contains all the performance information for each cell in the design libraries. the pds design software suite accesses this data, and the simulation program automatically calculates the design's performance under the selected operating c onditions. prior to layout, estimates of the interconnection loadings are used in the simulations. after layout, track loadings are extracted f rom the physical design to allow re-simulation with actual values to confirm device performance. the effect of those factors on the propagation delays of arange of selected cells is illustrated in the tables below. fanout is in gate load units typical propagation delay ns worst case propagation delay (ns) 3 volts 70 c fanout name cells description symbol fanout = 10pf 10pf 50pf op3 - standard output buffer tplh 0.73 2.58 8.83 tplh 0.49 1.73 5.98 op6 - medium output buffer tphl 0.50 1.77 4.88 tplh 0.33 1.16 3.29 op12 - large output buffer tplh 0.38 1.35 2.91 tplh 0.25 0.90 2.04 5 volts 25 c typical propagation delay ns worst case propagation delay (ns) 3 volts 70 c fanout name cells description symbol fanout = 2 2 4 inv2 1 inverter dual drive tplh 0.27 0.95 1.14 tplh 0.18 0.64 0.76 nand2 1 2-input nand gate tphl 0.39 1.37 1.75 tplh 0.30 1.07 1.41 nor2 1 2-input nor gate tplh 0.50 1.77 2.46 tplh 0.22 0.78 1.09 df 4 master slave d-type flip flop tphl 0.54 1.90 2.18 tplh 0.55 1.96 2.11 5 volts 25 c typical propagation delay ns worst case propagation delay (ns) 3 volts 70 c fanout name cells description symbol fanout = 2 2 4 ibgate - large 2 input nand gate +2 input nor tplh 0.34 1.20 1.39 tplh 0.27 0.97 1.14 ibdf - master slave d-type flip flop tphl 0.48 1.69 1.96 tplh 0.50 1.78 1.93 ibcmos1 - cmos input buffer with 2 input nand gate tplh 0.60 2.15 2.28 tplh 0.45 1.59 1.65 5 volts 25 c output buffer cells intermediate buffer cells internal core cells
cla70000v 4 value characteristic sym min typ max unit conditions low level input voltage vil v ttl inputs (ibttl1/ibttl2) 0.6 cmos inputs (ibcmos1/ibcmos2) 0.2vdd high level input voltage vih v ttl inputs (ibttl1/ibttl2) 2.2v cmos inputs (ibcmos1/ibcmos2) 0.75vdd input hysteresis v (ibst1) rising vt+ 1.9 vil to vih falling vt- 1.2 vih to vil (ibst2) rising vt+ 1.3 vil to vih falling vt- 0.8 vih to vil input current/resistance (cmos / ttl inputs) iin no resistor 1 m a vin = vdd or vss inputs with 1kohm resistors 0.50 1.00 2 k w inputs with 2kohm resistors 1.00 2.00 4 k w inputs with 4kohm resistors 2.00 4.00 8 k w inputs with 75kohm resistors 20.00 75.00 250 k w resistor values nominal - see note 1 high level output voltage voh v all outputs vdd - 0.05 ioh = -1 m a smallest drive cell op1/opt1/opos1 0.75vdd 0.9vdd ioh = -1ma low drive cell op2/opt2/opos2 0.75vdd 0.9vdd ioh = -2ma standard drive cell op3/opt3/opos3 0.75vdd 0.9vdd ioh = -3ma medium drive cell op6/opt6/opos6 0.75vdd 0.9vdd ioh = -6ma large drive cell op12/opt12/opos12 0.75vdd 0.9vdd ioh = -12ma low level output voltage vol v all outputs vss + 0.05 iol = 1 m a smallest drive cell op1/opt1/opod1 0.2 0.4 iol = 1ma low drive cell op2/opt2/opod2 0.2 0.4 iol = 2ma standard drive cell op3/opt3/opod3 0.2 0.4 iol = 3ma medium drive cell op6/opt6/opod6 0.2 0.4 iol = 6ma large drive cell op12/opt12/opod12 0.2 0.4 iol = 12ma tristate output leakage current tristate, open drain and open source output cells ioz -1 1 m a vout = vss or vdd output short circuit current ios ma standard outputs op3/opt3/opod3 67 135 270 vdd = max, vout = vdd (see note 2) op3/opt3/opos3 37 75 150 vdd = max, vout = 0v operating supply current (per gate) (see note 3) iddop 1 m a/mhz input capacitance ci 5 pf any inputs (note 4) output capacitance cout 5 pf any output (note 4) bidirectional pin capacitance cvo 7 pf any i/o pin (note 5) dc electrical characteristics all characteristics at 3 - 5.5 volts and 0 -70 c temperature note 1: if resistors are used with outputs the correct value of the resistor must be used to maintain vol/voh logic levels. note 2: standard driver output op3 etc. short circuit current for other outputs will scale. not more than one output may be sho rted at a time for a maximum duration of one second. note 3: excluding peripheral buffers. note 4: excludes package leadframe capacitance or bidirectional pins. note 5: excludes package. recommended operating limits parameter min max units supply voltage 3.0 5.5 v input voltage vss vdd v output voltage vss vdd v current per pad 100 ma operating temperature: commercial grade 0 70 degree c industrial grade -40 85 degree c military grade -55 125 degree c parameter min max units supply voltage - 0.5 7.0 v input voltage - 0.5 vdd+0.5 v output voltage - 0.5 vdd+0.5 v operation above these absolute maximum ratings or prolonged periods above the recommended operating limits may permanently damage device characteristics and may affect reliability. storage temperature: ceramic -65 150 degree c plastic - 40 125 degree c absolute maximum ratings vdd =3v
cla70000v 5 pds2 - the gps asic design system n behavioral, functional, and gate level modelling n vhdl and third party links n supports hierarchical design techniques n edif 2.0 interface pds2 is gps? own proprietary asic design system. it provides a fully-integrated, technology independent vlsi design environment for all gps cmos semicustom products. pds2 runs on digital equipment computers and is self configuring according to the available machine resources. it comprises design capture (schematic capture or vhdl), testability analysis, logic simulation, fault simulation, auto place and route, and back annotation. the system offers full support for hierarchical design techniques, maintained from design capture through to layout, as well as advanced design management tools. pds2 may be used either at a gps design center or under licence at the customer? premises. a three day training course is available for first time users. third party software support n design kits for major industry standard asic design software tools n all libraries include fully detailed timing information n edif 2.0 interface n post layout back annotation available gps supports a wide range of third party design tools including ikos, mentor, verilog, and viewlogic. the design kits offer fully detailed timing information for all cell libraries, netlist extraction utilities, and post layout back annotation capability where applicable. an example of a workstation design flow is shown in the figure 5 (opposite). please contact your local gec plessey semiconductor? sales office for further information about support of particular tools. schematic capture test vector generation simulation vector translation back - annotation erc & netlist translation schematic symbols cla libraries simulation models mle place & route design verification test program generation pds environment workstation environment figure 5 : workstation design flow design support design support is available from various centres worldwide each of which is connected to our headquarters via high speed data links. a design centre engineer is assigned to each customers circuit, to ensure good communication, and a smooth and efficient design flow. as part of the design process gps operates a thorough design audit procedure to verify compliance with customer specifica- tion and to ensure manufacturability. the procedure includes four separate review meetings, with the customer, held a key stages of the design. the standard design audit procedure is outlined opposite. review 1: held at the beginning of the design cycle to check and agree on specifications and design timescales. review 2 held after logic simulation and prior to layout. checks to ensure satisfactory functionality, tim- ing performance, and adequate fault coverage review 3 held after layout and post layout simulation. verification of design performance after inser- tion of actual track loads. final check of all device specifications before prototype manu- facture. review 4 held after prototype delivery. confirms that the devices meet the specification and are suitable for full scale production. design tools the focus of the gec plessey design tool methodology is that of maintaining an open cad system with all interfaces standardized via edif 2.0 . this enables us to provide full support for a variety of 3rd party asic design tools and facilitates rapid upda ting of associated libraries. it also provides an interface to the gec plessey (pds2) design system, which offers a total design environment including behavioral and functional level modelling.
cla70000v 6 this publication is issued to provide outline information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned. the company reserves the r ight to alter without notice the specification, design, price or conditions of supply of any product or service. headquarters operations gec plessey semiconductors cheney manor, swindon, wiltshire sn2 2qw, united kingdom. tel: (0793) 518000 tx: 449637 fax: (0793) 518411 gec plessey semiconductors sequoia research park, 1500 green hills road, scotts valley, california 95066, united states of america. tel (408) 438 2900 itt telex: 4940840 fax: (408) 438 5576 customer service centres france & benelux les ulis cedex tel: (1) 64 46 23 45 tx: 602858f fax : (1) 64 46 06 07 germany munich tel: (089) 3609 06-0 tx: 523980 fax : (089) 3609 06-55 italy milan tel: (02) 33001044/45 tx: 331347 fax: (gr3) 316904 japan tokyo tel: (03) 3296-0281 fax: (03) 3296-0228 north america integrated circuits, scotts valley, usa tel (408) 438 2900 itt tx: 4940840 fax: (408) 438 7023. sos, microwave and hybrid products, farmingdale, usa tel (516) 293 8686 fax: (516) 293 0061. south east asia singapore tel: 2919291 fax: 2916455 sweden johanneshov tel: 46 8 7228690 fax: 46 8 7227879 united kingdom & scandinavia swindon tel: (0793) 518510 tx: 444410 fax : (0793) 518582 these are supported by agents and distributors in major countries world-wide. gec plessey semiconductors 1992 publication no. ds 3535 issue no. 1.0 august 1992 packaging production quantities of the cla70000 family are available in industry-standard ceramic and plastic packages according the codes shown below. prototype samples are normally supplied in ceramic only. dc dilmon dual in line, multilayer ceramic. brazed leads metal sealed lid. through board. dg cerdip dual in line, ceramic body, alloy leadframe, glass sealed, through board. dp plasdip dual in line, copper or alloy leadframe, plastic moulded. through board. ac p.g.a. pin grid array, multilayer ceramic. metal sealed lid. through board. ac (p) power p.g.a. as above with cavity down and cu/w heat plate. mp small outline (s.o.) dual in line, ?ullwing?formed leads. plastic moulded surface mount. lc lcc leadless chip carrier. multilayer ceramic. metal sealed lid. surface mount. hc leaded chip carrier quad multilayer ceramic. brazed j formed leads. metal sealed lid. surface mount gc leaded chip carrier quad multilayer ceramic. brazed leads. metal sealed lid. surface mount. gc (p) power leaded chip carrier as above with cavity down, and cu/w heat plate. hg quad cerpac quad ceramic body, ??formed leads. glass sealed. surface mount. gg ceramic quad flatpack quad ceramic body, ?ullwing?formed leads. glass sealed. surface mount. hp plcc quad plastic leaded chip carrier. ??formed leads. plastic moulded. surface mount gp pqfp plastic quad flat pack. ?ullwing?formed leads. plastic moulded. surface mount. united kingdom: swindon, tel: (0793) 518000 tx: 449637 fax: (0793) 518411. oldham, tel: (061) 682 6844, fax: (061) 688 7898. lincoln, tel: (0522) 500500 tx: 56380 fax: (0522) 500550. wembley, tel: (081) 908 4111 tx: 28817 fax: (081) 908 3801. united states of america: scotts valley, tel: (408) 438 2900 itt tx: 4940840 fax: (408) 438 5576. dedham, tel: (617) 320-9369. fax: (617) 320-9383. irvine, tel: (714) 455-2950. fax: (714) 455-9671. australia: rydalmere, nsw, tel: (612) 638 1888. fax: (612) 638 1798. france: les ulis cedex, tel: (6) 446 23 45 tx: 602858f. fax: (6) 446 06 07. italy: milan, tel: (02) 33001044/45 tx: 331347 fax: (gr3) 2316904. germany: munich, tel: (089) 3609 06 0 tx: 523980. fax: (089) 3609 06 55. japan: tokyo, tel: (3) 839 3001. fax: (3) 839 3005. primary semi-custom design centres
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